Indicating device

Abstract

Reduce the bezel area of the display device to implement a high-resolution zero-bezel display device. 【Solution means】The display device according to an embodiment of the present specification includes a substrate on which a plurality of light-emitting elements are arranged, a transistor arranged on the substrate, a plurality of signal wirings arranged on the substrate, a plurality of link wirings arranged under the substrate, and a plurality of upper pads arranged on the substrate and connected to the plurality of signal wirings. The plurality of upper pads are arranged so as to overlap at least one of the plurality of signal wirings and the plurality of transistors.

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, to a display device with a reduced bezel area.

Background Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display devices (OLEDs) that emit light by themselves, and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The application range of display devices is diverse not only for computer monitors and TVs but also for personal mobile devices, and research is underway on display devices that have a reduced volume and weight while having a large display area.

[0004] In recent years, display devices including LEDs (Light Emitting Diodes) have attracted attention as next-generation display devices. Since LEDs are made of inorganic materials rather than organic materials, they are highly reliable and have a longer lifespan than liquid crystal display devices and organic light emitting display devices. In addition, LEDs not only have a fast lighting speed but also excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by this specification is to provide a display device with a reduced bezel area.

[0006] The problem to be solved by this specification is to provide a display device with a reduced bezel area and capable of realizing high resolution.

[0007] Another problem to be solved by this specification is to provide a display device in which the problem of disconnection between a plurality of pads is reduced.

[0008] Another problem to be solved by this specification is to provide a display device in which the problem that the substance constituting the side wiring is not applied to the side surface of the substrate of the display device is improved.

[0009] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0010] The display device according to an embodiment of this specification includes a substrate on which a plurality of light-emitting elements are arranged, a transistor arranged on the substrate, a plurality of signal wirings arranged on the substrate, a plurality of link wirings arranged under the substrate, and a plurality of upper pads arranged on the substrate and connected to the plurality of signal wirings. The plurality of upper pads are arranged so as to overlap at least one of the plurality of signal wirings and the plurality of transistors. Therefore, it is possible to reduce the bezel area of the display device and implement a high-resolution zero-bezel display device.

[0011] Specific matters of other embodiments are included in the detailed description and the drawings.

Effects of the Invention

[0012] This specification can reduce the bezel area of the display device by arranging it so as to overlap at least one of the plurality of signal wirings and the plurality of transistors.

[0013] This specification can reduce the bezel area and implement a high-resolution display device.

[0014] This specification can improve the problem that a plurality of pads are disconnected due to physical impact.

[0015] This specification can uniformly arrange side wirings disposed on the side surface of a substrate.

[0016] The effects according to this specification are not limited by the content exemplified above, and more various effects are included in this specification.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2a

Figure 2b

Figure 3a

Figure 3b

Figure 4a

Figure 4b

Figure 5

Modes for Carrying Out the Invention

[0018] The advantages, features, and the methods for achieving them of this specification will become clear by referring to the embodiments described in detail hereinafter together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and is embodied in various different shapes. Merely, these embodiments are provided so that the disclosure of this specification becomes complete and so that those having ordinary knowledge in the technical field to which this specification pertains can fully know the scope of the invention.

[0019] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, in explaining this specification, if it is determined that a detailed description of related known technologies may muddy the gist of this specification, the detailed description thereof will be omitted. When terms such as "including", "having", "being made" are used in this specification, unless "only" is used, other parts may be added. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0020] In interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0021] In the case of an explanation of a positional relationship, for example, when a two-part positional relationship such as "on", "above", "below", "next to" is described, unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0022] An element or layer referred to as "on" another element or layer includes both the case where it is immediately above the other element and the case where another layer or another element is interposed in the middle.

[0023] Also, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0024] Throughout the specification, the same reference numerals refer to the same components.

[0025] The areas and thicknesses of the respective components shown in the drawings are shown for the convenience of explanation, and this specification is not necessarily limited to the areas and thicknesses of the shown components.

[0026] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various linkages and drives technically, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0027] In the following, various embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0028] FIG. 1 is a plan view of a display device according to an embodiment of this specification. For the convenience of explanation, in FIG. 1, only the substrate 110, data wiring DL, scan wiring SL, a plurality of sub-pixels SP, and the upper pad PAD1 of the display device 100 are shown.

[0029] Referring to FIG. 1, the substrate 110 is a substrate that supports components disposed on the upper part of the display device 100 and may be an insulating substrate. For example, the substrate 110 may be made of glass, resin, or the like. Also, the substrate 110 may comprise a polymer or plastic. In some embodiments, the substrate 110 may be made of a plastic material having flexibility.

[0030] On the substrate 110, a display area AA and a non-display area NA surrounding the display area AA may be defined.

[0031] The display area AA is an area where an image is displayed by the display device 100. In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be arranged.

[0032] The plurality of sub-pixels SP are the minimum units that constitute the display area AA, and a light-emitting element and a thin-film transistor or the like for driving the light-emitting element can be arranged in each of the plurality of sub-pixels SP. A more detailed description of the plurality of sub-pixels SP will be given later with reference to FIGS. 2a to 3b.

[0033] In the display area AA, a plurality of signal wirings for transmitting various signals to the plurality of sub-pixels SP are arranged. For example, the plurality of signal wirings can include a plurality of data wirings DL for supplying data voltages to each of the plurality of sub-pixels SP, a plurality of scan wirings SL for supplying scan voltages to each of the plurality of sub-pixels SP, and the like. A more detailed description of the plurality of signal wirings will be given later with reference to FIGS. 2a to 3b.

[0034] The non-display area NA is an area where an image is not displayed and can be defined as an area surrounding the display area AA. In the non-display area NA, link wirings for transmitting signals to the sub-pixels SP in the display area AA, pad electrodes, and driving ICs such as a gate driver IC and a data driver IC can be arranged.

[0035] In the non-display area NA, a plurality of upper pads PAD1 for transmitting various signals to the plurality of sub-pixels SP on the substrate 110 are arranged. The plurality of upper pads PAD1 are arranged so as to overlap the plurality of signal wirings described later. Further, the plurality of upper pads PAD1 are electrically connected to the side wirings and the plurality of signal wirings in the display area AA, and signals can be transmitted from a plurality of flexible films and printed circuit boards arranged on the back surface of the substrate 110 to the plurality of sub-pixels SP. A more detailed description of the plurality of upper pads PAD1 will be given later with reference to FIGS. 2a to 3b.

[0036] On the one hand, the plurality of upper pads PAD1 do not have to overlap with the plurality of signal wirings. For example, the plurality of upper pads PAD1 can be alternately arranged with the plurality of signal wirings on a plane. At this time, the plurality of upper pads PAD1 and the plurality of signal wirings can be electrically connected on the side surface of the substrate 110 through side wirings arranged on the side surface of the substrate 110. Further, the side wirings can extend from the side surface of the substrate 110 to cover the ends of the plurality of upper pads PAD1 and the ends of the side wirings, but are not limited thereto.

[0037] On the other hand, in this specification, although it has been described that the display area AA and the non-display area NA are defined on the front surface of the display device 100, the front surface of the display device 100 may be defined as having no non-display area NA, and is not limited thereto. When a plurality of display devices 100 according to an embodiment of this specification are connected to implement a tiling display having a large screen, the interval between the outermost sub-pixels SP of one display device 100 and the outermost sub-pixels SP of another adjacent display device 100 can be made the same as the interval between the plurality of sub-pixels SP within one display device 100. Therefore, it is possible to implement a zero bezel with substantially no bezel area. Accordingly, only the display area AA where an image is displayed may be defined on the front surface of the display device 100, and is not limited thereto.

[0038] FIG. 2a is a schematic plan view of a state before the grinding process of a display device according to an embodiment of this specification. FIG. 2b is a schematic cross-sectional view of the display device taken along line II-II' of FIG. 2a. FIG. 2a is an enlarged plan view of the X region in FIG. 1. In FIG. 2a, only the plurality of upper pads PAD1, the plurality of signal wirings, the plurality of light-emitting elements LED, and the plurality of pixels P on the substrate 110 are shown.

[0039] Referring to FIG. 2a, the plurality of display modules include the plurality of signal wirings and the plurality of pixels P.

[0040] The plurality of pixels P can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be sub-pixels that emit different colors from each other. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel that emits red light, a green sub-pixel that emits green light, and a blue sub-pixel that emits blue light, respectively, but is not limited thereto. For example, the plurality of pixels P can further include a white sub-pixel that emits white light.

[0041] Each of the plurality of sub-pixels SP1, SP2, and SP3 can include a light-emitting region and a circuit region. The light-emitting region can be defined as a region where the light emitted from the light-emitting element LED can travel to the outside. The light-emitting region is a region that can independently emit light of one hue, and the light-emitting element LED can be disposed therein. For example, a first light-emitting element LED1 that emits red light can be disposed in the first sub-pixel SP1, a second light-emitting element LED2 that emits green light can be disposed in the second sub-pixel SP2, and a third light-emitting element LED3 that emits blue light can be disposed in the third sub-pixel SP3.

[0042] The circuit region is the remaining region excluding the light-emitting region, and a drive circuit for driving the plurality of light-emitting elements LED can be disposed therein. For example, a drive circuit including a transistor TR and a storage capacitor SC can be disposed in the circuit region.

[0043] A plurality of signal wirings are disposed on the substrate 110. The side surfaces of the plurality of signal wirings can be disposed on the same plane as the side surface of the first line L1 at which the grinding process of the substrate 110 ends.

[0044] The plurality of signal wirings are wirings that transmit various signals to the drive circuit, and can include a scan wiring SL, a data wiring DL, a high-potential voltage wiring VDDL, a reference wiring RL, a low-potential voltage wiring VSSL, etc., but is not limited thereto.

[0045] The data wiring DL is a wiring that transmits data signals to each of the sub-pixels SP1, SP2, and SP3. A plurality of data wirings DL extend in the column direction between the plurality of sub-pixels SP1, SP2, and SP3, and may include a first data wiring DL1, a second data wiring DL2, and a third data wiring DL3. The first data wiring DL1, the second data wiring DL2, and the third data wiring DL3 can transmit data voltages to their respective sub-pixels SP1, SP2, and SP3. For example, the first data wiring DL1 can transmit a data voltage to the first sub-pixel SP1, the second data wiring DL2 can transmit a data voltage to the second sub-pixel SP2, and the third data wiring DL3 can transmit a data voltage to the third sub-pixel SP3.

[0046] The plurality of high-potential power supply wirings VDDL are wirings that transmit high-potential power supply voltages to each of the plurality of sub-pixels SP1, SP2, and SP3. The plurality of high-potential power supply wirings VDDL can extend in the column direction.

[0047] The plurality of sub-pixels SP1, SP2, and SP3 can share one high-potential power supply wiring VDDL. For example, one high-potential power supply wiring VDDL is arranged between the first sub-pixel SP1 and the third sub-pixel SP3, and can supply a high-potential power supply voltage to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0048] The plurality of reference wirings RL are wirings that extend in the column direction and transmit reference voltages to each of the plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can share one reference wiring RL. For example, one reference wiring RL is arranged between the third sub-pixel SP3 and the first sub-pixel SP1, and can transmit a reference voltage to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0049] The low-potential voltage wiring VSSL is a wiring for applying a low-potential voltage to a plurality of pixels P. The low-potential voltage wiring VSSL can extend in the column direction. The sub-pixels SP1, SP2, and SP3 can share one low-potential voltage wiring VSSL. For example, one low-potential voltage wiring VSSL is disposed between the first sub-pixel SP1 and the third sub-pixel SP3, and can supply a low-potential power supply voltage to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0050] In the following, for a more detailed description of various components of the display device 100, reference is made to FIG. 2b together.

[0051] Referring to FIG. 2b together, a substrate 110 for supporting various components disposed in the display device 100 can be disposed in the display device 100.

[0052] The substrate 110 can include a first substrate 101 and a second substrate 102.

[0053] The first substrate 101 is a substrate that supports components disposed on the upper part of the display device 100, and may be an insulating substrate. For example, the first substrate 101 can be made of glass, resin, or the like. Also, the first substrate 101 may include a polymer or plastic.

[0054] The second substrate 102 is disposed under the first substrate 101. The second substrate 102 is a substrate that supports components disposed on the lower part of the display device 100, and may be an insulating substrate. For example, the second substrate 102 can be made of glass, resin, or the like. Also, the second substrate 102 may include a polymer or plastic. The second substrate 102 can be made of the same material as the first substrate 101.

[0055] A bonding layer 121 is disposed between the first substrate 101 and the second substrate 102. The bonding layer 121 can be made of a material that can be cured through various curing methods to bond the first substrate 101 and the second substrate 102 together. The bonding layer 121 may be disposed only in some regions between the first substrate 101 and the second substrate 102, or may be disposed in the entire region.

[0056] Referring to FIG. 2b, a light-shielding layer LS is disposed on the first substrate 101. The light-shielding layer LS is disposed so as to overlap with the active layer ACT of the transistor TR and can block light incident on the active layer ACT. If the active layer ACT is irradiated with light, a leakage current may occur, so the reliability of the transistor TR, which is a driving transistor, may be reduced. At this time, if a light-shielding layer LS made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof is disposed to overlap with the active layer ACT, light incident on the active layer ACT from the lower part of the display module 110 can be blocked, so the reliability of the transistor TR can be improved.

[0057] A buffer layer 111 is disposed on the first substrate 101 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 101. For example, the buffer layer 111 can be composed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the buffer layer 111 may be omitted depending on the type of the first substrate 101 or the type of the transistor TR, and is not limited thereto.

[0058] Transistors TR are disposed on the buffer layer 111 in each of the plurality of sub-pixels SP1, SP2, and SP3.

[0059] The transistor TR includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0060] An active layer ACT is disposed on a buffer layer 111. The active layer ACT can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. For example, when the active layer ACT is formed of an oxide semiconductor, the active layer ACT includes a channel region, a source region, and a drain region, and the source region and the drain region may be, but are not limited to, conductive regions.

[0061] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is a layer for insulating the gate electrode GE and the active layer ACT and can be made of an insulating material. For example, the gate insulating layer 112 can be composed of a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0062] The gate insulating layer 112 and the gate electrode GE can be formed in the same pattern, but are not limited thereto, and the gate insulating layer 112 may be formed on the front surface of the first substrate 101.

[0063] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE can be disposed so as to overlap the gate insulating layer 112, and the gate electrode GE can be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0064] An interlayer insulating layer 113 is disposed on the gate electrode GE and the buffer layer 111. The interlayer insulating layer 113 is a layer for insulating the gate electrode GE from the source electrode SE and the drain electrode DE, and can be made of an inorganic material in the same manner as the gate insulating layer 112. For example, the interlayer insulating layer 113 can be composed of a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0065] A source electrode SE and a drain electrode DE are arranged on the interlayer insulating layer 113, separated from each other. The source electrode SE and the drain electrode DE can be electrically connected to the active layer ACT through via holes formed in the interlayer insulating layer 113. The source electrode SE and the drain electrode DE can be arranged in the same layer as the gate electrode GE and formed of the same conductive material, but are not limited thereto. For example, the source electrode SE and the drain electrode DE can be composed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited to this.

[0066] The drain electrode DE is electrically connected to the low-potential power supply wiring VSSL. For example, the drain electrodes DE of the second sub-pixel SP2 and the third sub-pixel SP3 can be electrically connected to the low-potential power supply wiring VSSL on the left side of the first sub-pixel SP1.

[0067] The source electrode SE can be electrically connected to the light-shielding layer LS through via holes formed in the interlayer insulating layer 113 and the buffer layer 111. If the light-shielding layer LS is floating, the threshold voltage of the transistor TR and the like may fluctuate, affecting the driving of the display device 100. Therefore, the light-shielding layer LS can be electrically connected to the source electrode SE to apply a voltage to the light-shielding layer LS, eliminating the need to affect the driving of the transistor TR. However, it is not limited to this, and either the active layer ACT or the source electrode SE can directly contact the light-shielding layer LS. A plurality of signal wirings can be arranged on the interlayer insulating layer 113. For example, the plurality of signal wirings can include a plurality of scan wirings SL, a plurality of high-potential power supply wirings VDDL, a plurality of data wirings DL, and a plurality of reference wirings RL, but are not limited thereto. The plurality of signal wirings are arranged in the same layer on the first substrate 101 and can be made of the same conductive material as each other.

[0068] The plurality of scan wirings SL, the plurality of high-potential power supply wirings VDDL, the plurality of data wirings DL, and the plurality of reference wirings RL can be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto. However, they are not limited to this, and the plurality of signal wirings are arranged in different layers from each other on the first substrate 101 and may be made of different conductive materials. Also, the plurality of signal wirings can be made of the same material as the drain electrode DE and the source electrode SE. On the other hand, the plurality of signal wirings can be arranged in different layers from each other on the first substrate 101 and may be made of different conductive materials. At this time, each of the plurality of signal wirings can be formed of the same material in the same layer as any one of the components constituting the transistor TR.

[0069] On the other hand, the plurality of signal wirings can include at least two signal wirings arranged to overlap each other. At this time, the two signal wirings can be electrically connected through a contact hole of an insulating layer arranged between the two signal wirings. Also, the plurality of signal wirings and the upper pad PAD1 can be connected through a contact hole of an insulating layer arranged between the plurality of signal wirings and the upper pad PAD1.

[0070] A storage capacitor SC is arranged in the circuit region of each of the plurality of sub-pixels SP1, SP2, and SP3. The storage capacitor SC can store the voltage between the gate electrode GE and the source electrode SE of the transistor TR so that the light-emitting element LED continuously maintains the same state during one frame. The storage capacitor SC includes a first capacitor electrode SC1 and a second capacitor electrode SC2.

[0071] A first capacitor electrode SC1 is arranged between the first substrate 101 and the buffer layer 111 in each of the plurality of sub-pixels SP. The first capacitor electrode SC1 can be arranged closest to the first substrate 101 among the conductive components arranged on the first substrate 101. The first capacitor electrode SC1 can be integrated with the light-shielding layer LS and can be electrically connected to the source electrode SE through the light-shielding layer LS.

[0072] A buffer layer 111 and a gate insulating layer 112 are disposed on the first capacitor electrode SC1, and a second capacitor electrode SC2 is disposed on the buffer layer 111 and the gate insulating layer 112. The second capacitor electrode SC2 can be disposed so as to overlap with the first capacitor electrode SC1. The second capacitor electrode SC2 can be made of the same material as the gate electrode GE. For example, a semiconductor material can be formed on the gate insulating layer 112, and a part of the semiconductor material can be patterned to form the gate electrode GE and the second capacitor electrode SC2.

[0073] A passivation layer 114 is disposed on the transistor TR and the storage capacitor SC. The passivation layer 114 is an insulating layer for protecting the structure below the passivation layer 114. For example, the passivation layer 114 can be composed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the passivation layer 114 may be omitted according to an embodiment.

[0074] A plurality of reflective layers 117 are disposed on the passivation layer 114. The reflective layer 117 is disposed so as to overlap with the light-emitting region including the light-emitting element LED, and can reflect the light incident from the light-emitting element LED to the upper side of the light-emitting element LED, thereby increasing the light efficiency of the display device 100. However, when the display device 100 is a rear light-emitting type, the reflective layer 117 may be omitted or disposed on the upper part of the light-emitting element LED.

[0075] An adhesive layer 118 covering the reflective layer 117 is disposed on the reflective layer 117. The adhesive layer 118 is an adhesive layer 118 for adhering the light-emitting element LED on the reflective layer 117, and can also insulate the reflective layer 117 made of a metal material from the light-emitting element LED. The adhesive layer 118 can be made of a thermosetting material or a photocuring material, but is not limited thereto. In FIG. 2b, the adhesive layer 118 is shown as being disposed so as to cover only the reflective layer 117, but the arrangement position of the adhesive layer 118 is not limited thereto.

[0076] On the subsequent layer 118, a plurality of light-emitting elements LED are arranged. The plurality of light-emitting elements LED are arranged to overlap with the plurality of reflective layers 117.

[0077] Each of the plurality of light-emitting elements LED can include an active layer made of an inorganic substance. The plurality of light-emitting elements LED may be micro light-emitting diodes (Micro LED).

[0078] The plurality of light-emitting elements LED include an n-type layer 131, an active layer 132, a p-type layer 133, an n electrode 135, and a p electrode 134. The n electrode 135 or the p electrode 134 can be arranged on the upper part of the light-emitting element LED. The n electrode 135 or the p electrode 134 can be arranged to be horizontally separated.

[0079] In the following, it will be described that a light-emitting element LED having a lateral structure is used as the light-emitting element LED, but the structure of the light-emitting element LED is not limited thereto.

[0080] Specifically, the n-type layer NL of the light-emitting element LED is arranged on the adhesion layer 118. The n-type layer NL can be formed by implanting n-type impurities into gallium nitride having excellent crystallinity. On the n-type layer NL, an active layer EL is arranged. The active layer EL is a light-emitting layer that emits light in the light-emitting element LED and can be made of a nitride semiconductor, for example, indium gallium nitride. On the active layer EL, a p-type layer PL is arranged. The p-type layer PL can be formed by implanting p-type impurities into gallium nitride. However, the constituent materials of the n-type layer NL, the active layer EL, and the p-type layer PL are not limited thereto.

[0081] On the p-type layer PL of the light-emitting element LED, a p-electrode PE is disposed. Also, on the n-type layer NL of the light-emitting element LED, an n-electrode NE is disposed. The n-electrode NE is disposed at a distance from the p-electrode PE. Specifically, the light-emitting element LED may be manufactured in such a manner that the n-type layer NL, the active layer EL, and the p-type layer PL are laminated in this order, and predetermined portions of the active layer EL and the p-type layer PL are etched away to form the n-electrode NE and the p-electrode PE. At this time, the predetermined portion is a space for separating the n-electrode NE and the p-electrode PE, and the predetermined portion may be etched away so that a part of the n-type layer NL is exposed. In other words, the surface of the light-emitting element LED on which the n-electrode NE and the p-electrode PE are disposed may have different height levels that are not flattened. Therefore, the p-electrode PE is disposed on the p-type layer PL, the n-electrode NE is disposed on the n-type layer NL, and the p-electrode PE and the n-electrode NE are disposed at different height levels and separated from each other. Therefore, the n-electrode NE may be disposed so as to be adjacent to the adhesive layer 118 as compared with the p-electrode PE. And the n-electrode NE and the p-electrode PE may be made of a conductive material, for example, may be made of a transparent conductive oxide. Also, the n-electrode NE and the p-electrode PE may be made of the same material, but are not limited thereto.

[0082] On the transistor TR, a first planarization layer 115a is disposed. The first planarization layer 115a may be disposed to planarize the upper surface of the transistor TR in a region excluding the region where the light-emitting element LED is disposed.

[0083] The first planarization layer 115a may be made of an organic material, for example, may be composed of a single layer or multiple layers of polyimide or photo acryl, but is not limited thereto.

[0084] On the first planarization layer 115a and the light-emitting element LED, a second planarization layer 115b is disposed. The second planarization layer 115b is a layer that planarizes the upper surfaces of the transistor TR and the light-emitting element LED. In FIG. 2b, the first planarization layer 115a and the second planarization layer 115b are shown as being disposed, but it is not limited thereto, and one planarization layer may be formed. When one planarization layer is disposed, an excessive increase in the time required for the process can be prevented. Also, the planarization layer may be composed of two or more layers. The second planarization layer 115b may be made of the same material as the first planarization layer 115a, but is not limited thereto.

[0085] The first electrode CE1 is an electrode that electrically connects the transistor TR and the light-emitting element LED. The first electrode CE1 is connected to the n electrode NE of the light-emitting element LED through a via hole formed in the second planarization layer 115b. Also, the first electrode CE1 is connected to the source electrode SE of the transistor TR through via holes formed in the planarization layers 115a, 115b, and the passivation layer 114. However, it is not limited thereto, and depending on the type of the transistor TR, the first electrode CE1 may be connected to the drain electrode DE of the transistor TR.

[0086] The second electrode CE2 is an electrode that electrically connects the light-emitting element LED and the high-potential voltage wiring VDDL. Specifically, the second electrode CE2 is connected to the high-potential voltage wiring VDDL through via holes formed in the planarization layers 115a, 115b, and the passivation layer 114, and is connected to the p electrode PE of the light-emitting element LED through a via hole formed in the second planarization layer 115b. Therefore, the high-potential voltage wiring VDDL and the p electrode PE of the light-emitting element LED are electrically connected.

[0087] The first electrode CE1 and the second electrode CE2 are arranged to be separated from each other. On the other hand, the second planarization layer 115b and the third planarization layer 115c can insulate the first electrode CE1 and the second electrode CE2. For example, the first electrode CE1 and the second electrode CE2 may be arranged on the first planarization layer 115a and the second planarization layer 115b, and the third planarization layer 115c may be arranged on the first electrode CE1 and the second electrode CE2. At this time, the third planarization layer 115c can cover the upper surface of the second planarization layer 115b exposed between the first electrode CE1 and the second electrode CE2 to insulate the first electrode CE1 and the second electrode CE2.

[0088] A bank 119 is arranged on the second planarization layer 115b, the first electrode CE1, and the second electrode CE2. The bank 119 is an insulating layer that defines a light-emitting region. The bank 119 may be made of an organic insulating material and may be made of the same material as the planarization layers 115a and 115b. Also, the bank 119 may be made of a material that absorbs light, for example, configured to include a black substance, in order to prevent the light emitted by the light-emitting element LED from being transmitted to adjacent sub-pixels SP1, SP2, and SP3 and causing a color mixing phenomenon.

[0089] The bank 119 may extend to the edge of the display device 100. The bank 119 is arranged on an electrostatic discharge circuit and may overlap a part or all of the electrostatic discharge circuit. Therefore, the bank 119 can prevent external light from being reflected by the electrostatic discharge circuit. As a result, the edge of the display device 100 can have the same appearance as the region between a plurality of sub-pixels SP.

[0090] Also, at the edge of the display device 100, the bank 119 may overlap a part or all of a plurality of signal wirings and / or the upper pads PAD1 and / or the lower pads PAD2. Therefore, the bank 119 can prevent external light from being reflected by the upper pads PAD1 and / or a plurality of signal wirings.

[0091] The bank 119 can have an inclined surface. Specifically, the side surface of the bank 119 can be formed by an inclined surface having a certain inclination. Also, the bank 119 can be superimposed on the upper pad PAD1 or the lower pad PAD2. The bank 119 can cover the area where the upper pad PAD1 and the lower pad PAD2 are arranged.

[0092] A third planarization layer 115c is disposed on the bank 119. The third planarization layer 115c can planarize the upper portion of the first substrate 101 and protect the configuration below the third planarization layer 115c. The third planarization layer 115c can be made of an organic insulating material and can be composed of, for example, a single layer or multiple layers of polyimide or photo acryl, but is not limited thereto.

[0093] Referring to FIG. 2b, a plurality of signal wirings are arranged at the end of the first substrate 101 on the first substrate 101. The plurality of signal wirings can include a plurality of scan wirings SL, a plurality of high potential power supply wirings VDDL, a plurality of low potential power supply wirings VSSL, a plurality of data wirings DL, and a plurality of reference wirings RL. In FIG. 2b, for convenience of explanation, the second data wiring DL2 among the plurality of signal wirings is shown.

[0094] The second data wiring DL2 can include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3.

[0095] The second data wiring DL2 can have a jumping line structure through the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3. For example, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 can be a jumping wiring. The first layer DL2-1, the second layer DL2-2, the third layer DL2-3, and the upper pad PAD1 can be connected in parallel to each other through contact holes of an insulating layer disposed between the first layer DL2-1, the second layer DL2-2, the third layer DL2-3, and the upper pad PAD1. Thereby, the resistance of the second data wiring DL2 can be reduced.

[0096] The first layer DL2-1 is disposed in the same layer as the light-shielding layer LS and can be formed of the same conductive material as the light-shielding layer LS, but is not limited thereto.

[0097] A buffer layer 111 and a second layer DL2-2 are disposed on the first layer DL2-1.

[0098] The second layer DL2-2 is disposed in the same layer as the gate electrode GE and can be formed of the same conductive material as the gate electrode GE, but is not limited thereto.

[0099] The outer end of the second layer DL2-2 can be disposed on the same plane as the outer end of the first layer DL2-1. For example, the outer end of the second layer DL2-2 can overlap with the first line L1 shown in FIGS. 2A and 2B.

[0100] Also, the second layer DL2-2 can be disposed so as to overlap with the first layer DL2-1 disposed therebelow. In FIG. 2B, it is shown that the second layer DL2-2 is disposed so as to overlap with a part of the first layer DL2-1, but it is not limited thereto, and the second layer DL2-2 can be disposed so as to completely overlap with the front surface of the first layer DL2-1.

[0101] The second layer DL2-2 can be electrically connected to the first layer DL2-1 through a contact hole formed in the buffer layer 111. Therefore, the second layer DL2-2 can embody a structure connected in parallel with the first layer DL2-1 to reduce the resistance of the second data wiring DL2.

[0102] An interlayer insulating layer 113 and a third layer DL2-3 are disposed on the second layer DL2-2. The third layer DL2-3 can be disposed so as to overlap with a plurality of upper pads PAD1 disposed above.

[0103] The third layer DL2-3 is disposed in the same layer as the source electrode SE and the drain electrode DE and can be formed of the same conductive material as the source electrode SE and the drain electrode DE, but is not limited thereto.

[0104] The outer end of the third layer DL2-3 can be arranged on the same plane as the ends of the first layer DL2-1 and the second layer DL2-2. For example, the outer end of the third layer DL2-3 can overlap with the first line L1 shown in FIGS. 2A and 2B. Also, the third layer DL2-3 can be arranged to overlap with the second layer DL2-2 and the first layer DL2-1. In FIG. 2B, the inner end of the third layer DL2-3 is shown to be arranged between the end of the second layer DL2-2 and the end of the first layer DL2-1, but the position of the inner end of the third layer DL2-3 is not limited to this.

[0105] The third layer DL2-3 can be electrically connected to the second layer DL2-2 through a contact hole formed in the interlayer insulating layer 113. Therefore, since the second layer DL2-2 and the third layer DL2-3 can be embodied in a structure connected in parallel with each other, the resistance of the second data wiring DL2 can be reduced.

[0106] On the other hand, an electrostatic discharge circuit may be arranged to overlap with a plurality of upper pads PAD1 on the substrate 110. The electrostatic discharge circuit is arranged in the region between the plurality of upper pads PAD1 and the display area AA. The electrostatic discharge circuit can be electrically connected to a plurality of signal wirings through the side wiring 140. For example, the electrostatic discharge circuit is electrically connected to the second data wiring DL2, and when static electricity flows in through the second data wiring DL2, it is turned on and the static electricity is discharged through the ground wiring to block the static electricity. Therefore, the electrostatic discharge circuit can block or discharge the flow of overcurrent due to static electricity to prevent damage to the display device 100. That is, the electrostatic discharge circuit can be selectively connected to the ground wiring and may be electrically connected to a plurality of signal wirings, for example, the second data wiring DL2, but is not limited thereto.

[0107] Also, the electrostatic discharge circuit is arranged to overlap with the upper pad PAD1 and / or the lower pad PAD2, and can reduce or eliminate the bezel area of the display device 100.

[0108] A passivation layer 114 and a plurality of upper pads PAD1 are arranged on the third layer DL2-3.

[0109] The sides of the plurality of upper pads PAD1 can be arranged on the same plane as the sides of the plurality of signal wirings including the second data wiring DL2. For example, the outer ends of the plurality of upper pads PAD1 can overlap with the first line L1 shown in FIGS. 2A and 2B.

[0110] On the other hand, in FIG. 2B, although the plurality of upper pads PAD1 are shown as only overlapping with the second data wiring DL2 which is a signal wiring, each of the plurality of upper pads PAD1 can be arranged to overlap at least one of the plurality of signal wirings and the plurality of transistors TR.

[0111] The plurality of upper pads PAD1 can overlap with the second data wiring DL2 or the plurality of transistors TR. Thus, the region between the plurality of light emitting elements LED and the edge of the display device 100 can be reduced. For example, the distance between the plurality of light emitting elements LED and the edge of the display device 100 can be half of the interval between adjacent plurality of light emitting elements LED. Thus, the size of the bezel of the display device 100 can be reduced or the bezel can be removed.

[0112] The plurality of upper pads PAD1 are electrically connected to the side wiring 140 described later and the plurality of signal wirings in the display area AA, and can transmit signals from the plurality of flexible films and printed circuit boards arranged on the back surface of the substrate 110 to the plurality of sub-pixels SP.

[0113] A plurality of lower pads PAD2 are arranged on the lower surface of the second substrate 102.

[0114] The plurality of lower pads PAD2 can transmit signals from the driving unit arranged on the back side of the second substrate 102 to the plurality of side wirings 140, the first substrate 101, the plurality of upper pads PAD1, and the plurality of signal wirings. The plurality of lower pads PAD2 are arranged at the ends of the second substrate 102 in the non-display area NA and can be electrically connected to the side wiring 140 covering the side surface of the second substrate 102.

[0115] The plurality of lower pads PAD2 can be arranged at positions overlapping the plurality of upper pads PAD1, and the plurality of upper pads PAD1 and the plurality of lower pads PAD2 overlapping each other can be electrically connected through the side wiring 140. On the other hand, although not shown in FIG. 2b, a driving unit including a plurality of link wirings, a plurality of flexible films, and a printed circuit board can be arranged under the second substrate 102.

[0116] The plurality of link wirings can transmit various signals and voltages from the driving unit to the plurality of signal wirings of the display device 100. For example, the plurality of link wirings can directly connect the driving unit and the side wiring 140, or electrically connect the driving unit and the side wiring 140 through other components such as the plurality of upper pads PAD1 and the plurality of lower pads PAD2. The plurality of link wirings can include, but are not limited to, a plurality of gate link wirings, a plurality of data link wirings, a plurality of high-potential voltage link wirings, a plurality of low-potential voltage link wirings, and a reference voltage link wiring.

[0117] The plurality of flexible films are components in which various components such as a gate driver IC and a data driver IC are arranged on a ductile base film and supply signals to the plurality of sub-pixels SP.

[0118] The printed circuit board is a component that is electrically connected to the plurality of flexible films and supplies signals to the driving IC. The printed circuit board can have various components arranged thereon for supplying various signals such as driving signals and data signals to the driving IC. For example, the plurality of lower pads PAD2 can be electrically connected to the plurality of flexible films or the printed circuit board through the plurality of link wirings, and the plurality of flexible films can supply various signals to the plurality of side wirings 140, the plurality of upper pads PAD1, the plurality of signal wirings, and the plurality of sub-pixels SP through the plurality of lower pads PAD2 and the plurality of link wirings. Therefore, signals from the driving unit can be transmitted to the signal wirings and the plurality of sub-pixels SP on the front surface of the first substrate 101 through the plurality of lower pads PAD2 of the second substrate 102, the side wiring 140, and the plurality of upper pads PAD1 of the first substrate 101.

[0119] Signals from the driving unit disposed below the substrate 110 can be transmitted to a plurality of sub-pixels SP disposed above the substrate 110 through the side wiring 140. The side wiring 140 is connected to the driving unit through the lower pad PAD2, and the side wiring 140 may be directly connected to a plurality of signal wirings or may be connected to the signal line through the upper pad PAD1.

[0120] Referring to FIG. 2b, after the first substrate 101 and the second substrate 102 are bonded together through the bonding layer 121, the first substrate 101 and the second substrate 102 can be ground up to the first line L1.

[0121] The grinder GR disposed outside the first substrate 101 and the second substrate 102 can grind the side surfaces of the first substrate 101 and the second substrate 102 while rotating around the rotation axis. The grinder GR can move to the first line L1 that overlaps the side surfaces of the plurality of signal wirings and the plurality of pads PAD including the upper pad PAD1 and the lower pad PAD2 to grind the side surfaces of the first substrate 101 and the second substrate 102. Therefore, a ground surface formed through the grinder GR can be formed on the side surfaces of the first substrate 101 and the second substrate 102. However, it is not limited thereto, and the side surfaces of the first substrate 101 and the second substrate 102 disposed outside the first line L1 can be removed through various methods such as cutting, sanding, filing, etc.

[0122] In the drawings, for convenience of explanation, a plurality of pads PAD remaining on the substrate 110 after grinding are shown to have a large area. However, substantially, in order to reduce the bezel area and eliminate the heterogeneity between adjacent display devices 100 when implementing the tiling display, the area of the plurality of pads PAD remaining on the substrate 110 may be very small.

[0123] For example, when implementing a tiling display with a large screen by connecting a plurality of display devices 100, the distance between the sub-pixel SP and the edge of the display device 100 may be half of the interval between adjacent sub-pixels SP. Therefore, when implementing a tiling display with a large screen by connecting a plurality of display devices 100, it is possible to prevent the interval difference between a plurality of sub-pixels SP from being visually recognized at the boundary of the display device 100 and reduce the heterogeneity between the display devices 100.

[0124] The polished surfaces of the first substrate 101 and the second substrate 102 formed by the grinder GR may be linear depending on the shape of the grinder GR. In the following, with reference to FIGS. 3a and 3b, the side surfaces of the first substrate 101 and the second substrate 102 will be described later.

[0125] FIG. 3a is a plan view of sub-pixels of a display device according to an embodiment of the present specification. FIG. 3b is a schematic cross-sectional view of the display device taken along line III-III' of FIG. 3a. FIGS. 3a and 3b are schematic cross-sectional views of a state in which the grinding process is completed. In FIG. 3a, only a plurality of upper pads PAD1, a plurality of signal wirings, a plurality of light-emitting elements LED, a plurality of side wirings 140, and a plurality of pixels P on the substrate 110 are shown. The display device 100 in a state where the grinding process is completed has a plurality of side wirings 140 and side insulating layers 150 added as compared with before the grinding process, and the configuration excluding the substrate 110 is substantially the same, so duplicate explanations are omitted.

[0126] Referring to FIGS. 3a and 3b, the side surfaces of the first substrate 101 and the second substrate 102 of the display device 100 are arranged in a linear shape. The side surfaces of the first substrate 101 and the second substrate 102 are arranged in the same plane as the side surfaces of the components of the display device 100 arranged above and below the substrate 110. For example, the side surface of the first substrate 101 may be arranged in the same plane as the side surfaces of each of the plurality of signal wirings and the plurality of upper pads PAD1, and may be arranged in the same plane as the side surfaces of the plurality of insulating layers arranged on the first substrate 101. The side surface of the second substrate 102 may also be arranged in the same plane as the side surfaces of each of the plurality of lower pads PAD2 arranged under the second substrate 102.

[0127] Next, a plurality of side wirings 140 are arranged on the side surfaces of the first substrate 101 and the second substrate 102. The plurality of side wirings 140 can electrically connect the plurality of upper pads PAD1 formed on the upper surface of the first substrate 101 and the plurality of lower pads PAD2 formed on the back surface of the second substrate 102, and can connect the plurality of signal wirings formed on the upper surface of the first substrate 101 and the plurality of link wirings formed on the back surface of the second substrate 102.

[0128] On the other hand, the plurality of signal wirings and the plurality of link wirings may be connected through the plurality of side wirings 140 without the plurality of lower pads PAD2 by a link line. The plurality of side wirings 140 may be arranged so as to surround the side surface of the display device 100. At this time, each of the plurality of side wirings 140 may be arranged without overlapping and spaced apart from each other.

[0129] Each of the plurality of side wirings 140 may be in contact with the side surfaces of the plurality of upper pads PAD1 at the end of the first substrate 101, the side surfaces of the plurality of signal wirings, the side surface of the first substrate 101, the side surface of the second substrate 102, and the side surfaces of the plurality of lower pads PAD2 arranged at the end of the second substrate 102. At this time, when the side surface of the substrate 110 is arranged in a direction perpendicular to the upper surface of the substrate 110, the plurality of side wirings 140 may also be arranged along a direction perpendicular to the upper surface of the substrate 110.

[0130] The plurality of side wirings 140 may be formed by a pad printing method using a conductive ink, for example, a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), etc.

[0131] A side insulating layer 150 covering the plurality of side wirings 140 is arranged. The side insulating layer 150 may be formed so as to cover the side wirings 140 on the upper surface of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 102, and the back surface of the second substrate 102. The side insulating layer 150 can protect the plurality of side wirings 140.

[0132] On the one hand, when the plurality of side wirings 140 are made of a metallic substance, there may arise a problem that external light is reflected by the plurality of side wirings 140, or light emitted by the light-emitting element LED is reflected by the plurality of side wirings 140 and visually recognized by the user. Therefore, the side insulating layer 150 is configured to contain a black substance, and can suppress external light reflection. For example, the side insulating layer 150 can be formed by a pad printing method using an insulating substance containing a black substance, for example, black ink.

[0133] On the other hand, although not shown in FIGS. 3A and 3B, a seal member and an optical film covering the side insulating layer 150 may be further disposed. The seal member is disposed so as to surround the side surface of the display device 100, and can protect the display device 100 from external impacts, moisture, oxygen, etc. For example, the seal member can be made of an insulating substance such as polyimide (PI), polyurethane (Poly Urethane), epoxy (Epoxy), acrylic (Acryl) series, but is not limited thereto.

[0134] An optical film may be disposed on the seal member, the side insulating layer 150, and the protective layer 116. The optical film may be a functional film that realizes a higher-quality image while protecting the display device 100. For example, the optical film can include, but is not limited to, an anti-glare film, an anti-reflecting film, a low-reflecting film, an oled transmittance controllable film, or a polarizing plate.

[0135] A plurality of pads for transmitting various signals to a plurality of sub-pixels are arranged on the upper and lower portions of the substrate in the non-display area of the display device. The plurality of pads are connected between the side wiring and the plurality of signal wirings in the display area, and signals can be transmitted from the plurality of flexible films and printed circuit boards arranged under the substrate to the plurality of sub-pixels. At this time, the plurality of pads are arranged in the outer contour portion of the display device, that is, the bezel area. In addition, since the plurality of pads are arranged outside the plurality of signal wirings and the plurality of transistors, a separate area for arranging the plurality of pads is required, which restricts the reduction of the bezel of the display device.

[0136] On the other hand, a tiling display is implemented by arranging a plurality of panels in a tile form with the same interval between the outermost light-emitting element LEDs of one panel and the outermost light-emitting element LEDs of another adjacent panel as the interval between the light-emitting element LEDs within one panel. Therefore, when the bezel area of the display device is larger than the interval from the light-emitting elements within one display panel due to the limit of reducing the size of the plurality of pads, the boundary between the display modules can be visually recognized by the user, which may give a sense of discontinuity in the displayed image. In particular, restrictions may occur in implementing large panels through tiling.

[0137] Therefore, in the display device 100 according to an embodiment of the present specification, the plurality of pads PAD are arranged to overlap at least one of the plurality of signal wirings and the plurality of transistors TR, so that a separate area for arranging the pads PAD can be deleted from the design, and the bezel area of the display device 100 can be reduced.

[0138] In addition, in the display device 100 according to an embodiment of the present specification, side wirings 140 are formed on the sides of the first upper pads PAD1 and the plurality of lower pads PAD2, so that the side surface of the substrate 110 can be ground into a straight line portion. That is, since the side wirings 140 can be formed without grinding the side surface of the substrate 110 into a slanted line to more smoothly connect the gate wiring GL and the data wiring DL on the upper surface of the first substrate 101 and the plurality of link wirings on the back surface of the second substrate 102, the manufacturing process can be more simplified.

[0139] In addition, in the display device 100 according to an embodiment of the present specification, it is possible to reduce the problems that occur when the side surface of the substrate 110 is ground diagonally without grinding the side surface of the substrate 110 diagonally.

[0140] First, it is possible to prevent defects that may occur in the side wiring and a plurality of pads during grinding. When performing a grinding process on the corners of the first substrate and the second substrate using a grinder, a problem occurred in that a part of the side wiring and a plurality of pads arranged above and below the substrate were removed together with the substrate, resulting in disconnection of the side wiring and a plurality of pads. In addition, a problem occurred in that cracks occurred from the ground side surface and propagated. Therefore, in the display device 100 according to an embodiment of the present specification, it is possible to prevent defects that may occur in the side wiring 140 and a plurality of pads PAD without forming a grinding process on the side surface of the substrate 110.

[0141] In addition, the side insulating layer 150 covering the plurality of side wirings 140 can be coated from the lower direction of the substrate 110 and filled in the directions of the side surface and the upper surface 110 of the substrate 110. Therefore, when the side surface of the substrate is ground diagonally, the side insulating layer may not be uniformly formed on the side surface of the substrate due to the inclined surface formed on the side surface of the substrate. Therefore, the side insulating layer may not be able to cover a part of the upper surface and the entire side surface of the substrate and may be unfilled at some points. Therefore, the side wiring is exposed at the point where the side insulating layer is unfilled, and problems may occur in that external light is reflected by the plurality of side wirings at that point, or light emitted by the light-emitting element is reflected by the plurality of side wirings and visually recognized by the user. Therefore, in the display device 100 according to an embodiment of the present specification, it is possible to prevent external light reflection of the side wiring 140 at the point where the side insulating layer 150 is uniformly arranged on the side surface of the substrate 110 without forming an inclined surface on the side surface of the substrate 110 in the grinding process and the side insulating layer 150 is unfilled.

[0142] FIG. 4a is a schematic cross-sectional view of a display device before a grinding process of a display device according to another embodiment of the present specification. FIG. 4b is a schematic cross-sectional view of a display device according to another embodiment of the present specification. Since the display device 400 according to another embodiment of the present specification has substantially the same configuration as the display device 100 according to an embodiment of the present specification, except for a substrate 410, a plurality of side wirings 440, and a plurality of pads PAD, duplicate descriptions are omitted.

[0143] Referring to FIG. 4a, the sides of the first substrate 101 and the second substrate 402 can be ground. The grinder GR can move to the first line L1 and grind the sides of the first substrate 101 and the second substrate 402. Therefore, a ground surface formed through the grinder GR can be formed on the sides of the first substrate 101 and the second substrate 402. At this time, the ground surface of the first substrate 101 formed by the grinder GR can be formed in a straight line depending on the shape of the grinder GR. On the other hand, the side surface of the second substrate 402 can be configured with a surface different from the side surface of the first substrate 101.

[0144] In the following, the sides of the first substrate 101 and the second substrate 402 will be described with reference to FIG. 4b.

[0145] Referring to FIG. 4b, the substrate 410 of the display device 400 includes a side surface formed as an inclined surface inclined with respect to the upper surface of the substrate 410. That is, a part of the side surface of the substrate 410 may be an inclined surface inclined with respect to the upper surface of the substrate 410.

[0146] First, the side surface of the first substrate 101 of the display device 400 is arranged in the same plane as the side surfaces of the components of the display device 400 arranged on the upper part of the substrate 410. For example, the side surface of the first substrate 101 can be arranged on the same plane as the side surfaces of the plurality of signal wirings and the plurality of upper pads PAD1, respectively, and can be arranged in the same plane as the side surfaces of the plurality of insulating layers arranged on the first substrate 101. At this time, the side surface of the first substrate 101 may be a surface perpendicular to the upper surface of the substrate 110.

[0147] The side surface of the second substrate 402 can include a side surface in a direction different from the side surface of the component of the display device 400 disposed on the upper portion of the substrate 410. For example, a part of the side surfaces of the second substrate 402 can include an inclined surface with respect to the upper surface of the substrate 110.

[0148] On the other hand, the side surfaces of the plurality of link wirings and the plurality of lower pads PAD2 disposed at the lower portion of the second substrate 402 can include inclined surfaces formed at the same angle as the side surface of the second substrate 402. Therefore, as shown in FIG. 4b, the ends of the plurality of link wirings and the plurality of lower pads PAD2 disposed at the lower portion of the second substrate 402 can be disposed inside the ends of the substrate 410.

[0149] Next, a plurality of side wirings 440 are disposed on the side surfaces of the first substrate 101 and the second substrate 402. The plurality of side wirings 440 can connect a plurality of upper pads PAD1 having linear side surfaces and a plurality of lower pads PAD2 including inclined side surfaces. At this time, the plurality of side wirings 440 can contact the side surface of the first substrate 101 and the inclined side surface of the second substrate 402. Therefore, when the plurality of lower pads PAD2 are disposed inside the side surface of the second substrate 402, the plurality of side wirings 440 can also contact the lower surface of the substrate 410.

[0150] A side insulating layer 450 covering the plurality of side wirings 440 is disposed. The side insulating layer 450 can be formed to cover the upper portion of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 402, and the lower portion of the second substrate 402 so as to cover the side wirings 440. The side insulating layer 450 can protect the plurality of side wirings 440.

[0151] In the display device 400 according to another embodiment of the present specification, the bezel region of the display device 400 can be reduced by disposing the plurality of pads PAD to overlap at least one of the plurality of signal wirings and the plurality of transistors TR.

[0152] In addition, in the display device 400 according to another embodiment of the present specification, the side surface of the substrate 410 can be arranged as an inclined surface to reduce the contact resistance of the plurality of pads PAD. When the side surface of the substrate 410 is arranged as a slanted line, the contact area between the plurality of pads PAD and the plurality of side wirings 440 can increase. Therefore, the resistance of the plurality of signal wirings and the plurality of pads PAD can be reduced.

[0153] FIG. 5 is a schematic cross-sectional view of a display device according to still another embodiment of the present specification. Since the display device 500 according to still another embodiment of the present specification has substantially the same configuration as the display device 100 according to one embodiment of the present specification, except for a plurality of signal wirings and a plurality of pads PAD, duplicate descriptions will be omitted.

[0154] Referring to FIG. 5, a plurality of signal wirings are arranged at the end of the first substrate 101 on the first substrate 101. In FIG. 5, for convenience of explanation, the second data wiring DL2 among the plurality of signal wirings is shown.

[0155] The second data wiring DL2 can include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3. The first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 are the same as the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 described with reference to FIGS. 1 to 3b.

[0156] On the third layer DL2-3, a passivation layer 114 and a first planarization layer 115a are arranged.

[0157] On the other hand, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 that constitute the second data wiring DL2 is electrically connected to the plurality of lower pads PAD2 through the side wiring 140, and various signals can be supplied to the plurality of sub-pixels SP. Therefore, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 that constitute the second data wiring DL2 can be referred to as an upper pad, and the plurality of upper pads may be a part of the plurality of signal wirings.

[0158] On the one hand, in FIG. 5, it is shown that the side surface of the substrate 110 is arranged in the same plane as the side surfaces of the components of the display device 500 arranged above the substrate 110. However, a part of the side surface of the substrate 110 may be an inclined surface inclined with respect to the upper surface of the substrate 110. For example, the side surface of the substrate 110 includes an inclined surface like the side surface of the substrate 410 in FIG. 4B, and a plurality of side wirings 140 can contact the side surfaces of the plurality of signal wirings.

[0159] In the display device 500 according to another embodiment of the present specification, since the plurality of side wirings 140 can be formed without grinding the side surface of the substrate 110 obliquely, the manufacturing process can be further simplified.

[0160] Also, in the display device 500 according to another embodiment of the present specification, without grinding the side surface of the substrate 110 obliquely, it is possible to prevent the problem that a part of the side wiring 140 and the plurality of pads PAD are removed and the side wiring 140 and the plurality of pads PAD are disconnected during grinding.

[0161] Also, in the display device 500 according to another embodiment of the present specification, without forming an inclined surface on the side surface of the substrate 110 in the grinding process, the side insulating layer 150 can be uniformly arranged on the side surface of the substrate 110, and external light reflection of the side wiring 140 can be prevented.

[0162] Also, in the display device 500 according to another embodiment of the present specification, a part of the plurality of signal wirings can be utilized as pads without separately arranging pads at the end of the display device 500. In the display device 500 according to another embodiment of the present specification, the plurality of side wirings 140 can contact the side surfaces of the plurality of signal wirings. Therefore, the signal applied from the driving unit can be transmitted to the plurality of pixels SP without arranging a conductive substance for forming the pads. Therefore, in the display device 500 according to another embodiment of the present specification, without performing a separate process for forming a conductive substance for forming the pads, the manufacturing process of the display device is simplified and the cost can also be reduced.

[0163] The display device according to the embodiment of this specification can be described as follows.

[0164] The display device according to an embodiment of this specification includes a substrate on which a plurality of light-emitting elements are arranged, transistors arranged on the substrate, a plurality of signal wirings arranged on the substrate, a plurality of link wirings arranged under the substrate, and a plurality of upper pads arranged on the substrate and connected to the plurality of signal wirings. The plurality of upper pads are arranged so as to overlap at least one of the plurality of signal wirings and the plurality of transistors.

[0165] According to another feature of this specification, it further includes a plurality of side wirings connecting the plurality of signal wirings and the plurality of link wirings, and the plurality of upper pads and the plurality of signal wirings may be in contact with the plurality of side wirings.

[0166] According to still another feature of this specification, the sides of the plurality of upper pads may be arranged on the same plane as the sides of the plurality of signal wirings.

[0167] According to still another feature of this specification, the plurality of side wirings may be in contact with the side surface and the lower surface of the substrate.

[0168] According to still another feature of this specification, it further includes a plurality of lower pads arranged on the lower surface of the substrate and connected to the plurality of link wirings, and the plurality of lower pads may be arranged at positions overlapping the plurality of upper pads.

[0169] According to still another feature of this specification, a part of the side surface of the substrate is an inclined surface inclined with respect to the upper surface of the substrate, and the plurality of side wirings may cover a part of the side surface and the lower surface of the substrate.

[0170] According to still another feature of this specification, the substrate includes a first substrate and a second substrate arranged under the first substrate, and a part of the side surface of the second substrate may be an inclined surface inclined with respect to the upper surface of the substrate.

[0171] According to another feature of the present specification, it further includes a plurality of lower pads disposed on the lower surface of the substrate and connected to a plurality of link wirings, and the ends of the plurality of lower pads may be located inside the ends of the substrate.

[0172] According to another feature of the present specification, it further includes a plurality of insulating layers disposed on the substrate and on the upper or lower portions of a plurality of signal wirings and a plurality of upper pads, and the sides of the plurality of insulating layers may be disposed on the same plane as the sides of the substrate.

[0173] According to another feature of the present specification, the sides of the plurality of insulating layers and the sides of the plurality of upper pads may be disposed on the same plane.

[0174] According to another feature of the present specification, the plurality of upper pads may be part of the plurality of signal wirings.

[0175] According to another feature of the present specification, it can further include an electrostatic discharge circuit disposed on the substrate so as to overlap with the plurality of upper pads.

[0176] As described above, with reference to the accompanying drawings, the embodiments of the present specification have been described in more detail. However, the present specification is not necessarily limited to such embodiments. Therefore, the embodiments disclosed in the present specification are not for limiting the technical idea of the present specification. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive. The present specification should be interpreted by all technical ideas within the scope of the following claims and their equivalents.

Claims

1. substrate; a plurality of light emitting devices disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal wirings disposed on the substrate; a plurality of link wires disposed beneath the substrate; A plurality of upper pads disposed on the substrate; and A plurality of side wirings are arranged on the side surfaces of the substrate, each of the plurality of upper pads is arranged to overlap at least one of the plurality of signal wirings or the plurality of transistors; Each of the plurality of side wirings connects a corresponding link wiring among the plurality of link wirings and a corresponding signal wiring among the plurality of signal wirings, Each of the plurality of light emitting elements comprises: n-type layer; an active layer on the n-type layer; a p-type layer on the active layer; an n-electrode on the n-type layer; and a p-electrode disposed on the p-type layer and spaced apart from the p-type layer; The p-electrode and the n-electrode have different height levels, The display device further includes a first planarization layer surrounding at least a portion of the plurality of light-emitting elements.

2. The display device according to claim 1 , wherein a side surface of the substrate is disposed on the same plane as side surfaces of the plurality of signal wirings.

3. The display device according to claim 1 , wherein the plurality of side wirings are in contact with a side surface of the substrate and in contact with a bottom surface of the substrate.

4. a plurality of lower pads disposed on a lower surface of the substrate and overlapping corresponding ones of the plurality of upper pads; The display device according to claim 1 , wherein the side wirings connect the lower pads to the upper pads and the signal wirings.

5. Further comprising a side insulating layer covering the plurality of side wirings, The display device of claim 1 , wherein the side insulating layer comprises a black material.

6. a part of the side surface of the substrate is an inclined surface connected to a lower surface of the substrate, the inclined surface being inclined toward a display area side with respect to another part of the side surface of the substrate; The display device according to claim 1 , wherein the plurality of side wirings cover the inclined surface and cover a part of the lower surface of the substrate.

7. The substrate includes a first substrate and a second substrate disposed below the first substrate, The display device according to claim 6 , wherein a part of the side surface of the second substrate is the inclined surface.

8. The display device according to claim 1 , wherein each of the plurality of side wirings is in contact with a corresponding one of the plurality of upper pads and a corresponding one of the plurality of signal wirings.

9. Each of the plurality of upper pads is electrically connected to a corresponding one of the plurality of signal wirings; or The display device according to claim 1 , wherein side surfaces of the plurality of upper pads are disposed on the same plane as side surfaces of the plurality of signal wirings.

10. a plurality of lower pads disposed on a lower surface of the substrate and connected to corresponding ones of the plurality of link wires; Each of the plurality of lower pads is disposed so as to overlap a corresponding one of the plurality of upper pads; or The display device according to claim 1 , wherein ends of the plurality of lower pads are disposed inwardly of an end of the substrate.

11. further comprising a plurality of insulating layers disposed on the substrate; the insulating layers are disposed above or below the upper pads and the signal wirings; The display device according to claim 1 , wherein the side surfaces of the insulating layers are disposed flush with the side surfaces of the substrate and the side surfaces of the upper pads.

12. The display device of claim 1 , further comprising a first electrode connected to the n-electrode and a second electrode connected to the p-electrode.

13. A second planarization layer on the first planarization layer and surrounding other portions of the plurality of light-emitting elements; and further comprising a third planarization layer on the second planarization layer; the first electrode and the second electrode are spaced apart from each other, and the third planarization layer is disposed between the first electrode and the second electrode; The display device according to claim 12 , wherein the second planarization layer and the third planarization layer are selectively in contact with each other in a region between the first electrode and the second electrode.

14. a bank disposed on the first electrode and the second electrode; the bank overlaps a portion of at least one of the plurality of upper pads; 14. The display device according to claim 12 or 13, wherein the banks optionally contain a light blocking material and / or a black material.

15. Further comprising a reflective layer corresponding to each of the plurality of light emitting elements, The display device according to claim 1 , wherein the plurality of light-emitting elements overlap the reflective layer.

16. The substrate further includes an electrostatic discharge circuit that is disposed on the substrate and selectively connects the signal wirings and a ground wiring; the electrostatic discharge circuit is disposed between the plurality of upper pads and a display area in which a plurality of sub-pixels are disposed; or The display device of claim 1 , wherein the electrostatic discharge circuit overlaps the plurality of upper pads.

17. substrate; a plurality of light emitting devices disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal wirings disposed on the substrate; a plurality of link wires disposed beneath the substrate; A plurality of upper pads disposed on the substrate; and A plurality of side wirings are arranged on the side surfaces of the substrate, each of the plurality of upper pads is arranged to overlap at least one of the plurality of signal wirings or the plurality of transistors; Each of the plurality of side wirings connects a corresponding link wiring among the plurality of link wirings and a corresponding signal wiring among the plurality of signal wirings, Each of the plurality of signal lines includes at least two signal lines connected in parallel to overlap each other, further comprising an insulating layer disposed between the at least two signal wirings; The insulating layer includes a contact hole connecting the at least two signal lines.

18. substrate; a plurality of light emitting devices disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal wirings disposed on the substrate; a plurality of link wires disposed beneath the substrate; A plurality of upper pads disposed on the substrate; and A plurality of side wirings are arranged on the side surfaces of the substrate, each of the plurality of upper pads is arranged to overlap at least one of the plurality of signal wirings or the plurality of transistors; Each of the plurality of side wirings connects a corresponding link wiring among the plurality of link wirings and a corresponding signal wiring among the plurality of signal wirings, the signal wirings are connected in parallel to corresponding upper pads among the upper pads; further comprising an insulating layer disposed between the plurality of upper pads and the plurality of signal wirings; The insulating layer includes contact holes electrically connecting the signal lines and the upper pads.

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