Imaging device and electronic device

Abstract

To provide an imaging device that facilitates pooling processing.SOLUTION: An imaging device includes a pixel region, the pixel region includes a plurality of pooling modules and an output circuit, the pooling module includes a pooling circuit and a comparison module, the pooling circuit includes a plurality of pixels and an arithmetic circuit, and the comparison module includes a plurality of comparison circuits and a determination circuit. A pixel acquires a first signal by photoelectric conversion, and multiplies the first signal by an arbitrary magnification to generate a second signal. The pooling circuit adds a plurality of second signals by the arithmetic circuit to generate a third signal. The comparison module compares the plurality of third signals, outputs the largest third signal to the determination circuit. The determination circuit determines and binarizes the largest third signal to generate a fourth signal, so that the pooling module performs pooling processing according to the number of pixels and outputs data subjected to the pooling processing.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. In particular, one aspect of the present invention relates to Semiconductor device, display device, light-emitting device, power storage device, memory device, driving method thereof, or the like The present invention relates to a method for producing the same.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. An example of such a device is a semiconductor element such as a transistor or a diode. In another example, a circuit having a semiconductor element is a semiconductor device. As another example, a device including a circuit having a semiconductor element is a semiconductor device. do. [Background technology]

[0004] IoT (Internet of things), AI (Artificial I) With the development of information technology such as AI, the amount of data handled is increasing. In order for electronic devices to utilize information technologies such as IoT and AI, large amounts of data are required. There is a demand for decentralized management of data.

[0005] Image processing system for in-vehicle electronic device and image processing system for monitoring moving object In the past, the use of AI has been attracting attention for its potential to improve image recognition processing speed. Patent Document 1 discloses a technique for adding a calculation function to a device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2016-123087 A Summary of the Invention [Problem to be solved by the invention]

[0007] With the advancement of technology, imaging devices equipped with solid-state imaging elements such as CMOS image sensors have In the next generation, imaging devices will be equipped with even more advanced functions. There is a demand for it to be equipped with intelligent functions.

[0008] To recognize objects from image data, advanced image processing is required. In the theory, various analytical processes such as filtering and comparison processing are used to analyze images. The amount of calculation required for image analysis increases according to the number of pixels to be processed. For example, in an in-vehicle image processing system, the processing time increases according to the In addition, the increase in the amount of calculations in image processing systems can cause problems that affect safety. This raises the issue of increased power consumption.

[0009] In view of the above problems, an object of one aspect of the present invention is to provide an imaging device having a novel configuration. Alternatively, one aspect of the present invention is a neural network having a pooling function. Another object of the present invention is to provide an imaging device that can reduce the amount of calculation. One of the objectives is to provide an imaging device with a novel configuration that can shorten the processing time. Another embodiment of the present invention provides an imaging device with a novel structure that can reduce power consumption. One of our goals is to provide

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc.

[0011] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. However, this does not preclude the existence of other problems. The other problems are described below. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by reading the specification or can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention is to achieve at least one of the above-listed and / or other objects. This is to solve one problem. [Means for solving the problem]

[0012] One embodiment of the present invention is an imaging device having a pixel region and a first circuit, The pooling module includes a pooling module and an output circuit. The pooling module includes a plurality of pools. The pooling circuit includes a plurality of pixels and a calculation circuit. The comparison module includes a plurality of comparison circuits and a judgment circuit, and the pixel includes a photoelectric conversion The pixel has a function of multiplying the first signal by an arbitrary magnification to obtain a first signal. The pooling circuit has a function of generating a second signal, and the pooling circuit calculates a plurality of second signals by a calculation circuit. and a comparison module for comparing the third signals to generate a third signal by adding the third signals. and a function of selecting the largest third signal and outputting it to a determination circuit, The third signal is determined to be the largest, and a fourth signal is generated by binarizing the third signal. The fourth signal is output to the output circuit. The pooling module controls the timing of the fourth signal output to the output circuit. Pooling is performed according to the prime number, and the pooling module is generated by the pooling process. and an imaging device that outputs a fourth signal obtained by the above-mentioned method.

[0013] In the above configuration, the imaging device further includes a second circuit, a third circuit, a first wiring, and a second wiring and a third wiring, the pixel has a first output terminal, and the arithmetic circuit has A second circuit includes a first transistor, a second transistor, and a third transistor. The circuit is electrically connected to a plurality of pixels extending in a row direction via a first wiring, and a third circuit is electrically connected to a plurality of pixels extending in the column direction via a second wiring, and a third wiring , one of the source or drain of the first transistor and the source or drain of the second transistor One of the drains is electrically connected to one of the source or drain of the third transistor. The gate of the first transistor is connected to the other of the source and drain of the first transistor. , a gate of the second transistor, a gate of the third transistor, and a pooling circuit are provided. The third circuit is electrically connected to the first output terminal of the pixel to be selected, and the third circuit is connected to the second wiring. The second circuit has a function of outputting a desired magnification to the pixel via the first wiring. The first transistor has a function of: The second transistor has the same channel length as the first transistor, and the second transistor has the same channel width as the first transistor. By having a width, the third signal is output by adding a plurality of second signals. The transistor has a channel width of the first transistor that is equal to the number of pixels that the pooling circuit has. The fifth signal is the third signal divided by the number of pixels. An imaging device having a function of outputting the above is preferable.

[0014] In the above configuration, the comparison module includes a first comparison circuit, a second comparison circuit, and a current a second comparison circuit including a fourth transistor to a ninth transistor, a first input terminal, a second input terminal, a second output terminal, and a fourth wiring; The second output terminal of the comparator is connected to the first input terminal of the second comparator via a current mirror circuit. The first input terminal is electrically connected to the source or drain of the fifth transistor. one of the source and drain of the seventh transistor, and the gate of the fourth transistor The gate of the fifth transistor is electrically connected to the gate of the sixth transistor. The second input terminal is connected to one of the source or drain of the eighth transistor and the sixth transistor. One of the source or drain of the transistor, the gate of the seventh transistor, and the eighth transistor a gate of the ninth transistor electrically connected to the gate of the second output transistor; The terminal is one of the source or drain of the fourth transistor and the source of the ninth transistor. The fourth to ninth transistors are electrically connected to either the drain or the gate of the first transistor. The first transistor has a channel length of the same magnitude, and the second transistor has a channel width of the fifth transistor. The channel width of the sixth transistor is preferably the same as that of the sixth transistor. The width is preferably twice the channel width of the fifth transistor, and the fourth to the fifth transistors The sixth transistor forms a first current mirror circuit, and the ninth transistor The channel width of the eighth transistor is preferably the same as the channel width of the seventh transistor. The channel width of the seventh transistor is preferably twice as wide as that of the eighth transistor. The first to ninth transistors form a second current mirror circuit, and the second comparison circuit A sixth signal is applied to a first input terminal of the first comparator circuit, and a sixth signal is applied to a second input terminal of the first comparator circuit. , a seventh signal is given, and the second output terminal of the first comparison circuit outputs the sixth signal or the seventh signal. the eighth signal, whichever is larger, is output as the eighth signal, and is input to the first input terminal of the second comparison circuit. The eighth signal is applied to the second input terminal of the second comparator, and the ninth signal is applied to the second input terminal of the second comparator. The second output terminal of the second comparator outputs the larger signal of the eighth signal or the ninth signal. The tenth signal is output to a decision circuit as a tenth signal, and the decision circuit decides the tenth signal and binarizes it. and a fourth signal is generated by the first circuit outputting the fourth signal to the output circuit. It is preferable that the imaging device has a function for controlling the timing of the imaging.

[0015] In the above configuration, the pixels are arranged in a matrix, and there is no shield between adjacent pixels. An imaging device having an illuminated area is preferred.

[0016] In the above configuration, the pixel further includes a photoelectric conversion element, a tenth transistor, and a first the first transistor, the twelfth transistor, the thirteenth transistor, and the first capacitance element One electrode of the photoelectric conversion element is connected to the source or drain of the tenth transistor. The other of the source and drain of the tenth transistor is electrically connected to the eleventh transistor. an eleventh transistor electrically connected to one of the source and drain of the first transistor, One of the source and the drain of the 12th transistor is electrically connected to the gate of the 13th transistor. The gate of the 12th transistor is electrically connected to one electrode of the first capacitance element. One of the source and the drain of the transistor is electrically connected to the first output terminal, The other electrode of the capacitor element 1 is electrically connected to one of the source and drain of the thirteenth transistor. The other of the source and the drain of the thirteenth transistor is electrically connected to the first wiring. The gate of the thirteenth transistor is electrically connected to the second wiring, and the gate of the thirteenth transistor is electrically connected to the first wiring. The transistors 0 and 12 each have a metal oxide in a channel formation region. An imaging device is preferred.

[0017] In the above structure, the metal oxide is In, Zn, and M (M is Al, Ti, Ga, Sn , Y, Zr, La, Ce, Nd or Hf) is preferred.

[0018] In the above-mentioned configuration, the photoelectric conversion element includes selenium or a compound containing selenium. is preferred. Effect of the Invention

[0019] In view of the above problem, one embodiment of the present invention can provide an imaging device with a novel structure. Alternatively, one aspect of the present invention is an imaging device having a pooling processing function of a neural network. Alternatively, one embodiment of the present invention can provide a device for reducing the amount of calculation and shortening the processing time. According to another embodiment of the present invention, an imaging device having a novel structure can be provided. It is possible to provide an imaging device with a novel configuration that can reduce power consumption.

[0020] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. However, this does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to those skilled in the art. can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention has at least one of the above-listed effects and / or other effects. Therefore, one aspect of the present invention is, in some cases, In some cases, it may not have the effects described above. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram illustrating an imaging apparatus. [Diagram 2] FIG. 1 is a block diagram illustrating an imaging apparatus. [Diagram 3] 1A is a block diagram illustrating an imaging device, and FIG. [Figure 4] FIG. 2 is a circuit diagram illustrating a pixel. [Diagram 5] 1A is a block diagram illustrating an imaging apparatus, and FIG. [Figure 6] FIG. 1 is a block diagram illustrating an imaging apparatus. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 8] 2A and 2B are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 9] 2A and 2B are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 10] 2A and 2B are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 11] 1A is a diagram illustrating a configuration of an imaging device, and FIG. [Figure 12] 2A and 2B are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 13]2A and 2B are diagrams illustrating the configuration of a pixel of an imaging device. [Figure 14] FIG. 1 is a perspective view of a package and module that houses an imaging device. [Figure 15] FIG. 1 illustrates an example of the configuration of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] (Embodiment 1) In this embodiment, an imaging device that efficiently performs neural network pooling processing is provided. This will be described with reference to FIGS. 1 to 7.

[0023] First, a block diagram of the imaging device 10 will be described with reference to FIG. 0, a pixel region, a driver 11, a driver 12, a driver 13, a plurality of wirings 111, a plurality of The pixel region includes a wiring 112 (not shown) and a plurality of wirings 113a (not shown). The area includes a plurality of pooling modules 200, a plurality of analog-to-digital conversion circuits 250, and The pooling module 200 includes a plurality of pooling circuits and an output circuit 251. 210 and a comparison module 220. The pooling circuit 210 is configured to 0 and an arithmetic circuit 212 (not shown). It includes a comparison circuit 230 (not shown) and a determination circuit 221 (not shown).

[0024] The pixel 100 can obtain a first signal by converting light into an electrical signal, and In addition, the pixel 100 can multiply the first signal by any factor to generate a second signal. The first signal and the second signal are output as a current. This indicates the value of the weight data used in the network pooling process.

[0025] The pooling circuit 210 adds the second signals by the arithmetic circuit 212 to obtain a third signal. Further, the arithmetic circuit 212 can average the plurality of second signals to generate a signal. A fifth signal can be generated by:

[0026] The comparison module 220 compares the third signals and selects the largest third signal. The third signal, which is the largest, can be output to the decision circuit 221. The signal can be judged and binarized to generate a fourth signal.

[0027] The pooling module 200 performs the following steps according to the number of pixels that the pooling module 200 has: That is, the pooling module 200 can perform pooling. Pooling first signals acquired from a plurality of pixels included in the module 200 The fourth signal generated by the first input may be output.

[0028] The driver 11 outputs a fourth signal to the output circuit 251 in response to a selection signal applied to the wiring 111. The output circuit 251 can control the timing of outputting the signal to the external device. However, a fourth signal is output to the neural network that controls the image capture device 10. The neural network receives the first data from the imaging device 10. By performing the filtering process, the data features are extracted and input as data. Since neural networks only need to process the extracted features of the data, This reduces the amount of data that is sent from the image sensor to the neural network. This reduces data transfer time and the amount of calculation required for the neural network. The amount of calculation required for the neural network is reduced, which reduces power consumption. It is possible.

[0029] The pooling module 200 preferably includes a plurality of pooling circuits 210. In FIG. 1, the pooling module 200 has four pooling circuits 210. The number of pooling circuits 210 included in the pooling module 200 is 1 or more. The number of pooling circuits can be up to n (n is a natural number equal to or greater than 2). This makes it easier to extract the features of the data. As the number of entries increases, the data compression rate increases, reducing the amount of calculations required by the neural network. Therefore, the power consumption of the neural network is further reduced.

[0030] FIG. 2 illustrates an example of a pulley circuit 210. The pixel circuit 210 includes a plurality of pixels 100, an arithmetic circuit 212, a switch 203, and a switch 204. 4. A plurality of wirings 112, a plurality of wirings 113a, a wiring 114, a wiring 115, and a wiring 210 The pixel 100 has a first output terminal, and the arithmetic circuit 212 has a transistor The transistor 212 includes a transistor 212a, a transistor 212b, and a transistor 212c. The pooling circuit 210 shown in FIG. 2 will be described as an example having four pixels.

[0031] The driver 12 is electrically connected to a plurality of pixels 100 arranged in the row direction via wiring 112. The driver 13 is connected to a plurality of pixels 100 arranged in the column direction via wiring 113a. are electrically connected.

[0032] The wiring 114 is connected to one of the source and drain of the transistor 212a and the One of the source or drain of transistor 12b and one of the source or drain of transistor 212c The gate of the transistor 212a is electrically connected to the gate of the transistor 212. the other of the source or drain of transistor 21a, the gate of transistor 212b, and transistor 21 The gate of transistor 212a is electrically connected to the gate of transistor 212c. The ring circuit 210 is electrically connected to the output terminals 100a of the pixels 100. There are.

[0033] The other of the source and drain of the transistor 212b is connected to one of the electrodes of the switch 203. The other of the source and drain of the transistor 212c is electrically connected to the switch 20 The other electrode of the switch 203 is electrically connected to one of the electrodes of the wiring 210. a is electrically connected to the other electrode of the switch 204 and the comparison module 220. do.

[0034] The driver 13 can output a selection signal to the wiring 113a. An arbitrary magnification can be set as weighting data for the pixel 100 via the wiring 112. Transistor 212a is in the same channel as transistor 212b and transistor 212c. The transistor 212b has the same channel width as the transistor 212a. In this way, a third signal obtained by adding a plurality of second signals can be output. 212c is a pixel 1 having the channel width of the transistor 212a in the pooling circuit 210. The channel width is divided by the number of 00s, so the magnitude of the third signal is divided by the number of pixels 100. The third signal and the fifth signal can be controlled by a current. The switches 203 and 204 are preferably in a complementary relationship.

[0035] The switches 203 and 204 are turned on and off by a first switching signal provided to the wiring 115. In FIG. 2, a p-channel transistor is applied to the switch 203. An example in which an n-channel transistor is applied to 204 is shown.

[0036] When the first switching signal is “L”, the pooling circuit 210 outputs the third signal to the wiring 21. 0a to the comparison module 220.

[0037] When the first switching signal is “H”, the pooling circuit 210 outputs the fifth signal to the wiring 21. 0a to the comparison module 220.

[0038] For example, in-vehicle image processing systems can instantly determine the situation around a fast-moving vehicle. Therefore, the imaging device 10 having the pooling module 200 is By specializing in detecting features from the data, the amount of calculations can be reduced and processing time can be shortened. can be done.

[0039] In FIG. 2, each pixel 100 in the pooling circuit 210 is assigned a different weight. The data is given as an example. Alternatively, the pulley 210 or pulley The same weight data may be given to each wiring module 200 as a unit. 112 and the wiring 113a are connected to the pooling circuit 210 or the pooling module 200. The imaging device 10 may be electrically connected as a single unit. The density can be increased by reducing 13a.

[0040] FIG. 3A illustrates an example of the comparison module 220 using a block diagram. The comparison module 220 includes a plurality of comparison circuits 230 and a plurality of current mirror circuits 222. , and a judgment circuit 221. Each comparison circuit 230 has an input terminal 231a and The determination circuit 221 has an input terminal 231b and an output terminal 231c. The current mirror circuit has a first terminal 221a, an input terminal 221b, and an output terminal 221c. 222 has an input terminal 224a and an output terminal 224b.

[0041] In FIG. 3A, the comparison module 220 receives output signals from the four pooling circuits 210. In addition, the comparison module 220 is connected to the wiring 210a (i , j) to four different pooling circuits 210a(i+1, j+1) via wiring 210a(i+1, j+1). The number of comparison circuits 230 may correspond to the number of input signals. In the example shown in FIG. 3A, the comparison module 220 includes a comparison circuit 230a, current mirror circuit 222a; 2b, and a determination circuit 221.

[0042] Next, the comparison circuit 230a, the comparison circuit 230b, the comparison circuit 230c, the current mirror circuit A connection example of the circuit 222a, the current mirror circuit 222b, and the determination circuit 221 will be described. The input terminal 231a of the comparison circuit 230a is electrically connected to the wiring 210a(i,j). The input terminal 231b is electrically connected to the wiring 210a(i+1, j), and the output terminal 23 An input terminal 224a of a current mirror circuit 222a is electrically connected to the input terminal 1c. The output terminal 224b of the mirror circuit 222a is connected to the input terminal 231a of the comparison circuit 230b. are electrically connected.

[0043] The input terminal 231b of the comparison circuit 230b is electrically connected to the wiring 210a(i, j+1). The output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222b. The output terminal 224b of the current mirror circuit 222b is connected to a comparator circuit 230c. The input terminal 231a of the comparison circuit 230c is electrically connected to the input terminal 231b of the comparison circuit 230c. is electrically connected to the wiring 210a(i+1, j+1), and the output terminal 231c is An input terminal 221a of the circuit 221 is electrically connected.

[0044] The current mirror circuit 222 includes a transistor 223a and a transistor 223b. The transistor 223a and the transistor 223b are p-channel transistors. One of the source and drain of the transistor 223a is preferably a transistor. The transistor 223b is electrically connected to one of the source and drain of the transistor 223b and the wiring 114. The gate of the transistor 223a is connected to the source or drain of the transistor 223a. The other terminal is electrically connected to the gate of the transistor 223b.

[0045] A signal a1 is input to an input terminal 231a of the comparison circuit 230a via a wiring 210a(i,j). The input terminal 231b receives a signal a2 via the wiring 210a(i+1, j). The larger of the signals a1 and a2 is output from the output terminal 231c. The signal a3 is output and provided to the input terminal 224a of the current mirror circuit 222a. The signal a3 is converted to a signal b1 having the same magnitude as the signal a3 by passing through the current mirror circuit 222a. This is given to the output terminal 224b of the current mirror circuit. A signal b1 having the same magnitude as the signal a3 is applied to the input terminal 231a of b. Signal a3 and signal b1 have different signal directions.

[0046] A signal is input to an input terminal 231b of the comparison circuit 230b via a wiring 210a(i, j+1). and the larger of the signals b1 and b2 is output from the output terminal 231c. The comparison circuit 230c outputs a signal b3 at its input terminal 231a. A signal c1 is applied via a - circuit 222b, and a wiring 210a (i +1, j+1) and a signal c2 is given from an output terminal 231c. The larger of the signals a1 and c2 is output as the signal c3 to the decision circuit 221. a2, a3, b1, b2, b3, c1, c2, and c3 are all analog signals. is preferred.

[0047] Therefore, the decision circuit 221 decides on the signal c3 input to the input terminal 221a, By converting the signal into a digital value, a fourth signal can be generated and output to the output terminal 221c. The fourth signal is output via the wiring 211 in response to a selection signal provided to the wiring 111 by the bus 11. The timing of output to the circuit 251 can be controlled.

[0048] FIG. 3B illustrates a circuit diagram of the comparison circuit 230. The comparison circuit 230 is Transistors 241 to 246, an input terminal 231a, an input terminal 231b, an output terminal The terminal 231c and the wiring 232 are provided.

[0049] The input terminal 231a is connected to one of the source and drain of the transistor 242. One of the source or drain of the transistor 244, the gate of the transistor 241, and the transistor The input terminal is electrically connected to the gate of the transistor 242 and the gate of the transistor 243. 231b is a connection between one of the source and drain of the transistor 245 and the One of the source or drain, the gate of the transistor 244, and the gate of the transistor 245 The output terminal 231c is electrically connected to the gate of the transistor 246. , one of the source or drain of the transistor 241 and the source or drain of the transistor 246 The wiring 232 is electrically connected to one of the drains of the transistors 241 to 242. It is electrically connected to the other of the source or drain of the transistor 246 .

[0050] Furthermore, the transistors 241 to 246 have the same channel length. is doing.

[0051] The channel width of the transistor 241 is the same as the channel width of the transistor 242. The channel width of the transistor 243 is preferably The transistors 241 to 243 are the first current A mirror circuit is formed.

[0052] The channel width of the transistor 246 is the same as that of the transistor 245. Preferably, the channel width of transistor 244 is equal to or larger than the channel width of transistor 245. The transistors 244 through 246 are second current A mirror circuit is formed.

[0053] Next, the operation of the comparison circuit 230 will be described. A current is applied to the output terminal 31b as an analog signal, and a current is applied to the output terminal 231c as an analog signal. For example, a signal input to input terminal 231a is input to input terminal 231b. When the signal applied to input terminal 231b is greater than the signal applied to transistor 24, As another example, if a signal input to the input terminal 231b is absorbed by the input terminal When the signal applied to the input terminal 231a is larger than the signal applied to the input terminal 231a, the signal applied to the input terminal 231a Therefore, the output terminal 231c is connected to the first current mirror. The input terminal 231a or the input terminal The output of the ... can.

[0054] However, when the magnitude of the input signals at the input terminals 231a and 231b is the same, The magnitude of the signal absorbed by the transistor 242 and the transistor 245 is half that of the transistor 242. Therefore, the output terminal 231c is connected to the transistor 241 and the transistor Therefore, the output terminal 231 c can absorb signals of the same magnitude as the input terminals 231a and 231b. The wiring 232 is preferably at a low potential so that it can sink a signal.

[0055] Therefore, the decision circuit 221 in FIG. 3A receives the signal given to the comparison module 220. The largest signal among the signals a1, a2, b2, and c2 is given as the signal c3. The driver 221 can determine the signal c3 and binarize it to generate a fourth signal. 11 supplies a selection signal to a decision circuit 221 via a wiring 111, and outputs the decision result to an output circuit 25 It can be made to output 1.

[0056] FIG. 4 illustrates an example of a pixel 100 using a circuit diagram. A switching element 101, a transistor 102, a transistor 103, a capacitance element 104, a transistor The pixel 100 also includes a wiring 112, wiring 113a, wiring 113b, wiring 117, wiring 118, and wiring 119 are electrically are connected to the network.

[0057] One electrode of the photoelectric conversion element 101 is connected to one of the source and drain of the transistor 102. The other of the source and the drain of the transistor 102 is electrically connected to One of the source and drain of the transistor 103, the gate of the transistor 105, and a capacitor The source or drain of the transistor 105 is electrically connected to one electrode of the transistor 104. One of the inputs is electrically connected to the output terminal 100a, and the other electrode of the capacitor 104 is The transistor 106 is electrically connected to one of the source and drain of the transistor 106. The other of the source and drain of the transistor 106 is electrically connected to the wiring 112. The gate of the transistor 106 is electrically connected to the wiring 113a. The gate of the transistor 103 is electrically connected to the wiring 113b. The other of the source and the drain of the transistor 103 is electrically connected to The other electrode of the photoelectric conversion element 101 is electrically connected to the wiring 117. The other of the source and the drain of the transistor 105 is electrically connected to the wiring 1. 19 is electrically connected to

[0058] The node FN is connected to the other of the source and drain of the transistor 102 and the transistor 10 One of the source or drain of the transistor 103, the gate of the transistor 105, and one of the capacitor elements 104 In addition, the capacitor 104 is not provided in the structure. It may be composed of

[0059] The transistor 103 can be turned on by a signal applied to a wiring 113c. Therefore, the node FN is initialized by a reset potential applied to the wiring 118. The transistor 102 can be turned on by a signal applied to the wiring 113b. Therefore, the photoelectric conversion element 101 can be turned into a node through the transistor 102. The data of the FN can be updated with the photoelectrically converted image data. The node 102 can be turned off by a signal applied to the wiring 113b. The FN can hold the image data by turning off the transistor 102. Therefore, the first signal is a signal obtained by applying image data to the gate of the transistor 105. This indicates the current that flows when

[0060] In FIG. 4, an example in which an n-channel transistor is used as the transistor 105 is shown. A p-channel transistor may be used. However, the transistor 105 is an n-channel In the case of the transistor, the potential applied to the wiring 119 is preferably low. Even when 105 is a p-channel type, the potential applied to the wiring 119 is low. is preferred.

[0061] The transistor 106 is turned on by a signal applied to the wiring 113a. The capacitance element 104 is connected to a weighting factor 112 via a transistor 106. The node FN can be connected to the transistors 102 and 103. It is preferable that the transistor is a floating node when it is in the off state. It is preferable to use a transistor with a low off-state current for the transistor 102 and the transistor 103. A transistor having a small off-state current is preferably a transistor having a metal oxide in a channel formation region. It is preferable to use an OS transistor. A detailed explanation will be given in the second embodiment.

[0062] Weighting data is added to the image data stored in the node FN via the capacitance element 104. That is, the gate of the transistor 105 is connected to a data signal in which weight data is added to the image data. Therefore, the conductor of the transistor 105 is Therefore, the second signal can be multiplied by any weighting factor. A data voltage obtained by adding weighting data to the image data is applied to the gate of the transistor 105. The figure shows the current that flows when the

[0063] FIG. 5 illustrates an example of how the pooling module 200 operates. ) For ease of explanation, the pooling module 200 is assumed to have four pooling circuits 21. 0 and a comparison module 220. In this example, the image capture device 10 has four pixels. The number of modules 200 is not limited.

[0064] FIG. 5B illustrates an example of how the pooling module 200 of FIG. 5A operates. The timing chart shown in FIG. 5(B) is not shown in the figure. However, when a signal of L is given to the wiring 115, the pooling circuit 210 This shows an example of adding a signal of 1.

[0065] At T1, a signal of H is applied to the wiring 113c, so that the transistors of each pixel 100 The transistor 103 is turned on. Therefore, the node FN is supplied with the potential Furthermore, a selection signal is applied to the wiring 113a, and the selection signal is applied to the wiring 112. The initial value Res of the weight data is given.

[0066] At T2, a signal of H is applied to the wiring 113b, and each pixel 100 has a photoelectric conversion element 1 01 performs photoelectric conversion (sensing) and updates the node FN with the imaging data.

[0067] At T3, a signal of L is applied to the wiring 113b to determine the imaging data of the node FN. A selection signal is applied to the wiring 113a(1) and a selection signal is applied to the wirings 112(1) to 112(4). The pixels 100(1), 100(2), 100(5), and 100(6) are Set the weight data.

[0068] At T4, a selection signal is applied to the wiring 113a(2), and the wirings 112(1) to 112( 4), pixel 100(3), pixel 100(4), pixel 100(7), and pixel 100(8). (8) Set the weight data.

[0069] At T5, a selection signal is applied to the wiring 113a(3), and the wirings 112(1) to 112( Pixel 100(9), pixel 100(10), pixel 100(13), and pixel 100(14) are connected via 00(14). Furthermore, the pooling circuit 210(1,1) sets the weight data The weighting data is added to the image data to produce a data signal a1, which is then output to the wiring 210a(1,1). Furthermore, the pooling circuit 210(2,1) generates a signal a2 by adding weighting data to the imaging data. The signal is output to the wiring 210a(2,1).

[0070] At T6, a selection signal is applied to the wiring 113a(4), and the wirings 112(1) to 112( 4) through pixel 100(11), pixel 100(12), pixel 100(15), and pixel Set the weight data to 100 (16).

[0071] T7 is a data signal obtained by adding weighting data to the imaging data by the pooling circuit 210(1,1). The pooling circuit 210(2,2) outputs the signal b2 to the wiring 210a(1,2). The signal c2 obtained by adding weighting data to the imaging data is output to the wiring 210a(2,2).

[0072] T8 is the maximum signal among a1, a2, b2, and c2 by the comparison module 220. The comparison module 220 includes a decision circuit 221 that decides which of the detected signals is the maximum. The digital signal out is output to the wiring 211 after being binarized. The output circuit 251 is provided with a neural network-friendly output. The digital signals out are combined and output as digital data of any data width. .

[0073] FIG. 6 shows an example of a pooling circuit 210 having a different configuration from that shown in FIG. 2 using a block diagram. In FIG. 6, a pooling circuit 210 includes a plurality of wirings 113d, 211a, and 2 in that the pixel 100 has an output terminal 100b. It has become.

[0074] The wiring 113d is electrically connected to a plurality of pixels extending in the column direction. The wiring a is electrically connected to the output terminal 100b of the pixel 100 extending in the row direction. Imaging data is output to the wiring 211a or the wiring 211b. The signal is then output to the analog-to-digital converter circuit 250 via the wiring 211b.

[0075] FIG. 7 illustrates an example of a pixel 100 having a different configuration from that of FIG. 4. In FIG. 4 in that it has a stator 107 and a transistor 108.

[0076] The gate of the transistor 107 is electrically connected to the node FN. One of the source and drain of the transistor 107 is the source or drain of the transistor 108. The other of the source and the drain of the transistor 108 is electrically connected to the output terminal The gate of the transistor 108 is electrically connected to the wiring 113d. The other of the source and the drain of the transistor 107 is electrically connected to the wiring 11. 9 is electrically connected to

[0077] The transistor 107 outputs a current according to the potential of the image data stored in the node FN. The transistor 108 is turned on by a selection signal applied to the wiring 113d. The image data can be output to the output terminal 100b. When the data is set, the weighting data is added to the image data and the transistor 105 is turned on. The multiplication result according to the inductance is output.

[0078] The imaging device 10 includes the pooling module 200, which allows the imaging device 10 to easily perform pooling processing. This reduces the amount of data transferred to the neural network. Furthermore, by reducing the amount of calculation, power consumption can be reduced.

[0079] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0080] (Embodiment 2) In this embodiment, the photoelectric conversion element 101 used in the imaging device 10 will be described with reference to FIGS. This will be explained using FIG.

[0081] <Pixel circuit configuration example> FIG. 8A illustrates a configuration of a pixel having the above-described pixel circuit. The element is an example having a laminated structure of a layer 61 and a layer 62.

[0082] The layer 61 includes a photoelectric conversion element 101. The photoelectric conversion element 101 is, as shown in FIG. As shown, the laminate may be a stack of layers 65a, 65b, and 65c.

[0083] The photoelectric conversion element 101 shown in FIG. 8C is a pn junction type photodiode, for example. Layer 65a to p+ a layer 65b is an n-type semiconductor, and a layer 65c is an n-type semiconductor. + Using a semiconductor Alternatively, layer 65a may have n + a layer 65b is a p-type semiconductor, and a layer 65c is a p-type semiconductor. + Type and a half Alternatively, a pin junction type photodiode in which the layer 65b is an i-type semiconductor may be used. may be also possible.

[0084] The pn junction photodiode or pin junction photodiode is a single crystal silicon The pin junction type photodiode can be formed using an amorphous silicon. It can also be formed using a thin film of crystalline silicon, microcrystalline silicon, polycrystalline silicon, etc. .

[0085] As shown in FIG. 8(D), the photoelectric conversion element 101 in the layer 61 includes a layer 66a and Alternatively, the layer 66b, the layer 66c, and the layer 66d may be laminated together. Reference numeral 101 denotes an example of an avalanche photodiode, and layers 66a and 66d correspond to electrodes. The layers 66b and 66c correspond to a photoelectric conversion section.

[0086] The layer 66a is preferably a low resistance metal layer, such as aluminum or titanium. For example, tungsten, tantalum, silver or a laminate thereof can be used.

[0087] The layer 66d may be a conductive layer having high transparency to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, Gallium-zinc oxide, indium-gallium-zinc oxide, graphene, etc. The layer 66d may be omitted.

[0088] The layers 66b and 66c of the photoelectric conversion portion are pn junction type photoelectric conversion layers made of, for example, a selenium-based material. The layer 66b is a p-type semiconductor made of selenium. It is preferable to use a gallium oxide-based material as the layer 66c, which is an n-type semiconductor. I wish.

[0089] Photoelectric conversion elements using selenium-based materials have the characteristic of having high external quantum efficiency for visible light. In this photoelectric conversion element, avalanche multiplication is used to In addition, selenium-based materials have a high optical absorption coefficient, This has the advantage in terms of production that the photoelectric conversion layer can be made as a thin film. The insulating film can be formed by using a vacuum deposition method, a sputtering method, or the like.

[0090] Selenium-based materials include crystalline selenium such as single crystal selenium and polycrystalline selenium, and amorphous selenium. Compounds of copper, indium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium Compounds such as CIGS can be used.

[0091] The n-type semiconductor is made of a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, Alternatively, oxides containing these materials can be used. It also functions as a blocking layer and can reduce dark current.

[0092] The layer 62 shown in FIG. 8(A) may be, for example, a silicon substrate. The silicon substrate is provided with a silicon transistor and the like, and in addition to the pixel circuit described above, A circuit for driving the image sensor, a circuit for reading out an image signal, an image processing circuit, and the like can be provided.

[0093] Also, the pixel has a laminated structure of layers 61, 63, and 62 as shown in FIG. It's fine.

[0094] Layer 63 includes OS transistors (e.g., transistors 102 and 103 of the pixel circuit). At this time, the layer 62 is a Si transistor (for example, a transistor of a pixel circuit). It is preferable that the casing has a resistor 107, 108.

[0095] By adopting this configuration, the elements constituting the pixel circuit are distributed across multiple layers, and the elements Since the imaging device can be made smaller in area, the area of ​​the imaging device can be reduced. In the configuration of FIG. 8(B), the layer 62 is a support substrate, and the pixel 100 and the peripheral Edge circuits may also be provided.

[0096] <OSトランジスタ> The semiconductor material used in the OS transistor is preferably a material having an energy gap of 2 eV or more. Preferably, a metal oxide having a polarization energy of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium. -OS, etc. can be used.

[0097] The semiconductor layer may be, for example, indium, zinc, and M (aluminum, titanium, gallium, germanium, etc.). Rumanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or halide The film may be a film represented by In-M-Zn oxide containing metals such as fluorine.

[0098] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of metal elements in the sputtering target used to form a film of the oxide is In≧ It is preferable that M and Zn satisfy the condition M. The atomic ratio of In:M:Zn is 1:1:1, In:M:Zn is 1:1:1.2, and I n:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4 .1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5 The atomic ratio of the semiconductor layers to be formed is preferably 1:1:8. The atomic ratio of metal elements contained in the target varies by ±40%. .

[0099] For the semiconductor layer, an oxide semiconductor having a low carrier density is used. For example, the semiconductor layer Carrier density is 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 The following is further Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or This is called a high-purity intrinsic oxide semiconductor. This results in a low impurity concentration and a low defect state density. Since the thermal expansion coefficient is low, it can be said that the oxide semiconductor has stable characteristics.

[0100] In addition, the semiconductor characteristics and electrical characteristics (electric field characteristics) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition depending on the characteristics of the device (e.g., effective mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer are It is preferable to appropriately set the recess density, the atomic ratio of metal elements to oxygen, the interatomic distance, the density, etc. It is nice.

[0101] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of com and carbon (obtained by secondary ion mass spectrometry) were 2 × 10 18 ato ms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0102] In addition, when alkali metals and alkaline earth metals combine with oxide semiconductors, they form carriers. This may cause an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the semiconductor layer (measured by secondary ion mass spectrometry) The concentration that can be obtained is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 a toms / cm 3 To the following:

[0103] In addition, when nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the electron This causes an increase in carrier density, making it easier to convert to n-type. Transistors using semiconductors tend to be normally-on. The nitrogen concentration in the sample (obtained by secondary ion mass spectrometry) was 5×10 18 atoms / cm 3 It is preferable to do the following:

[0104] The semiconductor layer may have a non-single crystal structure. The non-single crystal structure may have a non-single crystal structure, for example, a structure in which the crystal is aligned along the c-axis. CAAC-OS (C-Axis Aligned Crystallography) ine Oxide Semiconductor or C-Axis Aligne d and AB-plane Anchored Crystalline Oxi de Semiconductor), including polycrystalline, microcrystalline, or amorphous structures In the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density. The defect level density is low.

[0105] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not contain a crystalline component. Alternatively, the oxide film having an amorphous structure is, for example, a completely amorphous structure having no crystalline portion. stomach.

[0106] In addition, the semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAA The film may be a mixed film having two or more of the C-OS region and the single crystal structure region. The composite film may be, for example, a single-layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0107] In the following, a CAC (Cloud-Aligned Crystal) layer, which is one aspect of a non-single crystal semiconductor layer, will be described. This paper explains the structure of the Composite-OS.

[0108] CAC-OS is, for example, an oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. A structure of a material unevenly distributed in a size range of 1 nm to 2 nm or less, preferably 1 nm to 2 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region having the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixture of particles with sizes of 2 nm or more or less, or close to that size, is also called a mosaic or patch pattern. say.

[0109] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, iridium, and zinc are preferably included. tritium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium , tantalum, tungsten, magnesium, etc. It may be possible.

[0110] For example, CAC-OS in In-Ga-Zn oxide (In- The Ga-Zn oxide may be specifically referred to as CAC-IGZO. (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0) . ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4(X4, Y4, and Z 4 is a real number greater than 0). The material is separated into the mosaic pattern. , mosaic InO X1 , or In X2 Zinc Y2 O Z2 is uniformly distributed in the film (Hereinafter, this will also be referred to as cloud-like.)

[0111] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than in region 2.

[0112] IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO 3 (ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of the crystalline compounds include those which are

[0113] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0114] On the other hand, CAC-OS refers to the material composition of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some of the nanoparticles are mainly composed of Ga. The region where In is observed as a nanoparticle and the region where In is observed as a nanoparticle are mainly composed of In are shown in Fig. Therefore, in CAC-OS, , crystal structure is a secondary factor.

[0115] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, Not at all.

[0116] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the region of the main component and the region of the main component may not be observed.

[0117] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium are used. Aluminum, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected from the group consisting of uranium, sodium, etc. are included, CAC-OS will The region observed is a nanoparticle of the metal element as the main component, and the other region is a nanoparticle of In as the main component. The regions observed as particles are randomly distributed in a mosaic pattern. cormorant.

[0118] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. In addition, the ratio of oxygen to the total flow rate of the deposition gas during deposition may be The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. Or, it is preferable to set it to 0% or more and 10% or less.

[0119] CAC-OS is a method for measuring X-ray diffraction (XRD). When measured using the out-of-plane θ / 2θ scan, In other words, no clear peaks are observed in the measurement area from the X-ray diffraction. It can be seen that the orientation of the regions in the ab plane direction and the c-axis direction is not observed.

[0120] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample with light, a ring-shaped region of high brightness and Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that CAC The crystal structure of -OS has no orientation in the planar direction and cross-sectional direction. It can be seen that the crystalline structure is (no-crystal).

[0121] For example, in the case of CAC-OS using In-Ga-Zn oxide, the energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectrometry) The EDX mapping obtained using oscopy revealed that GaO X3 The area where is the main component Area and In X2 Zinc Y2 OZ2 , or InO X1 The areas where the main component is It can be confirmed that the compound has a structure similar to that shown in FIG.

[0122] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from GZO compounds. That is, CAC-OS is GaO X3 The main components are and the region where In X2 Zinc Y2 O Z2 , or InO X1 The region where is the main component and The phase is separated into two layers, and the regions each containing one element as a main component are arranged in a mosaic pattern.

[0123] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y 2 O Z2 , or InO X1 The carriers flow through the area where the oxide is the main component. The conductivity of a semiconductor is expressed. X2 Zinc Y2 O Z2 , or InO X 1 The regions mainly composed of are distributed in a cloud-like shape in the oxide semiconductor, which results in a high electric field effect. Mobility (μ) can be achieved.

[0124] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X 1 This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching performance. Switching operation can be achieved.

[0125] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation due to Sex and In X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ This can be done.

[0126] In addition, semiconductor devices using CAC-OS have high reliability. is suitable as a constituent material for various semiconductor devices.

[0127] FIG. 9A is a diagram illustrating an example of a cross section of the pixel shown in FIG. The conversion element 101 is a pn junction type photodiode with a silicon photoelectric conversion layer. The layer 62 includes Si transistors and the like that constitute pixel circuits.

[0128] In the photoelectric conversion element 101, the layer 65a is p + A type region, layer 65b, is an n-type region, layer 65c is + The layer 65b can be used as a mold region. The layer 65b is connected to a power supply line and the layer 65c. For example, the region 36 is p + It can be a mold region.

[0129] In FIG. 9A, a Si transistor has a channel forming region in a silicon substrate 40. As shown in Fig. 12(A) and (B), the planar type structure is a silicon-based The plate 40 may have a fin-shaped semiconductor layer. FIG. 12(B) corresponds to a cross section in the channel width direction.

[0130] Alternatively, as shown in FIG. 12(C), a transistor having a semiconductor layer 45 made of a silicon thin film may be used. The semiconductor layer 45 may be formed on an insulating layer 46 on a silicon substrate 40, for example. The silicon on insulator (SOI) is This can be done.

[0131] In FIG. 9A, the electrical connection between the elements of layer 61 and the elements of layer 62 is This shows an example of a configuration in which the above is obtained using a bonding technique.

[0132] The layer 61 is provided with an insulating layer 42, a conductive layer 33 and a conductive layer 34. Conductive layer 34 has an area embedded in insulating layer 42. Conductive layer 33 is electrically connected to layer 65a. The conductive layer 34 is electrically connected to the region 36. The insulating layer 42 and the conductive layer The surfaces of the conductive layer 33 and the conductive layer 34 are flattened to have the same height.

[0133] The layer 62 includes an insulating layer 41, a conductive layer 31, and a conductive layer 32. The conductive layer 32 has a region buried in the insulating layer 41. The conductive layer 32 is electrically connected to the power supply line. The conductive layer 31 is electrically connected to the source or drain of the transistor 102. The surfaces of the insulating layer 41, the conductive layer 31, and the conductive layer 32 are arranged so that their heights are the same. The surface is flattened to the right.

[0134] Here, it is preferable that the conductive layer 31 and the conductive layer 33 have the same metal element as a main component. It is preferable that the conductive layer 32 and the conductive layer 34 have the same metal element as a main component. It is preferable that the insulating layers 41 and 42 are made of the same component.

[0135] For example, the conductive layers 31, 32, 33, and 34 may be made of Cu, Al, Sn, Zn, W, Mo, or A. For ease of bonding, Cu, Au, etc. can be used. The insulating layers 41 and 42 are made of silicon oxide, silicon oxynitride, or the like. For example, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0136] That is, the combination of the conductive layer 31 and the conductive layer 33 and the combination of the conductive layer 32 and the conductive layer 34 It is preferable to use the same metal material as described above for each of the laminates. It is preferable to use the same insulating material for each of the insulating layers 41 and 42, as described above. By adopting this configuration, it is possible to perform bonding at the boundary between the layer 61 and the layer 62. can.

[0137] By this bonding, a combination of the conductive layer 31 and the conductive layer 33 and a combination of the conductive layer 32 and Electrical connection can be obtained for each combination of the conductive layers 34. 1 and the insulating layer 42, a connection having sufficient mechanical strength can be obtained.

[0138] To bond metal layers together, the oxide film and impurity adsorption layer on the surface are removed by sputtering. The surface activated bonding method is used to bond the two cleaned and activated surfaces together. Alternatively, a method such as diffusion bonding, which uses a combination of temperature and pressure to bond the surfaces together, can be used. In both cases, bonding occurs at the atomic level, so they can be bonded not only electrically but also mechanically. Also, excellent bonding can be obtained.

[0139] In addition, to bond the insulating layers together, the layers are polished to a high degree of flatness, and then the layers are bonded using oxygen plasma. The surfaces are temporarily bonded by contacting each other after being treated with hydrophilicity, etc., and then the actual bonding is performed by dehydrating them with heat treatment. Hydrophilic bonding methods can be used. Hydrophilic bonding methods also involve bonding at the atomic level, so Therefore, it is possible to obtain a mechanically excellent bond.

[0140] When the layer 61 and the layer 62 are bonded to each other, an insulating layer and a metal layer are mixed on each bonding surface. To achieve this, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0141] For example, the surface is cleaned after polishing, and the surface of the metal layer is treated to prevent oxidation and then made hydrophilic. Alternatively, the surface of the metal layer may be treated with gold or other metals to bond the metal to the substrate. It is also possible to use a metal that is difficult to oxidize and to perform hydrophilic treatment. It's fine.

[0142] FIG. 9B shows a pn-type photoelectric conversion layer made of a selenium-based material in the layer 61 of the pixel shown in FIG. 1 is a cross-sectional view of a junction photodiode. It has layers 66b and 66c as electric conversion layers and a layer 66d as the other electrode.

[0143] In this case, layer 61 can be formed directly on layer 62. Layer 66a is a transistor. The layer 66d is electrically connected to the source or drain of the capacitor 102 via the conductive layer 37. It is electrically connected to the power supply line.

[0144] FIG. 10A is a diagram illustrating an example of a cross section of the pixel shown in FIG. The photoelectric conversion element 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 62 includes a Si transistor and the like. The layer 63 includes an OS transistor and the like. The layer 61 and the layer 63 show a configuration example in which electrical connection is achieved by bonding them together.

[0145] In FIG. 10A, the OS transistor has a self-aligned structure. As shown in FIG. 12(D), a non-self-aligned top-gate transistor This is also fine.

[0146] The transistor 102 has a back gate 35. The back gate 35 may be formed by a pair of opposing gate electrodes 34, as shown in FIG. In some cases, the front gate of the transistor provided in the buffer is electrically connected to the front gate of the transistor provided in the buffer. The gate 35 can be supplied with a fixed potential different from that of the front gate. Good too.

[0147] Between the region where the OS transistor is formed and the region where the Si transistor is formed, An insulating layer 43 having a function of preventing hydrogen diffusion is provided. The hydrogen in the insulating layer provided in the vicinity of the channel formation region of 8 is induced by the dangling bonds of silicon. On the other hand, an insulating layer provided in the vicinity of a channel formation region of the transistor 102 The hydrogen in the oxide semiconductor layer is one of factors that generate carriers in the oxide semiconductor layer.

[0148] The insulating layer 43 confines hydrogen to one layer, thereby forming the transistors 107 and 108. The reliability can be improved. In addition, the diffusion of hydrogen from one layer to another is suppressed. This can also improve the reliability of the transistor 102.

[0149] The insulating layer 43 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0150] FIG. 10B shows a pixel layer 61 shown in FIG. 8B, in which a selenium-based material is used as a photoelectric conversion layer. A cross-sectional view of a case where an n-junction photodiode is used. The layer 61 is formed directly on the layer 63. For details of the layers 61, 62, and 63, see the above description.

[0151] FIG. 11A is a diagram for explaining the configuration of FIG. 10. The sensor region is a photoelectric conversion element 10 The calculation region is composed of a layer 61 having a MOS transistor 1 and a layer 63 having an OS transistor. The calculation area is composed of a layer 63 having a Si transistor, etc. Registers 107 and 108, and the pooling circuit and drivers 11, 12, and 13 of the first embodiment The sensor area and the calculation area are laminated to form a circuit surface. The product can be made smaller.

[0152] FIG. 11(B) is a cross-sectional photograph of the sensor area and the calculation area. The sensor area is , a pn junction photodiode with a selenium-based material as a photoelectric conversion layer, and an OS transistor ( The calculation area is composed of a silicon transistor (SiFET). Various circuits are constructed.

[0153] <Other pixel components> FIG. 13A illustrates an example in which a color filter or the like is added to a pixel of an imaging device according to one embodiment of the present invention. In this perspective view, cross sections of a plurality of pixels are also shown. An insulating layer 80 is formed on the layer 61 on which the conversion element 101 is formed. The insulating layer 80 is A silicon oxide film having high light transmittance can be used for the passivation. A silicon nitride film may be laminated as the anti-reflective film. Alternatively, a dielectric film such as the above may be laminated.

[0154] A light-shielding layer 81 may be formed on the insulating layer 80. The light-shielding layer 81 is formed by blocking the color filter on the upper side. The light shielding layer 81 has a function of preventing the mixing of colors of the light passing through the filter. A metal layer such as a tin film can be used. The metal layer and the function as an anti-reflection film can also be used. A dielectric film having such a structure may be laminated.

[0155] An organic resin layer 82 may be provided on the insulating layer 80 and the light-shielding layer 81 as a planarizing film. In addition, color filters 83 (color filters 83a, 83b, 83c) are formed for each pixel. For example, R (red), G (green), B (blue), and C (green) are respectively arranged in the color filters 83a, 83b, and 83c. By assigning colors such as (blue), Y (yellow), C (cyan), and M (magenta), A color image can be obtained.

[0156] An insulating layer 86 having transparency to visible light is provided on the color filter 83. This can be done.

[0157] Also, as shown in FIG. 13(B), an optical conversion layer 85 is used instead of the color filter 83. With such a configuration, it is possible to obtain images in various wavelength regions. The present invention can be an apparatus.

[0158] For example, if a filter that blocks light having wavelengths shorter than visible light is used for the optical conversion layer 85, infrared The optical conversion layer 85 may be provided with a filter that blocks light having wavelengths shorter than near-infrared rays. If a visible light filter is used, a far-infrared imaging device can be formed. If a filter that blocks light longer than the wavelength of the light is used, it can be used as an ultraviolet imaging device. A visible color filter may be combined with an infrared or ultraviolet filter.

[0159] In addition, if a scintillator is used for the optical conversion layer 85, the amount of radiation used in X-ray imaging devices, etc. It is possible to use an imaging device that can obtain images that visualize the intensity of radiation such as X-rays that has passed through a subject. When radiation enters the scintillator, it emits visible and ultraviolet light due to the photoluminescence phenomenon. The light is converted into light (fluorescence) such as rays. The light is then detected by the photoelectric conversion element 101. Image data can also be obtained by using an imaging device with this configuration as a radiation detector. good.

[0160] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include substances that emit visible or ultraviolet light as a result of photoelectron irradiation. For example, Gd 2 O 2 S: Tb, Gd 2 O 2 S: Pr, Gd 2 O 2 S:Eu, BaFCl:Eu, NaI, CsI, CaF 2 , BaF 2 , CeF 3LiF, LiI, ZnO, etc. dispersed in resin or ceramics are used. This can be done.

[0161] In addition, the photoelectric conversion element 101 using a selenium-based material converts radiation such as X-rays into electric charges. Since direct conversion is possible, a configuration may be made in which a scintillator is not required.

[0162] As shown in FIG. 13C, a microlens array 84 is disposed on the color filter 83. The light passing through each lens of the microlens array 84 is reflected by the color The light passes through the filter 83 and is irradiated onto the photoelectric conversion element 101. A microlens array 84 may be provided on an optical conversion layer 85 shown in FIG.

[0163] <Package and module configuration examples> Below, we will introduce an example of a package containing an image sensor chip and a camera module. The image sensor chip can use the configuration of the imaging device described above. do.

[0164] FIG. 14(A1) is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 410 to which an image sensor chip 450 is fixed. , a cover glass 420 and an adhesive 430 for bonding the two together.

[0165] FIG. 14(A2) is a perspective view of the bottom surface of the package. The present invention has a BGA (Ball Grid Array) with solder balls as bumps 440. In addition to BGA, LGA (Land grid array) and PGA (Pi n Grid Array) may also be included.

[0166] FIG. 14(A3) shows a package in which the cover glass 420 and the adhesive 430 are partially omitted. Electrode pads 460 are formed on the package substrate 410, and electrodes The pad 460 and the bump 440 are electrically connected via a through hole. The head 460 is electrically connected to the image sensor chip 450 by a wire 470. There are.

[0167] FIG. 14(B1) shows an image sensor chip housed in a lens-integrated package. FIG. 1 is a perspective view of the appearance of a top surface of a camera module. A package substrate 411 for fixing the chip 451, a lens cover 421, and a lens 43 5. In addition, between the package substrate 411 and the image sensor chip 451, An IC chip 490 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0168] FIG. 14(B2) is a perspective view showing the appearance of the lower surface side of the camera module. The bottom and side surfaces of the board 411 are provided with lands 441 for mounting. The structure is a lat no-lead package. Note that this structure is just one example. It is equipped with QFP (Quad flat package) and the BGA mentioned above. Good too.

[0169] FIG. 14(B3) is a diagram showing the lens cover 421 and the lens 435 with parts thereof omitted. The land 441 is electrically connected to the electrode pad 461. The lead 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471. are electrically connected.

[0170] By housing the image sensor chip in the above-mentioned package, a printed circuit board This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible to do so.

[0171] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0172] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, a mobile phone; a mobile phone; Game consoles, including those of the 1990s, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of such electronic devices are shown in Figure 15.

[0173] FIG. 15A shows a surveillance camera, which includes a support stand 951, a camera unit 952, and a protective cover. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling. This allows the camera unit to capture images of the entire surroundings. The imaging device of one embodiment of the present invention can be included as one of the products. This is a common name and does not limit the use. For example, Such a device is also called a camera or a video camera.

[0174] FIG. 15B shows a video camera, which includes a first housing 971, a second housing 972, and a display unit 973. The operation key 974, the lens 975, the connection part 976, etc. The lens 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring an image in the video camera, an embodiment of the present invention is The imaging device may be provided in the same manner.

[0175] FIG. 15C shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone. The digital camera has a light source 963, a light emitting unit 967, a lens 965, etc. The imaging device according to one embodiment of the present invention can be provided as one of the components for obtaining the above object.

[0176] FIG. 15D shows a wristwatch-type information terminal, which includes a display unit 932 and a housing / wristband 933. , a camera 939, etc. The display unit 932 is a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and can be easily attached to the body. The present invention is one of the components for acquiring images in the information terminal. An imaging device according to an embodiment may be provided.

[0177] FIG. 15E shows an example of a mobile phone, which includes a housing 981, a display unit 982, and an operation button 983. , an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display unit 982. All operations, such as inputting, can be performed by touching the display 982 with a finger or a stylus. As one of the components for acquiring images in the mobile phone, The imaging device may include an imaging device according to the present invention.

[0178] FIG. 15F shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. As one of the components for acquiring images in the portable data terminal, An imaging device may be provided.

[0179] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0180] In the present specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element, or the light-emitting device may include, for example, an E EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements) , inorganic EL elements), LED chips (white LED chips, red LED chips, green LED chips chips, blue LED chips, etc.), transistors (transistors that emit light according to the current), Plasma display panel (PDP), electron emission element, carbon nanotube Display elements, liquid crystal elements, electronic ink, electrowetting elements, electrophoretic elements, ME Display elements using MS (microelectromechanical systems) (e.g., gray Light valve (GLV), digital micromirror device (DMD), DM S (Digital Micro Shutter), MIRASOL (registered trademark), IMOD (In Terferometric modulation element, shutter-type MEMS display element, Optical interference type MEMS display element, piezoelectric ceramic display, etc.) or quantum dot In addition to these, display elements, display devices, light-emitting elements, or The light emitting device is a device that uses electrical or magnetic effects to improve contrast, brightness, reflectance, transmittance, etc. An example of a display device using an EL element is an E One example of a display device using electron emission elements is the field FED (Fiber Emission Display) or SED (Semiconductor Device) Flat Panel Display rface-conduction Electron-emitter Displa An example of a display device using liquid crystal elements is a liquid crystal display (transmissive type Liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display Display, projection type liquid crystal display), etc. Electronic ink, electronic liquid powder (registered trademark ) or an example of a display device using an electrophoretic element is electronic paper. An example of a display device using dots for each pixel is a quantum dot display. The quantum dots may be provided as part of a backlight, rather than as a display element. By using the child dots, it is possible to display with high color purity. In the case of realizing a liquid crystal display or a reflective liquid crystal display, a part of the pixel electrode or For example, a part of the pixel electrode or In this case, the entire surface of the substrate may be made of aluminum, silver, etc. It is also possible to provide a memory circuit such as an SRAM under the projection electrode. In addition, when using LED chips, the LED chips Graphene or graphite may be placed under the electrode or the nitride semiconductor. Graphite may be formed into a multilayer film by stacking multiple layers. By providing graphite, a nitride semiconductor, for example, an n-type G It is easy to form aN semiconductor layers and the like. Furthermore, a p-type A GaN semiconductor layer or the like can be provided to form an LED chip. An AlN layer may be provided between the graphite and the n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the LED chip may be formed by MOCVD. By providing graphene, the GaN semiconductor layer of the LED chip can be formed by sputtering. It is also possible to form a film by MEMS (Micro-Electro-Mechanical Systems). In the case of a display element using a stem, the space in which the display element is sealed (for example, the display element between an element substrate on which the element is arranged and an opposing substrate arranged opposite the element substrate By providing a desiccant, MEMS and the like can be prevented from being affected by moisture. This can prevent the material from becoming difficult to move and from deteriorating easily.

[0181] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0182] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the description of each component in the above embodiment.

[0183] <Additional Notes on One Aspect of the Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, a plurality of configuration examples may be shown. In this case, the configuration examples can be appropriately combined with each other.

[0184] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment and one or more other embodiments The content described in the article (or a part of it) is applied to, combined with, or at least one of the contents. Alternatively, a replacement or the like can be performed.

[0185] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. The content is described in the specification or using sentences in the description.

[0186] In addition, a figure (or a part of it) described in one embodiment may be replaced with another part of the figure. In the embodiment, another figure (or a part of it) and one or more other embodiments may be used. At least one of the figures (or a part of the figures) described in the embodiment is combined. By adding more, more figures can be constructed.

[0187] <Note on ordinal numbers> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the components. Therefore, the number of components is not limited. In addition, the order of the components is not limited. The element referred to as "first" in one embodiment may be used in another embodiment or in the claims. In addition, for example, the second component may be the component referred to in the present specification. A component referred to as "first" in one embodiment may be used in another embodiment, or It may be omitted in the claims.

[0188] <Notes on the description explaining the drawings> The embodiments are described with reference to the drawings. However, the embodiments may differ in many ways. It is possible to carry out the invention in various forms without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. The present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. The above descriptions are used in common among the various systems, and the repeated explanations will be omitted.

[0189] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship is used for convenience in describing the drawings. The terms and expressions indicating the arrangement may be changed as appropriate depending on the direction in which each component is depicted. The present invention is not limited to the above description, and may be rephrased appropriately depending on the situation.

[0190] In addition, the terms "above" and "below" refer to the positional relationship of a component directly above or below and directly adjacent to it. For example, if the expression is "electrode B on insulating layer A," It is not necessary that the electrode B is formed directly on the insulating layer A. This does not exclude the inclusion of other components in between.

[0191] In addition, in the drawings, the size, layer thickness, and area are shown arbitrarily for convenience of explanation. The drawings are not necessarily limited to the scale shown. The drawings are merely schematic illustrations for the purpose of illustration only, and are not limited to the shapes or values ​​shown in the drawings. , noise, signal, voltage, or current variations, or timing errors These may include variations in signal, voltage, or current.

[0192] In addition, in the drawings, some components are illustrated in perspective views and the like in order to clarify the drawings. In some cases, the description of the element is omitted.

[0193] In addition, in the drawings, the same elements, elements having similar functions, elements of the same material, or In some cases, the same reference numerals may be used to denote elements that are formed simultaneously, and repeated explanations of such elements will be omitted. It may be omitted.

[0194] <Notes on possible alternative descriptions> In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is called the source or drain. The other of the source and drain is referred to as the "other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, it is better to use the term source (drain) terminal or source (drain) electrode, etc., depending on the situation. In this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. In addition, the terminals may be called terminals, third terminals, and fourth terminals. When a transistor has two or more gates (this configuration is called a dual-gate structure), These gates are sometimes called the first gate, the second gate, the front gate, It may be called a back gate. In particular, the phrase "front gate" is often used interchangeably with "gate". " The term "backgate" can be used interchangeably with the term "backgate." They can simply be interchanged with the term "gate". When manufacturing a transistor, this refers to the terminal that is formed before the channel formation region. The term "top gate" refers to a gate that is formed behind the channel formation region during the manufacture of a transistor. This refers to a terminal formed on a

[0195] A transistor has three terminals called the gate, the source, and the drain. The source terminal is a terminal that functions as a control terminal for controlling the conductive state of a transistor. The two input / output terminals that function as drains are given to the transistor type and each terminal. Depending on the level of the potential, one becomes the source and the other becomes the drain. etc., the terms source and drain may be used interchangeably.

[0196] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the wiring is formed integrally.

[0197] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. This is the potential difference from a reference potential. For example, the reference potential is the ground potential (earth potential). If we define the potential as the ground potential, the voltage can be expressed as the potential. It is important to note that potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0198] In this specification, the terms "film" and "layer" may be used depending on the circumstances. For example, the term "conductive layer" can be used interchangeably with "conductive layer" depending on the application. Alternatively, for example, the term "insulating film" may be used. The term may be changed to the term "insulating layer" in some cases. Or, depending on the situation, words such as "film" and "layer" may be replaced with other terms instead of using them. For example, the term "conductive layer" or "conductive film" may be changed to "conductive body". In some cases, it may be possible to change the term to, for example, "insulating layer" or "insulating film." It may be possible to change the term to "insulator."

[0199] In this specification, the terms "wiring", "signal line", "power line", etc. may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" and In some cases, it may be possible to change the term "signal line" to "signal line". It may be possible to change the term "wiring" to a term such as "power line." Also, , and vice versa, changing terms such as "signal line" and "power line" to the term "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". Also, the opposite is true for terms such as "signal line" and "power line." In addition, the term "potential" applied to the wiring may be changed to " Change the term to "signal" or similar, if necessary or appropriate. and vice versa, terms such as "signal" may be used interchangeably with "potential". It may be possible to change it to a word.

[0200] <Notes on definitions of terms> The following provides definitions of terms used in the above embodiments.

[0201] <<About impurities in semiconductors>> The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor layer. For example, Elements that are less than 0.1 atomic percent are impurities. DOS (Density of States) is formed in the In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, There are elements, group 13 elements, group 14 elements, group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (which is also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, when the semiconductor is a silicon layer, the characteristics of the semiconductor may be deteriorated. Examples of impurities that change the value of the valence number include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and These include Group 3 elements and Group 15 elements.

[0202] <<About transistors>> In this specification, a transistor is defined as a transistor that includes at least a gate, a drain, and a source. Both are elements with three terminals. The drain (drain terminal, drain region or A channel is formed between the drain electrode and the source (source terminal, source region or source electrode). By applying a voltage between the gate and source that exceeds the threshold voltage, A channel is formed in the channel formation region, allowing current to flow between the source and drain. .

[0203] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0204] <<About switches>> In this specification, a switch refers to a device that is in a conductive state (on state) or a non-conductive state (off state). A switch is a device that has the function of controlling whether or not current flows by switching on or off. A switch is a device that has the function of selecting and switching the path through which a current flows.

[0205] As an example, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific one as long as it can control the current.

[0206] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these There is.

[0207] When a transistor is used as a switch, the "conduction state" of the transistor is The state in which the source and drain electrodes of a transistor can be considered to be electrically shorted is called In addition, the "non-conducting state" of a transistor means that the source electrode and drain electrode of the transistor are This refers to a state in which the electrodes can be considered to be electrically disconnected. Note that a transistor is not considered a simple switch. When the transistor is operated as a transistor having a polarity (conductivity type), there is no particular limitation.

[0208] An example of a mechanical switch is a digital micromirror device (DMD). In 2013, a switch using MEMS (microelectromechanical system) technology was developed. The switch has a mechanically movable electrode, and when the electrode moves, Therefore, the device operates by controlling conduction and non-conduction.

[0209] <<About connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. There are three cases: when X and Y are physically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, a predetermined connection relationship, for example, The connections are not limited to those shown in the text, but include connections other than those shown in the drawings or text. It shall be so.

[0210] The X, Y, etc. used here represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0211] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be on and off. A switch can be in a conductive state (on) or a non-conductive state (off) and can either pass current or It has a function to control whether or not water is flushed.

[0212] An example of a case where X and Y are functionally connected is the case where the functional connection between X and Y is possible. Circuits that perform the functions of the following: logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0213] In addition, when it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is placed between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it should simply be "connected" to the "other" section.

[0214] For example, the source (or the first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be A part of Z1 is directly connected to X, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, the following expression is obtained: It can be realized.

[0215] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals, etc.) are electrically connected to each other, and X, the source (or The first terminal, the drain of the transistor, the second terminal, etc., and the Y are electrically connected in this order. "The source (or the first) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Or, "X is the source (or first terminal, etc.) of the transistor. ) and the drain (or second terminal, etc.) of the transistor Y, and X, The source (or first terminal, etc.) of a transistor, and the drain (or second terminal, etc.) of a transistor. , Y are provided in this connection order." By using the expression method, the order of connections in the circuit configuration is specified, A distinction is made between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the object (e.g., device, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0216] In addition, the circuit diagram shows that independent components are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0217] <<About parallel and perpendicular>> In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Explanation of symbols]

[0218] 10: imaging device, 11: driver, 12: driver, 13: driver, 31: conductive layer, 3 2: conductive layer, 33: conductive layer, 34: conductive layer, 35: back gate, 36: region, 37: conductive layer, 40: silicon substrate, 41: insulating layer, 42: insulating layer, 43: insulating layer, 45: semiconductor layer, 46: insulating layer, 80: insulating layer, 81: light-shielding layer, 82: organic resin layer, 83: color filter filter, 83a: color filter, 83b: color filter, 83c: color filter, 8 4: microlens array, 85: optical conversion layer, 86: insulating layer, 100: pixel, 100a : output terminal, 100b: output terminal, 101: photoelectric conversion element, 102: transistor, 10 3: transistor, 104: capacitance element, 105: transistor, 106: transistor, 107: transistor, 108: transistor, 111: wiring, 112: wiring, 113a :Wiring, 113b:Wiring, 113c:Wiring, 113d:Wiring, 114:Wiring, 115:Wiring Line, 117: Wiring, 118: Wiring, 119: Wiring, 200: Pooling module, 20 3: switch, 204: switch, 210: pooling circuit, 210a: wiring, 211: Wiring, 211a: wiring, 211b: wiring, 212: arithmetic circuit, 212a: transistor, 212b: transistor, 212c: transistor, 220: comparison module, 221: Determination circuit, 221a: input terminal, 221b: input terminal, 221c: output terminal, 223a: transistor, 223b: transistor, 224a: input terminal, 224b: output terminal, 2 30: Comparison circuit, 230a: Comparison circuit, 230b: Comparison circuit, 230c: Comparison circuit, 23 1a: input terminal, 231b: input terminal, 231c: output terminal, 232: wiring, 236: Transistor, 241: transistor, 242: transistor, 243: transistor, 2 44: transistor, 245: transistor, 246: transistor, 250: analog Digital conversion circuit, 251: output circuit, 410: package substrate, 411: package substrate Plate, 420: cover glass, 421: lens cover, 430: adhesive, 435: lens, 440: bump, 441: land, 450: image sensor chip, 451: image sensor sensor chip, 460: electrode pad, 461: electrode pad, 470: wire, 471: wire ya, 490: IC chip, 911: housing, 912: display unit, 919: camera, 932: table Display unit, 933: housing / wristband, 939: camera, 951: support stand, 952: camera Unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: 965: Lens, 967: Light-emitting part, 971: Housing, 972: Housing, 973: Display part 974: operation keys, 975: lens, 976: connection section, 981: housing, 982: display section , 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera

Claims

1. An imaging device having a pooling module and an output circuit, The pooling module includes a plurality of pooling circuits and a comparison module; each of the plurality of pooling circuits includes a plurality of pixels, an arithmetic circuit, a first switch, and a second switch; the arithmetic circuit includes a first transistor, a second transistor, and a third transistor; the plurality of pixels are electrically connected to the gates of the first transistors; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor and one of a source or a drain of the third transistor; a gate of the first transistor is electrically connected to the other of the source or the drain of the first transistor, a gate of the second transistor, and a gate of the third transistor; the other of the source and the drain of the second transistor is electrically connected to one of the electrodes of the first switch; the other of the source and the drain of the third transistor is electrically connected to one of the electrodes of the second switch; The other electrode of the first switch is electrically connected to the comparison module; The other electrode of the second switch is electrically connected to the comparison module; the arithmetic circuit has a function of adding up signals obtained from the plurality of pixels to generate a first signal; The comparison module has a function of binarizing the largest signal among the first signals obtained from the plurality of pooling circuits to generate a third signal and outputting the third signal to the output circuit.

2. An electronic device comprising the imaging device according to claim 1 and a display device.

Images