Method and network device for adjusting a scheduling cycle

Abstract

The present invention provides a method and a network device for adjusting a scheduling cycle, which includes the steps of: after receiving a packet transmitted from a second network device, determining a transmission scheduling cycle when the packet is transmitted on the second network device, and determining a reception scheduling cycle when the packet is received on a first network device; determining a target scheduling cycle on the first network device corresponding to the transmission scheduling cycle, where the packet corresponds to a CQ corresponding to the target scheduling cycle; and, if it is determined that the initial time length of a scheduling cycle needs to be adjusted based on the number of interval cycles between the reception scheduling cycle and the target scheduling cycle, adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length. The technical solution of the present invention dynamically controls the scheduling cycle of a deterministic network, so that the CSQF does not rely on strict frequency synchronization and can adapt to the variation of link transmission delay, and greatly improves the adaptability of the CSQF in a wide area network.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a method for adjusting a scheduling cycle and a network device.

Background Art

[0002] A Deterministic Network (DetNet) can provide deterministic service functions for bearer services in a network domain. These deterministic service functions may include delay, packet loss rate, etc. Time Sensitive Networking (TSN) is a deterministic network realized based on a local area network. In TSN, by using Cyclic Queuing and Forwarding (CQF), deterministic transmission at the transport layer is guaranteed, and deterministic service functions are provided for bearer services. For the sake of simplicity, a service flow with deterministic service functions (such as delay and packet loss rate) transmitted in a deterministic network is called a deterministic flow. For other service flows different from the deterministic flow, they can be transferred in a best effort manner. Therefore, other service flows different from the deterministic flow are called best effort flows.

Summary of the Invention

[0003] The present invention provides a method for adjusting a scheduling cycle, which is applied to a first network device. After receiving a packet sent from a second network device, determining the transmission scheduling cycle when the packet is sent on the second network device, and determining the reception scheduling cycle when the packet is received on the first network device; Determining a target scheduling cycle corresponding to the transmission scheduling cycle on the first network device, wherein the packet corresponds to a cycle queue CQ corresponding to the target scheduling cycle, and the step; When it is determined that it is necessary to adjust the initial time length of the scheduling cycle based on the number of interval cycles between the reception scheduling cycle and the target scheduling cycle, adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length.

[0004] The present invention provides a network device, which includes a processor and a machine-readable storage medium. The machine-readable storage medium stores machine-executable instructions executable by the processor. The processor is used to execute machine-executable instructions so as to implement the method for adjusting the scheduling cycle disclosed in the above embodiment of the present invention.

Advantages of the Invention

[0005] As can be seen from the above technical solutions, in the embodiments of the present invention, packet transmission of a deterministic network is realized based on cycle specified queuing and forwarding (CSQF), and the actual time length of the scheduling cycle of the deterministic network is adjusted (that is, adjusted from the initial time length to the target time length), thereby dynamically controlling the scheduling cycle of the deterministic network. Thereby, CSQF does not depend on strict frequency synchronization and can adapt to fluctuations in link transmission delay, and the adaptability of CSQF in a wide area network is greatly improved. By realizing CSQF, a deterministic transmission capability can be provided without affecting ongoing transmission services.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0007] TSN (Time Sensitive Networking) is a deterministic network realized based on a local area network. In TSN, by using CQF (Cyclic Queuing and Forwarding), deterministic transmission in the transport layer is guaranteed, and a deterministic service function is provided for the bearer service. Of course, CQF is only an example for providing a deterministic service, and deterministic transmission in the transport layer may be guaranteed by other methods, which is not limited here. In this embodiment, CQF is taken as an example for explanation as a technology similar to CSQF. The basic operating principle of CQF is that the egress interface of each network device is associated with two queues, the time domain is divided into two cycles, and these two queues alternately perform transmission and reception in these two cycles. For example, let these two queues be queue Q1 and queue Q2 respectively, and let these two cycles be cycle T0 and cycle T1 respectively. In cycle T0, queue Q1 performs transmission, and queue Q2 performs reception (reception of queue Q1 is off, reception of queue Q2 is on, transmission of queue Q1 is on, transmission of queue Q2 is off), and in cycle T1, queue Q1 performs reception, and queue Q2 performs transmission. In this way, queue Q1 and queue Q2 can alternately perform transmission and reception in odd cycles and even cycles.

[0008] In CQF, it is necessary to perform one-hop packet transmission in one cycle. A packet is received at a certain cycle by a certain network device and transmitted in the next cycle. The network device of the next hop receives the packet in the next cycle, and so on. Thus, when the cycle T is a determined value, the transmission delay (end-to-end transmission delay) of the packet on the path is determined. The minimum value of the transmission delay is (H - 1)*T, and the maximum value is (H + 1)*T. Here, H is the number of hops representing the total number of network devices passing on the path.

[0009] CQF is a technology based on local area networks and cannot be realized in wide area networks. In order to realize deterministic transmission in wide area networks, cycle-specified queuing and forwarding (CSQF) based on CQF has been proposed. CSQF is used in combination with segment routing (SR) and SRv6 to realize deterministic transmission in wide area networks. Here, SR may be SR based on multi-protocol label switching (MPLS), and SRv6 may be SRv6 based on IPV6.

[0010] FIG. 1 is a schematic diagram showing the operating principle of CSQF. The controller 10 is used to collect information on each network device, such as transmission capacity, interface, number of cycles, maximum jitter within the node, etc. In response to the deterministic transmission request between the transmission side and the reception side, if the controller 10 determines through calculation that there are sufficient transmission resources, it allocates a transmission path and distributes the information of the transmission path to the edge node. As shown in FIG. 1, the transmission path between the transmission side and the reception side may be network device 11 - network device 12 - network device 13 - network device 14, and the edge node of the transmission path (i.e., the first network device) is network device 11. When network device 11 receives a packet to be transferred, it adds information on each network device on the transmission path to the packet, such as the node identifier of the network device on the transmission path (e.g., the position (Locator) in the segment identifier (SID) of SRv6), the egress interface of the network device, and the cycles transmitted by each network device. In this way, when a packet arrives at a certain network device, the network device can obtain the corresponding interface and cycle information and store the packet in the queue corresponding to the cycle. Each network device may transmit the packets in each queue periodically according to a certain cycle, that is, each queue corresponds to one cycle, and the packets in the queue may be transmitted in that cycle. Since the cycles of the network devices are based on a certain method, in network device 11, the designated cycle of each packet on the transmission side is determined, and the cycle of packet transfer from the transmission side to the reception side on each network device is also determined. Therefore, the delay of the entire packet is also determined, and deterministic transmission is realized.

[0011] As can be seen from the above, the implementation processes of CSQF and CQF are similar, and the differences between the two are as follows. In CSQF, at least three queues (for example, 3, 6, 8, 9, 10, 12, 15 queues, etc.) are required. In each cycle, only one queue is in the transmission state, and the other queues are in the reception state. In CQF, it is required that the cycles of each network device are strictly synchronized including phase synchronization, while in CSQF, only frequency synchronization is required and phase synchronization is not required. Also, when the transmission delay of a certain hop does not fit within one cycle, the transmission queue for the next cycle can be specified, thereby adapting to the transmission delays of different network devices in the wide area network.

[0012] Figure 2 is a schematic diagram showing the comparison between CSQF and CQF. For CQF, in the transmission process of a certain packet, network device 11 transmits the packet in cycle 1, network device 12 receives the packet in cycle 1 and transmits the packet in cycle 2, network device 13 receives the packet in cycle 2 and transmits the packet in cycle 3, and network device 14 receives the packet in cycle 3 and transmits the packet in cycle 4. For CSQF, taking the example that CSQF requires three queues, in the transmission process of a certain packet, network device 11 transmits the packet in cycle 1, network device 12 receives the packet in cycle 1 or cycle 2 and transmits the packet in cycle 3, network device 13 receives the packet in cycle 3 and transmits the packet in cycle 4, and network device 14 receives the packet in cycle 4 or cycle 5 and transmits the packet in cycle 6.

[0013] In the CSQF implementation process, each network device divides time into time slices with a certain length as a cycle, and performs unified flow scheduling for deterministic service flows. As a result, the flow is transferred within the determined time slice, so it is possible to ensure that the delay of the entire packet is determined. For each network device on the transmission path, since the transmission time is limited within a specific time slice, the delay jitter of the packets on the network device is determined. Even if the number of network devices increases, the jitter of the previous network device will not affect the jitter delay of the next network device. Of course, when the total number of network devices increases, the total delay of packet transfer also increases. When the distance of the path through which the packet passes increases, the total delay of packet transfer may also increase.

[0014] At the last network device, the packet is only transmitted and received within the determined time slice, that is, the jitter range of the packet on the last network device is limited within one determined time slice.

[0015] CSQF can achieve deterministic transmission in a wide area network and provide deterministic service functions for bearer services. However, in the prior art, there is no reasonable solution regarding how each network device realizes CSQF.

[0016] For example, the scheduling cycle of CSQF needs to meet frequency synchronization. Otherwise, cumulative errors will occur over time, leading to the invalidation of the scheduling cycle between upstream and downstream network devices. FIG. 3A is a schematic diagram showing the occurrence of cumulative errors due to frequency asynchrony. Network device 1 and network device 2 each have an independent clock source, and it is assumed that there is no Synchronous Ethernet (SyncE) mechanism and no hardware support for the Precision Time Synchronization Protocol (PTP) between network device 1 and network device 2, that is, clock synchronization cannot be performed between network device 1 and network device 2. Therefore, when there is a frequency difference between network device 1 and network device 2, when realizing the scheduling cycle of CSQF using their respective clock sources, the lengths of the scheduling cycles of network device 1 and network device 2 will be different. Although this difference is very small, with the passage of time and the accumulation of errors, the mapping relationship of the scheduling cycle changes, eventually resulting in a delay jump and relatively large jitter.

[0017] Furthermore, when the link is affected by thermal expansion (also called catenary sagging), the length of the broadband copper wire (for example, a cable network) may also be affected by the day and night temperatures, resulting in a maximum change of 20%. As a result, the transmission delay between network devices changes, which in turn changes the mapping relationship of the scheduling cycle, and ultimately a delay jump may occur, and relatively large jitter may occur.

[0018] Figure 3B is a schematic diagram showing the mapping relationship of the scheduling cycles between network devices. There is a mapping relationship between the scheduling cycle a0 of network device 1 and the scheduling cycle b3 of network device 2. That is, the packet transmitted by network device 1 in scheduling cycle a0 may be stored by network device 2 in the cycle queue (CQ: Cycle Queue) corresponding to scheduling cycle b3. Also, when the packet transmitted by network device 1 in scheduling cycle a0 arrives at network device 2, if network device 2 is scheduling scheduling cycle b2, the packet can be stored in the CQ corresponding to scheduling cycle b3. Therefore, the above mapping relationship is reasonable.

[0019] The frequencies of the scheduling cycles between network device 1 and network device 2 are not synchronized and are continuously accumulated. Therefore, after a certain period of time, as shown in Figure 3C, when the packet transmitted by network device 1 in scheduling cycle a0 arrives at network device 2, if network device 2 is scheduling scheduling cycle b4, the packet cannot be stored in the CQ corresponding to scheduling cycle b3. That is, the above mapping relationship is not reasonable, and the mapping relationship between scheduling cycle a0 and scheduling cycle b3 becomes invalid. In summary, due to the accumulation of errors, the scheduling cycles between network device 1 and network device 2 do not correspond, and large jitter and congestion packet loss may occur. As a result, the realization of CSQF cannot obtain the theoretical effect, and CSQF may become unusable.

[0020] Exemplarily, the CSQF queue may include a sending queue (SQ), a receiving queue (RQ), and a tolerating queue (TQ). The SQ is the queue being sent by CSQF, and the RQ is the queue being received by CSQF. When the received packet cannot normally enter the RQ due to jitter or the like, it enters the TQ. In this embodiment, for convenience of explanation, SQ, RQ, and TQ are collectively referred to as CQ. That is, the scheduling cycle corresponds to CQ.

[0021] Exemplarily, the scheduling cycle is also called a scheduling time slot. For example, each of the above scheduling cycles may be a scheduling time slot, but is not limited thereto. In this embodiment, for convenience of explanation, the scheduling cycle is taken as an example for explanation.

[0022] Regarding the problem of invalid mapping relationship, an embodiment of the present invention provides a method for realizing a wide-area deterministic network based on CSQF. By this method, the invalidation of the mapping relationship between scheduling cycles is avoided, and CSQF does not depend on strict frequency synchronization and can adapt to the delay variation of link transmission. Thereby, the adaptability of CSQF in a wide-area network is greatly improved, and the deterministic transmission ability can be provided by realizing CSQF.

[0023] An embodiment of the present invention provides a method for adjusting a scheduling cycle. The method can be applied to a system for realizing a deterministic network using CSQF. The system may include a plurality of network devices (network devices are also called network nodes or transfer nodes). Two adjacent network devices are called the first network device and the second network device, and the second network device sends packets to the first network device. FIG. 4 is a flowchart showing a method for adjusting a scheduling cycle. The method can be applied to the first network device and may include the following steps.

[0024] In step 401, after receiving a packet transmitted from a second network device, determine the transmission scheduling cycle when the packet is transmitted on the second network device, and determine the reception scheduling cycle when the packet is received on the first network device.

[0025] Exemplarily, for the transmission scheduling cycle when the packet is transmitted on the second network device, it represents that the packet is transmitted by the second network device within the transmission scheduling cycle. For example, when the second network device transmits the packet in a certain scheduling cycle, for the sake of convenience of distinction, this scheduling cycle can be referred to as the transmission scheduling cycle. Also, for the reception scheduling cycle when the packet is received on the first network device, it represents that the packet is received by the first network device within the reception scheduling cycle. For example, when the first network device receives a packet transmitted from the second network device in a certain scheduling cycle, for the sake of convenience of distinction, this scheduling cycle can be referred to as the reception scheduling cycle.

[0026] Exemplarily, the second network device transmits packets in a specified scheduling cycle, and the first network device determines that the transmission scheduling cycle when the packet is transmitted on the second network device is the specified scheduling cycle. For example, if the second network device fixedly transmits packets in scheduling cycle a0 (transmits packets only in scheduling cycle a0), the specified scheduling cycle of the second network device is scheduling cycle a0. Based on this, the first network device determines that the transmission scheduling cycle is scheduling cycle a0. Alternatively, when the second network device transmits a packet, it adds cycle information (such as a cycle identifier) of the transmission scheduling cycle to the packet, and the first network device determines that the transmission scheduling cycle when the packet is transmitted on the second network device is the scheduling cycle corresponding to the cycle information. For example, when the second network device transmits a packet in scheduling cycle a0, the cycle information of scheduling cycle a0 may be added to the packet. Based on this, the first network device determines that the transmission scheduling cycle is the scheduling cycle a0 corresponding to the cycle information.

[0027] Exemplarily, after receiving a packet transmitted from the second network device, the first network device determines the scheduling cycle being executed on the first network device, and this scheduling cycle is the reception scheduling cycle when the packet is received on the first network device. For example, when the first network device receives a packet, if scheduling cycle b2 is being executed on the first network device, it may be determined that the reception scheduling cycle is scheduling cycle b2.

[0028] In step 402, determine the target scheduling cycle corresponding to the transmission scheduling cycle on the first network device. Here, the packet corresponds to the CQ corresponding to the target scheduling cycle. For example, the packet is stored in the CQ corresponding to the target scheduling cycle.

[0029] Exemplarily, a mapping relationship between the scheduling cycle of the second network device and the scheduling cycle of the first network device may be set in advance. For example, when there is a mapping relationship between the scheduling cycle a0 of the second network device and the scheduling cycle b3 of the first network device, when the second network device transmits a packet in the scheduling cycle a0, it means that the packet needs to be stored in the CQ corresponding to the scheduling cycle b3. Based on this, after the first network device determines the transmission scheduling cycle when the packet is transmitted on the second network device, it can determine the target scheduling cycle corresponding to the transmission scheduling cycle. For example, when the transmission scheduling cycle is the scheduling cycle a0, the target scheduling cycle is the scheduling cycle b3.

[0030] In a possible embodiment, the first network device may maintain a session information table including a mapping relationship between a node identifier (for example, a unique identifier of the network device), egress interface information (for example, an egress interface identifier of the first network device), and a related scheduling cycle. The related scheduling cycle is a related scheduling cycle corresponding to the specified scheduling cycle of the network device corresponding to the node identifier. That is, a packet transmitted in the specified scheduling cycle is stored in the CQ corresponding to this related scheduling cycle.

[0031] Based on this, after the first network device receives a packet sent from the second network device, it may obtain the node identifier of the second network device and the egress interface information corresponding to the packet (indicating that the packet is sent through the egress interface corresponding to this egress interface information). For example, the node identifier and the egress interface information are parsed from the packet. The first network device queries the set session information table based on the node identifier and the egress interface information, and obtains the related scheduling cycle corresponding to the specified scheduling cycle of the second network device. For example, since the session information table includes the mapping relationship between the node identifier, the egress interface information, and the related scheduling cycle, the related scheduling cycle can be obtained by querying the session information table.

[0032] The first network device determines a target scheduling cycle corresponding to the transmission scheduling cycle on the first network device based on the transmission scheduling cycle, the associated scheduling cycle, and the specified scheduling cycle. Here, the number of interval cycles between the transmission scheduling cycle and the specified scheduling cycle may be equal to the number of interval cycles between the target scheduling cycle and the associated scheduling cycle. For example, if the specified scheduling cycle of the second network device is scheduling cycle a0 and the associated scheduling cycle of the first network device is scheduling cycle b3, when the second network device transmits a packet in scheduling cycle a0, that is, when the transmission scheduling cycle is scheduling cycle a0 and the number of interval cycles between the transmission scheduling cycle and the specified scheduling cycle is 0, the target scheduling cycle is scheduling cycle b3. Also, as another example, when the second network device transmits a packet in scheduling cycle a1, that is, when the transmission scheduling cycle is scheduling cycle a1 and the number of interval cycles between the transmission scheduling cycle and the specified scheduling cycle is 1, the target scheduling cycle is scheduling cycle b4.

[0033] In a possible embodiment, for the packet that the second network device transmits to the first network device, the packet may be a test packet or a data packet belonging to a deterministic flow. When the packet is a data packet, the data packet may be stored in the CQ corresponding to the target scheduling cycle. At the target scheduling cycle, the data packet in the CQ corresponding to the target scheduling cycle is transmitted to an external device.

[0034] For example, in the packet transmission process of a deterministic network, packets may be exchanged between a second network device and a first network device. For example, the second network device may send data packets belonging to a best-effort flow to the first network device, or may send data packets belonging to a deterministic flow to the first network device. Regarding the data packets belonging to the best-effort flow, the description thereof is omitted in this embodiment. Regarding the data packets belonging to the deterministic flow, after receiving the data packets, the first network device may store the data packets in a CQ corresponding to the target scheduling cycle. In the target scheduling cycle, the data packets in the CQ corresponding to the target scheduling cycle are sent to an external device. Based on this, in this embodiment, a scheduling cycle adjustment process is triggered based on the data packets, that is, the scheduling cycle is adjusted based on the process shown in FIG. 4.

[0035] As another example, in this embodiment, in order to adjust the scheduling cycle, a second network device sends a test packet to a first network device, and the first network device triggers a scheduling cycle adjustment process based on the test packet, that is, the scheduling cycle may be adjusted based on the process shown in FIG. 4. In this case, the first network device does not need to store the test packet in a CQ corresponding to the target scheduling cycle, nor does it need to send the test packet to an external device. This test packet is only used to trigger a scheduling cycle adjustment process in the first network device.

[0036] In step 403, if it is determined that it is necessary to adjust the initial time length of the scheduling cycle based on the number of interval cycles between the reception scheduling cycle and the target scheduling cycle, the actual time length of the scheduling cycle on the first network device is adjusted from the initial time length to the target time length. That is, the actual time length is updated to the target time length.

[0037] Exemplarily, after the reception scheduling cycle and the target scheduling cycle are determined, the number of interval cycles between the reception scheduling cycle and the target scheduling cycle may be determined, and based on the number of interval cycles, it may be determined whether it is necessary to adjust the initial time length of the scheduling cycle. If it is determined that it is necessary to adjust the initial time length of the scheduling cycle, the initial time length is adjusted to the target time length. That is, the actual time length of the scheduling cycle is updated from the initial time length to the target time length. If it is determined that it is not necessary to adjust the initial time length of the scheduling cycle, the initial time length of the scheduling cycle is not changed. That is, the actual time length of the scheduling cycle remains the initial time length.

[0038] Exemplarily, when the reception scheduling cycle is before the target scheduling cycle (i.e., the reception scheduling cycle is earlier than the target scheduling cycle) and the number of such interval cycles is greater than the first threshold, it is determined that it is necessary to adjust the initial time length of the scheduling cycle. When the reception scheduling cycle is before the target scheduling cycle and the number of such interval cycles is not greater than the first threshold, it is determined that there is no need to adjust the initial time length of the scheduling cycle. When the reception scheduling cycle is after the target scheduling cycle (i.e., the reception scheduling cycle is later than the target scheduling cycle) and the number of such interval cycles is greater than the second threshold, it is determined that it is necessary to adjust the initial time length of the scheduling cycle. When the reception scheduling cycle is after the target scheduling cycle and the number of such interval cycles is not greater than the second threshold, it is determined that there is no need to adjust the initial time length of the scheduling cycle. Here, the first threshold and the second threshold may be the same or different. The first threshold may be 0, 1, 2, etc., and is not particularly limited. Also, the second threshold may be 0, 1, 2, etc., and is not particularly limited. In the following embodiments, for the sake of convenience of explanation, it will be described by taking the first threshold and the second threshold as 1 as an example.

[0039] Exemplarily, when adjusting the initial time length to the target time length, if the reception scheduling cycle is before the target scheduling cycle, a decrease adjustment is performed on the initial time length based on the set time length adjustment amount (which may be set based on experience) to obtain the adjusted target time length. If the reception scheduling cycle is after the target scheduling cycle, an increase adjustment is performed on the initial time length based on the time length adjustment amount to obtain the adjusted target time length.

[0040] For example, when the reception scheduling cycle is scheduling cycle b2 and the target scheduling cycle is scheduling cycle b3, the number of interval cycles is 1, and the reception scheduling cycle is before the target scheduling cycle. Since the number of interval cycles 1 is not greater than the first threshold 1, there is no need to adjust the initial time length of the scheduling cycle.

[0041] As another example, when the reception scheduling cycle is scheduling cycle b1 and the target scheduling cycle is scheduling cycle b3, the number of interval cycles is 2, and the reception scheduling cycle is before the target scheduling cycle. Since the number of interval cycles 2 is greater than the first threshold 1, it is necessary to adjust the initial time length of the scheduling cycle.

[0042] In this case, since the reception scheduling cycle is before the target scheduling cycle, a decrease adjustment may be performed on the initial time length based on the time length adjustment amount to obtain the adjusted target time length. That is, the target time length may be the difference between the initial time length and the time length adjustment amount.

[0043] Also, for example, when the reception scheduling cycle is scheduling cycle b4 and the target scheduling cycle is scheduling cycle b3, the number of interval cycles is 1, and the reception scheduling cycle is after the target scheduling cycle. Since the number of interval cycles 1 is not greater than the second threshold 1, there is no need to adjust the initial time length of the scheduling cycle.

[0044] As another example, when the reception scheduling cycle is scheduling cycle b5 and the target scheduling cycle is scheduling cycle b3, the number of interval cycles is 2, and the reception scheduling cycle is after the target scheduling cycle. Since the number of interval cycles 2 is greater than the second threshold 1, it is necessary to adjust the initial time length of the scheduling cycle.

[0045] In this case, since the reception scheduling cycle is after the target scheduling cycle, an increase adjustment may be performed on the initial time length based on the time length adjustment amount to obtain the adjusted target time length. That is, the target time length may be the sum of the initial time length and the time length adjustment amount.

[0046] Exemplarily, when the actual time length of the scheduling cycle on the first network device is the initial time length, it is assumed that the first network device sequentially includes scheduling cycles b1, b2, b3, etc., and the interval between the end time of scheduling cycle b1 and the start time of scheduling cycle b1 is the initial time length, and the interval between the end time of scheduling cycle b2 and the start time of scheduling cycle b2 (the start time of scheduling cycle b2 is the end time of scheduling cycle b1) is the initial time length. The same applies hereinafter.

[0047] When the actual time length of the scheduling cycle on the first network device is the target time length, the interval between the end time of scheduling cycle b1 and the start time of scheduling cycle b1 is the target time length, and the interval between the end time of scheduling cycle b2 and the start time of scheduling cycle b2 is the target time length. The same applies hereinafter.

[0048] Exemplarily, based on the first clock count corresponding to the initial time length, the set time length adjustment amount, and the interval cycle count, the total adjustment integer K of the scheduling cycle may be determined, and the actual time lengths of K consecutive scheduling cycles on the first network device may be updated to the target time length (that is, updated from the initial time length to the target time length). After updating the actual time lengths of K consecutive scheduling cycles to the target time length, the actual time length of the scheduling cycle on the first network device may be updated to the initial time length (that is, updated from the target time length to the initial time length).

[0049] For example, the overall adjustment integer K can be determined by the formula K = the number of first clock counts * the number of interval cycles / the time length adjustment amount. Note that the above formula is just an example and is not limited to this. After obtaining the overall adjustment integer K, the actual time length of K consecutive scheduling cycles may be updated to the target time length.

[0050] For example, the first network device sequentially includes scheduling cycles b1, b2, b3,.... Assume that the actual time length of scheduling cycle b1 is the initial time length. Based on this, if it is determined that the initial time length of the scheduling cycle needs to be adjusted in scheduling cycle b1 and the initial time length is adjusted to the target time length, the actual time length of scheduling cycle b2 will be the target time length, and the actual time length of scheduling cycle b3 will be the target time length. In this way, after the actual time lengths of K consecutive scheduling cycles (that is, K scheduling cycles starting from scheduling cycle b2) become the target time length, next time, if it is determined that the initial time length of the scheduling cycle needs to be adjusted and until the initial time length is adjusted to the target time length, the actual time length of the (K + 1)-th scheduling cycle is updated to the initial time length, and the actual time length of each scheduling cycle becomes the initial time length.

[0051] Hereinafter, the adjustment process of the scheduling cycle will be described in combination with a specific application scenario.

[0052] FIG. 5A is a schematic diagram showing the division of the scheduling cycle of CSQF. For the first network device, SQ is the transmission queue corresponding to scheduling cycle b0, RQ is the reception queue corresponding to scheduling cycle b1 immediately after scheduling cycle b0, and TQ is the tolerance queue corresponding to scheduling cycle b2 immediately after scheduling cycle b1.

[0053] In the above application scenario, due to causes such as jitter, the mapping relationship of the scheduling cycle may become invalid. For example, when the scheduling cycle a0 of the second network device corresponds to the scheduling cycle b1 of the first network device, if the first network device receives the packet sent by the second network device in the scheduling cycle a0 in the scheduling cycle b0, the packet can be stored in the RQ corresponding to the scheduling cycle b1. However, if the first network device receives the packet in the scheduling cycle b2, the packet cannot be stored in the RQ corresponding to the scheduling cycle b1. Therefore, the mapping relationship between the scheduling cycle a0 and the scheduling cycle b1 becomes invalid.

[0054] Based on the above findings, in the embodiments of the present invention, by adjusting the actual time length of the scheduling cycle, the invalidation of the mapping relationship of the scheduling cycle is avoided. FIG. 5B is a schematic diagram showing the division of the scheduling cycle of CSQF. In this application scenario, CSQF includes, for example, 10 queues corresponding to 10 scheduling cycles. The 10 scheduling cycles of the second network device are the scheduling cycle a0, the scheduling cycle a1, the scheduling cycle a2,..., the scheduling cycle a9, and the 10 scheduling cycles of the first network device are the scheduling cycle b0, the scheduling cycle b1, the scheduling cycle b2,..., the scheduling cycle b9. Of course, as long as the number of queues of CSQF is 3 or more, it may be 10 or more or 10 or less.

[0055] In this application scenario, assume that the transmission scheduling cycle when a packet is transmitted on the second network device is scheduling cycle a0, and the target scheduling cycle corresponding to scheduling cycle a0 on the first network device is scheduling cycle b3. That is, there is a mapping relationship between scheduling cycle a0 and scheduling cycle b3. Of course, the above mapping relationship is just an example and is not limited to this. For the convenience of distinction, the target scheduling cycle is denoted as Anchor, and here Anchor is scheduling cycle b3.

[0056] Based on Anchor, expand it in the front-back direction within a certain range to form a reasonable jitter interval. For example, expand it forward at the scheduling cycle of the first threshold, set the first threshold as Jitter1, the value of Jitter1 as 1, expand it backward at the scheduling cycle of the second threshold, set the second threshold as Jitter2, and the value of Jitter2 as 1. In this way, the reasonable jitter interval is scheduling cycle b2, scheduling cycle b3, and scheduling cycle b4.

[0057] After a certain period of time, for the packet sent by the second network device to the first network device, when the packet arrives at the first network device, if the first network device is scheduling scheduling cycle b2, scheduling cycle b3, or scheduling cycle b4, it indicates that there is no need to adjust the initial time length of the scheduling cycle. When the packet arrives at the first network device, if the first network device is scheduling scheduling cycle b1, it indicates that the scheduling cycle at which the packet arrives is relatively forward, and it is necessary to adjust the initial time length of the scheduling cycle. For example, shorten the initial time length of the scheduling cycle so that the scheduling cycle at which the packet arrives becomes scheduling cycle b2, scheduling cycle b3, or scheduling cycle b4. When the packet arrives at the first network device, if the first network device is scheduling scheduling cycle b5, scheduling cycle b6, or scheduling cycle b7, it indicates that the scheduling cycle at which the packet arrives is relatively backward, and it is necessary to adjust the initial time length of the scheduling cycle. For example, increase the initial time length of the scheduling cycle so that the scheduling cycle at which the packet arrives becomes scheduling cycle b2, scheduling cycle b3, or scheduling cycle b4.

[0058] Here, for scheduling cycles before a reasonable jitter interval, such as scheduling cycle b0 and scheduling cycle b1, the area where these scheduling cycles are located is called the forward adjustment interval and denoted as Area1. Also, for scheduling cycles after a reasonable jitter interval, such as scheduling cycle b5, scheduling cycle b6, and scheduling cycle b7, the area where these scheduling cycles are located is called the backward adjustment interval and denoted as Area2.

[0059] In order to avoid excessive jitter between adjacent packets due to significant adjustment, in this embodiment, the initial time length of the scheduling cycle may be adjusted using a progressive adjustment method. That is, determine the total adjustment integer K of the scheduling cycle, and complete the adjustment of the initial time length after passing through K scheduling cycles. Let the initial time length of the scheduling cycle be C, with the unit being ticks (clock count unit), the number of interval cycles between the received scheduling cycle and the target scheduling cycle be TsNum, and the number of ticks (time length adjustment amount) adjusted in each scheduling cycle be Jitter_Adjustment. When it is necessary to increase the initial time length of the scheduling cycle, Jitter_Adjustment is a positive value; when it is necessary to decrease the initial time length of the scheduling cycle, Jitter_Adjustment is a negative value. Based on this, let the total adjustment integer of the scheduling cycle be Adjust_Counter, and Adjust_Counter = C * TsNum / |Jitter_Adjustment|.

[0060] Assume that the clock frequency of the timer that generates the scheduling cycle is 1G, that is, each tick is 1ns. A clock signal is generated every 1ns (that is, each tick). If the initial time length of the scheduling cycle is 30us, the count of 30,000 ticks corresponds to 1 scheduling cycle. Therefore, C is 30,000, representing the first clock count number corresponding to the initial time length. When the received scheduling cycle is scheduling cycle b1 and the target scheduling cycle is scheduling cycle b3, the number of interval cycles between the received scheduling cycle and the target scheduling cycle is 2, that is, TsNum is 2.

[0061] Since the reception scheduling cycle is before the target scheduling cycle and the number of interval cycles 2 is greater than the first threshold 1, a decrease adjustment may be performed on the initial time duration based on the time duration adjustment amount Jitter_Adjustment. For example, shorten the initial time duration of the scheduling cycle, that is, reduce the ticks counted by the timer. Assuming that the adjusted Jitter_Adjustment is -1000 each time, the "-" means a decrease adjustment is performed on the initial time duration. When the initial time duration corresponds to 30000 ticks, the target time duration after the decrease adjustment corresponds to 29000 ticks.

[0062] Exemplarily, based on Jitter_Adjustment, C, and TsNum, the total adjustment integer Adjust_Counter of the scheduling cycle is determined in the way that Adjust_Counter = C * TsNum / |Jitter_Adjustment| = 30000 * 2 / 1000 = 60. As above, each scheduling cycle may be adjusted from the initial time duration of 30 us to the target time duration (30 us - 1 us). After 60 adjustments, the total adjusted time duration is 29 us * 60 = 1.74 ms. If the adjustment process of the scheduling cycle is extended to 1.74 ms, each scheduling cycle decreases by 1000 ns, which is hardly perceptible at the macro level. Therefore, the packet jitter caused by the change of the scheduling cycle can be ignored.

[0063] When the reception scheduling cycle is scheduling cycle b5 and the target scheduling cycle is scheduling cycle b3, the number of interval cycles between the reception scheduling cycle and the target scheduling cycle is 2, that is, TsNum is 2.

[0064] Since the reception scheduling cycle is after the target scheduling cycle and the number of interval cycles 2 is greater than the second threshold 1, an increase adjustment may be performed on the initial time length based on the time length adjustment amount Jitter_Adjustment. For example, increase the initial time length of the scheduling cycle, that is, increase the ticks counted by the timer. Assuming that the adjusted Jitter_Adjustment is +1000 each time, the "+" means an increase adjustment is performed on the initial time length. When the initial time length corresponds to 30000 ticks, the target time length after the increase adjustment corresponds to 31000 ticks.

[0065] Exemplarily, based on Jitter_Adjustment, C, and TsNum, the total adjustment integer Adjust_Counter of the scheduling cycle is determined in the way of Adjust_Counter = C * TsNum / |Jitter_Adjustment| = 30000 * 2 / 1000 = 60. As above, each scheduling cycle may be adjusted from the initial time length of 30 us to the target time length (30 us + 1 us). After 60 adjustments, the total adjusted time length is 31 us * 60 = 1.86 ms. Extending the adjustment process of the scheduling cycle to 1.86 ms, each scheduling cycle increases by 1000 ns, which is hardly perceptible at the macro level. Therefore, the packet jitter due to the change of the scheduling cycle can be ignored.

[0066] Through the above adjustment process of the scheduling cycle, for the packet sent by the second network device in the scheduling cycle a0, when the packet arrives at the first network device, the reception scheduling cycle of the first network device can be adjusted near the reference point Anchor (i.e., the target scheduling cycle), that is, a reasonable jitter range interval can be maintained.

[0067] Next, the effectiveness and constraints of the scheduling cycle adjustment process are analyzed. FIG. 6A is a schematic diagram showing a normal scheduling cycle. The CPU transmission time for deterministic flow scheduling is in units of 2 hours, each transmission scheduling cycle is in units of 16 hours, the deterministic flow transmission time at the port is in units of 8 hours, and the best effort flow transmission time at the port is in units of 8 hours. FIG. 6B is a schematic diagram showing adjusting the scheduling cycle forward by 1 hour. Adjusting forward corresponds to shortening the time length of the scheduling cycle, that is, reducing the number of deterministic flow packets transferred in the scheduling cycle. Due to reasons such as the adjustment amount of each scheduling cycle being very small, there is a margin for the deterministic flow assigned to each scheduling cycle to ensure transfer determinism, and the cumulative error does not continue to accumulate in one direction due to the introduction of the adjustment, functionally, there is no case where the deterministic flow packets are not completely transmitted in the scheduling cycle. FIG. 6C is a schematic diagram showing adjusting the scheduling cycle backward by 1 hour. Adjusting backward corresponds to increasing the time length of the scheduling cycle, that is, increasing the number of deterministic flow packets transferred in the scheduling cycle. Functionally, there is no case where the deterministic flow packets are not completely transmitted in the scheduling cycle. In summary, neither forward adjustment nor backward adjustment affects the functions of periodic scheduling and transfer.

[0068] In a possible embodiment, the second network device is an upstream node, and the first network device is a downstream node. The second network device transmits, for example, test packets to the first network device. The second network device transmits test packets in a certain cycle, and the second network device fixedly transmits test packets in the scheduling cycle a0. That is, in each scheduling cycle a0, test packets are transmitted to the first network device.

[0069] After receiving the test packet, the first network device determines that the transmission scheduling cycle when the test packet is transmitted on the second network device is the scheduling cycle a0. The first network device determines the target scheduling cycle corresponding to the scheduling cycle a0 on its own device and designates it as Anchor. For example, the target scheduling cycle is scheduling cycle b3. Also, the first network device may determine the reception scheduling cycle when the test packet is received on its own device, and designates the reception scheduling cycle as Current.

[0070] Based on this, compare Current and Anchor. If Current exceeds the reasonable jitter range of Anchor, it is determined that it is necessary to adjust the initial time length of the scheduling cycle. If Current does not exceed the reasonable jitter range of Anchor, it may be determined that there is no need to adjust the initial time length of the scheduling cycle.

[0071] For example, assume that the number of scheduling cycles is d (d > 7), that is, there are a total of d CQs, and d scheduling cycles and d CQs correspond one-to-one. The target scheduling cycle is Anchor, the reasonable jitter range is three scheduling cycles, and the reception scheduling cycle is Current. Based on this, the adjustment direction of the initial time length (that is, whether to perform an increase adjustment or a decrease adjustment on the initial time length) and the adjustment amount (that is, the number of interval cycles TsNum between the reception scheduling cycle and the target scheduling cycle) may be determined in the following steps.

[0072] In step S11, calculate the adjustment cycle number Adjust using the following formula: Adjust = (Current + d - Anchor) mod d.

[0073] In step S12, when Adjust is greater than d / 2, it is determined that the adjustment direction of the initial time length is forward adjustment, and the adjustment amount is (d - Adjust) scheduling cycles. When Adjust is not greater than d / 2, it is determined that the adjustment direction of the initial time length is backward adjustment, and the adjustment amount is Adjust scheduling cycles.

[0074] Here, forward adjustment indicates decreasing the initial time length of the scheduling cycle. The adjustment amount is (d - Adjust) scheduling cycles, and the number of interval cycles TsNum is d - Adjust. Backward adjustment indicates increasing the initial time length of the scheduling cycle. The adjustment amount is Adjust scheduling cycles, and the number of interval cycles TsNum is Adjust.

[0075] In step S13, the value of the time length adjustment amount Jitter_Adjustment is set. The absolute value of Jitter_Adjustment may be set globally, such as 1000 for example. Also, the positive or negative of Jitter_Adjustment may be determined based on the adjustment direction. For example, when the adjustment direction of the initial time length is forward adjustment, that is, when it is necessary to decrease the initial time length of the scheduling cycle, Jitter_Adjustment is a negative value, and the sign is "-". When the adjustment direction of the initial time length is backward adjustment, that is, when it is necessary to increase the initial time length of the scheduling cycle, Jitter_Adjustment is a positive value, and the sign is "+".

[0076] In step S14, based on the number of interval cycles TsNum and the time length adjustment amount Jitter_Adjustment, the total adjustment number Adjust_Counter of the scheduling cycle is determined. The specific determination method can refer to the above embodiments, and the description is omitted here.

[0077] In a possible embodiment, in order to support the adjustment function of the scheduling cycle of the deterministic network, in this embodiment, the configuration and functions of the network device (in this embodiment, taking the configuration and functions of the first network device as an example, the configurations and functions of other network devices are similar) may be as follows.

[0078] In Method 1, as shown in FIG. 7A, the first network device may include a hardware timer and a deterministic transfer unit. The deterministic transfer unit may include a transfer module, a session management module, and a scheduling cycle management module. In this method, the hardware timer is used to receive a clock input signal. The hardware timer determines the clock signal accumulation number based on the clock input signal, and generates a trigger signal when the clock signal accumulation number reaches a second clock count number corresponding to the target time length. The generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle. Here, the interval between two adjacent trigger signals generated by the hardware timer is the target time length.

[0079] 1. Session management module: The session management module is used to establish a session with the second network device. The function of this session is that the second network device periodically sends test packets to the first network device through the session. The transmission cycle T of the test packet is set according to the error accumulation speed, which is not limited here. The adjustment process of the scheduling cycle of the deterministic network is triggered by the test packet. Of course, in actual applications, the adjustment process of the scheduling cycle of the deterministic network may also be triggered by data packets belonging to the deterministic flow.

[0080] The session management module may receive scheduling cycle information from the transfer module, and the scheduling cycle information may include, but is not limited to, Temp_CSQF_Jiffies, a node identifier, and CSQF parameters when the transfer module receives a test packet. Here, Temp_CSQF_Jiffies represents the value of the global count (CSQF_Jiffies) of the scheduling cycle for determining the current scheduling cycle of the first network device. For example, when Temp_CSQF_Jiffies is 1, it represents the first scheduling cycle, for example, scheduling cycle b0. When Temp_CSQF_Jiffies is 2, it represents the second scheduling cycle, for example, scheduling cycle b1. The same applies hereinafter. The node identifier represents the node identifier of the second network device. The CSQF parameter may include egress interface information, that is, egress interface information corresponding to the test packet.

[0081] The session management module may maintain a session information table. The session information table includes, but is not limited to, the mapping relationship between UpNodeId, InterfaceId, and Anchor. Here, UpNodeId represents the node identifier of the second network device, and may be manually set by the user as long as it is unique, or may be a unique identifier of the device such as an IP address. InterfaceId represents the interface identifier of the first network device, and may be manually set by the user.

[0082] An Anchor represents an identifier of a scheduling cycle and is used to represent a related scheduling cycle corresponding to a specified scheduling cycle of a second network device. That is, after a packet transmitted by the second network device in the specified scheduling cycle arrives at the first network device, the packet should be stored in a CQ corresponding to the related scheduling cycle.

[0083] Here, the mapping relationship between the specified scheduling cycle and the related scheduling cycle, that is, the mapping relationship between the scheduling cycle of the second network device and the scheduling cycle of the first network device, may be set in advance or determined using some algorithm. There is no particular limitation on the method for obtaining the mapping relationship.

[0084] In this embodiment, the specified scheduling cycle of the second network device is set as scheduling cycle a0, and the related scheduling cycle of the first network device is set as scheduling cycle b3. Based on this, the Anchor in the session information table represents the identifier of scheduling cycle b3, that is, scheduling cycle b3 can be known from the value of Anchor.

[0085] After receiving the scheduling cycle information from the transfer module, the session management module may query the session information table using the node identifier and the egress interface information as indexes, obtain the Anchor value, and determine the related scheduling cycle based on the Anchor value. When Anchor represents the identifier of scheduling cycle b3, the related scheduling cycle is determined to be scheduling cycle b3 corresponding to the scheduling cycle a0 of the second network device.

[0086] Based on the transmission scheduling cycle of the second network device, the specified scheduling cycle of the second network device, and the related scheduling cycle of the first network device, the target scheduling cycle corresponding to the transmission scheduling cycle on the first network device can be determined. For example, the number of interval cycles between the transmission scheduling cycle and the specified scheduling cycle may be equal to the number of interval cycles between the target scheduling cycle and the related scheduling cycle. For example, if the transmission scheduling cycle of the second network device is scheduling cycle a0, that is, when the test packet is transmitted in scheduling cycle a0, it indicates that the transmission scheduling cycle and the specified scheduling cycle of the second network device are the same. Therefore, it is determined that the target scheduling cycle and the related scheduling cycle of the first network device are the same, that is, the target scheduling cycle is scheduling cycle b3.

[0087] As described above, the session management module can determine the target scheduling cycle, such as scheduling cycle b3.

[0088] After receiving the scheduling cycle information from the transfer module, the session management module may determine the reception scheduling cycle of the first network device based on Temp_CSQF_Jiffies in the scheduling cycle information. The reception scheduling cycle is denoted as Current, indicating that the first network device receives the test packet in the reception scheduling cycle.

[0089] Based on the target scheduling cycle Anchor and the received scheduling cycle Current, the session management module determines parameters such as the number of adjustment cycles Adjust, the adjustment direction, the number of interval cycles TsNum, the time length adjustment amount Jitter_Adjustment, and the total adjustment integer Adjust_Counter using steps S11 to S14, which will be omitted here for explanation.

[0090] 2. Hardware timer: The hardware timer is a high-precision hardware timer inside the CPU and can generate a trigger signal based on the set parameters. The input of the hardware timer is the clock input signal of the system clock. When the frequency of the system clock is 1G, that is, each tick is 1ns, it indicates that one clock input signal is generated every 1ns. The hardware timer can receive one clock input signal every 1ns and can determine the accumulated number of clock signals based on the clock input signal. That is, every time a clock input signal is received, 1 is added to the accumulated number of clock signals.

[0091] The scheduling cycle management module may distribute setting parameters (e.g., count value) to the hardware timer. When the actual time length of the scheduling cycle is the initial time length, the first clock count number corresponding to the initial time length is used as the count value. For example, the first clock count number is 30000. Based on this, every time the accumulated number of clock signals reaches the first clock count number, the hardware timer generates a trigger signal and outputs it to the scheduling cycle management module. Since the trigger signal is generated based on the first clock count number, the interval between two adjacent trigger signals coincides with the first clock count number, that is, the interval between two adjacent trigger signals is the initial time length. Also, when the actual time length of the scheduling cycle is the target time length, the second clock count number corresponding to the target time length can be used as the count value. For example, the second clock count number is 29000 or 31000. Based on this, every time the accumulated number of clock signals reaches the second clock count number, the hardware timer generates a trigger signal and outputs it to the scheduling cycle management module. Since the trigger signal is generated based on the second clock count number, the interval between two adjacent trigger signals is the target time length.

[0092] Exemplarily, for the trigger signal generated by the hardware timer, the generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle. The trigger signal may be an interrupt signal or another type of signal as long as the start time and end time of the scheduling cycle can be determined based on the trigger signal, and is not particularly limited.

[0093] 3. Transfer Module: The transfer module receives test packets sent from a second network device, obtains the node identifier and CSQF parameters (such as egress interface information corresponding to the test packet) of the second network device from the test packets, obtains Temp_CSQF_Jiffies from the scheduling cycle management module, constructs scheduling cycle information with the node identifier, the CSQF parameters, and Temp_CSQF_Jiffies, and is used to send the scheduling cycle information to the session management module. The session management module determines parameters such as Adjust_Counter and Jitter_Adjustment based on the scheduling cycle information. For the specific process, reference can be made to the related functions of the session management module.

[0094] 4. Scheduling Cycle Management Module: The scheduling cycle management module receives a trigger signal generated by a hardware timer and is used to update Temp_CSQF_Jiffies every time the trigger signal is received. For example, when the trigger signal is received for the first time, Temp_CSQF_Jiffies is updated to 1, representing the first scheduling cycle; when the trigger signal is received for the second time, Temp_CSQF_Jiffies is updated to 2, representing the second scheduling cycle. The same applies hereinafter.

[0095] The scheduling cycle management module obtains parameters such as Jitter_Adjustment and Adjust_Counter from the session management module, determines setting parameters (such as count values) based on Jitter_Adjustment and Adjust_Counter, distributes the count values to the hardware timer, and adjusts the count value of the hardware timer.

[0096] For example, assuming that the first clock count corresponding to the initial time length is 30000, when the actual time length of the scheduling cycle is the initial time length, the scheduling cycle management module distributes the count value 30000 to the hardware timer.

[0097] After the actual time length of the scheduling cycle is updated to the target time length, if Jitter_Adjustment is "+1000", the scheduling cycle management module distributes the count value 31000 to the hardware timer; if Jitter_Adjustment is "-1000", the scheduling cycle management module distributes the count value 29000 to the hardware timer.

[0098] After the updated count value 31000 or 29000 is distributed to the hardware timer, assuming Adjust_Counter is 60, the scheduling cycle management module redistributes the count value 30000 to the hardware timer after continuously receiving 60 trigger signals until the actual time length of the scheduling cycle is updated to the initial time length and until the next update of the actual time length of the scheduling cycle.

[0099] Exemplarily, the process of adjusting the count value can be executed in the following steps as shown in FIG. 7B.

[0100] In step S21, if Adjust_Counter is 0, step S27 is executed; otherwise, step S22 is executed.

[0101] In step S22, if Jitter_Adjustment is 0, step S24 is executed; otherwise, step S23 is executed.

[0102] In step S23, write the count value of the hardware timer to C + Jitter_Adjustment to adjust the actual time duration of the scheduling cycle. That is, update the actual time duration of the scheduling cycle from the initial time duration to the target time duration. Note that Jitter_Adjustment here can be either a positive value or a negative value. After writing the count value of the hardware timer to C + Jitter_Adjustment, Jitter_Adjustment can be set to 0 and step S26 can be executed.

[0103] According to the actual situation, the adjustment process of the scheduling cycle may be extended not only to the adjustment of one scheduling cycle but also to multiple scheduling cycles. Therefore, after adjusting the first scheduling cycle, since the scheduling cycle is not immediately restored, after setting Jitter_Adjustment to 0, step S26 is executed instead of step S24.

[0104] In step S24, if Adjust_Counter is greater than 1, execute step S26; otherwise, execute step S25.

[0105] In step S25, write the register of the hardware timer to Jitter_Adjustment, restore the scheduling cycle, and execute step S26, that is, restore the actual time duration to the initial time duration and write the count value of the hardware timer to C.

[0106] In step S26, decrement Adjust_Counter by 1 and return to step S21.

[0107] In step S27, perform other processing of the timer interrupt service.

[0108] In Method 2, as shown in FIG. 7C, the first network device may include a hardware module (e.g., a hardware timer) and a deterministic transfer unit. The deterministic transfer unit may include a transfer module, a session management module, and a scheduling cycle management module. The hardware module may include a register and is used to receive a clock input signal. Each time the hardware module receives a clock input signal, it determines a clock signal accumulation number based on the clock input signal and stores the clock signal accumulation number in the register of the hardware module. At the start of the current scheduling cycle, the transfer module determines a target number of clock signals for the current scheduling cycle based on a second clock count number corresponding to a target time duration. The transfer module queries the register for the clock signal accumulation number, and if the obtained clock signal accumulation number reaches the target number of clock signals, it determines that the current scheduling cycle has ended and updates the next scheduling cycle of the current scheduling cycle to the current scheduling cycle.

[0109] 1. Hardware Timer: The input of the hardware timer is the clock input signal of the system clock. When the frequency of the system clock is 1G, the hardware timer can receive one clock input signal every 1 ns. Each time the hardware timer receives a clock input signal, it determines a clock signal accumulation number based on the clock input signal. That is, each time a clock input signal is received, 1 is added to the clock signal accumulation number. Each time a clock input signal is received, the clock signal accumulation number can be stored in the register of the hardware timer.

[0110] Compared with Method 1, in Method 2, the hardware timer only needs to store the clock signal accumulation number in the register and does not need to generate a trigger signal and output it to the scheduling cycle management module, and the scheduling cycle management module also does not need to distribute setting parameters (e.g., a count value) to the hardware timer.

[0111] 2. Session Management Module: The session management module receives scheduling cycle information from the transfer module. The scheduling cycle information includes, but is not limited to, Temp_CSQF_Jiffies, node identifier, and CSQF parameters. The session management module queries the session information table based on the scheduling cycle information, obtains the relevant scheduling cycle, and determines the target scheduling cycle. The session management module determines the received scheduling cycle based on Temp_CSQF_Jiffies. Based on the target scheduling cycle and the received scheduling cycle, parameters such as the number of adjustment cycles Adjust, adjustment direction, number of interval cycles TsNum, time length adjustment amount Jitter_Adjustment, and total adjustment integer Adjust_Counter are determined.

[0112] 3. Transfer Module: The transfer module receives the test packet sent from the second network device, obtains the node identifier and CSQF parameters of the second network device from the test packet, obtains Temp_CSQF_Jiffies from the scheduling cycle management module, constructs scheduling cycle information with the node identifier, the CSQF parameters, and Temp_CSQF_Jiffies, and is used to send the scheduling cycle information to the session management module.

[0113] Regarding the current scheduling cycle, at the start of the current scheduling cycle, assume that the initial number of clock signals is x (indicating that the accumulated number of clock signals stored in the register of the hardware timer is x). Based on this, the transfer module can determine the target number of clock signals for the current scheduling cycle. For example, when the actual time duration of the scheduling cycle is the initial time duration, the transfer module determines the first clock count number corresponding to the initial time duration, such as 30000, and sets the sum of the initial number x and the first clock count number as the target number of clock signals for the current scheduling cycle. When the actual time duration of the scheduling cycle is updated to the target time duration, the transfer module determines the second clock count number corresponding to the target time duration, such as 29000 or 31000, and sets the sum of the initial number x and the second clock count number as the target number of clock signals for the current scheduling cycle.

[0114] Based on the target number of clock signals for the current scheduling cycle, the transfer module queries the register of the hardware timer for the accumulated number of clock signals. If the obtained accumulated number of clock signals has not reached the target number of clock signals, the current scheduling cycle is maintained. If the obtained accumulated number of clock signals has reached the target number of clock signals, it is determined that the current scheduling cycle has ended, the next scheduling cycle of the current scheduling cycle is updated to the current scheduling cycle, and the target number of clock signals is set as the initial number x of the clock signals for the scheduling cycle.

[0115] Here, the scheduling cycle management module may distribute the setting parameters to the transfer module. For example, it distributes the first clock count number corresponding to the initial time duration or the second clock count number corresponding to the target time duration to the transfer module. The transfer module determines the target number of clock signals for the current scheduling cycle based on the setting parameters.

[0116] The transfer module may generate a trigger signal when the accumulated number of clock signals reaches the target number of clock signals, and output it to the scheduling cycle management module. Here, for the trigger signal generated by the transfer module, the generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle.

[0117] 4. Scheduling cycle management module: The scheduling cycle management module receives the trigger signal generated by the transfer module and is used to update Temp_CSQF_Jiffies every time the trigger signal is received. The scheduling cycle management module can obtain parameters such as Jitter_Adjustment and Adjust_Counter from the session management module, determine the setting parameters based on Jitter_Adjustment and Adjust_Counter, and distribute the setting parameters to the transfer module. The implementation method of the scheduling cycle management module can refer to Method 1 and will not be repeated here.

[0118] In Method 3, as shown in FIG. 7D, the first network device may include a cycle adjustment unit and a deterministic transfer unit. The deterministic transfer unit may include a transfer module, a session management module, and a scheduling cycle management module. The cycle adjustment unit may include control logic (e.g., FPGA, CPLD, ASIC), a first register, a second register, and a third register. The control logic is used to receive a clock input signal, the first register is used to store a first clock count corresponding to an initial time length, the second register is used to store a time length adjustment amount Jitter_Adjustment, and the third register is used to store a total adjustment integer Adjust_Counter of a scheduling cycle. Here, the most significant bit of the second register may be a sign bit, where 1 represents "-" and 0 represents "+". The remaining bits other than the most significant bit of the second register represent |Jitter_Adjustment|.

[0119] In this method, the control logic determines a second clock count corresponding to a target time length based on the first clock count and the time length adjustment amount, determines a clock signal accumulation count based on the clock input signal, and generates a trigger signal when the clock signal accumulation count reaches the second clock count. Here, the generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle. After generating Adjust_Counter trigger signals based on the second clock count, the control logic continues to determine the clock signal accumulation count based on the clock input signal and generates a trigger signal when the clock signal accumulation count reaches the first clock count corresponding to the initial time length.

[0120] 1. Session Management Module: The session management module receives scheduling cycle information from the transfer module. The scheduling cycle information includes, but is not limited to, Temp_CSQF_Jiffies, node identifier, and CSQF parameters. The session management module queries the session information table based on the scheduling cycle information, obtains the relevant scheduling cycle, and determines the target scheduling cycle. The session management module determines the received scheduling cycle based on Temp_CSQF_Jiffies. Based on the target scheduling cycle and the received scheduling cycle, parameters such as the adjustment cycle number Adjust, adjustment direction, interval cycle number TsNum, time length adjustment amount Jitter_Adjustment, and total adjustment integer Adjust_Counter are determined.

[0121] As an example, the session management module can write Jitter_Adjustment to the second register of the cycle adjustment unit and write Adjust_Counter to the third register of the cycle adjustment unit.

[0122] 2. Transfer Module: The transfer module receives the test packet sent from the second network device, obtains the node identifier and CSQF parameters of the second network device from the test packet, obtains Temp_CSQF_Jiffies from the scheduling cycle management module, constructs scheduling cycle information with the node identifier, the CSQF parameters, and Temp_CSQF_Jiffies, and is used to send the scheduling cycle information to the session management module.

[0123] 3. Scheduling Cycle Management Module: The scheduling cycle management module receives the trigger signal generated by the control logic and is used to update Temp_CSQF_Jiffies every time the trigger signal is received. The scheduling cycle management module determines the first clock count corresponding to the initial time length and writes the first clock count to the first register.

[0124] 4. Control Logic: The input of the control logic is the clock input signal of the system clock. When the frequency of the system clock is 1G, one clock input signal is received every 1ns, and the clock signal accumulation number is determined based on the clock input signal. That is, every time the clock input signal is received, 1 is added to the clock signal accumulation number.

[0125] In the initial state, the actual time length of the scheduling cycle is the initial time length, the first register stores the first clock count, and the second and third registers are empty. Based on this, every time the clock signal accumulation number reaches the first clock count, the control logic generates a trigger signal and outputs it to the scheduling cycle management module. The interval between two adjacent trigger signals generated by the control logic is the initial time length.

[0126] When the actual time length of the scheduling cycle is updated to the target time length, the session management module writes Adjust_Counter to the third register and Jitter_Adjustment to the second register. After the control logic knows that data has been written to the second and third registers, it reads the first clock count number from the first register, reads Jitter_Adjustment from the second register, and determines the second clock count number corresponding to the target time length based on the first clock count number and Jitter_Adjustment. Based on this, every time the accumulated number of clock signals reaches the second clock count number, the control logic generates a trigger signal and outputs it to the scheduling cycle management module. The interval between two adjacent trigger signals generated by the control logic is the target time length.

[0127] Exemplarily, for the trigger signal generated by the control logic, the generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle. The trigger signal may be an interrupt signal or another type of signal as long as the start time and end time of the scheduling cycle can be determined based on the trigger signal, and is not particularly limited.

[0128] Exemplarily, the control logic reads Adjust_Counter from the third register, generates Adjust_Counter trigger signals based on the second clock count number, and then updates the actual time length of the scheduling cycle to the initial time length, that is, it may return from the target time length to the initial time length. Therefore, the control logic reads the first clock count number from the first register and generates a trigger signal based on the first clock count number. For example, every time the accumulated number of clock signals reaches the first clock count number, the control logic generates a trigger signal and outputs it to the scheduling cycle management module. The interval between two adjacent trigger signals is the initial time length.

[0129] Exemplarily, as shown in FIG. 7E, the processing flow of the control logic may include the following steps.

[0130] In step S31, after initialization by power-on, the first clock count number is written into the first register, and the control logic initializes AdjustEvent (adjustment event) to 0. The control logic reads the first clock count number from the first register and writes it into CounterValue (count value), and generates a trigger signal with CounterValue. The trigger signal may be an interrupt signal or another type of signal. Hereinafter, the interrupt signal will be taken as an example for explanation.

[0131] In step S32, during execution, the control logic determines whether a write to the second register has occurred. If there is no write, it continues to determine whether a write to the second register has occurred. If there is a write, the control logic modifies AdjustEvent to 1. Here, the session management module may write Jitter_Adjustment to the second register and write Adjust_Counter to the third register. Therefore, the control logic can detect a write to the second register. The session management module may first execute a write to the second register and then execute a write to the third register after the write to the second register is completed.

[0132] In step S33, when the interrupt signal is generated, the control logic determines whether AdjustEvent is 1. If AdjustEvent is 1, it sets AdjustEvent to 0 and executes step S34. If AdjustEvent is not 1, it executes step S36.

[0133] In step S34, the control logic reads Adjust_Counter from the third register and writes Adjust_Counter to AdjustCount (adjustment integer). The control logic reads the first clock count number BaseCounter from the first register, reads Jitter_Adjustment from the second register, and executes step S35.

[0134] In step S35, if the most significant bit of Jitter_Adjustment is 1, the control logic can write, as the second clock count number, to CounterValue a value obtained by subtracting Jitter_Adjustment excluding the most significant bit from BaseCounter. If the most significant bit of Jitter_Adjustment is 0, the control logic can write, as the second clock count number, to CounterValue a value obtained by adding Jitter_Adjustment excluding the most significant bit to BaseCounter.

[0135] In step S36, if AdjustCount is not 0, the control logic generates an interrupt signal based on CounterValue (that is, generates an interrupt signal when the accumulated number of clock signals reaches the value of CounterValue) and decrements AdjustCount by 1. If AdjustCount is 0, the control logic reads the first clock count number from the first register and writes it to CounterValue, and generates a trigger signal with CounterValue.

[0136] In Method 4, as shown in FIG. 7F, the first network device may include a hardware module (e.g., control logic) and a deterministic transfer unit. The control logic may include registers and is used to receive a clock input signal. Each time the control logic receives a clock input signal, it determines a clock signal accumulation number based on the clock input signal and stores the clock signal accumulation number in the register. The embodiments of Method 4 are similar to Method 2 and only need to replace the hardware timer with control logic, so it will not be repeated here.

[0137] As can be seen from the above technical solutions, in the embodiments of the present invention, packet transmission in a deterministic network is realized based on CSQF, and the actual time length of the scheduling cycle of the deterministic network is adjusted (i.e., adjusted from the initial time length to the target time length), thereby dynamically controlling the scheduling cycle of the deterministic network. Thereby, CSQF does not depend on strict frequency synchronization and can adapt to fluctuations in link transmission delay, greatly improving the adaptability of CSQF in a wide-area network. By implementing CSQF, a deterministic transmission capacity can be provided without affecting ongoing transmission services. By detecting and quantifying the cumulative error of cycle mapping between adjacent network devices, a mechanism for adjusting the cumulative error is established, enabling the process of adjusting the cumulative error to be performed smoothly. When the cumulative error reaches a certain threshold, the cumulative error is converted into the required adjustment amount, smoothly realizing the adjustment of the time lengths of multiple scheduling cycles. When the adjustment number is reached, the time length of the scheduling cycle is reset to the initial time length.

[0138] Based on the same idea as the above method, the embodiments of the present invention further provide a network device, which includes a processor and a machine-readable storage medium. The machine-readable storage medium stores machine-executable instructions executable by the processor, and the processor is used to execute the machine-executable instructions to implement the method for adjusting the scheduling cycle disclosed in the above embodiments of the present invention.

[0139] Based on the same idea as the above method, an embodiment of the present invention further provides a machine-readable storage medium storing a plurality of computer instructions, and when the computer instructions are executed by a processor, the method for adjusting the scheduling cycle disclosed in the above embodiment of the present invention can be implemented.

[0140] Here, the above machine-readable storage medium may be any electronic, magnetic, optical or other physical storage device, and can contain or store information such as executable instructions and data. For example, the machine-readable storage medium may be a random access memory (RAM), volatile memory, non-volatile memory, flash memory, storage drive (such as a hard drive), solid state drive, any storage disk (such as an optical disk, DVD, etc.), or a similar storage medium, or a combination thereof.

[0141] The system, device, module or unit described in the above embodiment may specifically be realized by a computer chip, an entity, or a product having some functions. A typical realization device is a computer, and the specific form of the computer may be a personal computer, a laptop computer, a mobile phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email sending and receiving device, a game console, a tablet, a wearable device, or any combination of several of these devices.

[0142] For the convenience of description, when the above device is described, it is divided into various units according to functions and described respectively. Of course, when implementing the present invention, the functions of each unit can also be realized by the same or multiple software and / or hardware.

[0143] As will be understood by those skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an embodiment consisting of only hardware, an embodiment consisting of only software, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may be in the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0144] The present invention will be described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, may be realized by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device implement the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0145] Also, these computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction apparatus for realizing the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0146] These computer program instructions may be loaded onto a computer or other programmable data processing device, thereby causing a series of operational steps to be executed on the computer or other programmable device to generate processing implemented by the computer, and thus the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in one or more flows of the flowchart and / or one or more blocks of the block diagram.

[0147] The above are only embodiments of the present invention and do not limit the present invention. For those skilled in the art, various modifications and changes are possible to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle scope of the present invention should all be included in the scope of the claims of the present invention.

Claims

1. A method for adjusting a scheduling cycle, which is applied to a first network device and, after receiving a packet sent from a second network device, determines a transmission scheduling cycle when the packet is sent on the second network device, and determines a reception scheduling cycle when the packet is received on the first network device; determining a target scheduling cycle corresponding to the transmission scheduling cycle on the first network device; when it is determined that it is necessary to adjust the initial time length of the scheduling cycle based on the number of interval cycles between the reception scheduling cycle and the target scheduling cycle, adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length. A method for adjusting a scheduling cycle, characterized by the above.

2. The step of determining a target scheduling cycle corresponding to the transmission scheduling cycle on the first network device includes: obtaining a node identifier of the second network device and egress interface information corresponding to the packet; querying a set session information table based on the node identifier and the egress interface information to obtain a related scheduling cycle corresponding to a specified scheduling cycle of the second network device, where the session information table includes a mapping relationship between a node identifier, egress interface information, and a related scheduling cycle; determining a target scheduling cycle corresponding to the transmission scheduling cycle on the first network device based on the transmission scheduling cycle, the related scheduling cycle, and the specified scheduling cycle. The method according to claim 1, characterized by the above.

3. The step of determining that it is necessary to adjust the initial time length of the scheduling cycle based on the number of interval cycles between the reception scheduling cycle and the target scheduling cycle includes: When the reception scheduling cycle is before the target scheduling cycle and the number of interval cycles is greater than a first threshold, it is determined that it is necessary to adjust the initial time length of the scheduling cycle. Including the step of determining that when the reception scheduling cycle is after the target scheduling cycle and the number of interval cycles is greater than a second threshold, it is necessary to adjust the initial time length of the scheduling cycle. The method according to claim 1, characterized in that.

4. The step of adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length is as follows. When the reception scheduling cycle is before the target scheduling cycle, a decrease adjustment is performed on the initial time length based on a set time length adjustment amount to obtain an adjusted target time length. Including the step of, when the reception scheduling cycle is after the target scheduling cycle, performing an increase adjustment on the initial time length based on the time length adjustment amount to obtain an adjusted target time length. The method according to claim 1, characterized in that.

5. The step of adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length is as follows. Based on a first clock count corresponding to the initial time length, a set time length adjustment amount, and the number of interval cycles, determining a total adjustment integer K of the scheduling cycle, and updating the actual time lengths of K consecutive scheduling cycles on the first network device to the target time length, including the step of. After updating the actual time lengths of K consecutive scheduling cycles on the first network device to the target time length. Further including the step of updating the actual time length of the scheduling cycle on the first network device from the target time length to the initial time length. The method according to claim 1, characterized in that.

6. The first network device includes a hardware timer for receiving a clock input signal, and the step of adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length is as follows. The step of determining the clock signal accumulation number based on the clock input signal by the hardware timer and generating a trigger signal when the clock signal accumulation number reaches a second clock count number corresponding to the target time length is included, wherein the generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle, The method according to any one of claims 1 to 5, characterized in that.

7. The first network device includes control logic for receiving a clock input signal, a first register for storing a first clock count number corresponding to the initial time length, and a second register for storing a set time length adjustment amount. The step of adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length is as follows: The control logic determines a second clock count number corresponding to the target time length based on the first clock count number and the time length adjustment amount, determines the clock signal accumulation number based on the clock input signal, and includes the step of generating a trigger signal when the clock signal accumulation number reaches the second clock count number. wherein the generation time of the trigger signal is the end time of the current scheduling cycle, and the generation time of the trigger signal is the start time of the next scheduling cycle of the current scheduling cycle, The method according to any one of claims 1 to 5, characterized in that.

8. The first network device includes a third register for storing the total adjustment integer K of the scheduling cycle. Further, After the control logic generates K trigger signals based on the second clock count number, it continues to determine the clock signal accumulation number based on the clock input signal, and includes the step of generating a trigger signal when the clock signal accumulation number reaches the first clock count number corresponding to the initial time length. The method according to claim 7, characterized in that.

9. The first network device includes a hardware module for receiving a clock input signal and a transfer module. The step of adjusting the actual time length of the scheduling cycle on the first network device from the initial time length to the target time length is as follows: Each time the hardware module receives a clock input signal, determining a clock signal accumulation number based on the clock input signal and storing the clock signal accumulation number in a register of the hardware module; At the start of the current scheduling cycle, the transfer module determines a target number of clock signals for the current scheduling cycle based on a second clock count number corresponding to the target time length; The transfer module queries the register for the clock signal accumulation number. When the obtained clock signal accumulation number reaches the target number of clock signals, it is determined that the current scheduling cycle has ended, and the next scheduling cycle of the current scheduling cycle is updated to the current scheduling cycle. The method according to any one of claims 1 to 5, characterized in that.

10. A network device, comprising a processor and a machine-readable storage medium, The machine-readable storage medium stores machine-executable instructions executable by the processor, The processor is used to execute machine-executable instructions so as to implement the method according to any one of claims 1 to 9. A network device characterized by this.

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