Split Semiconductor Wafer Camera System and Method

Abstract

To provide a method and a system for imaging a cleaved wafer.SOLUTION: An imaging system 110 for imaging a semiconductor wafer 104 includes: a shroud panel 126 defining a dark box 118; a camera 146 for imaging the semiconductor wafer 104 disposed in the dark box 118; and an illumination panel 144 for directing diffused light to the semiconductor wafer 104. Part of the diffused light is reflected by the semiconductor wafer 104, and the camera 146 images the semiconductor wafer 104 by detecting the reflected diffused light.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority based on U.S. Provisional Patent Application No. 62 / 706,894 filed on September 16, 2020, U.S. Provisional Patent Application No. 62 / 706,895 filed on September 16, 2020, and U.S. Provisional Patent Application No. 62 / 706,897 filed on September 16, 2020. All disclosures of the applications on which the priority is based are hereby incorporated by reference in their entirety into this application.

[0002] The field of the present disclosure relates to methods and systems for imaging semiconductor substrates, particularly for imaging cleaved wafers.

Background Art

[0003] Semiconductor wafers are typically used in the manufacture of integrated circuit (IC) chips on which circuits are printed. First, circuits are printed in a miniaturized state on the surface of the wafer, and then the wafer is diced into circuit chips. During the manufacturing process, the wafers are processed and polished so that the front and back surfaces of each wafer have mirror - like reflective surfaces. To reduce manufacturing costs, the wafers are imaged during the manufacturing process to detect defects on the surface of the wafers before the wafers are further processed.

[0004] Some imaging systems used in quality control systems image manufactured articles by reflecting light off the manufactured articles and detecting the reflected light with a camera. The camera typically images non - specular reflective surfaces of the manufactured articles. However, since the surface of the wafer is specular, the light directed at the wafer needs to be uniform diffused light. Otherwise, the image captured by the imaging system will be a reflection image of the light source rather than a feature of the wafer.

[0005] There is also an imaging system for imaging the reflective surface of a wafer. However, since the imaging system typically includes a large parabolic mirror, the size of the imaging system becomes large, and the location where the imaging system can be placed within the manufacturing process is limited. Specifically, due to the parabolic mirror, the height and width of the imaging system are significantly increased. The imaging system can only be placed in a location where there is sufficient space to accommodate a large-volume system. A location suitable for the system may interfere with the manufacturing process.

[0006] This section is intended to introduce readers to various aspects of technologies that may be related to the various aspects of the present disclosure described and / or claimed below. This discussion is considered useful in providing readers with background information for a better understanding of the various aspects of the present disclosure. Therefore, it should be understood that these descriptions should be read from this perspective and do not admit prior art.

Summary of the Invention

[0007] One aspect of the present disclosure relates to a semiconductor wafer imaging system for imaging a semiconductor wafer. The system includes a shroud panel defining a dark box, a camera disposed in the dark box for imaging the semiconductor wafer, and an illumination panel for directing diffused light onto the semiconductor wafer. A part of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

[0008] Other aspects of the present disclosure relate to a camera obscura for imaging a semiconductor wafer. The camera obscura includes a shroud panel that defines an upper chamber and a lower chamber. A support plate separates the upper chamber from the lower chamber. A bottom shroud panel at least partially defines the lower chamber and defines a wafer opening. The support plate defines a camera opening. The camera obscura further includes a camera disposed in the upper chamber for imaging the semiconductor wafer and an illumination panel for directing diffused light onto the semiconductor wafer. The diffused light is transmitted through the wafer opening to the semiconductor wafer, and a portion of the diffused light is reflected by the semiconductor wafer through the wafer opening and the camera opening. The camera images the semiconductor wafer by detecting the reflected diffused light.

[0009] Still other aspects of the present disclosure relate to a semiconductor wafer processing system for processing a semiconductor wafer. The system includes a semiconductor wafer processing station for processing the semiconductor wafer and a semiconductor wafer imaging system for imaging the semiconductor wafer after the semiconductor wafer processing station has processed the semiconductor wafer. The semiconductor wafer imaging system includes a shroud panel that defines a camera obscura, a camera disposed in the camera obscura for imaging the semiconductor wafer, and an illumination panel for directing diffused light onto the semiconductor wafer. A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

[0010] Still other aspects of the present disclosure relate to a semiconductor wafer processing system for processing semiconductor wafers. The system includes a first semiconductor wafer processing station for processing a first semiconductor wafer, and includes a first manufacturing line for processing the first semiconductor wafer. The system further includes a second semiconductor wafer processing station for processing a second semiconductor wafer, and further includes a second manufacturing line for processing the second semiconductor wafer. The second manufacturing line intersects the first manufacturing line at a common location. The system further includes a semiconductor wafer imaging system for imaging the first semiconductor wafer and the second semiconductor wafer, disposed within the common location where the first manufacturing line and the second manufacturing line intersect. The semiconductor wafer imaging system images the first semiconductor wafer and the second semiconductor wafer after the first semiconductor wafer processing station and the second semiconductor wafer processing station have processed the first semiconductor wafer and the second semiconductor wafer. The semiconductor wafer imaging system includes a shroud panel defining a light-tight box, a camera disposed within the light-tight box for imaging the semiconductor wafer, and a lighting panel for directing diffused light onto the semiconductor wafer. A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

[0011] Still other aspects of the present disclosure relate to a semiconductor wafer imaging station of a semiconductor wafer processing system for imaging semiconductor wafers. The station includes a frame, a positioning plate attached to the frame, and a light-tight box movably attached to the positioning plate. The light-tight box includes a shroud panel defining the light-tight box, a camera disposed within the light-tight box for imaging the semiconductor wafer, and a lighting panel for directing diffused light onto the semiconductor wafer. A portion of the diffused light is reflected by the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light. The station further includes an end effector for positioning the semiconductor wafer within the field of view of the camera.

[0012] Still other aspects of the present disclosure relate to a method for detecting defects in a semiconductor wafer. The method includes directing diffused light onto the semiconductor wafer and reflecting the diffused light from the semiconductor wafer. The method further includes detecting the diffused light with a camera, generating an image of the semiconductor wafer, and analyzing the image to detect defects in the semiconductor wafer.

[0013] Still other aspects of the present disclosure relate to a method for processing a semiconductor wafer. The method includes cleaving the semiconductor wafer at a cleaving station, positioning the semiconductor wafer within the field of view of a camera, and directing diffused light onto the semiconductor wafer. The method further includes reflecting the diffused light from the semiconductor wafer, detecting the diffused light with the camera, generating an image of the semiconductor wafer, and analyzing the image to detect defects in the semiconductor wafer.

[0014] Still other aspects of the present disclosure relate to a method for processing a semiconductor wafer using a semiconductor wafer processing system. The semiconductor wafer processing system includes a processing station and a semiconductor wafer imaging station. The method includes processing the semiconductor wafer at the processing station, positioning the semiconductor wafer within the field of view of a camera of the semiconductor wafer imaging station, and directing diffused light onto the semiconductor wafer. The method further includes reflecting the diffused light from the semiconductor wafer, detecting the diffused light with the camera, generating an image of the semiconductor wafer, and analyzing the image to detect defects in the semiconductor wafer.

[0015] Still other aspects of the present disclosure relate to a method for processing a semiconductor wafer using a semiconductor wafer processing system. The semiconductor wafer processing system includes a first manufacturing line, a second manufacturing line, and a semiconductor wafer imaging station disposed within a common location where the first manufacturing line and the second manufacturing line intersect. The first manufacturing line and the second manufacturing line each include a processing station for processing a semiconductor wafer. The method includes: i) processing a first semiconductor wafer at the processing station of the first manufacturing line; ii) positioning the first semiconductor wafer within the field of view of a camera of the semiconductor wafer imaging station; iii) directing diffused light toward the first semiconductor wafer. The method further includes: iv) reflecting the diffused light off the first semiconductor wafer; v) detecting the diffused light with the camera to generate an image of the first semiconductor wafer; vi) analyzing the image to detect defects of the semiconductor wafer. The method further includes: vii) processing a second semiconductor wafer at the processing station of the second manufacturing line; viii) repeating steps ii through vi to image the second semiconductor wafer.

[0016] There are various improvements to the features described in connection with the aspects above. Similarly, further features may be incorporated into the aspects above. These improvements and additional features may exist individually or in any combination. For example, the various features described hereinafter in connection with any of the illustrated embodiments may be incorporated into any of the aspects above, alone or in any combination. BRIEF DESCRIPTION OF THE DRAWINGS

[0017]

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[0018] The specific features of various examples may be shown in one drawing and not in others, which is for convenience. Any feature of any drawing may be referenced and / or claimed in combination with any feature of any other drawing.

[0019] Unless otherwise indicated, the drawings are for the purpose of illustrating the features of the examples of the present disclosure. These features are considered applicable in various systems having one or more examples of the present disclosure. The drawings are not intended to include all conventional features known to those skilled in the art that are required for the implementation of the disclosed examples.

Best Mode for Carrying Out the Invention

[0020] Semiconductor wafers (which may be referred to as "wafers" or "substrates" of semiconductor or silicon) are generally prepared from single crystal ingots (e.g., silicon ingots) formed by a crystal growth process and cut into individual wafers. Suitable crystal growth processes include the Czochralski process, the float zone process, the hydrothermal process, the Bridgman process, the Kyropoulos process, and / or any other crystal growth process. In this specification, semiconductor wafers composed of silicon are referred to, but other materials such as germanium, silicon carbide, silicon germanium, germanium arsenide, and other alloys of group III and group IV elements such as gallium nitride or indium phosphide, or alloys of group II and group VI elements such as cadmium sulfide or zinc oxide may be used to prepare semiconductor wafers. Each semiconductor wafer includes a central axis, a front surface, and a rear surface parallel to the front surface. The front surface and the rear surface are generally perpendicular to the central axis. The front surface and the rear surface are joined by a periphery.

[0021] Semiconductor wafers may be used to prepare composite layer structures. Composite layer structures (e.g., semiconductor-on-insulator, more specifically, silicon-on-insulator (SOI) structures) generally comprise a handleware or handle layer, a device layer, and an insulating (e.g., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, composite layer structures such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz are manufactured by placing two wafers in close contact, bonding them by van der Waals forces, and then strengthening the bond by heat treatment. Annealing converts terminal silanol groups between one interface into siloxane bonds to strengthen the bond.

[0022] After thermal annealing, the bonding structure undergoes further processing to remove a substantial portion of the donor wafer in order to achieve layer transfer. For example, a common method for achieving layer transfer utilizes thermally induced layer separation that is performed after hydrogen implantation. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a predetermined depth below the front surface of the donor wafer. The implanted particles form a cleavage plane in the donor wafer at the predetermined depth where the particles are embedded. The surface of the donor wafer is cleaned to remove other contaminants such as organic compounds or boron compounds that have accumulated on the wafer during the implantation process.

[0023] Next, the front surface of the donor wafer is bonded to the handle wafer to form a bonded wafer via a hydrophilic bonding process. Prior to bonding, the donor wafer and / or the handle wafer are activated by exposing the surface of the wafer to a plasma containing, for example, oxygen or nitrogen. Exposure to the plasma changes the surface structure in a process that is often referred to as surface activation. The activation process makes the surface of one or both of the donor wafer and the handle wafer hydrophilic. The surface of the wafer may be further chemically activated by a wet process such as SC1 cleaning or hydrofluoric acid. The wet process and the plasma activation may be performed in either order, or the wafer may be subjected to only one of the processes. Next, the wafers are pressed against each other and a bond is formed between the wafers. This bond is relatively weak because it is due to van der Waals forces and needs to be strengthened before further processing is performed.

[0024] In a certain process, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonding wafer) is strengthened by heating or annealing the pair of bonding wafers. In a certain process, the wafer bonding may be performed at a low temperature such as about 300 °C to 500 °C. In a certain process, the wafer bonding may be performed at a high temperature such as about 800 °C to 1100 °C. By raising the temperature, covalent bonds are formed between the adjacent surfaces of the donor wafer and the handle wafer, thereby strengthening the bond between the donor wafer and the handle wafer. Simultaneously with the heating or annealing of the bonding wafer, the particles previously implanted in the donor wafer weaken the cleavage plane.

[0025] Next, a part of the donor wafer is separated (i.e., cleaved) from the bonding wafer along the cleavage plane to form an SOI wafer. The bonding wafer may be placed in a fixture, and cleavage may be performed by applying a mechanical force perpendicular to both surfaces of the bonding wafer and pulling to separate a part of the donor wafer from the bonding wafer. According to some methods, a suction cup is used to apply the mechanical force. The separation of a part of the donor wafer is initiated by applying a mechanical wedge to the edge of the bonding wafer at the cleavage plane to cause crack propagation along the cleavage plane. Next, a part of the donor wafer is pulled away from the bonding wafer by the mechanical force applied by the suction cup, thereby forming an SOI wafer.

[0026] In one example, a semiconductor wafer imaging system images a wafer to detect defects in the wafer during the manufacturing process. The imaging system images the wafer after the wafer has been cleaved and detects defects in the wafer formed in any upstream manufacturing process including the cleaving process. When the semiconductor wafer imaging system detects a defect in the wafer, the wafer is removed from the manufacturing process, thereby reducing the wafer manufacturing cost. The wafer has a mirror-like reflective surface, and the semiconductor wafer imaging system images the wafer without imaging the light source reflected by the reflective surface. Specifically, the semiconductor wafer imaging system includes a dark box surrounding the camera and an illumination panel. The dark box minimizes reflections in the semiconductor wafer imaging system, and the illumination panel directs diffused light toward the wafer. The diffused light is reflected by the wafer toward the camera. Since the light generated by the illumination panel is scattered, the camera detects the reflected diffused light but does not image the illumination panel. Thereby, the camera images the wafer but does not image the light source, enabling the controller to analyze the defects in the wafer and reducing the manufacturing cost.

[0027] Referring to FIG. 1, a semiconductor wafer processing system 100 includes a manufacturing line 102 for manufacturing a semiconductor wafer 104. The manufacturing line 102 includes a semiconductor wafer processing station 106 for processing the wafer 104. The semiconductor wafer processing station 106 includes a cleaving station 108 and a semiconductor wafer imaging station or system 110 for imaging the wafer 104. In the illustrated embodiment, the imaging system 110 is disposed above the cleaving station 108 and images the wafer 104 after the wafer 104 has been cleaved by the cleaving station. The imaging system 110 images each wafer 104, and the controller 112 analyzes the image to detect defects in the wafer. If the wafer 104 includes a defect, the wafer is disposed of before further processing, thereby reducing the wafer manufacturing cost.

[0028] Referring to FIG. 2, an alternative semiconductor wafer processing system 114 includes two or more manufacturing lines 102 for manufacturing a wafer 104. Similar to the processing system 100, each manufacturing line 102 includes a processing station 106 that includes a cleaving station 108. The manufacturing lines 102 include a common location 116 where the manufacturing lines intersect. An imaging system 110 is disposed within the common location 116 and images the wafers 104 manufactured by all the manufacturing lines 102 that intersect at the common location. In the illustrated embodiment, the processing system 114 includes two manufacturing lines 102. However, in alternative embodiments, the processing system 114 may include any number of manufacturing lines 102 that enable the processing system 114 to operate as described herein. Also, in the embodiments illustrated in FIGS. 1 and 2, the imaging system 110 is disposed above or immediately downstream of the cleaving station 108. In alternative embodiments, the imaging system 110 may be disposed at any location within the processing systems 100, 114 that enables the processing system to operate as described herein.

[0029] Referring to FIGS. 3 and 4, the imaging system 110 includes a camera obscura 118, an end effector 120, and a positioning plate 122. As described below, the camera obscura 118 includes a camera for imaging the wafer 104. The positioning plate 122 positions the camera obscura 118 at the common location 116, and the end effector 120 positions the wafer 104 under the camera obscura 118 for imaging. The positioning plate 122 is attached to a frame 124, and the camera obscura 118 is movably attached to the positioning plate. The position of the camera obscura 118 can be adjusted by adjusting its position on the positioning plate 122. Also, the end effector 120 is movable relative to the camera obscura 118 so that the position of the wafer 104 can be adjusted during imaging.

[0030] Referring to FIG. 5, the shroud panel 126 defines a light-tight box 118. Specifically, the shroud panel 126 defines an upper chamber 128 and a lower chamber 130. The support plate 132 is disposed within the light-tight box 118 and separates the upper chamber 128 from the lower chamber 130. Also, the bottom shroud 134 defines the bottom 136 of the light-tight box 118. The support plate 132 defines a support plate opening 138, and the bottom shroud 134 defines a bottom shroud opening 140. In the illustrated embodiment, both the support plate opening 138 and the bottom shroud opening 140 are circular and correspond to the size and shape of the wafer 104. However, in alternative embodiments, the support plate opening 138 and the bottom shroud opening 140 may be of any shape that allows the imaging system 110 to operate as described herein. Also, the support plate opening 138 is aligned with the bottom shroud opening 140 such that when the wafer is disposed in the bottom shroud opening 140, it can be viewed through a direct and unobstructed line of sight 142 from the wafer to the upper chamber 128. The shroud panel 126 is preferably made of a black anodized aluminum panel to minimize reflections within the light-tight box 118. In alternative embodiments, the shroud panel 126 may be made of any material that allows the light-tight box 118 to operate as described herein.

[0031] The light-tight box 118 includes an illumination panel 144 for directing diffused light onto the wafer 104. The illumination panel 144 is disposed in the lower chamber 130 and directs diffused light through the bottom shroud opening 140 onto the wafer 104 positioned in the bottom shroud opening. Next, the diffused light reflects from the wafer 104 into the upper chamber 128 through the support plate opening 138 and the bottom shroud opening 140. In the illustrated embodiment, the illumination panel 144 is rectangular, and the shape of the lower chamber 130 conforms to the shape of the illumination panel. In alternative embodiments, the illumination panel 144 may have any shape including circular and / or polygonal that allows the semiconductor wafer imaging system 110 to operate as described herein.

[0032] Referring to FIG. 6, the lighting panel 144 includes a frame 186, a light 188, and a transparent plate 190. The frame 186 is rectangular and conforms to the shape of the lower chamber 130. In the illustrated embodiment, the light 188 is a light emitting diode (LED) light. In an alternative embodiment, the light 188 may be any type of light that enables the semiconductor wafer imaging system 110 to operate as described herein. The light 188 is attached to the frame 186 such that the light directs visible light in the horizontal direction 152 through the transparent plate 190. The transparent plate 190 includes a first edge 192, a second edge 194, a top surface 196, a bottom surface 198, and a reflector 200.

[0033] Light 188 directs light toward a first edge 192 of a transparent plate 190, and the light either exits through a second edge 194 or is directed by a reflector 200 to pass through a bottom surface 198. Light 188 substantially surrounds the transparent plate 190 such that visible light emitted by the light is scattered throughout the transparent plate and moves and reflects in all directions parallel to a top surface 196 and the bottom surface 198. The visible light remains within the transparent plate 190 until it is directed downward by the reflector 200. The top surface 196 is textured with a regular geometric arrangement of reflectors 200 so as to direct a portion of the visible light emitted by the light 188 downward through the bottom surface 198. In the illustrated embodiment, the reflector 200 includes raised and / or recessed features formed in the transparent plate 190 and including holes and / or protrusions that reflect, diffuse, and / or scatter visible light downward. For example, the raised features formed in the transparent plate 190 may include pyramid-shaped or cone-shaped protrusions extending from the transparent plate, and the recessed features formed in the transparent plate 190 may include holes that allow a portion of the reflected light to pass through. The raised features and the recessed features are not aligned so that reflections from the features do not interfere with each other. When the visible light hits one of the reflectors 200, the visible light is scattered or reflected downward and intersects the bottom surface 198 at a substantially perpendicular incidence so as not to internally reflect and exits the transparent plate 190. The reflector 200 scatters the visible light so that the visible light is directed downward toward the wafer 104 as diffused light.

[0034] The diffused light is reflected by the wafer 104 and returns upward through the transparent plate 190. A portion of the reflected diffused light passes through the transparent plate 190 without hitting the reflector 200 and is imaged by a camera as described later. However, the reflected diffused light that hits the reflector 200 is scattered or refracted so that the camera cannot image the scattered diffused light, generating an array of dark spots on the image of the wafer 104.

[0035] The light-tight box 118 includes a camera 146 for imaging the wafer 104. The camera 146 includes a monochrome digital camera for taking a black and white digital photograph of the wafer 104. The camera 146 is disposed in the upper chamber 128 and images the wafer 104 through the support plate opening 138 and the bottom shroud opening 140. In the illustrated embodiment, as will be described later, the camera 146 is disposed in proximity to a mirror 148 that reflects light reflected by the wafer 104 toward the camera. In an alternative embodiment, the light-tight box 118 may not include the mirror 148, and the camera 146 may be disposed in the upper chamber 128 such that the wafer 104 can be imaged directly.

[0036] The light-tight box 118 is attached to the camera 146 and includes a slide lock 150 for positioning the camera in the upper chamber 128. The camera 146 is movably attached to the slide lock 150 so as to position and reposition the camera in the upper chamber 128. Specifically, as shown in FIGS. 5 and 7-10, the slide lock 150 is oriented in the horizontal direction 152 and slides the camera 146 horizontally to focus the camera on the wafer 104. In an alternative embodiment, the light-tight box 118 may not include the mirror 148 and the slide lock 150, and the camera 146 may be oriented in the vertical direction 154. The slide lock 150 slides the camera 146 in the vertical direction 154 to focus the camera on the wafer 104. In an alternative embodiment, the camera 146 may have an adjustable focus and the light-tight box 118 may not include the slide lock 150.

[0037] Mirror 148 includes a planar mirror 156 attached to a mirror positioning system 158. The planar mirror 156 reflects the diffused light reflected by the wafer 104 towards the camera 146, and the mirror positioning system 158 positions the planar mirror 156 in the upper chamber 128. Mirror 148 redirects the diffused light reflected by wafer 104 from the vertical direction 154 to the horizontal direction 152, thereby enabling the camera 146 to be oriented horizontally and reducing the height 160 of the dark box 118. Thus, mirror 148 enables the semiconductor wafer imaging system 110 to be miniaturized and placed within the semiconductor wafer processing system 100.

[0038] The mirror positioning system 158 includes a base 162, a mirror holder 164, and a plurality of mirror screws 166. The mirror holder 164 is rotatably attached to the base 162, and the screws 166 attach the planar mirror 156 to the mirror holder. By rotating the screws 166, the angle α of the planar mirror 156 with respect to the camera 146 is adjusted. By rotating the screws 166, fine adjustment of the angle α is possible. In an alternative embodiment, the mirror positioning system 158 may include a slide similar to the slide lock 150.

[0039] The dark box 118 may optionally include a filter 168 disposed in the upper chamber 128. The filter 168 may be a polarizing filter, a color filter, a high-pass filter, and / or any other type of filter that enables the imaging system 110 to operate as described herein. The filter 168 is disposed at either a first position 170 on the camera 146 or a second position 172 above the support plate opening 138. The filter 168 creates a contrast between the wafer 104 and the surrounding environment, enabling the camera 146 to image the wafer. Specifically, the filter 168 reduces or eliminates reflections, enabling the camera 146 to image the wafer 104 rather than the light or objects reflected by the wafer.

[0040] For example, when the filter 168 is a polarizing filter, the filter creates contrast using polarization between the wafer 104 and the surrounding environment. As described above, the light emitted from the illumination panel 144 is reflected by the mirror-like surface of the wafer 104 and is diffused light that has passed through and returned from the light emitted from the illumination panel. The light reflected from other surfaces is reflected and scattered. Since the scattered diffused light is not polarized and the reflected light is polarized, the filter 168 allows only the transmission of the diffused light reflected by the wafer 104. Reflections from the surrounding surfaces are reduced or not transmitted to the camera 146. By reducing or eliminating the reflections, the camera 146 is enabled to image the wafer 104 rather than the light reflected by the wafer or an object.

[0041] Similarly, when the filter 168 is a color filter, the filter creates contrast between the wafer 104 and the surrounding environment based on the wavelength of the light reflected by the mirror-like surface of the wafer 104. The filter 168 selectively transmits light of different wavelengths. For example, the filter 168 may transmit only long wavelengths (long pass), only short wavelengths (short pass), or a wavelength band (band pass) that blocks both longer and shorter wavelengths. Reflections from the surrounding surfaces may have a predetermined wavelength, and the filter 168 reduces or eliminates the reflections by absorbing the light within the predetermined wavelength. By reducing or eliminating the reflections, the camera 146 is enabled to image the wafer 104 rather than the light reflected by the wafer or an object.

[0042] Also, when the filter 168 is a high-pass filter, the filter 168 creates a contrast between the wafer 104 and the surrounding environment based on the wavelength of the light reflected from the mirror-like surface of the wafer 104. Specifically, the filter 168 transmits light having a wavelength of 600 nanometers (nm) or more while absorbing light having a wavelength of less than 600 nm. Reflections from the surrounding surfaces may have wavelengths of less than 600 nm, and the filter 168 reduces or eliminates the reflections by absorbing light having a wavelength of less than 600 nm. By reducing or eliminating the reflections, the camera 146 is enabled to image the wafer 104 rather than the light reflected from the wafer or an object.

[0043] The imaging system 110 includes an end effector positioner 174 that is attached to the dark box 118 and calibrates (adjusts) the position 176 of the end effector 120. The end effector positioner 174 is removed from the dark box 118 after the position 176 of the end effector 120 has been calibrated. The end effector positioner 174 includes a dark box brace 178, an arm 180, and a pack 182. The end effector positioner 174 is attached to the dark box 118 before the imaging system 110 images the wafer 104. The pack 182 is attached to the arm 180, and the arm and the pack are attached to the dark box brace 178, and the arm, the pack, and the dark box brace are attached to the dark box 118. The dark box brace 178 and the arm 180 have a size and shape for positioning the pack 182 under the bottom shroud opening 140 within the field of view 184 of the camera 146. The end effector 120 is positioned such that the end effector is attached to the pack 182, and the controller 112 records and calibrates the position 176 such that the end effector positions the wafer 104 at the position 176 for each imaging. The end effector positioner 174 is removed from the dark box 118 after the position 176 has been calibrated.

[0044] Before manufacturing the wafer 104, the imaging system 110 is disposed and calibrated within the processing system 100. Specifically, the positioning plate 122 is attached to the frame 124, and the imaging system 110 is attached to the positioning plate 122. More specifically, the camera obscura 118 is attached to the positioning plate 122.

[0045] The camera 146 and the mirror 148 are disposed and calibrated within the camera obscura 118 when the imaging system 110 is disposed and calibrated within the processing system 100. Specifically, an operator positions the mirror 148 in the upper chamber 128 of the camera obscura 118 using the mirror positioning system 158. More specifically, the operator attaches the planar mirror 148 to the mirror holder 164 and attaches the mirror holder and the planar mirror to the base 162. The operator also attaches the camera 146 to the slide lock 150 and positions the camera and the slide lock in the upper chamber 128 of the camera obscura 118. The operator simultaneously adjusts the slide lock 150, the camera 146, and the planar mirror 156 to ensure that the field of view 184 of the camera is centered on the bottom shroud opening 140. More specifically, the operator simultaneously performs the adjustment of the screw 166, the rotation of the mirror holder 164, and the sliding of the camera 146 on the slide lock 150 to ensure that the field of view 184 of the camera is centered on the bottom shroud opening 140.

[0046] The operator attaches the pack 182 to the arm 180, attaches the pack and the arm to the shroud brace 178, and attaches the pack, the arm, and the shroud brace to the shroud, thereby attaching the end effector positioner 174 to the shroud 118. The end effector positioner 174 is attached to the shroud 118 such that the pack 182 is centered at the bottom shroud opening 140. The operator positions the end effector 120 such that the end effector is attached to the pack 182 either directly or indirectly. The controller 112 records and calibrates the position 176 of the end effector 120 such that the end effector is positioned at the position 176 for each wafer imaging. The operator removes the end effector positioner 174 from the shroud 118.

[0047] During operation, the wafer processing system 100 manufactures the wafer 104 at least in part. Specifically, in the illustrated embodiment, the cleaving station 108 cleaves the wafer 104 and sends the wafer to the imaging system 110 for imaging. More specifically, after the cleaving station 108 cleaves the wafer 104, the end effector 120 positions the wafer 104 under the bottom shroud opening 140, and the camera 146 generates an image 202 of the wafer (a schematic representation 203 of the image 202 is shown in FIG. 13 and the image 202 is shown in FIG. 14). The image 202 of the wafer 104 is sent to the controller 112 for analysis as described below.

[0048] Referring to FIGS. 13 and 14, as shown in image 202 and schematic representation 203 of image 202, wafer 104 includes a base 204 and a transfer layer 206 deposited on the base. The base 204 has a wafer boundary 208, and the transfer layer 206 has a transfer layer boundary 210. The wafer boundary 208 and the transfer layer boundary 210 define a terrace width 212 between the wafer boundary 208 and the transfer layer boundary 210. Also, the wafer 104 includes a notch 222. The controller 112 detects the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212 in the image 202 and analyzes the detected regions for defects of the wafer 104. Also, as described above, the arrangement of the reflector 200 on the top surface 196 of the transparent plate 190 causes a regular geometric arrangement of periodic artifacts (as shown by the fold pattern in image 202) in the image 202. Specifically, the reflector 200 causes a grid pattern of periodic artifacts 214 in the image 202. The grid pattern of periodic artifacts 214 may include a periodic arrangement of out-of-focus points, slightly in-focus points, and / or regularly spaced dark spots.

[0049] The controller 112 includes a computer program 300 for imaging and analyzing the wafer 104. FIG. 18 is a diagram of the computer program 300 for imaging and analyzing the wafer 104. The computer program 300 includes an image capture module 302, a data management module 304, and a data analysis module 306. The image capture module 302 controls the semiconductor wafer imaging system 110 to position the wafer 104 within the bottom shroud opening 140, capture an image 202 of the wafer, and return the wafer to the semiconductor wafer processing system 100 for further processing. The data management module 304 records identification information for each wafer 104, stores the image 202 for analysis, and notifies the data analysis module 306 that the image 202 is ready for analysis. The data analysis module 306 analyzes the image 202, determines whether the wafer is acceptable for further processing, and, if necessary, removes the wafer from the manufacturing process by controlling the semiconductor wafer processing system 100.

[0050] The computer program 300 may be a single program that includes all three modules, or it may be multiple programs that interact with each other. For example, in a first embodiment, the computer program 300 is a single program that includes all three modules. In this embodiment, the computer program 300 images and analyzes the wafer 104 before other wafers are imaged and analyzed. The modules 302-306 are executed sequentially before other wafers 104 are imaged and analyzed.

[0051] In the second embodiment, the computer program 300 includes a single program that executes modules 302-306 discontinuously. For example, in this embodiment, the computer program 300 may sequentially execute the image capture module 302 and the data management module 304, but may not execute the data analysis module 306 until a plurality of wafers 104 are imaged, so that the controller 112 can analyze the wafers in a batch. When there is an error in the data analysis module 306, the image 202 is stored by the data management module 304 for later analysis.

[0052] In the third embodiment, the computer program 300 includes a plurality of programs each including one or more of the modules 302-306. In this embodiment, the modules 302-306 are separated into separate programs so that the modules 302-306 can be executed discontinuously. For example, the first computer program may include the image capture module 302 and the data management module 304, and the second computer program may include the data analysis module 306. Also, the first computer program and the second computer program may be executed on different controllers 112 or computing devices, enabling the controller to execute the image capture module 302 and the data management module 304 without simultaneously analyzing the image 202. According to the third embodiment, the manufacturing process can continue even if the data analysis module 306 and / or the controller or computing device executing the data analysis module becomes temporarily unable to execute the analysis.

[0053] Figures 19 through 21 are flow diagrams of a method for imaging and analyzing wafer 104. Each module 302 - 306 performs a specific step of method 400, and the modules may be executed discontinuously. Method 400 includes imaging wafer 104 using semiconductor wafer imaging system 110 as described above at 402. Specifically, imaging wafer 104 using semiconductor wafer imaging system 110 at 402 includes positioning wafer 104 within bottom shroud opening 140 using end effector 120 at 404, directing diffused light toward wafer 104 using illumination panel 144 at 406, reflecting the diffused light off the wafer at 408, and detecting the diffused light with camera 146 to generate an image 202 of the wafer at 410.

[0054] Method 400 includes saving and transmitting the image at 412. Image 202 is transmitted to controller 112, and the controller analyzes the image before another wafer 104 is imaged. Controller 112 analyzes the image as soon as it receives the image from camera 146. However, controller 112 and / or the analysis may create a bottleneck in the manufacturing process. To shorten the manufacturing time, camera 146 may transmit the image to controller 112 along with a wafer identification number, and the controller may analyze the image while wafer 104 is progressing through the manufacturing process.

[0055] Method 400 further includes analyzing wafer 104 using controller 112 to detect defects in the wafer 414. Defects include voids (defective portions within transfer layer 206 that do not intersect transfer layer boundary 210), edge voids (defective portions of transfer layer 206 that intersect transfer layer boundary 210), asymmetric terrace widths 212, notch terrace widths that are too large or too small, alignment of transfer layer 206 within wafer 104, various metrics of terrace width area and symmetry, dirt (dark and / or bright regions), and / or any other defects included in at least one of base 204, wafer boundary 208, transfer layer 206, transfer layer boundary 210, and terrace width 212. As described above, the placement of reflector 200 on top surface 196 of transparent plate 190 may result in a regular geometric arrangement of periodic artifacts 214 in image 202. To remove or reduce periodic artifacts 214, analyzing wafer 104 using controller 112 to detect defects in the wafer 414 may include applying a software filter to image 202 to remove or reduce periodic artifacts 214 416.

[0056] The software filter may include a Fast Fourier Transform (FFT) that identifies and removes periodic artifacts 214 from the image 202. Specifically, since the grid pattern of the periodic artifacts 214 is a regularly spaced periodic array, the FFT decomposes the image 202 into sine and cosine components, while the image 202 corresponds to the spatial domain and generates an output image 216 (shown in FIG. 17) in the Fourier or frequency domain. The regular spacing of the grid pattern of the periodic artifacts 214 enables the FFT to identify the periodic artifacts 214 from the image 202. In the output image 216, each point represents a specific frequency included in the spatial domain image or the image 202. Specifically, the controller 112 generates 418 the raw FFT image 218 (shown in FIG. 15), detects 420 the periodic artifacts 214 of the image 202, removes or reduces 422 the periodic artifacts 214 from the image, and converts 424 the image into the output image 216 (shown in FIG. 17, and a schematic representation 217 of the image 216 is shown in FIG. 16). The software filter is insensitive to translational position variations of the wafer, the diffusion plate, and / or the camera, and is basically self-compensating for rotational position variations of the wafer, the diffusion plate, or the camera. Therefore, the software filter improves the image 202 prior to the analysis of the image 202 for detecting defects of the wafer 104.

[0057] At high magnification, the periodic artifacts 214 caused by the arrangement of the reflectors 200 on the top surface 196 of the transparent plate 190 can be visually recognized. The grid pattern of the periodic artifacts 214 may reduce the accuracy of the results of the analysis 414. When the image 202 is converted into the frequency domain, the periodic artifacts 214 are represented as high-intensity spots 228 on the raw FFT image 218. By removing the high-intensity spots 228 in the raw FFT image 218 and converting the raw FFT image 218 back into the spatial domain image, the grid pattern of the periodic artifacts 214 can be removed from the image 202.

[0058] The raw FFT image 218 is generated to enable visualization of the FFT analysis, and the form of the raw FFT image 218 enables visualization of a specific form of the FFT analysis. For example, the raw FFT image 218 is generated using a conventional FFT method and includes a central spot 224 and a pair of vertical axes 226. The size of the central spot 224 visually represents the period or distance between the periodic artifacts 214 in the image 202. Further, the raw FFT image 218 includes high-intensity spots 228, and the vertical axes 226 are aligned with the high-intensity spots 228. As shown in FIG. 14, the grid pattern of the periodic artifacts 214 is diagonally oriented. The high-intensity spots 228 are oriented at the same angle as the orientation angle of the grid pattern of the periodic artifacts 214, and the pair of vertical axes 226 are oriented at the same angle as the high-intensity spots 228 and the grid pattern of the periodic artifacts 214. Therefore, the raw FFT image 218 enables visualization of the FFT analysis.

[0059] When the output image 216 is generated, the controller 112 analyzes the output image to detect defects on the wafer 104. Specifically, the controller 112 detects 426 the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, the terrace width 212, and the notch 222 in the output image 216. More specifically, the controller 112 detects 428 the wafer boundary 208 by dividing and separating the wafer boundary in the output image 216, and detects 430 the transfer layer boundary 210 by dividing and separating the transfer layer boundary in the output image 216. The transfer layer 206, the notch 222, and the boundaries of voids in the transfer layer are segmented using various image processing techniques including image blurring, gradient calculation, high-gradient edge detection, and contour calculation from edge detection. When the boundary is ambiguous or fuzzy, further processing is performed to emphasize the edge position, and in some embodiments where the output image 216 has incomplete or missing edges, an estimation of boundary closure is performed if possible. For example, when small edge segments are missing, edge boundary extrapolation may be used, and the detected edges may be smoothed to reduce noise introduced by the edge detection technique. If the controller 112 cannot estimate the closure, the output image 216 is flagged for manual inspection.

[0060] After the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212 are detected in the output image 216, the controller 112 analyzes 432 the detected regions for defects. More specifically, the controller 112 analyzes 432 at least one of the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212 for defects. For example, the controller 112 detects 434 at least one feature of the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212, and quantifies the detected feature into a metric. Next, the controller 112 compares 438 the quantified metric with a predetermined metric, and based on the comparison, detects 440 at least one defect of the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212.

[0061] Specifically, detecting at least one of the features of the base 204, the wafer boundary 208, the transfer layer 206, the transfer layer boundary 210, and the terrace width 212 434, and quantifying the detected feature into a metric 436 includes detecting the terrace width 212 and quantifying the detected feature of the terrace width 212 into various global and local terrace width statistics. For example, in some embodiments, the terrace width 212 is divided into 12 30° segments around the edge of the wafer 104, and the detected feature of the terrace width 212 is quantified into local terrace width statistics based on each segment.

[0062] FIG. 22 shows a graphical user interface display 500 used to calibrate the position of the end effector 120 (shown in FIG. 12) and / or the wafer 104 with respect to the camera 146 (shown in FIG. 9) by an image analysis process. The user interface display 500 displays a captured image 502 of the wafer 104 and centering meters 504 - 508. To calibrate the position of the end effector 120 and / or the wafer 104 by image analysis, the end effector 120 is positioned below the bottom shroud opening 140 (shown in FIG. 5) and at least partially within the field of view 184 (shown in FIG. 9) of the camera 146. The camera 146 captures an image 502 of the wafer 104, and the image 502 is transmitted to the controller 112. Next, the controller 112 analyzes the captured image 502 of the wafer 104 to determine whether the wafer 104 is within a predetermined positioning range and is properly centered within the field of view 184. When the controller 112 determines that the wafer 104 is not properly centered within the field of view 184, the wafer 104 and / or the end effector 120 are adjusted based on that determination. After adjustment, a new image is captured, and the controller 112 again determines whether the detected position of the wafer 104 is within the predetermined positioning range. The image analysis process may be used with or as an alternative to the end effector positioner 174 described above with respect to FIG. 12.

[0063] During operation, to determine whether the wafer 104 is properly centered within the field of view 184, the controller 112 captures an image 502 of the wafer 104 and detects the boundary 208 of the wafer 104 as described above with respect to FIGS. 14 - 21. Next, the controller 112 measures the distance between the edges 510 - 516 of the image 502 and the wafer boundary 208 on the captured image 502.

[0064] For example, with respect to positioning along the X-axis, the controller 112 measures a first horizontal distance X1 from the first side edge 510 of the captured image 502 to the wafer boundary 208 and a second horizontal distance X2 from the second side edge 512 of the image 502 to the wafer boundary 208. Next, the controller 112 determines a delta X value corresponding to the difference between the first horizontal distance X1 and the second horizontal distance X2. With respect to positioning along the Y-axis, the controller 112 measures a first vertical distance Y1 from the bottom wall 514 of the image 502 to the wafer boundary 208 and a second vertical distance Y2 from the top edge 516 of the image 502 to the wafer boundary 208. Next, the controller 112 determines a delta Y value corresponding to the difference between the first vertical distance Y1 and the second vertical distance Y2. With respect to positioning along the Z-axis, the controller determines the minimum distance among X1, X2, Y1, and Y2 in order to determine the minimum gap of the wafer 104 from the edges 510 - 516 of the image 502. Next, the controller 112 compares the determined delta X value, delta Y value, and minimum gap value with a predetermined tolerance range (such as that shown by the centering meters 504 - 508) to determine whether further adjustment of the wafer 104 and / or the end effector 120 in the X-direction, Y-direction, or Z-direction is necessary. The color-coded indicator 520 is provided on or near the image 502 on the user interface 500 and indicates to the technician whether the wafer 104 is centered within its respective ranges along the X-axis, Y-axis, and Z-axis. For example, the indicator 520 changes color based on whether each of the delta X value, delta Y value, or minimum gap value is within the corresponding ideal range, tolerance range, or out-of-range range.

[0065] In the embodiment of FIG. 22, the centering meters 504-508 include an X-axis centering meter 504, a Y-axis centering meter 506, and a Z-axis or zoom centering meter 508. Each of the centering meters 504-508 indicates an ideal range, a tolerance range, and out of range. The controller 112 projects the determined delta X value, delta Y value, and minimum gap value onto the X-axis centering meter 504, Y-axis centering meter 506, and Z-axis centering meter 508, respectively. As shown in FIG. 22, the delta Y value of the image 502 is equal to -20 and is within the ideal range of -20 to 20 on the Y-axis centering meter 506. The minimum gap value is equal to 25 and is within the ideal range of 20 to 40 on the Z-axis centering meter 508. The delta X value is equal to 130 and is outside the ideal range and tolerance range on the X-axis centering meter 504. Next, the positioning of the wafer 104 and / or the end effector 120 is adjusted (e.g., by a technician or by an automatic positioning system communicating with the controller 112). In particular, the positioning of the wafer is adjusted based on the determined values displayed on the centering meters 504-508. As an example, as shown in FIG. 22, based on the display results from the centering meters 504-508, the technician may move the wafer 104 to the left side of the page as shown in FIG. 22 to reduce the displayed delta X value. After adjustment, the image is captured again, and the process is repeated until each of the delta X value, delta Y value, and minimum gap value all fall within the tolerance range and / or ideal range.

[0066] The semiconductor wafer imaging system described in this specification images a wafer to detect defects in the wafer during the manufacturing process. The imaging system images the wafer after it has been diced to detect defects in the wafer formed during the dicing process. When the semiconductor wafer imaging system detects a defect in the wafer, the wafer is removed from the manufacturing process, thereby reducing the wafer manufacturing cost. The wafer has a mirror-like reflective surface, and the semiconductor wafer imaging system images the wafer without imaging the light source reflected by the reflective surface. Specifically, the semiconductor wafer imaging system includes a dark box that surrounds a camera and an illumination panel. The dark box minimizes reflections in the semiconductor wafer imaging system, and the illumination panel directs diffused light toward the wafer. The diffused light is reflected by the wafer toward the camera. Since the light generated by the illumination panel is diffused, the camera detects the reflected diffused light and does not image the illumination panel. Thus, the camera images the wafer rather than the light source, enabling the controller to analyze the wafer for defects and reducing the wafer manufacturing cost.

[0067] As used herein, the terms “about,” “substantially,” “essentially,” “approximately” when used in connection with a range of dimensions, density, temperature, or other physical or chemical property or characteristic, mean to encompass variations that may exist at the upper and / or lower limits of the property or characteristic. Such variations can include, for example, variations resulting from rounding, measurement methods, or other statistical variations.

[0068] When introducing elements of the present disclosure or embodiments of the present disclosure, the articles "a", "an", "the", and "said" are intended to mean that there is one or more elements. The terms "comprising", "including", "containing", and "having" are intended to be inclusive and mean that additional elements other than the recited elements may be present. The use of terms indicating a particular orientation (e.g., "top", "bottom", "side") is for convenience of description and does not require a particular orientation of the article being described.

[0069] Without departing from the scope of the present disclosure, various changes are possible in the above-described structures and methods, and thus all matters included in the above description and shown in the accompanying drawings are intended to be construed as illustrative rather than in a limiting sense.

Claims

1. 1. A semiconductor wafer processing system for processing semiconductor wafers, comprising: a semiconductor wafer processing station for processing the semiconductor wafer; a semiconductor wafer imaging system for imaging the semiconductor wafer; Equipped with the semiconductor wafer imaging system images the semiconductor wafer after the semiconductor wafer processing station processes the semiconductor wafer; the semiconductor wafer imaging system comprises: a plurality of shroud panels defining a dark box, one of the plurality of shroud panels defining a shroud opening; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an end effector movable relative to the dark box to position the semiconductor wafer in alignment with the shroud opening and within the field of view of the camera; an illumination panel disposed within the dark box between the camera and the shroud opening and within a field of view of the camera, the illumination panel including a light source and a reflector that scatters light from the light source to direct diffuse light through the shroud opening onto the semiconductor wafer; Equipped with A portion of the diffused light is reflected off of the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

2. the semiconductor wafer processing station comprises a cleaving station; The system of claim 1 , wherein the semiconductor wafer imaging system is located above the cleaving station.

3. 2. The system of claim 1, wherein the semiconductor wafer processing station includes a cleaving station disposed upstream of the semiconductor wafer imaging system, and the end effector receives the semiconductor wafer after the semiconductor wafer is cleaved by the cleaving station and the camera images the cleaved semiconductor wafer.

4. a semiconductor wafer imaging station; the semiconductor wafer imaging system is disposed at the semiconductor wafer imaging station; The lighting panel includes a transparent plate having a first side and an opposing second side; 10. The system of claim 1, wherein the first surface is textured with an array of reflectors for directing at least a portion of the diffuse light through the second surface and toward the semiconductor wafer on the end effector.

5. A frame, A positioning plate attached to the frame; Further comprising: The system of claim 1 , wherein the semiconductor wafer imaging system is attached to the positioning plate.

6. the semiconductor wafer imaging system is movably mounted on the positioning plate; The system of claim 5 , wherein the position of the semiconductor wafer imaging system is adjusted by adjusting the position of the semiconductor wafer imaging system on the positioning plate.

7. the end effector is mounted to the frame such that the semiconductor wafer is visible through a direct, unobstructed line of sight from the semiconductor wafer to an upper chamber when the semiconductor wafer is positioned on the end effector; The system of claim 5 , wherein the end effector receives the semiconductor wafer from the semiconductor wafer processing station.

8. 1. A semiconductor wafer processing system for processing semiconductor wafers, comprising: a first manufacturing line for processing a first semiconductor wafer, the first manufacturing line including a first semiconductor wafer processing station for processing the first semiconductor wafer; a second manufacturing line for processing a second semiconductor wafer, the second manufacturing line including a second semiconductor wafer processing station for processing the second semiconductor wafer, wherein the second manufacturing line intersects with the first manufacturing line at a common location; a semiconductor wafer imaging system for imaging the first semiconductor wafer and the second semiconductor wafer disposed within the common location where the first manufacturing line and the second manufacturing line intersect, wherein the semiconductor wafer imaging system images the first semiconductor wafer and the second semiconductor wafer after the first semiconductor wafer processing station and the second semiconductor wafer processing station have processed the first semiconductor wafer and the second semiconductor wafer; Equipped with the semiconductor wafer imaging system comprises: a plurality of shroud panels defining a dark box, one of the plurality of shroud panels defining a shroud opening; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an end effector movable relative to the dark box to position the semiconductor wafer in alignment with the shroud opening and within the field of view of the camera; an illumination panel disposed within the dark box between the camera and the shroud opening and within a field of view of the camera, the illumination panel including a light source and a reflector that scatters light from the light source to direct diffuse light through the shroud opening onto the semiconductor wafer; Equipped with A portion of the diffused light is reflected off of the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

9. 10. The system of claim 8, wherein at least one of the first semiconductor wafer processing station and the second semiconductor wafer processing station includes a cleaving station, the cleaving station being located upstream of the semiconductor wafer imaging system.

10. a semiconductor wafer imaging station disposed within the common location where the first and second manufacturing lines intersect; The system of claim 8 , wherein the semiconductor wafer imaging system is disposed at the semiconductor wafer imaging station.

11. A frame, A positioning plate attached to the frame; Further comprising: The system of claim 8 , wherein the semiconductor wafer imaging system is attached to the positioning plate.

12. the semiconductor wafer imaging system is movably mounted on the positioning plate; The system of claim 11 , wherein the position of the semiconductor wafer imaging system is adjusted by adjusting the position of the semiconductor wafer imaging system on the positioning plate.

13. 12. The system of claim 11, further comprising an end effector attached to the frame for positioning the first semiconductor wafer and the second semiconductor wafer within a field of view of the camera.

14. The system of claim 13 , wherein the end effector receives the semiconductor wafer from at least one of the first semiconductor wafer processing station and the second semiconductor wafer processing station.

15. 10. The system of claim 8, wherein the semiconductor wafer imaging system is disposed downstream of the first semiconductor wafer processing station and the second semiconductor wafer processing station and alternately images the first and second semiconductor wafers from the first and second manufacturing lines.

16. 1. A semiconductor wafer imaging station of a semiconductor wafer processing system for imaging a semiconductor wafer, comprising: A frame, a positioning plate attached to the frame; a dark box movably attached to the positioning plate; End effector and Equipped with The dark box is a plurality of shroud panels defining a dark box, one of the plurality of shroud panels defining a shroud opening; a camera disposed in the dark box for capturing an image of the semiconductor wafer; an illumination panel disposed within the dark box between the camera and the shroud opening and within a field of view of the camera, the illumination panel including a light source and a reflector that scatters light from the light source to direct diffuse light through the shroud opening onto the semiconductor wafer; Equipped with a part of the diffused light is reflected by the semiconductor wafer, and the camera captures an image of the semiconductor wafer by detecting the reflected diffused light; The end effector is movable relative to the dark box to position the semiconductor wafer in alignment with the shroud opening and within the field of view of the camera.

17. The station of claim 16 , wherein the position of the dark box is adjusted by adjusting the position of the dark box on the positioning plate.

18. The station of claim 16 , wherein the end effector is mounted to the frame and positions the semiconductor wafer within a field of view of the camera.

19. The lighting panel includes a transparent plate; 2. The system of claim 1, wherein the reflector is disposed on the transparent plate such that the reflector directs diffuse light from the light source through a first side of the transparent plate, the first side being oriented facing the shroud opening.

20. the transparent plate further includes a second surface and a side edge extending from the first surface toward the second surface; the light source is disposed so as to direct light emitted from the light source through the side edge into the transparent plate toward the reflector; 20. The system of claim 19, wherein the transparent plate is positioned such that a portion of the diffuse light reflected from the semiconductor wafer is directed through the first side and the second side of the transparent plate toward a camera.

Images