Gate driver, display device

Abstract

A semiconductor device that shifts a low-level signal using a small number of transistors is provided. A first terminal is electrically connected to a first wiring, and a second terminal is electrically connected to a second wiring. a first transistor electrically connected to the first wiring, and a first terminal electrically connected to the third wiring; a second transistor having a second terminal electrically connected to a second wiring; The second terminal is electrically connected to the wiring of the second transistor, and the second terminal is electrically connected to the gate of the second transistor. a third transistor having a first terminal electrically connected to a fifth wiring and a second terminal The gate of the third transistor is electrically connected to the sixth wiring. a fourth transistor having a first terminal electrically connected to the third wiring and a second terminal The first transistor has a first switch electrically connected to the gate of the first transistor.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, or the like. [Background technology]

[0002] In recent years, the development of shift register circuits consisting of transistors of the same polarity has been actively promoted. The shift register circuit of Patent Document 1 is an N-channel type transistor. When the clock signal goes high, the clock By outputting a lock signal, high-level signals are sequentially output. The shift register circuit 1 outputs low-level signals in order to output the clock signal. It is not possible.

[0003] In addition, when the shift register of Patent Document 1 is configured with P-channel transistors, However, it is not possible to output high-level signals in sequence. You will no longer be able to exert force. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-103226 A Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, in a shift register circuit composed of N-channel transistors, It is required to output a signal of the same level sequentially. In a shift register circuit configured as such, it is required to sequentially output high-level signals. It is required.

[0006] Therefore, one aspect of the present invention aims to provide a circuit configured with N-channel transistors for sequentially outputting low-level signals. Another aspect of the present invention aims to provide a circuit configured with P-channel transistors for sequentially outputting high-level signals. Another aspect of the present invention aims to reduce the circuit scale. Another aspect of the present invention aims to reduce power consumption. It is required. It is required. It is required. It is required. It is required.

Means for Solving the Problems

[0007] One aspect of the present invention includes a first transistor having one of a source and a drain electrically connected to a first wiring and the other of the source and the drain electrically connected to a second wiring, a second transistor having one of a source and a drain electrically connected to a third wiring and the other of the source and the drain electrically connected to the second wiring, a third transistor having one of a source and a drain electrically connected to a fourth wiring and the other of the source and the drain electrically connected to the gate of the second transistor, a fourth transistor having one of a source and a drain electrically connected to a fifth wiring and the other of the source and the drain electrically connected to the gate of the third transistor and having a gate electrically connected to a sixth wiring, and a first switch having a first terminal electrically connected to the third wiring and a second terminal electrically connected to the gate of the first transistor. It is required. It is required. It is required. It is required. It is required. It is required. It is required. It is required. It is required.

[0008] In addition, in one aspect of the present invention, the first terminal is electrically connected to the first wiring, and the second terminal may have a second switch electrically connected to the gate of the first transistor .

[0009] In addition, in one aspect of the present invention, the first terminal is electrically connected to the third wiring, and the second terminal may have a third switch electrically connected to the gate of the second transistor .

[0010] In addition, in one aspect of the present invention, the first to fourth transistors may include an oxide semiconductor in the channel formation region . [Advantages of the Invention]

[0011] One aspect of the present invention can provide a circuit composed of N-channel transistors for sequentially outputting low-level signals. Further, one aspect of the present invention can provide a circuit composed of P-channel transistors for sequentially outputting high-level signals. Further, one aspect of the present invention can reduce the circuit scale. Further, one aspect of the present invention can reduce power consumption . Further, one aspect of the present invention can provide a circuit composed of P-channel transistors for sequentially outputting high-level signals . Further, one aspect of the present invention can reduce the circuit scale. Further, one aspect of the present invention can reduce power consumption . Further, one aspect of the present invention can reduce the circuit scale. Further, one aspect of the present invention can reduce power consumption . [Brief Description of the Drawings]

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the configuration of the present invention can be implemented in many different modes, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, it should not be construed as being limited to the description of the present embodiment. In the configuration of the present invention described below, the same reference numerals indicate the same objects among different drawings. In addition, in the drawings and the like of each embodiment, the size, layer thickness, signal waveform, or

[0014] region of each configuration shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Furthermore, the terms first, second, third, up to N (N is a natural number) used in this specification are for the purpose of clarifying the structure.

[0015] clarifying the structure. Note that this is for avoiding confusion of components and is not intended to be numerically limiting. Do.

[0016] (Embodiment 1) In this embodiment, a basic circuit, a sequential circuit, and a shift register circuit according to one aspect of the present invention will be described. will be described.

[0017] First, the basic circuit (also referred to as a semiconductor device or a drive circuit) of this embodiment will be described.

[0018] FIG. 1(A) is a circuit diagram of the basic circuit of this embodiment. The basic circuit in FIG. 1(A) includes transistors 101 to 105. have.

[0019] In one aspect of the present invention, the polarity of the transistor may be N-channel type or P-channel type. However, it is preferable that the polarities of transistors 101 to 105 are the same polarity. In this embodiment, transistors 101 to 105 will be described as being N-channel type. is. are. will be described.

[0020] In one aspect of the present invention, as the transistor, a transistor including a semiconductor such as silicon or germanium in the channel formation region can be used. Also, as the transistor, a transistor including a semiconductor such as an oxide semiconductor or a nitride semiconductor in the channel formation region can be used. Note that the semiconductor described above has a region that is amorphous, microcrystalline, polycrystalline, or single crystal. is. can be used. is. has.

[0021] In one aspect of the present invention, as the transistor, a thin film transistor (TFT) can be used. Also, as the transistor, a semiconductor substrate or an SOI substrate can be used. using. MOS transistors, junction transistors, bipolar transistors, etc. to be formed can be used.

[0022] Next, the connection relationship of the basic circuit in Fig. 1(A) will be described.

[0023] The first terminal (either the source or the drain) of transistor 101 is connected to wiring 11 and continued, the second terminal (the other of the source and the drain) of transistor 101 is connected to wiring 12. The first terminal of transistor 102 is connected to wiring 13, and the second terminal of transistor 102 is connected to wiring 12, and the gate of transistor 102 is connected to wiring 14 The first terminal of transistor 103 is connected to wiring 15, and the second terminal of transistor 10 3 is connected to wiring 14. The first terminal of transistor 104 is connected to wiring 13 and the second terminal of transistor 104 is connected to the gate of transistor 101, and the gate of transistor 104 is connected to wiring 14. The first terminal of transistor 105 is connected to wiring 17, and the second terminal of transistor 105 is connected to the gate of transistor 103 and the gate of transistor 105 is connected to wiring 16.

[0024] Note that the connection point between the gate of transistor 103 and the second terminal of transistor 105 is denoted as node N1. Also, the connection point between the gate of transistor 101 and the second terminal of transistor 104 is denoted as node N2.

[0025] In this specification, etc., "connection" means electrical connection, which corresponds to a state where current, voltage, potential, signal, charge, etc. can be supplied or transmitted. Therefore, "being connected" means In addition to the direct connection, for example, wiring, conductive film, resistor, diode, transistor This also includes indirect connections via elements such as inverters and switching elements. nothing.

[0026] Next, signals, potentials, and the like of the wirings 11 to 17 will be described.

[0027] A potential VDD is supplied to the wiring 11. A signal OUTA is output from the wiring 12. A potential VSS is supplied to the wiring 13. A signal OUTB is output from the wiring 14. A signal CK1 is input to the wiring 16. A signal CK2 is input to the wiring 17. The SP is entered.

[0028] The potentials VDD and VSS are constant potentials. This is a higher potential than

[0029] In addition, the signals OUTA, OUTB, CK1, CK2, and SP are at high level. and a low level.

[0030] Note that the signals, potentials, and the like of the wirings 11 to 17 are not limited to those described above. A signal or potential for increasing the potential of the wiring 12 may be supplied to the wiring 1. 3 is a signal or potential for lowering the potential of the wiring 12, and / or a transistor A signal or potential for turning off the wiring 101 may be supplied to the wiring 15. A signal or potential to raise the potential of line 14, turning on transistor 102 and / or a signal or potential for turning on transistor 104. A potential or the like may be input to the wiring 16. It is only necessary that a signal for control is input. For the wiring 17, it is only necessary that a signal, potential, or the like for turning on the transistor 103 is input.

[0031] In this specification and the like, the wiring to which a signal is input may be referred to as a signal line. Also, the wiring to which a potential is supplied may be referred to as a power line.

[0032] In one aspect of the present invention, the wiring has a function of transmitting a signal, potential, or the like. For example, the wiring 15 has a function of transmitting the signal CK1.

[0033] Next, the operation of the basic circuit in FIG. 1(A) will be described.

[0034] FIG. 1(B) is a timing chart for explaining the operation of the basic circuit in FIG. 1(A). . The timing chart in FIG. 1(B) shows the signal CK1, signal CK2, signal SP, the potential VN1 of the node N1, the potential VN2 of the node N2, the signal OUTA, and the signal OUTB.

[0035] For convenience, the high-level potential of the signal SP, signal CK1, and signal CK2 is described as the potential VDD, and the low-level potential is described as the potential VSS.

[0036] For convenience, the initial value of the potential VN1 of the node N1 is described as the potential VSS, and the initial value of the potential VN2 of the node N2 is described as a potential exceeding the sum of the potential VDD and the threshold voltage of the transistor 101.

[0037] For convenience, it will be described separately for the period T1 and the period T2.

[0038] In the period T1, the signal SP becomes high level, the signal CK1 becomes low level, and the signal CK 2 becomes high level. ​​​​

[0039] When the transistor 105 is turned on, the signal SP on the wiring 17 is supplied to the node N1. . Since the signal SP is at a high level during the period T1, the potential of the node N1 rises. The node When the potential of N1 rises to a potential obtained by subtracting the threshold voltage of the transistor 105 from the potential of the gate of the transistor 105 (for example, the potential VDD), the transistor 105 turns off. Thus , the node N1 becomes a floating state.

[0040] When the transistor 103 is turned on, the signal CK1 is supplied to the wiring 14. During the period T1 , since the signal CK1 is at a low level, the potential of the wiring 14 becomes the potential VSS. That is, the signal OUTB becomes a low level.

[0041] When the transistor 104 is turned off, the node N2 becomes a floating state. Thus, the potential of the node N2 is maintained at a potential exceeding the sum of the potential VDD and the threshold voltage of the transistor 101 .

[0042] When the transistor 101 is turned on and the transistor 102 is turned off, the potential VDD of the wiring 11 is supplied to the wiring 12. Thus, the potential of the wiring 12 becomes the potential VDD. That is , the signal OUTA becomes a high level.

[0043] During the period T2, the signal SP becomes a low level, the signal CK1 becomes a high level, and the signal CK 2 becomes a low level.

[0044] When the transistor 105 is turned off, the node N1 becomes a floating state.

[0045] When the transistor 103 is turned on, the signal CK1 on the wiring 15 is supplied to the wiring 14 . During period T2, since signal CK1 is at a high level, the potential of wiring 14 rises. At this time, node N1 is in a floating state, and transistor 103 holds the potential difference between node N1 and wiring 14. Therefore, as the potential of wiring 14 rises, the potential of node N1 also rises. When the potential of node N1 exceeds the sum of the potential of the first terminal of transistor 103 (for example, potential V DD) and the threshold voltage of transistor 103, the potential of wiring 14 becomes potential VDD. That is, signal OUTB becomes a high level.

[0046] When transistor 104 turns on, the potential VSS of wiring 13 is supplied to node N2 . Therefore, the potential of node N2 becomes potential VSS.

[0047] When transistor 101 turns off and transistor 102 turns on, the potential VSS of wiring 13 is supplied to wiring 12. Therefore, the potential of wiring 12 becomes potential VSS. That is, signal OUTA becomes a low level.

[0048] As described above, signal OUTA becomes a high level in period T1 and a low level in period T2. Also, signal OUTB becomes a low level in period T1 and a high level in period T2.

[0049] Next, a sequential circuit using the basic circuit of FIG. 1(A) will be described.

[0050] FIG. 2(A) is a circuit diagram of the sequential circuit of the present embodiment. The sequential circuit of FIG. 2(A) includes transistors 101 to 107. Note that transistors 106 and 107 have the same polarity as transistor 101.

[0051] ​ It is preferable. In this embodiment, transistors 106 and 107 are described as being of the N channel type.

[0052] Note that the transistor 106 of the sequential circuit in Fig. 2(A) may not be provided. Also, the transistor 107 of the sequential circuit in Fig. 2(A ) may not be provided.

[0053] Next, the connection relationship of the sequential circuit in Fig. 2(A) will be described.

[0054] The connection relationships of transistors 101 to 105 are the same as those of the basic circuit in Fig. 1(A), so the description thereof will be omitted. The first terminal of transistor 106 is connected to wiring 13, the second terminal of transistor 106 is connected to wiring 14, and the gate of transistor 106 is connected to node N2. The first terminal of transistor 107 is connected to wiring 11, and the second terminal of transistor 107 is connected to node N2, and the gate of transistor 107 is connected to wiring 16.

[0055] Next, the operation of the sequential circuit in Fig. 2(A) will be described.

[0056] Fig. 2(B) is a timing chart for explaining the operation of the sequential circuit in Fig. 2(A). . The timing chart in Fig. 2(B) shows the signal CK1, signal CK2, signal SP, the potential VN1 of node N1 , the potential VN2 of node N2, signal OUTA, and signal OUTB.

[0057] For the sake of convenience, the high-level potential of signal SP, signal CK1, and signal CK2 is described as potential VDD, and the low-level potential is described as potential VSS.

[0058] For the sake of convenience, the initial value of the potential VN1 of node N1 is the potential VSS, and the potential VN2 of node N2 is described as a potential exceeding the sum of the potential VDD and the threshold voltage of transistor 101.

[0059] For the sake of convenience, it will be described separately in terms of period T1, period T2, period T3, and period T4.

[0060] In period T1, signal SP becomes high level, signal CK1 becomes low level, and signal CK 2 becomes high level.

[0061] When transistor 105 turns on, the signal SP on wiring 17 is supplied to node N1. Since signal SP is at high level in period T1, the potential of node N1 rises. Node When the potential of N1 rises to a potential obtained by subtracting the threshold voltage of transistor 105 from the potential of the gate of transistor 105 (for example, potential VDD), transistor 105 turns off. Thus node N1 becomes floating.

[0062] When transistor 103 turns on and transistor 106 turns on, the signal CK1 on wiring 15 and the potential VSS on wiring 13 are supplied to wiring 14. Since signal CK1 is at low level in period T1, the potential of wiring 14 becomes potential VSS. That is, signal OUTB becomes low level.

[0063] When transistor 107 turns off and transistor 104 turns off, node N2 becomes floating. Thus, the potential of node N2 is maintained at a potential exceeding the sum of the potential of the first terminal of transistor 101 (for example, potential VDD) and the threshold voltage of transistor 101.

[0064] ​​​​If the initial value of the potential VN2 of the node N2 is the potential VSS, the transistor 107 turns on, and the potential VDD of the wiring 11 is supplied to the node N2. When the transistor 101 turns on and the transistor 102 turns off, the potential VDD of the wiring 11 is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. That is, the signal OUTA becomes high level.

[0065] When the transistor 101 turns on and the transistor 102 turns off, the potential VDD of the wiring 11 is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. That is, the signal OUTA becomes high level. When the transistor 101 turns on and the transistor 102 turns off, the potential VDD of the wiring 11 is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. That is, the signal OUTA becomes high level. When the transistor 101 turns on and the transistor 102 turns off, the potential VDD of the wiring 11 is supplied to the wiring 12. Therefore, the potential of the wiring 12 becomes the potential VDD. That is, the signal OUTA becomes high level.

[0066] In the period T2, the signal SP becomes low level, the signal CK1 becomes high level, and the signal CK2 becomes low level. In the period T2, the signal SP becomes low level, the signal CK1 becomes high level, and the signal CK2 becomes low level.

[0067] Since the transistor 105 turns off, the node N1 becomes a floating state.

[0068] When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level. When the transistor 103 turns on and the transistor 106 turns off, the signal CK1 of the wiring 15 is supplied to the wiring 14. Since the signal CK1 is high level in the period T2, the potential of the wiring 14 rises. At this time, the node N1 is in a floating state, and a potential difference between the node N1 and the wiring 14 is held between the gate of the transistor 103 and the second terminal of the transistor 103. Therefore, as the potential of the wiring 14 rises, the potential of the node N1 also rises. When the potential of the node N1 rises to a potential exceeding the sum of the potential of the first terminal of the transistor 103 (for example, the potential VDD) and the threshold voltage of the transistor 103, the potential of the wiring 14 becomes the potential VDD. That is, the signal OUTB becomes high level.

[0069] When the transistor 107 turns off and the transistor 104 turns on, the potential VSS of the wiring 13 is supplied to the node N2. Therefore, the potential of the node N2 becomes the potential VSS. When the transistor 107 turns off and the transistor 104 turns on, the potential VSS of the wiring 13 is supplied to the node N2. Therefore, the potential of the node N2 becomes the potential VSS.

[0070] When transistor 101 turns off and transistor 102 turns on, the potential of wiring 13 The potential VSS is supplied to wiring 12. Thus, the potential of wiring 12 becomes the potential VSS. That is the signal OUTA becomes a low level.

[0071] During period T3, the signal SP becomes a low level, the signal CK1 becomes a low level, and the signal CK 2 becomes a high level.

[0072] When transistor 105 turns on, the signal SP on wiring 17 is supplied to node N1 . Since the signal SP is at a low level during period T3, the potential of node N1 becomes the potential VSS .

[0073] When transistor 103 turns off and transistor 106 turns on, the potential of wiring 13 The potential VSS is supplied to wiring 14. Thus, the potential of wiring 14 becomes the potential VSS. That is the signal OUTB becomes a low level.

[0074] When transistor 107 turns on and transistor 104 turns off, the potential of wiring 11 The potential VDD is supplied to node N2. Thus, the potential of node N2 rises. The potential of node N 2 rises from the potential of the gate of transistor 107 (for example, potential VDD) to the potential obtained by subtracting the threshold voltage of transistor 1 07, then transistor 107 turns off. Thus , node N2 becomes a floating state.

[0075] When transistor 101 turns on and transistor 102 turns off, the potential of wiring 11 The potential VDD is supplied to wiring 12. Thus, the potential of wiring 12 rises. At this time, node Node N2 is in a floating state, and the potential difference between the gate of transistor 101 and the second terminal of transistor 101 is maintained between node N2 and wiring 12. Therefore, as the potential of wiring 1 2 rises, the potential of node N2 also rises. When the potential of node N2 rises to a potential exceeding the sum of the potential of the first terminal of transistor 101 (for example, potential VDD) and the threshold voltage of transistor 101, the potential of wiring 12 becomes potential VDD. That is, signal OUT TA becomes high level.

[0076] During period T4, signal SP becomes low level, signal CK1 becomes high level, and signal CK 2 becomes low level.

[0077] When transistor 105 turns off, node N1 becomes a floating state. Therefore, the potential of node N1 is maintained at the potential in period T3.

[0078] When transistor 103 turns off and transistor 106 turns on, potential VSS of wiring 13 is supplied to wiring 14. Therefore, the potential of wiring 14 becomes potential VSS. That is, signal OUTB becomes low level.

[0079] When transistor 107 turns off and transistor 104 turns off, node N2 becomes a floating state. Therefore, the potential of node N2 is maintained at the potential in period T3.

[0080] When transistor 101 turns on and transistor 102 turns off, potential VDD of wiring 11 is supplied to wiring 12. Therefore, the potential of wiring 12 becomes potential VDD. That is, signal OUTA becomes high level.

[0081] As described above, signal OUTA goes low during period T2 and goes high during periods T1, T 3, and T4. Also, signal OUTB goes high during period T2 and goes low during periods T1, T3, and T4.

[0082] Next, a shift register circuit using the sequential circuit of FIG. 2(A) will be described.

[0083] FIG. 3 is a circuit diagram of the shift register circuit of the present embodiment. The shift register circuit of FIG. 3 has N (N is a natural number) sequential circuits 100 (also referred to as N stages). However, in FIG. 3, only the first to third sequential circuits (shown as sequential circuits 100[1], 100[2], and sequential circuit 100[3]) are shown.

[0084] Note that as the N sequential circuits 100, the sequential circuit of FIG. 2(A) is used respectively.

[0085] Next, the connection relationship of the shift register circuit of FIG. 3 will be described.

[0086] The shift register circuit of FIG. 3 is connected to N wirings 21, N wirings 22, wiring 23, wiring 24, wiring 25, wiring 26, and wiring 27.

[0087] Specifically, in the i-th (where i is any one of 2 to N) sequential circuit 100 (shown as sequential circuit 100 i]), the second terminal of transistor 101 is connected to wiring 21[i]. The gate of transistor 102 is connected to wiring 22[i]. The first terminal of transistor 105 is connected to wiring 22[i - 1]. The first terminal of transistor 101 is connected to wiring 2 3. The first terminal of transistor 102 is connected to wiring 24. The transistor The first terminal of the transistor 103 is connected to one of the wirings 25 and 26. The gate of the transistor 107 is connected to the other of the wirings 25 and 26.

[0088] That is, in the sequential circuit 100[i], the wiring 21[i] corresponds to the wiring 12. The wiring 22[i] corresponds to the wiring 14. The wiring 23 corresponds to the wiring 11. The wiring 24 corresponds to the wiring 13. One of the wirings 25 and 26 corresponds to the wiring 15. The other of the wirings 25 and 2 6 corresponds to the wiring 16. The wiring 22[i - 1] corresponds to the wiring 17.

[0089] Note that in the sequential circuit 100[i - 1] or the sequential circuit 100[i + 1], the first terminal of the transistor 103 is connected to the other of the wirings 25 and 26. The gate of the transistor 107 is connected to one of the wirings 25 and 26. That is, the connection destinations of the first terminal of the transistor 103 and the gate of the transistor 107 are interchanged between the odd-numbered stages and the even-numbered stages.

[0090] Note that in the sequential circuit 100[1], the connection of the first terminal of the transistor 105 to the wiring 27 is different from that of the sequential circuit 100 at the i-th stage.

[0091] Next, the signals or potentials of the wirings 21 to 27 will be described.

[0092] The signal SOUTA is output from the wiring 21. The signal SOUTB is output from the wiring 22 The potential VDD is supplied to the wiring 23. The potential VSS is supplied to the wiring 24. The wiring 25 receives the signal SCK1. The wiring 26 receives the signal SCK2. The wiring 27 receives the signal SSP.

[0093] ​ Note that signal SOUTA corresponds to signal OUTA. Signal SOUTB corresponds to signal OUTB. Signal SCK1 corresponds to signal CK1 or signal CK2. Signal SCK2 corresponds to signal CK1 or signal CK2. Signal SSP corresponds to signal SP.

[0094] Next, the operation of the shift register circuit in FIG. 3 will be described.

[0095] FIG. 4 is a timing chart for explaining the operation of the shift register circuit in FIG. 3. The timing chart in FIG. 4 shows signals SSP, SCK1, SCK2, SOUT A[1] to SOUTA[3], SOUTA[N - 1], SOUTA[N] , SOUTB[1] to SOUTB[3], SOUTB[N - 1], S OUTB[N].

[0096] When signal SOUTB[i - 1] becomes high level, sequential circuit 100[i] performs the operation during period T1. Therefore, signal SOUTA[i] becomes high level and signal SOUTB [i] becomes low level.

[0097] After that, when signals SCK1 and SCK2 are inverted, sequential circuit 100[i] performs the operation during period T2. Therefore, signal SOUTA[i] becomes low level and signal SOUT B[i] becomes high level.

[0098] After that, until signal SOUTB[i - 1] becomes high level again, every time signals SCK1 and SCK2 are inverted, sequential circuit 100[i] repeats the operation during period T3 and the operation during period T4. Therefore, signal SOUTA[i] becomes high level and signal SOU TB[i] becomes low level.

[0099] When the signal SSP goes high, the sequential circuit 100[1] stops operating during the period T1. The difference from the sequential circuit 100[i] is that

[0100] As described above, the signals SOUTA[1] to SOUTA[N] are generated when the signal SSP is at a high level. After the signal SOUTB[1] becomes a high level, the signal SOUTB[2] becomes a low level. After the signal SSP goes to high level, TB[N] goes to high level in sequence.

[0101] Next, the functions of the transistors 101 to 107 will be described.

[0102] Each of the transistors 101 to 107 has a first terminal connected to a second terminal. The first terminal has a function to control the continuity between the first terminal and the connected terminal. The transistor 10 has a function of supplying a signal or potential to a connection destination of the second terminal. 2 has a function of controlling electrical continuity or non-conduction between the wiring 13 and the wiring 12. to the wiring 12.

[0103] In addition, the transistors 101 and 103 have gates and second terminals connected to each other. For example, the transistor 101 has a function of holding a potential difference between the node N2 and It has a function of maintaining a potential difference with the wiring 12 .

[0104] The transistor 105 and the transistor 107 have first terminals connected to the second terminals. After the connection of the first terminal is made conductive, the connection of the second terminal is made non-conductive. It has a function. Also, it has a function of supplying the signal or potential etc. at the connection destination of the first terminal to the connection destination of the second terminal and then stopping the supply of the signal or potential etc. at the connection destination of the first terminal. For example, after making the transistor 105 conduct the wiring 17 and the node N1, the transistor 105 has a function of making the wiring 17 and the node N1 non-conductive. Also, after supplying the signal SP to the node N1, it has a function of stopping the supply of the signal SP .

[0105] Also, the transistor 101 has a function of supplying a signal or potential etc. for raising the potential of the wiring 12 . The transistor 102 has a function of supplying a signal or potential etc. for lowering the potential of the wiring 12 . The transistor 103 has a function of supplying a signal or potential etc. for raising the potential of the wiring 14 . The transistor 104 has a function of supplying a signal or potential etc. for turning off the transistor 101 to the node N2 . The transistor 105 has a function of supplying a signal or potential etc. for turning on the transistor 103 to the node N1 . The transistor 106 has a function of supplying a signal or potential etc. for lowering the potential of the wiring 14 . The transistor 107 has a function of supplying a signal or potential etc. for turning on the transistor 101 to the node N2 .

[0106] In one aspect of the present invention, the transistor may be replaced with a switch having a function of controlling conduction or non-conduction between the first terminal and the second terminal. The first terminal of the transistor corresponds to the first terminal of the switch, and the second terminal of the transistor corresponds to the second terminal of the switch . Also, if necessary, the gate of the transistor corresponds to the control terminal of the switch.

[0107] ​​Next, the W / L (W: channel width, L: channel length) of transistors 101 to 107 will be described.

[0108] The W / L of transistor 101 is preferably larger than the W / L of transistors 102 to 107. Also, the W / L of transistor 102 is preferably larger than the W / L of transistor 104. Also, the W / L of transistor 103 is preferably larger than the W / L of transistor 105. Also, the W / L of transistor 104 is preferably larger than the W / L of transistor 106.

[0109] By the way, when P-channel transistors are used as transistors 101 to 107, it is preferable to supply the potential VSS to wiring 11 and supply the potential VDD to wiring 13. Also, it is preferable to invert signals CK1, signal CK2, and signal SP. Then, signals OUTA and OUTB are also inverted. Also, when P-channel transistors are used as transistors 101 to 107, in the above description, "rising" may be replaced with "falling" and "falling" may be replaced with "rising".

[0110] Next, the effects exhibited by the basic circuit, sequential circuit, and shift register circuit of this embodiment will be described.

[0111] In a circuit composed of N-channel transistors, a low-level signal can be shifted. Also, in a circuit composed of P-channel transistors, a high-level signal can be shifted.

[0112] ​​​​​​​​​​​​​In addition, signals such as signal OUTA and signal SOUTA can be generated with a small number of transistors. This is possible.

[0113] In addition, since it is possible to eliminate the period during which both transistor 107 and transistor 104 are turned on, the current generated between wiring 11 and wiring 13 can be reduced. Therefore, power consumption can be reduced. Therefore, power consumption can be reduced.

[0114] In addition, since it is possible to eliminate the period during which both transistor 101 and transistor 102 are turned on, the current generated between wiring 11 and wiring 13 can be reduced. Therefore, power consumption can be reduced. Therefore, power consumption can be reduced.

[0115] In addition, during the period when signal CK1 is at a high level, since it is possible to eliminate the period during which both transistor 103 and transistor 106 are turned on, the current generated between wiring 15 and wiring 13 can be reduced. Therefore, power consumption can be reduced. Therefore, power consumption can be reduced.

[0116] In addition, during period T3, by turning on transistor 105, a low-level signal SP can be supplied to node N1. Therefore, the potential of node N1 can be easily maintained at potential VSS, and malfunction can be prevented. Therefore, the potential of node N1 can be easily maintained at potential VSS, and malfunction can be prevented.

[0117] In addition, during period T3, by turning on transistor 107, potential VDD can be supplied to node N2. Therefore, the potential of node N2 can be easily maintained at a high potential, and malfunction can be prevented. Therefore, the potential of node N2 can be easily maintained at a high potential, and malfunction can be prevented.

[0118] In addition, during period T3 and period T4, by turning on transistor 106, wiring 1 The potential VSS of 3 can be supplied to the wiring 14. Therefore, it is possible to easily maintain the potential of the wiring 14 at the potential VS S and prevent malfunction.

[0119] This embodiment can be implemented in appropriate combination with other embodiments etc.

[0120] (Embodiment 2) In this embodiment, a basic circuit, a sequential circuit, and a shift register circuit different from those in Embodiment 1 will be described. However, parts common to Embodiment 1 are denoted by common reference numerals and the description thereof is omitted. description is omitted.

[0121] In this embodiment, the basic circuit, the sequential circuit, and the shift register circuit of this embodiment may be described using a drawing in which the sequential circuit in Fig. 2(A) is modified. However, the configuration described in this embodiment can be applied not only to the sequential circuit in Fig. 2(A), but also to other basic circuits, sequential circuits, and shift register circuits described in Embodiment 1.

[0122] The basic circuit, the sequential circuit, and the shift register circuit of this embodiment exhibit the same effects as those described in Embodiment 1.

[0123]

[0124]

[0124] 05 may be connected to the wiring 17.

[0125] FIG. 5(A) is a circuit diagram of a sequential circuit in which the first terminal of transistor 105 is connected to wiring 17, the second terminal of transistor 10 5 is connected to node N1, and the gate of transistor 105 is connected to wiring 17 .

[0126] Next, a connection relationship different from that of Embodiment 1 of transistor 107 will be described.

[0127] The first terminal of transistor 107 may be connected to wiring 16, the second terminal of transistor 107 may be connected to node N2, and the gate of transistor 107 may be connected to wiring 16. Also , the first terminal of transistor 107 may be connected to wiring 11, the second terminal of transistor 107 may be connected to node N2, and the gate of transistor 107 may be connected to wiring 11.

[0128] FIG. 5(B) is a circuit diagram of a sequential circuit in which the first terminal of transistor 107 is connected to wiring 16, the second terminal of transistor 10 7 is connected to node N2, and the gate of transistor 107 is connected to wiring 16 .

[0129] Next, a connection relationship different from that of Embodiment 1 of transistor 104 will be described.

[0130] The first terminal of transistor 104 may be connected to wiring 13, the second terminal of transistor 104 may be connected to node N2, and the gate of transistor 104 may be connected to node N1 or wiring 17 .

[0131] FIG. 6(A) is a circuit diagram of a sequential circuit in which the first terminal of transistor 104 is connected to wiring 13, the second terminal of transistor 10 4 is connected to node N2, and the gate of transistor 104 is connected to node N1 .

[0132] Next, a connection relationship different from Embodiment 1 of transistor 102 will be described.

[0133] Connect the first terminal of transistor 102 to wiring 13, and the second terminal of transistor 102 to wiring 12, and connect the gate of transistor 102 to node N1 or wiring 17. This is also possible.

[0134] FIG. 6(B) is a circuit diagram of a sequential circuit in which the first terminal of transistor 102 is connected to wiring 13, the second terminal of transistor 10 2 is connected to wiring 12, and the gate of transistor 102 is connected to node N1. is a circuit diagram of a sequential circuit.

[0135] Next, a connection relationship different from Embodiment 1 of transistor 106 will be described.

[0136] Connect the first terminal of transistor 106 to wiring 13, and the second terminal of transistor 106 to wiring 14, and connect the gate of transistor 106 to wiring 16. This can shorten the time when transistor 106 turns on, and since the potential VSS of wiring 13 can be supplied to wiring 14 during period T3, the potential of wiring 14 can be stably maintained. in the period T3, the potential of wiring 13 can be supplied to wiring 14, so the potential of wiring 14 can be stably maintained.

[0137] FIG. 7(A) is a circuit diagram of a sequential circuit in which the first terminal of transistor 106 is connected to wiring 13, the second terminal of transistor 10 6 is connected to wiring 14, and the gate of transistor 106 is connected to wiring 16. is a circuit diagram of a sequential circuit.

[0138] Next, a configuration in which transistors 201, 202, 203, and transistor 204 are provided will be described.

[0139] FIG. 7(B) is a circuit diagram of a sequential circuit provided with transistors 201, 202, 203, and 204. The first terminal of transistor 201 is connected to wiring 13, the second terminal of transistor 201 is connected to node N1, and the gate of transistor 201 is connected to wiring 31. The first terminal of transistor 202 is connected to wiring 11, the second terminal of transistor 202 is connected to node N2, and the gate of transistor 202 is connected to wiring 31. The first terminal of transistor 203 is connected to wiring 11, the second terminal of transistor 203 is connected to wiring 12, and the gate of transistor 203 is connected to wiring 31. The first terminal of transistor 204 is connected to wiring 13, the second terminal of transistor 204 is connected to wiring 14, and the gate of transistor 204 is connected to wiring 31.

[0140] A signal RE is input to wiring 31. The signal RE is a digital signal having a high level and a low level. However, it is sufficient that a signal for controlling conduction or non-conduction of transistors 201 to 204 is input to wiring 31.

[0141] In the sequential circuit 100[i], the wiring 31 corresponds to the wiring 22[i + 1]. However, the wiring 31 may correspond to the wiring 22[i + n] (n is a natural number) such as the wiring 22[i + 2] or the wiring 22[i + 3].

[0142] When the signal RE becomes high level, transistors 201 to 204 turn on. When transistors 201 and 204 turn on, the potential V of wiring 13 ​​​​​​​​​​​​​​SS is supplied to node N1 and wiring 14. Therefore, the potentials of node N1 and wiring 14 become the potential VSS. Also, when transistors 202 and 203 are turned on , the potential VDD of wiring 11 is supplied to node N2 and wiring 12. Therefore, the potential of node N2 and wiring 12 becomes a potential higher than the potential VDD or the potential VSS.

[0143] On the other hand, when the signal RE becomes a low level, transistors 201 to 204 are turned off.

[0144] An example of the timing of the signal RE will be described. When wiring 31 corresponds to wiring 22[i + 1] , the signal RE corresponds to the signal OUTB[i + 1]. Therefore, the signal RE becomes a high level after the period T2 (for example, in the period T3 immediately after the period T2), and becomes a low level in other periods. Therefore, after the period T2, the sequential circuit can be initialized.

[0145] Note that only one, two, or three transistors selected from transistors 201 to 204 may be provided.

[0146] Next, a configuration in which transistors 205, 206, 207, and transistor 208 are provided will be described.

[0147] FIG. 8(A) is a circuit diagram of a sequential circuit in which transistors 205, 206, 207, and tra nsistor 208 are provided. The connection relationship of transistors 205 to 208 is different from that of transistors 201 to 204 in that the gate is connected to wiring 32.

[0148] ​​​​ In all or at least two of the N sequential circuits 100, the connection destinations of the gates of the transistors 205 to 208 are common. The signal INI is input to the wiring 32. The signal INI is a digital signal having a high level and a low level. However, it is sufficient that a signal for controlling the conduction or non - conduction of the transistors 205 to 208 is input to the wiring 32.

[0149] When the signal INI becomes high level, the transistors 205 to 208 turn on. When the transistors 205 and 208 turn on, the potential VSS of the wiring 13 is supplied to the node N1 and the wiring 14. Therefore, the potentials of the node N1 and the wiring 14 become the potential VSS. Also, when the transistors 206 and 207 turn on, the potential VDD of the wiring 11 is supplied to the node N2 and the wiring 12. Therefore, the potentials of the node N2 and the wiring 12 become a potential higher than the potential VDD or the potential VSS.

[0150]

[0151]

[0152] On the other hand, when the signal INI becomes low level, the transistors 205 to 208 turn off.

[0151]

[0152] An example of the timing of the signal INI will be described. Before the period during which the signal SSP becomes high level, the signal INI becomes high level. Therefore, before the first - stage sequential circuit 100 performs the operation in the period T1, each sequential circuit 100 can be initialized. Therefore, malfunction can be prevented.

[0153]

[0153] After the signal OUTB[N] becomes high level and the signal SSP becomes high level Before becoming so, it is preferable that the signal INI becomes high level. Also, after power-on and when present and before the signal SSP becomes high level, it is also acceptable that the signal INI becomes high level and so on.

[0154] Note that the first terminal of the transistor 207 may be connected to the wiring 13.

[0155] Note that the gates of the transistors 205 to 208 may be connected to the wiring 27 . That is, the signal SSP may be used as the signal INI.

[0156] Note that only one, two, or three transistors selected from the transistors 205 to 208 may be provided.

[0157] Next, a configuration in which the transistors 209 and 210 are provided will be described.

[0158] FIG. 8(B) is a circuit diagram of a sequential circuit in which the transistors 209 and 210 are provided . The first terminal of the transistor 209 is connected to the wiring 13, and the second terminal of the transistor 209 is connected to the wiring 14, and the gate of the transistor 209 is connected to the wiring 16. The first terminal of the transistor 210 is connected to the wiring 11, and the second terminal of the transistor 210 is connected to the wiring 12, and the gate of the transistor 210 is connected to the wiring 16.

[0159] When the signal CK2 becomes high level, the transistors 209 and 210 turn on. When the transistor 209 turns on, the potential VSS of the wiring 13 is supplied to the wiring 14 . When the transistor 210 turns on, the potential VDD of the wiring 11 is supplied to the wiring 12 .

[0160] On the other hand, when the signal CK2 becomes low level, the transistors 209 and 210 turn off.

[0161] The signal CK2 becomes high level in the periods T1 and T3, and becomes low level in the periods T2 and T4. Therefore, in the periods T1 and T3, the potential V SS of the wiring 13 is supplied to the wiring 14, and the potential VDD of the wiring 11 is supplied to the wiring 12. In particular, when the signal CK2 becomes high level in the period T3, the potential VSS of the wiring 13 is periodically supplied to the wiring 1 4, and the potential VDD of the wiring 11 is periodically supplied to the wiring 12. Therefore , it becomes easier to maintain the potentials of the wiring 14 and the wiring 12.

[0162] Note that only one of the transistors 209 and 210 may be provided.

[0163] Next, a configuration in which the transistors 211 and 212 are provided will be described.

[0164] FIG. 9(A) is a circuit diagram of a sequential circuit in which the transistors 211 and 212 are provided therein. The first terminal of the transistor 211 is connected to the wiring 17, and the second terminal of the transistor 211 is connected to the first terminal of the transistor 105, and the gate of the transistor 211 is connected to the wiring 33. The first terminal of the transistor 212 is connected to the wiring 31, and the second terminal of the transistor 212 is connected to the first terminal of the transistor 105, and the gate of the transistor 212 is connected to the wiring 34.

[0165] Note that in all or at least two of the N sequential circuits 100, the The connection destinations of the gates are common, and the connection destinations of the gates of the transistor 212 are also common.

[0166] A signal SC1 is input to the wiring 33. The signal SC1 has a high level and a low level and is a digital signal. However, it is sufficient that a signal or potential for controlling conduction or non - conduction of the transistor 211 is input to the wiring 33. Also, a signal SC2 is input to the wiring 34 . The signal SC2 has a high level and a low level and is a digital signal. However , it is sufficient that a signal or potential for controlling conduction or non - conduction of the transistor 212 is input to the wiring 34.

[0167] When the signal SC1 becomes high level and the signal SC2 becomes low level, the transistor 211 turns on and the transistor 212 turns off. When the transistor 211 turns on, the signal SP on the wiring 17 is supplied to the first terminal of the transistor 105.

[0168] On the other hand, when the signal SC1 becomes low level and the signal SC2 becomes high level, the transistor 211 turns off and the transistor 212 turns on. When the transistor 212 turns on, the signal RE on the wiring 31 is supplied to the first terminal of the transistor 105.

[0169] An example of the timing of the signal SC1 and the signal SC2 will be described. When the shift direction of the shift register circuit is from the sequential circuit 100[1] to the sequential circuit 100[N], the signal SC1 becomes high level and the signal SC2 becomes low level. Also, when the shift direction of the shift register circuit is from the sequential circuit 100[N] to the sequential circuit 100[1], the signal SC1 becomes low level and the signal SC2 becomes high level. ​

[0170] Next, a configuration in which transistors 213 and 214 are provided will be described.

[0171] FIG. 9(B) is a circuit diagram of a sequential circuit in which transistors 213 and 214 are provided. One terminal of transistor 213 is connected to the second terminal of transistor 105. The second terminal of transistor 213 is connected to the gate of transistor 103, and the gate of transistor 213 is connected to wiring 11. One terminal of transistor 214 is connected to the second terminal of transistor 107. The second terminal of transistor 214 is connected to the gate of transistor 101, and the gate of transistor 214 is connected to wiring 11. By including transistor 213, it is possible to prevent the potential of the gate of transistor 103 from rising too high. Therefore, it is possible to suppress deterioration of transistor 103 or prevent dielectric breakdown.

[0172] Also, by including transistor 214, it is possible to prevent the potential of the gate of transistor 101 from rising too high. Therefore, it is possible to suppress deterioration of transistor 101 or prevent dielectric breakdown. In addition, since the Vgs of transistor 106 can be reduced, deterioration of transistor 106 can be suppressed.

[0173] Note that the gate of transistor 213 may be connected to wiring 12, wiring 16, wiring 17, the gate of transistor 101, etc. Also, the first terminal of transistor 213 may be connected to wiring 17, and the second terminal of transistor 213 may be connected to the first terminal of transistor 105. Furthermore, the second terminal of transistor 214 may be connected to the gate of transistor 106, and the gate of transistor 214 may be connected to wiring 12, wiring 16, wiring 17, the gate of transistor 101, etc. Moreover, since the Vgs of transistor 106 can be made small, deterioration of transistor 106 can be suppressed.

[0174] Note that the gate of transistor 213 may be connected to wiring 12, wiring 16, wiring 17, the gate of transistor 101, etc. Also, the first terminal of transistor 213 may be connected to wiring 17, and the second terminal of transistor 213 may be connected to the first terminal of transistor 105. Moreover, the second terminal of transistor 214 may be connected to the gate of transistor 106, and the gate of transistor 214 may be connected to wiring 12, wiring 16, wiring 17, the gate of transistor 101, etc. Okay.

[0175] Note that the gate of transistor 214 may be connected to wirings 12, 16, etc. Also, the first terminal of transistor 214 may be connected to wiring 11, and the second terminal of transistor 214 may be connected to the first terminal of transistor 107.

[0176] Note that the gate of transistor 106 may be connected to the second terminal of transistor 104. .

[0177] Note that only one of transistors 213 and 214 may be provided.

[0178] Next, a configuration in which a part of the transistors is replaced with switches will be described.

[0179] FIG. 10(A) is a circuit diagram of a sequential circuit using switches as transistors 104, 106, and 107. Switches 104S, 106S, and 107S respectively correspond to transistors 104, 106, and transistor 107. Also, the first terminal of switch 104S is connected to wiring 13, and the second terminal of switch 104S is connected to the gate of transistor 101. The first terminal of switch 106S is connected to wiring 13, and the second terminal of switch 106S is connected to wiring 14. The first terminal of switch 107S is connected to wiring 11, and the second terminal of switch 107S is connected to the gate of transistor 101. During period T1, switch 104S turns off, switch 106S turns on, and switch

[0180] 107S turns on. Also, during period T2, switch 104S turns on. and switches 106S and 107S turn off. , switch 106S turns off and switch 107S turns off. Also, during period T3 , switch 104S turns off, switch 106S turns on, and switch 107 S turns on. Also, during period T4, switch 104S turns off, switch 1 06S turns on, and switch 107S turns off.

[0181] Note that switch 104S may turn on during period T1. Also, switch 106 S may turn off during one of period T3 and period T4. Also, switch 107S may turn on during period T4.

[0182] Note that FIG. 10(B) is a circuit diagram of a basic circuit using switch 104S as transistor 104. Also, FIG. 11(A) is a circuit diagram of a basic circuit with switch 106S added to the basic circuit of FIG. 10(B). Also, FIG. 11(B) is a circuit diagram of a basic circuit with switch 107S added to the basic circuit of FIG. 10(B).

[0183] Next, the functions of transistors 201 to 214 will be described.

[0184] Each of transistors 201 to 214 has a function of controlling conduction or non - conduction between the connection destination of the first terminal and the connection destination of the second terminal. Also, it has a function of supplying a signal or potential, etc. of the connection destination of the first terminal to the connection destination of the second terminal. For example, transistor 2 01 has a function of controlling conduction or non - conduction between wiring 13 and node N1. Also, it has a function of supplying potential V SS to node N1.

[0185] Also, transistors 213 and 214 are between the connection destination of the first terminal and the second terminal​​ After making the connection destination of [the relevant part] conductive, make the connection destination of the first terminal and the connection destination of the second terminal non-conductive. It has a function. Also, supply the signal or potential etc. of the connection destination of the first terminal to the connection destination of the second terminal and then has a function of stopping the supply of the signal or potential etc. of the connection destination of the first terminal. For example, transistor 213 makes the second terminal of transistor 105 and the gate of transistor 103 conductive and then has a function of making the second terminal of transistor 105 and the gate of transistor 103 non-conductive. Also, after supplying the potential of the second terminal of transistor 105 to node N1 it has a function of stopping the supply of the potential of the second terminal of transistor 105.

[0186] By the way, transistors 201 to 214 preferably have the same polarity as transistor 101.

[0187] Also, it is preferable that the W / L of transistor 101 is larger than the W / L of transistors 201 to 214.

[0188] This embodiment can be implemented in appropriate combination with other embodiments etc.

[0189] (Embodiment 3) In this embodiment, a display device according to an aspect of the present invention will be described.

[0190] FIG. 12(A) is a circuit diagram of the display device of this embodiment. The display device in FIG. 12(A) has a pixel portion 300, a gate driver 301, a gate driver 302, and a source driver 3 03. The pixel portion 300 has a plurality of pixels 310. Each of the plurality of pixels 310 has a transistor 311, a transistor 312, a display element 313, and a circuit 32 ​​It has 0 and. Note that as the gate driver 302, the shift register circuits of Embodiment 1 and Embodiment 2 can be used.

[0191] Note that in one aspect of the present invention, as the display element, a liquid crystal element (also referred to as a liquid crystal display element) , a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes an element whose luminance is controlled by current or voltage within its scope. Specifically, it includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Also, a display medium whose contrast changes due to an electrical action, such as an electro ink, can also be applied.

[0192]

[0193] Next, the connection relationship of the display device in FIG. 12(A) will be described.

[0193] The gate driver 301 is connected to N wirings 41. The gate driver 302 is connected to N wirings 42. The source driver 303 is connected to M (M is a natural number) wirings 43. Note that in FIG. 12(A), the i-th wiring 41 (shown as wiring 41[i]) among the N wirings 41, the i-th wiring 42 (shown as wiring 42[i]) among the N wirings 42, and the j-th (j is any one of 1 to M) wiring 43 (shown as wiring 43[j]) among the M wirings 43 are shown.

[0194]

[0195] The pixel 310 (shown as pixel 310[i, j]) belonging to the i-th row and j-th column among the plurality of pixels 310 is connected to wiring 41[i], wiring 42[i], wiring 43[j], and wiring 44.

[0195] In pixel 310[i, j], the first terminal of transistor 311 is connected to wiring 44 , the gate of transistor 311 is connected to circuit 320. The first terminal of transistor 312 is connected to the second terminal of transistor 311, and the second terminal of transistor 312 is connected to display element 313, and the gate of transistor 312 is connected to wiring 42[i]. . Also, circuit 320 is connected to wiring 43[j] and wiring 41[i].

[0196] Note that a voltage is input to wiring 44. Wiring 44 has a function of supplying the current flowing through display element 313.

[0197] Note that when the shift register circuits of Embodiment 1 and Embodiment 2 are used as gate driver 302, N pieces of wiring 42 correspond to N pieces of wiring 21. For example, wiring 42[i] corresponds to wiring 21[i].

[0198] Next, the operation of the display device in FIG. 12(A) will be described.

[0199] Gate driver 301 sequentially outputs high-level signals to N pieces of wiring 41. Gate driver 302 sequentially outputs low-level signals to N pieces of wiring 42. Source driver 3 03 outputs a video signal to M pieces of wiring 43.

[0200] For example, in pixel 310[i, j], when gate driver 301 outputs a high-level signal to wiring 4 1[i], the video signal on wiring 43[j] is written. This video signal is the video signal output by source driver 303 to wiring 43[j]. Thereafter, pixel 31 0[i, j] holds the video signal until gate driver 301 outputs a high-level signal to wiring 41[i] again, and performs display according to the video signal.

[0201] Specifically, when the gate driver 301 outputs a high-level signal to the wiring 41[i], the video signal is input to the circuit 320. The circuit 320 corrects the video signal according to the threshold voltage and / or mobility of the transistor 311, etc., and supplies the corrected video signal to the gate of the transistor 311. Then, the transistor 311 can supply a current according to the corrected video signal. However, during the period when the video signal is input to the circuit 320, the period when the circuit 320 corrects the video signal, and / or during the initialization period before the video signal is input to the circuit 32 0, etc., the current of the transistor 311 is often an incorrect value. If this current is supplied to the display element, the gradation may shift or black floating may occur. Therefore, during the above-described period, the gate driver 302 outputs a low-level signal to the wiring 42[i], thereby turning off the transistor 312.

[0202] When the shift register circuits of Embodiment 1 and Embodiment 2 are used as the gate driver 302, the signals output by the gate driver 302 to the wirings 42[1] to 42[N] correspond to the signals SOUTA[1] to signals SOUTA[N]. For example, the signal output by the gate driver 302 to the wiring 42[i] corresponds to the signal SOUTA[i].

[0203] As shown in FIG. 12(B), the connection point between the transistor 311 and the transistor 312 may be swapped.

[0204] When the shift register circuits of Embodiment 1 and Embodiment 2 are used as the gate driver 302, By doing so, the gate driver 302 can be configured with transistors having the same polarity as the transistors of the pixels. Therefore, not only the gate driver 301 but also the gate driver 302 can be formed on the same substrate as the pixel section 300.

[0205] This embodiment can be implemented in appropriate combination with other embodiments.

[0206] (Embodiment 4) In this embodiment, the cross-sectional configuration of the pixel and the drive circuit of the display device according to one aspect of the present invention will be described by taking an EL display device as an example.

[0207] FIG. 13 is a cross-sectional view of the display device of this embodiment, showing the cross-sectional views of the pixel 840 and the drive circuit 841.

[0208] The pixel 840 has a light-emitting element 832 and a transistor 831 having a function of supplying current to the light-emitting element 832. Note that the pixel 840 may have various semiconductor elements such as a transistor that controls the input of the image signal to the pixel 840 and / or a capacitor element that holds the potential of the image signal, in addition to the light-emitting element 832 and the transistor 831.

[0209] The drive circuit 841 has a transistor 830 and a capacitor element 833 for holding the gate voltage of the transistor 830. The drive circuit 841 corresponds to the basic circuit, the sequential circuit, the shift register circuit, etc. of Embodiment 1 or Embodiment 2. Specifically, the transistor 8 30 corresponds to the transistor 101 or the like. Note that the drive circuit 841 may have various semiconductor elements such as transistors and capacitor elements, in addition to the transistor 83 0 and the capacitor element 833. ​​​​​

[0210] The transistor 831 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 816, the gate insulating film 802 on the conductive film 816, and the conductive film 816 at a position overlapping the gate insulating film 802. A semiconductor film 817 located on the gate insulating film 802 and a source terminal or a drain terminal The conductive film 815 and the conductive film 818 are located over the semiconductor film 817. The film 816 also functions as a scan line.

[0211] The transistor 830 is formed by forming a conductive film serving as a gate on a substrate 800 having an insulating surface. 812, the gate insulating film 802 on the conductive film 812, and the conductive film 812 at a position overlapping the gate insulating film 802 A semiconductor film 813 located on the gate insulating film 802 and a source terminal or a drain terminal The semiconductor film 813 includes a conductive film 814 and a conductive film 819 located over the semiconductor film 813 .

[0212] The capacitor 833 is formed by forming a conductive film 812 over a substrate 800 having an insulating surface. The gate insulating film 802 and the conductive film 812 are overlapped with each other. The conductive film 819 is disposed on the substrate 811.

[0213] An insulating film 820 and an insulating layer 821 are formed on the conductive film 814, the conductive film 815, the conductive film 818, and the conductive film 819. The insulating film 821 is provided so as to be laminated in order. A conductive film 822 serving as an electrode is provided. The conductive film 822 is formed by insulating film 820 and The insulating film 821 is connected to the conductive film 818 via a contact hole 823 formed in the insulating film 821. do.

[0214] An insulating film 824 having an opening through which a part of the conductive film 822 is exposed is formed on the insulating film 821. is provided. On a part of the conductive film 822 and the insulating film 824, an EL layer 825 and a conductive film 826 that functions as a cathode are provided so as to be laminated in this order. The region where the conductive film 822, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. In addition, in one aspect of the present invention, the semiconductor of the transistor may be silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, and is used for the semiconductor film, or a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor film of the transistor, an impurity element that imparts conductivity is added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed.

[0215] When an oxide semiconductor is used for the semiconductor film of the transistor, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. Ion implantation can be used for adding the dopant. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 In addition, in one aspect of the present invention, the semiconductor of the transistor may be silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, and is used for the semiconductor film, or a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor film of the transistor, an impurity element that imparts conductivity is added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed.

[0216] When an oxide semiconductor is used for the semiconductor film of the transistor, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. Ion implantation can be used for adding the dopant. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 / cm When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, is used for the semiconductor film of the transistor, an impurity element that imparts conductivity is added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed. When an oxide semiconductor is used for the semiconductor film of the transistor, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. Ion implantation can be used for adding the dopant. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 / cm

[0217] When an oxide semiconductor is used for the semiconductor film of the transistor, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. Ion implantation can be used for adding the dopant. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 / cm When an oxide semiconductor is used for the semiconductor film of the transistor, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. Ion implantation can be used for adding the dopant. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 / cm When an oxide semiconductor is used for the semiconductor film of the transistor, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. Ion implantation can be used for adding the dopant. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 element such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 / cm 19 / cm3 Above 1×10 22 / cm 3 and below is desirable.

[0218] Note that as the silicon semiconductor, amorphous silicon produced by a vapor phase growth method such as plasma CVD method or sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by treatment such as laser annealing, single crystal silicon wafer into which hydrogen ions etc. are implanted to peel off the surface layer, single crystal silicon etc. can be used.

[0219] Note that as the oxide semiconductor, it is preferable to contain at least indium (In) or zinc (Zn). Particularly, it is preferable to contain In and Zn. Further, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Further, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer.

[0220] In addition, as other stabilizers, any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), which are lanthanoids, may be included. (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu)

[0221] ​​For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn -Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide can be used. Further, the above oxide semiconductor may contain silicon.

[0222] Note that, for example, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Further, it may contain metal elements other than In, Ga, and Zn. The In-Ga-Zn-based oxide has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high mobility, so it is suitable as a semiconductor material used for transistors.

[0223] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) of the In-Ga-Zn-based oxide and oxides in the vicinity of its composition can be used. Alternatively, In:Sn:Zn = 1: 1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) of the original atom ratio of In-Sn-Zn-based oxides and oxides in the vicinity of their compositions may be used.

[0224] For example, in the In-Sn-Zn-based oxide, a relatively high mobility can be obtained relatively easily. However, even in the In-Ga-Zn-based oxide, the mobility can be increased by reducing the defect density in the bulk.

[0225] In addition, an oxide semiconductor (purified Oxi de Semiconductor) that is highly purified by reducing impurities such as moisture or hydrogen that serve as electron donors (donors) and reducing oxygen deficiency is of type i (intrinsic semiconductor) or extremely close to type i. Therefore, a transistor using the above oxide semiconductor has the characteristic that the off-current is extremely low. In addition, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film that is highly purified by sufficiently reducing the concentration of impurities such as moisture or hydrogen and reducing oxygen deficiency, the off-current of the transistor can be reduced.

[0226] Specifically, the off-current of a transistor using a highly purified oxide semiconductor for the semiconductor film is low. This can be proven by various experiments. For example, even in an element with a channel width of 1×10 6 μm and a channel length of 10μm, when the voltage between the source terminal and the drain terminal (drain voltage) is in the range of 1V to 10V, the off-current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. In this case, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100zA / μm or less. Also, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or out of the capacitor element is controlled by the transistor to measure the off-current density. In this measurement, a highly purified oxide semiconductor film is used in the channel formation region of the transistor, and the off-current density of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, when the voltage between the source terminal and the drain terminal of the transistor is 3V, an even lower off-current density of several tens of yA / μm is obtained -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13 -13

[0227] Note that in this specification and the like, the off-current in an n-channel transistor means the current flowing between the source terminal and the drain terminal when the potential of the gate is 0 or less with the potential of the source terminal as a reference in a state where the drain terminal is at a higher potential than the source terminal and the gate -13 -13 -13 When the drain terminal is at a lower potential than the source terminal and the gate, the current flowing between the source terminal and the drain terminal means that the potential of the gate is 0 or higher when the potential of the source terminal is taken as a reference. When the potential of the gate is 0 or higher when the potential of the source terminal is taken as a reference, it means the current flowing between the source terminal and the drain terminal. end

[0228] For example, the oxide semiconductor film can be formed by a sputtering method using a target containing In (indium), Ga (gallium), and Zn ( zinc). When forming an In-Ga- Zn-based oxide semiconductor film by sputtering, preferably, a target of In-Ga-Zn-based oxide represented by an atomic ratio of In :Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 is used. By forming an oxide semiconductor film using a target of In-Ga-Zn-based oxide having the above atomic ratio , polycrystals or CAACs described later are likely to be formed. Also, the filling rate of the target containing In, Ga, and Zn is 90% or more and 100% or less, preferably 95% or more and less than 100% . By using a target with a high filling rate, the formed oxide semiconductor film becomes a dense film. end

[0229] When using a material of In-Zn-based oxide as the oxide semiconductor film, the composition of the target to be used is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (converted to molar ratio, In O 2 O 3 :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (converted to molar ratio In 2 O 3 :ZnO = 10:1 to 1:2), more preferably In:Zn = 1.5:1 to 15:1 (converted to molar ratio, In 2 O 3:ZnO = 3:4 to 15:2) is used. For example, the target used for forming an oxide semiconductor film which is an In-Zn based oxide , when the atomic ratio is In:Zn:O = X:Y:Z, Z > 1.5X + Y. By keeping the ratio of Zn within the above range, improvement in mobility can be achieved.

[0230] And specifically, for the oxide semiconductor film, a substrate is held in a processing chamber maintained in a reduced pressure state, and while removing residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and it may be formed using the above-mentioned target. During film formation, the substrate temperature may be 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the film while heating the substrate , the impurity concentration contained in the formed oxide semiconductor film can be reduced. Also, damage due to sputtering is reduced. In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump . Also, as an exhaust means, a turbo pump with a cold trap added may be used . When evacuating the film formation chamber using a cryopump , for example, compounds containing hydrogen atoms such as hydrogen atoms, water (H 2 2 O), etc. (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced.

[0231] Note that in an oxide semiconductor film formed by sputtering or the like, there may be a large amount of moisture or hydrogen ( containing a hydroxyl group) as an impurity. Since moisture or hydrogen easily forms donor levels , it is an impurity for the oxide semiconductor. Therefore, in one aspect of the present invention, oxidation​ To reduce impurities such as moisture or hydrogen in semiconductor films (dehydration or dehydrogenation) For the oxide semiconductor film, a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an oxygen atmosphere is used. Under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. The heat treatment is performed in an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less. Carry out.

[0232] By performing heat treatment on the oxide semiconductor film, moisture or hydrogen is released from the oxide semiconductor film. Specifically, the substrate temperature is 250° C. or higher and 750° C. or lower, preferably 400° C. or higher. For example, the heat treatment may be performed at 500° C. for 3 to 6 minutes. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be carried out in a short time. Therefore, processing can be performed at temperatures exceeding the distortion point of the glass substrate.

[0233] Note that the heat treatment causes oxygen to be released from the oxide semiconductor film and the oxygen to be left in the oxide semiconductor film. Therefore, in one embodiment of the present invention, a vacancy may be formed in the gate electrode in contact with the oxide semiconductor film. An insulating film containing oxygen is used as an insulating film such as a gate insulating film. After the insulating film is formed, heat treatment is performed, whereby oxygen is supplied from the insulating film to the oxide semiconductor film. With the above structure, oxygen vacancies serving as donors are reduced, and oxygen atoms contained in the oxide semiconductor film are As a result, the oxide semiconductor film can have a stoichiometric composition. This makes it possible to approach the i-type, and reduces the variation in the electrical characteristics of transistors due to oxygen vacancies. It is possible to reduce the capacitance and improve the electrical characteristics.

[0234] In addition, the heat treatment for supplying oxygen to the oxide semiconductor film is preferably performed at 200°C or higher and 400°C or lower (for example, 250°C or higher and 350°C or lower) in an atmosphere of nitrogen, ultra-dry air, or a rare gas (argon, helium, etc.). The above gas desirably has a water content of 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less.

[0235] The oxide semiconductor film may be in a single crystal, polycrystalline (also referred to as polycrystal), or amorphous state.

[0236] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

[0237] In addition, the crystal part often has a size that fits within a cube with a side length of less than 100 nm. Also, in the observation image by a transmission electron microscope (TEM: Transmission Electron Microscope), the boundaries between the amorphous part and the crystal part included in the CAAC-OS film and the boundaries between the crystal parts are not clear. Also, no clear grain boundaries (also referred to as grain boundaries) can be confirmed in the CAAC-OS film by TEM. Therefore, the electron mobility reduction due to grain boundaries is suppressed in the CAAC-OS film.

[0238] The crystal parts included in the CAAC-OS film have their c-axes aligned in a direction parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are in a layered or columnar arrangement, and the crystal parts are arranged in a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 8 5° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5 ° or more and 5° or less is also included.

[0239] Note that in the CAAC-OS film, the distribution of crystal parts may not be uniform. For example, in the process of forming a CAA C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CA AC-OS film, the crystal parts may be amorphized in the impurity addition region.

[0240] The c-axis of the crystal parts included in the CAAC-OS film aligns in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface. Therefore, depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions. Note that the direction of the c-axis of the crystal parts is parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface when the CAAC-OS film is formed. The crystal parts are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation.

[0241] A transistor using a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0242] Note that part of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

[0243] ​​​​​​ Next, a specific example of a structure of a transistor according to one embodiment of the present invention will be described.

[0244] The transistor shown in FIG. 14A is a bottom-gate type transistor with a channel-etched structure.

[0245] The transistor shown in FIG. 14(A) has a gate electrode (gate) 16 formed on an insulating surface. 1602, a gate insulating film 1603 on the gate electrode 1602, and A semiconductor film 1604 overlapping the gate electrode 1602 and a gate electrode 1603 formed on the semiconductor film 1604 The transistor further includes a conductive film 1605 and a conductive film 1606. 1604, a conductive film 1605, and an insulating film 1607 formed on the conductive film 1606. It may be included in the composition element.

[0246] Note that the transistor shown in FIG. 14A has an insulating layer at a position overlapping with the semiconductor film 1604. It may further include a back gate electrode formed on the insulating film 1607 .

[0247] The transistor shown in FIG. 14B is a bottom-gate transistor with a channel protection structure.

[0248] The transistor shown in FIG. 14B has a gate electrode 1612 formed on an insulating surface and a gate A gate insulating film 1613 on the gate electrode 1612 and a gate insulating film 1613 on the gate electrode 1612 A semiconductor film 1614 overlapping the electrode 1612 and a channel formed on the semiconductor film 1614 A conductive film 1615 and a conductive film 1616 are formed on the semiconductor film 1614. The transistor further includes a channel protective film 1618, a conductive film 1615, and An insulating film 1617 formed over the conductive film 1616 may be included as a component thereof.

[0249] Note that the transistor shown in FIG. 14B has an insulating layer at a position overlapping with the semiconductor film 1614. It may further include a back gate electrode formed on the insulating film 1617 .

[0250] By providing a channel protective film 1618, the channel forming region of the semiconductor film 1614 and In the later process, the film is formed by plasma or etching agent during etching on the part that will be This prevents damage such as wear and tear, thus improving the reliability of the transistor. can be done.

[0251] The transistor shown in FIG. 14C is a bottom-gate type transistor having a bottom-contact structure.

[0252] The transistor shown in FIG. 14C has a gate electrode 1622 formed on an insulating surface and a gate A gate insulating film 1623 on the gate electrode 1622 and a conductive film 162 on the gate insulating film 1623 5. A conductive film 1626 and a gate electrode 1622 are overlapped on the gate insulating film 1623. In addition, the semiconductor film 1624 is formed over the conductive film 1625 and the conductive film 1626. Further, the transistor includes a conductive film 1625, a conductive film 1626, and a semiconductor film 162 The insulating film 1627 formed on the semiconductor device 4 may be included as a component thereof.

[0253] Note that the transistor shown in FIG. 14C has an insulating layer at a position overlapping with the semiconductor film 1624. It may further include a back gate electrode formed on the insulating film 1627 .

[0254] The transistor shown in FIG. 14D is a top-gate type with a bottom-contact structure.

[0255] The transistor shown in FIG. 14(D) includes a conductive film 1645 formed on an insulating surface, a conductive film 1 646, a semiconductor film 164 4 formed on the insulating surface, the conductive film 1645, and the conductive film 1646, a gate insulating film 1643 formed on the semiconductor film 1644, the conductive film 1645, and the conductive film 1646, and a gate electrode 1642 overlapping the semiconductor film 1644 on the gate insulating film 1643. Further, the transistor may include an insulating film 1647 formed on the gate electrode 1642 as its component.

[0256] The transistor of this embodiment can be used in the basic circuits, sequential circuits, and shift register circuits of Embodiment 1 and Embodiment 2, and the transistors constituting the display device of Embodiment 3. In particular, a transistor using an oxide semiconductor has high mobility and a small off-current. Therefore, the basic circuits, sequential circuits, and shift register circuits of Embodiment 1 and Embodiment 2, and the display device of Embodiment 3 can operate at high speed. Also, the amount of charge leaking from each node can be reduced.

[0257] This embodiment can be implemented in appropriate combination with other embodiments.

[0258] (Embodiment 5) The basic circuits, sequential circuits, shift register circuits, display devices, etc. according to one aspect of the present invention can be used in display devices, personal computers, and image playback devices equipped with a recording medium (typically a device having a display capable of playing back a recording medium such as a Digital Versatile Disc and displaying the image). In addition, according to one aspect Electronic devices that can use a basic circuit, a sequential circuit, a shift register circuit, a display device, etc. include mobile phones, game machines including portable ones, portable information terminals, e-books, video cameras, digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction machines, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 15.

[0259] FIG. 15(A) is a portable game machine, which has a housing 5001, a housing 5002, a display unit 5003, a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, a start button 5008, etc. Note that the portable game machine shown in FIG. 15(A) has two display units 5003 and 5004, but the number of display units of the portable game machine is not limited to this.

[0260] FIG. 15(B) is a display device, which has a housing 5201, a display unit 5202, a support base 5203, etc. Note that the display device includes all display devices for information display for personal computers, TV broadcast reception, advertisement display, etc.

[0261] FIG. 15(C) is a notebook personal computer, which has a housing 5401, a display unit 5402 a keyboard 5403, a pointing device 5404, etc.

[0262] FIG. 15(D) is a portable information terminal, which has a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. The first The display unit 5603 is provided on the first housing 5601, and the second display unit 5604 is provided on the second housing 56 02. The first housing 5601 and the second housing 5602 are connected by a connecting portion 56 05, and the angle between the first housing 5601 and the second housing 5602 is movable by the connecting portion 5605. The switching of the video on the first display unit 5603 may be configured to be switched according to the angle between the first housing 5601 and the second housing 5602 at the connecting portion 5605.

[0263] FIG. 15(E) shows a mobile phone, which has a housing 5801, a display unit 5802, a voice input unit 5803, a voice output unit 5804, operation keys 5805, a light receiving unit 5806, etc. By converting the light received by the light receiving unit 5806 into an electrical signal, an external image can be captured.

[0264] This embodiment can be implemented in appropriate combination with other embodiments.

Explanation of Reference Numerals

[0265] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 26 Wiring 27 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 41 Wiring 42 Wiring 43 Wiring 44 Wiring ​​100 Sequential Circuit 101 Transistor 102 Transistor 103 Transistor 104 Transistor 104S Switch 105 Transistor 106 Transistor 106S Switch 107 Transistor 107S Switch 201 Transistor 202 Transistor 203 Transistor 204 Transistor 205 Transistor 206 Transistor 207 Transistor 208 Transistor 209 Transistor 210 Transistor 211 Transistor 212 Transistor 213 Transistor 214 Transistor 300 Pixel Section 301 Gate Driver 302 Gate Driver 303 Source Driver 310 Pixel 311 Transistor 312 Transistor 313 Display Element 320 Circuit 800 Substrate 802 Gate Insulating Film 812 Conductive Film 813 Semiconductor Film 814 Conductive Film 815 Conductive Film 816 Conductive Film 817 Semiconductor Film 818 Conductive Film 819 Conductive Film 820 Insulating Film 821 Insulating Film 822 Conductive film 823 Contact hole 824 Insulating film 825 EL layer 826 Conductive film 830 Transistor 831 Transistor 832 Light-emitting element 833 Capacitor element 840 Pixel 841 Driving circuit 1602 Gate electrode 1603 Gate insulating film 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Gate electrode 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protection film 1622 Gate electrode 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Gate electrode 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 Housing 5002 Housing 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Housing 5202 Display unit 5203 Support Stand 5401 Housing 5402 Display Unit 5403 Keyboard 5404 Pointing Device 5601 Housing 5602 Housing 5603 Display Unit 5604 Display Unit 5605 Connection Part 5606 Operation Key 5801 Housing 5802 Display Unit 5803 Voice Input Unit 5804 Voice Output Unit 5805 Operation Key 5806 Light Receiving Unit CK1 Signal CK2 Signal N1 Node N2 Node SC1 Signal SC2 Signal SCK1 Signal SCK2 Signal T1 Period T2 Period T3 Period T4 Period VN1 Potential VN2 Potential VDD Potential VSS Potential SP Signal SSP Signal OUTA Signal OUTB Signal SOUTA Signal SOUTB Signal RE Signal INI Signal

Claims

1. A gate driver having a plurality of sequential circuits, wherein at least one of the plurality of sequential circuits has at least first to seventh transistors, one of the source or drain of the first transistor is electrically connected to a first power line, the other of the source or drain of the first transistor is electrically connected to a first wiring through which an output signal is output, one of the source or drain of the second transistor is electrically connected to a second power line, the other of the source or drain of the second transistor is electrically connected to the first wiring, one of the source or drain of the third transistor is electrically connected to the gate of the second transistor, the other of the source or drain of the third transistor is electrically connected to the second power line, the gate of the third transistor is electrically connected to a second wiring to which a first signal is input, one of the source or drain of the fourth transistor is electrically connected to a third wiring to which a second signal is input, the other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor, the gate of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor, the other of the source or drain of the fifth transistor is electrically connected to a fourth wiring to which a third signal is input, the gate of the fifth transistor is electrically connected to the second wiring, one of the source or drain of the sixth transistor is electrically connected to the second power line, the other of the source or drain of the sixth transistor is electrically connected to the gate of the first transistor, the gate of the sixth transistor is electrically connected to the gate of the second transistor, one of the source or drain of the seventh transistor is electrically connected to the gate of the first transistor, the other of the source or drain of the seventh transistor is electrically connected to the first power line, the gate of the seventh transistor is electrically connected to the second wiring, the first signal is a signal for controlling on or off of the third transistor, a signal for controlling on or off of the fifth transistor, and a signal for controlling on or off of the seventh transistor, The second signal is a signal for controlling on or off of the second transistor when the fourth transistor is on. The third signal is a gate driver that is a signal for controlling on or off of the fourth transistor when the fifth transistor is on. **Claim 2**: A gate driver having a plurality of sequential circuits, at least one of the plurality of sequential circuits has at least first to seventh transistors, One of the source or drain of the first transistor is always in conduction with a first power line. The other of the source or drain of the first transistor is always in conduction with a first wiring through which an output signal is output. One of the source or drain of the second transistor is always in conduction with a second power line. The other of the source or drain of the second transistor is always in conduction with the first wiring. One of the source or drain of the third transistor is always in conduction with the gate of the second transistor. The other of the source or drain of the third transistor is always in conduction with the second power line. When the potential of the first signal input to the second wiring is input to the gate of the third transistor, the third transistor is controlled to be on or off at least according to the potential of the first signal. One of the source or drain of the fourth transistor is always in conduction with a third wiring to which a second signal is input. When one of the source or drain of the fourth transistor is in conduction with the gate of the second transistor through at least the channel formation region of the fourth transistor, the potential of the third wiring is input to the gate of the second transistor through at least the channel formation region of the fourth transistor. The gate of the fourth transistor is always in conduction with one of the source or drain of the fifth transistor. The other of the source or drain of the fifth transistor is always in conduction with a fourth wiring to which a third signal is input. When the potential of the first signal input to the second wiring is input to the gate of the fifth transistor, the fifth transistor is controlled to be on or off at least according to the potential of the first signal. One of the source or drain of the sixth transistor is always in conduction with the second power line. When the second power line is in conduction with the gate of the first transistor through at least the channel formation region of the sixth transistor, the potential of the second power line is input to the gate of the first transistor through at least the channel formation region of the sixth transistor. The gate of the sixth transistor is always in conduction with the gate of the second transistor. One of the source or drain of the seventh transistor is always in conduction with the gate of the first transistor. The other of the source or drain of the seventh transistor is always in conduction with the first power line. The gate of the seventh transistor is always in conduction with the second wiring. The second signal is a signal for controlling the on or off of the second transistor when the fourth transistor is on. The third signal is a gate driver that is a signal for controlling the on or off of the fourth transistor when the fifth transistor is on.

3. In claim 1 or claim 2, The first to seventh transistors are gate drivers having the same polarity.

4. Regarding any one of claims 1 to 3, The W / L (W is the channel width and L is the channel length) of the fourth transistor is a gate driver that is larger than the W / L of the fifth transistor.

5. A gate driver having a plurality of sequential circuits, and a pixel portion formed on the same substrate as the gate driver. At least one of the plurality of sequential circuits has at least the first to seventh transistors. One of the source or drain of the first transistor is electrically connected to the first power line. The other of the source or drain of the first transistor is electrically connected to the first wiring from which an output signal is output. One of the source or drain of the second transistor is electrically connected to the second power line. The other of the source or drain of the second transistor is electrically connected to the first wiring. One of the source or drain of the third transistor is electrically connected to the gate of the second transistor. The other of the source or drain of the third transistor is electrically connected to the second power line. The gate of the third transistor is electrically connected to the second wiring to which the first signal is input. One of the source or drain of the fourth transistor is electrically connected to a third wiring to which a second signal is input, The other of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor, The gate of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor, The other of the source or drain of the fifth transistor is electrically connected to a fourth wiring to which a third signal is input, The gate of the fifth transistor is electrically connected to the second wiring, One of the source or drain of the sixth transistor is electrically connected to the second power line, The other of the source or drain of the sixth transistor is electrically connected to the gate of the first transistor, The gate of the sixth transistor is electrically connected to the gate of the second transistor, One of the source or drain of the seventh transistor is electrically connected to the gate of the first transistor, The other of the source or drain of the seventh transistor is electrically connected to the first power line, The gate of the seventh transistor is electrically connected to the second wiring, The first signal is a signal for controlling on or off of the third transistor, a signal for controlling on or off of the fifth transistor, and a signal for controlling on or off of the seventh transistor, The second signal is a signal for controlling on or off of the second transistor when the fourth transistor is on, The third signal is a signal for controlling on or off of the fourth transistor when the fifth transistor is on, The pixel portion includes at least an eighth transistor, a ninth transistor, a light-emitting element, and a wiring having a function of supplying a current flowing through the light-emitting element, The wiring having a function of supplying a current to the light-emitting element is electrically connected to one of the source or drain of the eighth transistor, The other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the ninth transistor, The other of the source or drain of the ninth transistor is electrically connected to the light-emitting element, The gate of the ninth transistor is electrically connected to the first wiring of the display device. **Claim 6**: A gate driver having a plurality of sequential circuits, and a pixel portion formed on the same substrate as the gate driver, at least one of the plurality of sequential circuits has at least first to seventh transistors, one of the source or drain of the first transistor is always in conduction with a first power line, the other of the source or drain of the first transistor is always in conduction with a first wiring through which an output signal is output, one of the source or drain of the second transistor is always in conduction with a second power line, the other of the source or drain of the second transistor is always in conduction with the first wiring, one of the source or drain of the third transistor is always in conduction with the gate of the second transistor, the other of the source or drain of the third transistor is always in conduction with the second power line, when the potential of a first signal input to a second wiring is input to the gate of the third transistor, the third transistor is controlled to turn on or off at least according to the potential of the first signal, one of the source or drain of the fourth transistor is always in conduction with a third wiring to which a second signal is input, when one of the source or drain of the fourth transistor is in conduction with the gate of the second transistor through at least the channel formation region of the fourth transistor, the potential of the third wiring is input to the gate of the second transistor through at least the channel formation region of the fourth transistor, the gate of the fourth transistor is always in conduction with one of the source or drain of the fifth transistor, the other of the source or drain of the fifth transistor is always in conduction with a fourth wiring to which a third signal is input, when the potential of the first signal input to the second wiring is input to the gate of the fifth transistor, the fifth transistor is controlled to turn on or off at least according to the potential of the first signal, one of the source or drain of the sixth transistor is always in conduction with the second power line, when the second power line is in conduction with the gate of the first transistor through at least the channel formation region of the sixth transistor, the potential of the second power line is input to the gate of the first transistor through at least the channel formation region of the sixth transistor, The gate of the sixth transistor is always conductive with the gate of the second transistor. One of the source or drain of the seventh transistor is always conductive with the gate of the first transistor. The other of the source or drain of the seventh transistor is always conductive with the first power line. The gate of the seventh transistor is always conductive with the second wiring. The second signal is a signal for controlling the on or off of the second transistor when the fourth transistor is on. The third signal is a signal for controlling the on or off of the fourth transistor when the fifth transistor is on. The pixel portion includes at least an eighth transistor, a ninth transistor, a light-emitting element, and a wiring having a function of supplying current to the light-emitting element. The wiring having a function of supplying current to the light-emitting element is always conductive with one of the source or drain of the eighth transistor. When the wiring having a function of supplying current to the light-emitting element is conductive with one of the source or drain of the ninth transistor through at least the channel formation region of the eighth transistor, the current of the wiring having a function of supplying current to the light-emitting element is input to one of the source or drain of the ninth transistor through at least the channel formation region of the eighth transistor. The other of the source or drain of the ninth transistor is always conductive with the light-emitting element. The gate of the ninth transistor is always conductive with the first wiring in the display device.

7. In claim 5 or claim 6, The first to ninth transistors have the same polarity in the display device.

8. Regarding any one of claims 5 to 7, The W / L (W is the channel width, L is the channel length) of the fourth transistor is larger than the W / L of the fifth transistor in the display device.

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