Signal generation device, signal generation method, and computer program

Abstract

This signal generation device comprises: a digital signal processing unit; a plurality of digital-analog conversion units that respectively convert a plurality of digital signals outputted from the digital signal processing unit into analog signals; and an analog multiplexer that interleaves the analog signals respectively outputted from the plurality of digital-analog conversion units to generate a broadband signal. The digital signal processing unit includes a serial-parallel conversion unit that generates a plurality of divided signals by dividing an input signal into a number corresponding to the ratio between the sampling frequency of the plurality of digital-analog conversion unit and the clock frequency of the analog multiplexer in a time domain, and a plurality of convolution operation units that, with the plurality of divided signals generated by the serial-parallel conversion unit as inputs, generate a plurality of digital signals corresponding to the respective digital-analog conversion units.　

Description

Technical Field

[0001] The present invention relates to a signal generation device, a signal generation method, and a computer program.

Background Art

[0002] High-quality high-speed signal generation technology for increasing the capacity of optical transmission has attracted attention. As such a technology, for example, a signal generation device has been proposed that divides a target input signal into a low frequency and a high frequency, and pre-equalizes the divided signal and the complex conjugate signal of the divided signal by MIMO (Multiple Input Multiple Output) processing (see, for example, Patent Document 1).

[0003] FIG. 6 is a diagram showing a configuration example of a conventional signal generation device 100. The signal generation device 100 includes a band division unit 611, a spectrum folding unit 612, a filter 613, a plurality of SubDACs (Sub Digital Analog Converters) 121 and 122, and an analog multiplexer 131. In the band division unit 611, the input signal 101 is divided into a low frequency and a high frequency. The spectrum folding unit 612 generates a complex conjugate signal of the divided signal. The filter 613 takes each divided signal and each complex conjugate signal as inputs, and generates a plurality of composite signals to be transmitted to the plurality of SubDACs 121 and 122. The SubDACs 121 and 122 convert the plurality of composite signals output from the filter 613 into a plurality of analog signals. The analog multiplexer 131 takes the plurality of analog signals as inputs and generates a high-speed signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the signal generation method by a conventional signal generation device, when dividing an input signal, a sharp cut-off occurs in the frequency domain, resulting in a problem that the signal quality deteriorates due to the influence of frequency ripple and the increase in PAPR (Peak-to-Average Power Ratio).

[0006] In view of the above circumstances, an object of the present invention is to provide a technology capable of generating a broadband signal with high signal quality.

Means for Solving the Problem

[0007] One aspect of the present invention includes a digital signal processing unit, a plurality of digital-to-analog conversion units that convert a plurality of digital signals output from the digital signal processing unit into analog signals respectively, and an analog multiplexer that interleaves the analog signals output from each of the plurality of digital-to-analog conversion units to generate a broadband signal. The digital signal processing unit includes a serial-to-parallel conversion unit that divides an input signal into a plurality of divided signals by dividing it in the time domain into a number corresponding to the ratio of the sampling frequency of the plurality of digital-to-analog conversion units to the clock frequency of the analog multiplexer, a plurality of convolution operation units that perform convolution operations on the plurality of divided signals generated by the serial-to-parallel conversion unit, and a plurality of addition units that add the plurality of divided signals on which the convolution operations have been performed by the plurality of convolution operation units to generate a plurality of digital signals corresponding to each digital-to-analog conversion unit, and is a signal generation device.

[0008] One aspect of the present invention is that a digital signal processing unit divides an input signal into a plurality of divided signals by dividing it in the time domain into a number corresponding to the ratio of the sampling frequency of a plurality of digital-to-analog conversion units and the clock frequency of an analog multiplexer, the digital signal processing unit performs a convolution operation on the plurality of divided signals, the digital signal processing unit adds the plurality of divided signals on which the convolution operation has been performed to generate a plurality of digital signals corresponding to each digital-to-analog conversion unit, the plurality of digital-to-analog conversion units each convert the plurality of digital signals output from the digital signal processing unit into analog signals, and an analog multiplexer interleaves the analog signals output from each of the plurality of digital-to-analog conversion units to generate a broadband signal.

[0009] One aspect of the present invention is a computer program for causing a computer to function as the above-described signal generation device.

Advantages of the Invention

[0010] According to the present invention, it becomes possible to generate a broadband signal with high signal quality.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a configuration example of an optical transmission apparatus including a signal generation apparatus 10 according to the first embodiment. The optical transmission apparatus includes a plurality of signal generation apparatuses 10, a laser light source 20, and an optical front-end circuit 30. The configurations of the respective signal generation apparatuses 10 are the same.

[0013] The signal generation apparatus 10 uses a plurality of DACs and high-speed analog devices to generate a signal (high-speed signal c in FIG. 1) with a wider bandwidth than the output bandwidth of a single DAC.

[0014] The laser light source 20 emits laser light.

[0015] The optical front-end circuit 30 transmits a modulation signal obtained by modulating the high-speed signals generated by the plurality of signal generation apparatuses 10 with the laser light output from the laser light source 20.

[0016] The signal generation apparatus 10 includes a digital signal processing unit 11, a plurality of DACs 12-1 and 12-2, a clock generator 13, and an analog multiplexer 14. In the example shown in FIG. 1, the case where the number of DACs 12 is two is illustrated, but it is applicable when the number of DACs 12 is three or more.

[0017] The digital signal processing unit 11 performs digital signal processing on the input signal to generate digital signals to be sent to the respective DACs 12-1 and 12-2 so that a desired analog signal can be obtained as the final output signal c(t) according to the characteristics of the analog multiplexer 14.

[0018] DAC12-1 and DAC12-2 each convert a plurality of digital signals output from the digital signal processing unit 11 into analog signals. For example, DAC12-1 converts the digital signal output from the digital signal processing unit 11 into an analog signal to generate a low-speed signal a(t), and DAC12-2 converts the digital signal output from the digital signal processing unit 11 into an analog signal to generate a low-speed signal b(t).

[0019] The clock generator 13 generates a clock for driving the analog multiplexer 14. In the first embodiment, it is assumed that the frequency of the clock generated by the clock generator 13 is half of the sampling frequency of the high-speed signal c.

[0020] The analog multiplexer 14 interleaves the low-speed signals a(t) and b(t) output from each of DAC12-1 and DAC12-2 to generate a broadband signal. Specific configuration examples of the analog multiplexer 14 include a configuration using the analog multiplexer shown in FIG. 2 of Patent Document 1, a configuration using a mixer and a combiner shown in FIG. 3 of Patent Document 1, an IQ modulator type configuration including a mixer, a combiner, and a 90-degree phase shifter shown in FIG. 4 of Patent Document 1, and the like.

[0021] In this example, as the configuration of the analog multiplexer 14, a configuration using an analog multiplexer will be described. The analog multiplexer is a switch (selector) circuit that outputs each analog signal output from each DAC12 while rapidly switching at a clock of frequency f clk output from the clock generator 13.

[0022] The digital signal processing unit 11 includes an encoding / symbol mapping unit 111, a waveform shaping unit 112, a serial-parallel conversion unit 113, a plurality of convolution operation units 114-1 to 114-4, and a plurality of addition units 115-1 and 115-2.

[0023] The symbol mapping unit 111 maps the transmission signal obtained by performing FEC (forward error correction) encoding on the transmission bit sequence to symbols.

[0024] The waveform shaping unit 112 restricts the bandwidth of the transmission signal.

[0025] The serial - parallel conversion unit 113 divides the transmission signal in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12 - 1, 12 - 2 and the clock frequency f clk of the analog multiplexer 14 to generate a plurality of divided signals.

[0026] The convolution operation units 114 - 1 to 114 - 4 perform convolution of the response function on the plurality of divided signals generated by the serial - parallel conversion unit 113. The number of convolution operation units 114 varies according to the number of divisions by the serial - parallel conversion unit 113. For example, when the number of divisions by the serial - parallel conversion unit 113 is 2 as in the first embodiment, the number of convolution operation units 114 is 2 N (N is the number of divisions).

[0027] The addition units 115 - 1, 115 - 2 generate a plurality of digital signals corresponding to each of the DACs 12 - 1, 12 - 2. The addition unit 115 - 1 adds the divided signal multiplied by the response function by the convolution operation unit 114 - 1 and the divided signal multiplied by the response function by the convolution operation unit 114 - 3 to generate a digital signal corresponding to the DAC 12 - 1. The addition unit 115 - 2 adds the divided signal multiplied by the response function by the convolution operation unit 114 - 2 and the divided signal multiplied by the response function by the convolution operation unit 114 - 4 to generate a digital signal corresponding to the DAC 12 - 2.

[0028] Figure 2 is a time chart showing an operation example of the signal generation device 10 in the first embodiment. The clock shown in FIG. 2 is the clock generated by the clock generator 13, the low-speed signal a is the signal output from the DAC12-1, the low-speed signal b is the signal output from the DAC12-2, and the high-speed signal c is the signal output from the analog multiplexer 14. When the clock indicates "1", the low-speed signal a is selected, and when the clock indicates "0", the low-speed signal b is selected. Therefore, as shown by the high-speed signal c, at the timing of C0, C2, C4, C6, C8, C 10 at the timing of 10 , the low-speed signal a is input to the analog multiplexer 14, and at the timing of C1, C3, C5, C7, C9, C 11 at the timing of 11 , the low-speed signal b is input to the analog multiplexer 14.

[0029] Next, a method for obtaining the response functions used by the convolution operation units 114-1 to 114-4 in the first embodiment for convolution operations will be described. The response functions in the first embodiment are calculated based on the following equations (1) and (2).

[0030]

Equation

[0031]

Equation

[0032] In Equation (1), the matrix represented by (1 + f0), (1 + f1), (1 - f0), (1 - f1) is a matrix representing the relationship between the low-speed signals a and b and the clock frequency. When f0 = 1 and f1 = -1, it corresponds to that shown in FIG. 2. Further, in Equation (1), the matrix represented by h b and 0 is a matrix representing the response of the DAC12, etc. to the low-speed signals a and b. a in Equation (1) n is represented by Equation (3), b n is represented by Equation (4), C 2n is represented by Equation (5), and C 2n+1 is represented by Equation (6).

[0033] [Number]

[0034] [Number]

[0035] [Number]

[0036] [Number]

[0037] In Equation (2), the matrix represented by w 11 , w 12 , w 21 , w 22 is a matrix representing the band limitation for the high-speed signal z and can be obtained by Equation (7).

[0038] [Number]

[0039] Using the above Equations (1) and (2), Equation (8) can be obtained.

[0040] [Number]

[0041] In Equation (8), the matrix represented by q 11 , q 12 , q 21 , q 22 is a matrix representing the system response after DAC12. By transforming Equation (8) as shown in Equation (9), the response functions of the convolution operation units 114-1 to 114-4 can be obtained.

[0042] [Number]

[0043] Specifically, q in formula (9) 11 , q 12 , q 21 , q 22 The inverse matrix represented by is the response function of the convolution operation units 114-1 to 114-4. In formula (9), z 2n , z 2n+1 The matrix represented by represents the desired high-speed signal.

[0044] Next, the operation of the signal generation device 10 will be described with reference to FIG. 1. The transmission bit sequence input to the signal generation device 10 is subjected to FEC encoding by the encoding / symbol mapping unit 111 and then mapped to symbols. The waveform shaping unit 112 restricts the bandwidth of the transmission signal mapped to symbols by the encoding / symbol mapping unit 111.

[0045] As shown in FIG. 1, a high-speed signal z(1, 2, 3, 4, 5, 6, …) is input to the serial-parallel conversion unit 113. The serial-parallel conversion unit 113 divides the input high-speed signal z into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f clk of the analog multiplexer 14 in the time domain to generate a plurality of divided signals. Here, in the first embodiment, the clock frequency f clk is half of the sampling frequency of the high-speed signal c. Therefore, the serial-parallel conversion unit 113 generates two divided signals by dividing the input high-speed signal z into two signals.

[0046] For example, the serial-parallel conversion unit 113 divides the input high-speed signal z into two signals to generate a first divided signal (the signal indicated by 1, 3, 5, … in FIG. 1) and a second divided signal (the signal indicated by 2, 4, 6, … in FIG. 1). The serial-parallel conversion unit 113 outputs the first divided signal to the convolution operation units 114-1 and 114-2, and outputs the second divided signal to the convolution operation units 114-3 and 114-4.

[0047] Each convolution operation unit 114 performs a convolution operation by multiplying the input divided signals (for example, the first divided signal and the second divided signal) by the response function obtained by the method described above. For example, convolution operation units 114-1 and 114-2 perform a convolution operation by multiplying the first divided signal by the response function obtained by the method described above. For example, convolution operation units 114-3 and 114-4 perform a convolution operation by multiplying the second divided signal by the response function obtained by the method described above.

[0048] The addition unit 115-1 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-1 and the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-3 to generate a digital signal. The addition unit 115-1 outputs the generated digital signal to the DAC 12-1.

[0049] The addition unit 115-2 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-2 and the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-4 to generate a digital signal. The addition unit 115-1 outputs the generated digital signal to the DAC 12-2.

[0050] The DAC 12-1 samples the digital signal output from the addition unit 115-1 at the set sampling frequency and converts it into an analog signal. Thereby, a low-speed signal a is generated. The DAC 12-2 samples the digital signal output from the addition unit 115-2 at the set sampling frequency and converts it into an analog signal. Thereby, a low-speed signal b is generated. The analog multiplexer 14 generates a high-speed signal c using the low-speed signal a generated by the DAC 12-1 and the low-speed signal b generated by the DAC 12-2.

[0051] According to the signal generation device 10 configured as described above, the digital signal processing unit 11 divides the input signal into a plurality of divided signals by dividing it in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12 and the clock frequency of the analog multiplexer 14, and generates a plurality of digital signals corresponding to each DAC 12 based on the plurality of divided signals. In this way, by dividing in the time domain and performing real-number MIMO processing, it is possible to compensate for the incompleteness of the device that becomes an issue during high-speed signal generation while suppressing the influence of frequency ripple due to steep filtering and the increase in PAPR. Therefore, synthesis of broadband signals with high signal quality is realized.

[0052] (Second Embodiment) In the second embodiment, the case where the frequency of the clock generated by the clock generator 13 is one-fourth of the sampling frequency of the high-speed signal c will be described.

[0053] FIG. 3 is a diagram showing a configuration example of an optical transmission device including the signal generation device 10a in the second embodiment. The optical transmission device includes a plurality of signal generation devices 10a, a laser light source 20, and an optical front-end circuit 30. The configuration of each signal generation device 10a is the same.

[0054] In the second embodiment, the difference from the first embodiment is that the configuration of the signal generation device 10a is different. Therefore, the configuration of the signal generation device 10a will be mainly described. The signal generation device 10a includes a digital signal processing unit 11a, a plurality of DACs 12-1, 12-2, a clock generator 13, and an analog multiplexer 14. The digital signal processing unit 11a includes an encoding / symbol mapping unit 111, a waveform shaping unit 112, a serial-parallel conversion unit 113a, a plurality of convolution operation units 114-1 to 114-16, a plurality of addition units 115-1 to 115-4, and parallel-serial conversion units 116-1, 116-2.

[0055] Note that in FIG. 3, for convenience of drawing, not all of the convolution operation units 114 are assigned symbols, but it is assumed that each convolution operation unit is assigned branch numbers from 2 to 16 in order from the convolution operation unit 114-1.

[0056] Similar to the first embodiment, the serial-parallel conversion unit 113a divides the transmission signal in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f of the analog multiplexer 14 to generate a plurality of divided signals. In the second embodiment, the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f of the analog multiplexer 14 is different from that of the first embodiment. Therefore, the number of divisions by the serial-parallel conversion unit 113a is different from that of the first embodiment. clk Similar to the first embodiment, the serial-parallel conversion unit 113a divides the transmission signal in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f of the analog multiplexer 14 to generate a plurality of divided signals. In the second embodiment, the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f of the analog multiplexer 14 is different from that of the first embodiment. Therefore, the number of divisions by the serial-parallel conversion unit 113a is different from that of the first embodiment. clk Similar to the first embodiment, the serial-parallel conversion unit 113a divides the transmission signal in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f of the analog multiplexer 14 to generate a plurality of divided signals. In the second embodiment, the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f of the analog multiplexer 14 is different from that of the first embodiment. Therefore, the number of divisions by the serial-parallel conversion unit 113a is different from that of the first embodiment.

[0057] The parallel-serial conversion unit 116-1 performs parallel-serial conversion on the digital signal output from the addition unit 115-1 and the digital signal output from the addition unit 115-2.

[0058] The parallel-serial conversion unit 116-2 performs parallel-serial conversion on the digital signal output from the addition unit 115-3 and the digital signal output from the addition unit 115-4.

[0059] FIG. 4 is a time chart showing an operation example of the signal generation device 10a in the second embodiment. The clock shown in FIG. 4 is the clock generated by the clock generator 13. The low-speed signal a is the signal output from the DAC 12-1, the low-speed signal b is the signal output from the DAC 12-2, and the high-speed signal c is the signal output from the analog multiplexer 14. When the clock indicates "1", the low-speed signal a is selected, and when the clock indicates "0", the low-speed signal b is selected. The × marks shown in the low-speed signals a and b represent the actually selected signals. The numbers shown in the low-speed signals a and b (for example, h a (±1 / 2), h a (±3 / 2), h a (±5 / 2), h b (±1 / 2), h b (±3 / 2), h b(±5 / 2)) represents the components of the signals marked with × shown in the low-speed signal a and the low-speed signal b that contribute to the high-speed signal c.

[0060] Next, the method for obtaining the response functions used by the convolution operation units 114-1 to 114-16 in the second embodiment for convolution operations will be described. The response functions in the second embodiment are calculated based on the following equations (10) and (11).

[0061]

Equation

[0062]

Equation

[0063] In Equation (10), the matrix on the left side of the right side is a matrix considering the relationship between the low-speed signals a and b and the clock waveforms f0, f1, f2, and f3 at the clock phases 0, 1, 2, and 3, and the response h a ,h b to the low-speed signals a and b, and the transition of the analog waveform (the numbers in parentheses are the time from the sampling points of the low-speed signals).

[0064] In Equation (11), the matrix on the left side of the right side is a matrix representing the band limitation for the high-speed signal z, and can be obtained by the above Equation (7).

[0065] Using the above Equations (10) and (11), Equation (12) can be obtained.

[0066]

Equation

[0067] In Equation (12), the matrix on the left side of the right side is a matrix representing the system response after DAC12. By transforming Equation (12) into the form of Equation (13), the response functions of the convolution operation units 114-1 to 114-16 can be obtained.

[0068]

Number

[0069] Specifically, the inverse matrix represented by the matrix on the left side of the right side in Equation (13) represents the response functions of the convolution operation units 114-1 to 114-16. In Equation (12), z 4n , z 4n+1 , z 4n+2 , z 4n+3 The matrix represented by, represents the desired high-speed signal.

[0070] Next, the operation of the signal generation device 10a will be described with reference to FIG. 3. The transmission bit sequence input to the signal generation device 10a is subjected to FEC encoding by the encoding / symbol mapping unit 111 and then mapped to symbols. The waveform shaping unit 112 restricts the bandwidth of the transmission signal mapped to symbols by the encoding / symbol mapping unit 111.

[0071] As shown in FIG. 3, a high-speed signal z(1, 2, 3, 4, 5, 6, 7, 8, …) is input to the serial-parallel conversion unit 113a. The serial-parallel conversion unit 113a divides the input high-speed signal z into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f clk of the analog multiplexer 14 in the time domain to generate a plurality of divided signals. Here, in the second embodiment, the clock frequency f clk is one-fourth of the sampling frequency of the high-speed signal c. Therefore, the serial-parallel conversion unit 113a generates four divided signals by dividing the input high-speed signal z into four signals.

[0072] For example, the serial-parallel conversion unit 113a divides the input high-speed signal z into four signals, thereby generating a first divided signal (a signal indicated by a number (1, 5, …) of 4k + 1 (k is a number of 0 or more) in FIG. 3), a second divided signal (a signal indicated by a number (2, 6, …) of 4k + 2 in FIG. 3), a third divided signal (a signal indicated by a number (3, 7, …) of 4k + 3 in FIG. 3), and a fourth divided signal (a signal indicated by a number (4, 8, …) of 4k + 4 in FIG. 3).

[0073] The serial-parallel conversion unit 113a outputs the first divided signal to the convolution operation units 114-1 to 114-4, outputs the second divided signal to the convolution operation units 114-5 to 114-8, outputs the third divided signal to the convolution operation units 114-9 to 114-11, and outputs the fourth divided signal to the convolution operation units 114-12 to 114-16.

[0074] Each convolution operation unit 114 performs a convolution operation by multiplying the input divided signal (the first divided signal to the fourth divided signal) by the response function obtained by the method described above. For example, the convolution operation units 114-1 to 114-4 perform a convolution operation by multiplying the first divided signal by the response function obtained by the method described above. For example, the convolution operation units 114-5 and 114-8 perform a convolution operation by multiplying the second divided signal by the response function obtained by the method described above. For example, the convolution operation units 114-9 to 114-12 perform a convolution operation by multiplying the third divided signal by the response function obtained by the method described above. For example, the convolution operation units 114-13 and 114-16 perform a convolution operation by multiplying the fourth divided signal by the response function obtained by the method described above.

[0075] The adder 115-1 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-1, the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-5, the third divided signal multiplied by a predetermined response function by the convolution operation unit 114-9, and the fourth divided signal multiplied by a predetermined response function by the convolution operation unit 114-13 to generate a digital signal. The adder 115-1 outputs the generated digital signal to the parallel-serial conversion unit 116-1.

[0076] The adder 115-2 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-2, the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-6, the third divided signal multiplied by a predetermined response function by the convolution operation unit 114-10, and the fourth divided signal multiplied by a predetermined response function by the convolution operation unit 114-14 to generate a digital signal. The adder 115-2 outputs the generated digital signal to the parallel-serial conversion unit 116-1.

[0077] The adder 115-3 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-3, the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-7, the third divided signal multiplied by a predetermined response function by the convolution operation unit 114-11, and the fourth divided signal multiplied by a predetermined response function by the convolution operation unit 114-15 to generate a digital signal. The adder 115-3 outputs the generated digital signal to the parallel-serial conversion unit 116-2.

[0078] The adder 115-4 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-4, the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-8, the third divided signal multiplied by a predetermined response function by the convolution operation unit 114-12, and the fourth divided signal multiplied by a predetermined response function by the convolution operation unit 114-16 to generate a digital signal. The adder 115-4 outputs the generated digital signal to the parallel-serial conversion unit 116-2.

[0079] The parallel-serial conversion unit 116-1 performs parallel-serial conversion on the digital signal output from the addition unit 115-1 and the digital signal output from the addition unit 115-2. As a result, the parallel-serial conversion unit 116-1 outputs the digitally signal after parallel-serial conversion (for example, the signal indicated by 1, 3, 5, 7,... in FIG. 3) to the analog multiplexer 14.

[0080] The parallel-serial conversion unit 116-2 performs parallel-serial conversion on the digital signal output from the addition unit 115-3 and the digital signal output from the addition unit 115-4. As a result, the parallel-serial conversion unit 116-2 outputs the digitally signal after parallel-serial conversion (for example, the signal indicated by 2, 4, 6, 8,... in FIG. 3) to the analog multiplexer 14.

[0081] The DAC 12-1 samples the digital signal output from the parallel-serial conversion unit 116-1 at the set sampling frequency and converts it into an analog signal. As a result, a low-speed signal a is generated. The DAC 12-2 samples the digital signal output from the parallel-serial conversion unit 116-2 at the set sampling frequency and converts it into an analog signal. As a result, a low-speed signal b is generated. The analog multiplexer 14 generates a high-speed signal c using the low-speed signal a generated by the DAC 12-1 and the low-speed signal b generated by the DAC 12-2.

[0082] According to the signal generation device 10a configured as described above, even when the ratio of the frequency of the clock generated by the clock generator 13 to the sampling frequency of the high-speed signal z is 1 / 4, the same effects as those of the first embodiment can be obtained.

[0083] (Third Embodiment) In the third embodiment, the case where the frequency of the clock generated by the clock generator 13 is 1 / 6 of the sampling frequency of the high-speed signal c will be described.

[0084] FIG. 5 is a diagram showing a configuration example of an optical transmission apparatus including a signal generation device 10b according to a third embodiment. The optical transmission apparatus includes a plurality of signal generation devices 10b, a laser light source 20, and an optical front-end circuit 30. The configurations of the respective signal generation devices 10b are the same.

[0085] In the third embodiment, the difference from the first embodiment is that the configuration of the signal generation device 10b is different. Therefore, the configuration of the signal generation device 10b will be mainly described. The signal generation device 10b includes a digital signal processing unit 11b, a plurality of DACs 12-1, 12-2, a clock generator 13, and an analog multiplexer 14. The digital signal processing unit 11b includes an encoding / symbol mapping unit 111, a waveform shaping unit 112, a serial-parallel conversion unit 113b, a plurality of convolution operation units 114-1 to 114-36, a plurality of addition units 115-1 to 115-6, and parallel-serial conversion units 116-1, 116-2.

[0086] Note that in FIG. 5, for convenience of the drawing, not all of the convolution operation units 114 are assigned symbols, but it is assumed that branch numbers from 2 to 36 are sequentially assigned to each convolution operation unit starting from the convolution operation unit 114-1.

[0087] Similar to the first embodiment, the serial-parallel conversion unit 113b divides the transmission signal in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1, 12-2 and the clock frequency f clk of the analog multiplexer 14 to generate a plurality of divided signals. In the third embodiment, the ratio of the sampling frequencies of the plurality of DACs 12-1, 12-2 and the clock frequency f clk of the analog multiplexer 14 is different from that of the first embodiment. Therefore, the number of divisions by the serial-parallel conversion unit 113b is different from that of the first embodiment.

[0088] Next, the operation of the signal generation device 10b will be described with reference to FIG. 5. The transmission bit sequence input to the signal generation device 10b is subjected to FEC encoding by the encoding and symbol mapping unit 111 and then mapped to symbols. The waveform shaping unit 112 restricts the bandwidth of the transmission signal mapped to symbols by the encoding and symbol mapping unit 111.

[0089] The high-speed signal z is input to the serial-parallel conversion unit 113b. The serial-parallel conversion unit 113b divides the input high-speed signal z in the time domain into a number corresponding to the ratio of the sampling frequencies of the plurality of DACs 12-1 and 12-2 and the clock frequency f clk of the analog multiplexer 14 to generate a plurality of divided signals. Here, in the second embodiment, the clock frequency f clk is one-sixth of the sampling frequency of the high-speed signal z. Therefore, the serial-parallel conversion unit 113b generates six divided signals by dividing the input high-speed signal z into six signals.

[0090] For example, the serial-parallel conversion unit 113b divides the input high-speed signal z into six signals, thereby generating a first divided signal (for example, a signal indicated by a number of 6k + 1 (1, 7,...)), a second divided signal (for example, a signal indicated by a number of 6k + 2 (2, 8,...)), a third divided signal (for example, a signal indicated by a number of 6k + 3 (3, 9,...)), a fourth divided signal (for example, a signal indicated by a number of 6k + 4 (4, 10,...)), a fifth divided signal (for example, a signal indicated by a number of 6k + 5 (5, 11,...)), and a sixth divided signal (for example, a signal indicated by a number of 6k + 6 (6, 12,...)).

[0091] The serial-parallel conversion unit 113b outputs the first divided signal to the convolution operation units 114-1 to 114-6, the second divided signal to the convolution operation units 114-7 to 114-12, the third divided signal to the convolution operation units 114-13 to 114-18, the fourth divided signal to the convolution operation units 114-19 to 114-24, the fifth divided signal to the convolution operation units 114-25 to 114-30, and the sixth divided signal to the convolution operation units 114-31 to 114-36.

[0092] Each convolution operation unit 114 performs a convolution operation on the input divided signal (the first divided signal to the sixth divided signal) by multiplying it with a response function. For example, the addition unit 115-1 adds the first divided signal multiplied by a predetermined response function by the convolution operation unit 114-1, the second divided signal multiplied by a predetermined response function by the convolution operation unit 114-7, the third divided signal multiplied by a predetermined response function by the convolution operation unit 114-13, the fourth divided signal multiplied by a predetermined response function by the convolution operation unit 114-19, the fifth divided signal multiplied by a predetermined response function by the convolution operation unit 114-25, and the sixth divided signal multiplied by a predetermined response function by the convolution operation unit 114-31 to generate a digital signal. The addition unit 115-1 outputs the generated digital signal to the parallel-serial conversion unit 116-1.

[0093] The addition units 115-2 to 115-6 also perform the same processing as the addition unit 115-1 to generate digital signals. The addition units 115-2 and 115-3 output the generated digital signals to the parallel-serial conversion unit 116-1. The addition units 115-4 to 115-6 output the generated digital signals to the parallel-serial conversion unit 116-2.

[0094] The parallel-serial conversion unit 116-1 performs parallel-serial conversion on the digital signal output from the addition unit 115-1, the digital signal output from the addition unit 115-2, and the digital signal output from the addition unit 115-3. As a result, the parallel-serial conversion unit 116-1 outputs digital signals indicated by odd numbers (signals indicated by 1, 3, 5,...).

[0095] The parallel-serial conversion unit 116-2 performs parallel-serial conversion on the digital signal output from the addition unit 115-4, the digital signal output from the addition unit 115-5, and the digital signal output from the addition unit 115-6. As a result, the parallel-serial conversion unit 116-2 outputs digital signals indicated by even numbers (signals indicated by 2, 4, 6,...).

[0096] The DAC 12-1 samples the digital signal output from the parallel-serial conversion unit 116-1 at a set sampling frequency and converts it into an analog signal. As a result, a low-speed signal a is generated. The DAC 12-2 samples the digital signal output from the parallel-serial conversion unit 116-2 at a set sampling frequency and converts it into an analog signal. As a result, a low-speed signal b is generated. The analog multiplexer 14 generates a high-speed signal c using the low-speed signal a generated by the DAC 12-1 and the low-speed signal b generated by the DAC 12-2.

[0097] According to the signal generation device 10b configured as described above, even when the ratio of the frequency of the clock generated by the clock generator 13 to the sampling frequency of the high-speed signal z is 1 / 6, the same effects as in the first embodiment can be obtained.

[0098] (Other configurations) In each of the above-described embodiments, the serial-parallel conversion units 113, 113a, and 113b are shown to have a configuration in which the high-speed signal z is divided into two signals, four signals, and six signals. The serial-parallel conversion unit 113 can also divide the high-speed signal z into 2M signals (where M is an integer of 1 or more), such as 8 signals or 10 signals, when the ratio of the frequency of the clock generated by the clock generator 13 to the sampling frequency of the high-speed signal z is 1 / 2M, such as 1 / 8 or 1 / 10. When configured in this way, the number of convolution operation units 114 increases according to the number of divisions of the high-speed signal z. For example, when the number of divisions of the high-speed signal z is 8, the number of convolution operation units 114 is 28 becomes individual.

[0099] Some functional parts of the signal generation devices 10, 10a, and 10b in the above-described embodiments may be realized by a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed to be realized. Here, the “computer system” shall include hardware such as an OS and peripheral devices.

[0100] Also, the “computer-readable recording medium” refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM (Read Only Memory), a CD-ROM, etc., and a storage device such as a hard disk built in a computer system. Further, the “computer-readable recording medium” refers to something that dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line, and may also include something that holds a program for a certain time like a volatile memory inside a computer system that becomes a server or a client in that case. Also, the above program may be for realizing a part of the aforementioned functions, and may further be realizable in combination with a program already recorded in a computer system for realizing the aforementioned functions, and may also be realized using a programmable logic device such as an FPGA (Field-Programmable Gate Array).

[0101] As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and designs and the like within the scope not departing from the gist of the present invention are also included.

Industrial Applicability

[0102] The present invention can be applied to the technology of generating high-speed signals.

Explanation of Signs

[0103] 10, 10a, 10b... signal generation devices, 11, 11a, 11b... digital signal processing units, 12-1, 12-2... DACs, 13... clock generators, 14... analog multiplexers, 111... encoding and symbol mapping units, 112... waveform shaping units, 113... serial-to-parallel conversion units, 114-1 to 114-36... convolution operation units, 115-1, 115-6... addition units, 116-1, 116-2... parallel-to-serial conversion units

Claims

1. A digital signal processing unit, A plurality of digital-to-analog conversion units that each convert a plurality of digital signals output from the digital signal processing unit into analog signals, An analog multiplexer that interleaves the analog signals output from each of the plurality of digital-to-analog conversion units to generate a broadband signal, comprising: The digital signal processing unit includes a serial-to-parallel conversion unit that divides an input signal in the time domain into a number corresponding to the ratio of the sampling frequency of the plurality of digital-to-analog conversion units to the clock frequency of the analog multiplexer to generate a plurality of divided signals, A plurality of convolution operation units that perform convolution operations on the plurality of divided signals generated by the serial-to-parallel conversion unit, and a plurality of addition units that add the plurality of divided signals on which the convolution operations have been performed by the plurality of convolution operation units to generate a plurality of digital signals corresponding to each digital-to-analog conversion unit. A signal generation device.

2. When the clock frequency for driving the analog multiplexer is one-half of the sampling frequency of the broadband signal, the plurality of convolution operation units are four convolution operation units, the plurality of addition units are two addition units, the serial-to-parallel conversion unit divides the input signal into two in the time domain to generate two divided signals, the four convolution operation units multiply a response function by one divided signal for every two convolution operation units, the two addition units add the four divided signals on which the convolution operations have been performed by the four convolution operation units to generate a plurality of digital signals corresponding to each digital-to-analog conversion unit, The signal generation device according to Claim 1.

3. When the clock frequency for driving the analog multiplexer is one-fourth of the sampling frequency of the broadband signal, The plurality of convolution operation units are 16 convolution operation units, The plurality of addition units are 4 addition units, Further provided are 2 parallel-serial conversion units for parallel-serial converting the plurality of digital signals output from the 4 addition units, The serial-parallel conversion unit divides the input signal into 4 in the time domain to generate 4 divided signals, The 16 convolution operation units multiply the response function by one divided signal for every 4 convolution operation units, The 4 addition units add the 16 divided signals obtained by performing convolution operations by the 16 convolution operation units to generate a plurality of digital signals corresponding to the respective digital-analog conversion units, Each of the 2 parallel-serial conversion units performs parallel-serial conversion on the plurality of digital signals output from two different addition units, The signal generation device according to claim 1.

4. When the clock frequency for driving the analog multiplexer is one-sixth of the sampling frequency of the broadband signal, The plurality of convolution operation units are 36 convolution operation units, The plurality of addition units are 6 addition units, Further provided are 2 parallel-serial conversion units for parallel-serial converting the plurality of digital signals output from the 6 addition units, The serial-parallel conversion unit divides the input signal into 6 in the time domain to generate 6 divided signals, The 36 convolution operation units multiply the response function by one divided signal for every 6 convolution operation units, The 6 addition units add the 36 divided signals obtained by performing convolution operations by the 36 convolution operation units to generate a plurality of digital signals corresponding to the respective digital-analog conversion units, Each of the two parallel serial conversion units performs parallel-serial conversion on a plurality of digital signals output from three different adder units respectively. The signal generation device according to claim 1.

5. The digital signal processing unit divides an input signal into a plurality of divided signals by dividing it in the time domain into a number corresponding to the ratio of the sampling frequency of a plurality of digital-to-analog conversion units and the clock frequency of the analog multiplexer, The digital signal processing unit performs a convolution operation on the plurality of divided signals, The digital signal processing unit adds the plurality of divided signals on which the convolution operation has been performed to generate a plurality of digital signals corresponding to the respective digital-to-analog conversion units, A plurality of digital-to-analog conversion units respectively convert the plurality of digital signals output from the digital signal processing unit into analog signals, The analog multiplexer interleaves the analog signals output from each of the plurality of digital-to-analog conversion units to generate a broadband signal. A signal generation method.

6. A computer program for causing a computer to function as the signal generation device according to any one of claims 1 to 4.

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