Indicating device

Abstract

To facilitate designing a circuit outputting a control signal for controlling a pixel circuit.SOLUTION: Each of a plurality of latch circuits outputs a first signal pulse to a corresponding pixel circuit row. A plurality of shift register units serially outputs second signal pulses. A second signal pulse from a first shift register unit and a second signal pulse from a second shift register unit of a latter stage than the first shift register unit are input to each of the latch circuits. The first signal pulse from each of the latch circuits changes from a first potential level to a second potential level in response to the second signal pulse from the first shift register unit, and changes from the second potential level to the first potential level in response to the second signal pulse from the second shift register unit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a display device.

Background Art

[0002] Since an OLED (Organic Light-Emitting Diode) element is a current-driven self-luminous element, it does not require a backlight, and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio, and is expected in the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in the OLED display device is a TFT (Thin Film Transistor), and generally, an LTPS (Low Temperature Poly-silicon) TFT is used.

[0004] TFTs have variations in threshold voltage and charge mobility. Since the driving transistor determines the light emission intensity of the OLED display device, such variations in electrical characteristics cause problems. Therefore, a correction circuit for correcting variations and fluctuations in the threshold voltage of the driving transistor is implemented in the pixel circuit of a general OLED display device.

[0005] For example, in an OLED display device, image retention may occur, and this phenomenon is called image retention. For example, after displaying a black-and-white checkerboard pattern for a specific time and then attempting to display intermediate gradations across the entire screen, afterimages of checkerboards with different gradations are displayed for a while.

[0006] This is caused by the history effect of the driving transistor. The history effect refers to a phenomenon in a field-effect transistor where the drain current when the voltage between the gate and source changes from a high voltage to a low voltage is different from the drain current when it changes from a low voltage to a high voltage.

[0007] That is, since the drain current when switching from black to the intermediate gradation is different from the drain current when switching from white to the intermediate gradation, there is a difference in the light emission intensity of the OLED display device. Further, since this difference in drain current continues for several frames or more, it is visually recognized as an afterimage.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0009] Image retention is caused by the current transient response characteristics due to the history effect of the driving TFT and the characteristics of the threshold voltage compensation of the driving TFT by the pixel circuit. Therefore, by increasing the time for threshold voltage compensation of the driving TFT, image retention can be reduced. In order to increase the time for threshold voltage compensation, it is important to perform threshold voltage compensation and data writing to the pixel circuit in different periods.

[0010] However, performing data writing and threshold voltage compensation in different periods requires different control signals for controlling them. Also, in a general OLED display device, the light emission of the OLED element is controlled by a light emission control signal. The threshold voltage compensation control signal and the light emission control signal can have different pulse widths from the data writing control signal.

[0011] The shift register can sequentially generate and output signal pulses having a predetermined pulse width. In a general display device, a circuit that outputs a pixel control signal including a shift register is disposed on the same substrate as the display area and outside the display area. For example, in order to reduce the bezel area of the display device, a circuit design for reducing the size of the circuit that outputs the control signal is required. Or, for example, the design of a shift register that outputs a light emission control signal for maintaining the light emission of the OLED element for a long time in one frame period is generally difficult compared to the design of a shift register that outputs a control signal for data writing.

[0012] Therefore, a technology that can more easily perform the design of a circuit that outputs a control signal for controlling a pixel circuit is desired.

Means for Solving the Problem

[0013] A display device according to an aspect of the present disclosure includes a display area including a plurality of pixel circuit rows, a shift register including a plurality of connected shift register units, and a plurality of latch circuits that output signal pulses to the plurality of pixel circuit rows in response to signals input from the shift register. Each latch circuit of the plurality of latch circuits outputs a first signal pulse to a corresponding pixel circuit row. The plurality of shift register units sequentially output second signal pulses. Each latch circuit of the plurality of latch circuits receives the second signal pulse from the first shift register unit and the second signal pulse from a second shift register unit subsequent to the first shift register unit. The first signal pulse from each latch circuit of the plurality of latch circuits changes from a first potential level to a second potential level in response to the second signal pulse from the first shift register unit, and changes from the second potential level to the first potential level in response to the second signal pulse from the second shift register unit.

[0014] A display device according to an aspect of the present disclosure includes a display area and a drive circuit for the display area disposed outside the display area. The display area includes a plurality of pixel circuits, and a plurality of first control lines, a plurality of second control lines, a plurality of signal lines, and a plurality of power lines connected to the plurality of pixels. Each pixel circuit of the plurality of pixel circuits includes a light-emitting element, a switch transistor having a plurality of first conductivity types, a light-emitting control transistor having a second conductivity type and controlling ON / OFF of light emission of the light-emitting element, a drive transistor having the second conductivity type and controlling the amount of current flowing to the light-emitting element, and a holding capacitor connected to the drive transistor. The plurality of first control lines each transmit a first control signal from the drive circuit to the switch transistor having the first conductivity type. The plurality of second control lines each transmit a second control signal from the drive circuit to the light-emitting control transistor having the second conductivity type. The drive circuit includes a plurality of transistors, a plurality of capacitors, and connection wiring. All transistors included in the drive circuit are transistors of the first conductivity type.

Effect of the Invention

[0015] According to an aspect of the present disclosure, the design of a circuit that outputs a control signal for a pixel circuit is facilitated.

Brief Description of the Drawings

[0016]

Figure 1

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Figure 10B

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Figure 20

Figure 21

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are assigned to common configurations in each figure. For ease of explanation, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0018] Hereinafter, in a light-emitting display device that uses a light-emitting element that emits light by a driving current, such as an OLED (Organic Light-Emitting Diode) display device, a configuration of a circuit that generates and outputs a control signal for a pixel circuit is disclosed. A display device according to an embodiment of the present specification generates and outputs a control signal for controlling a pixel circuit by a combination of a shift register circuit and a plurality of latch circuits. By combining the shift register circuit and the plurality of latch circuits, a circuit that outputs a signal pulse having a desired pulse width can be easily designed.

[0019] For example, image retention can be reduced by increasing the time for threshold voltage compensation of the driving TFT. By performing data writing and threshold voltage compensation in different periods, a longer threshold voltage compensation period becomes possible. By combining the shift register circuit and the plurality of latch circuits, a control signal for the data writing period and a control signal for the threshold voltage compensation period can be easily generated.

[0020] The shift register circuit includes a plurality of connected shift register units. For example, each shift register unit outputs a control signal for the data writing period for a corresponding pixel circuit row. Each latch circuit receives control signals from two different shift register units and outputs a control signal for the threshold voltage compensation period for a corresponding pixel circuit row. In this configuration, a shift register circuit for the control signal for the threshold voltage compensation period is unnecessary, and the circuit area can be reduced.

[0021] In other examples, the combination of the shift register circuit and the plurality of latch circuits can generate and output a light emission control signal for controlling the ON / OFF of the light emission of the light emitting element. Each latch circuit receives signals from two different shift register units and outputs a light emission control signal for the corresponding pixel circuit row. With this configuration, a driver circuit for generating the light emission control signal can be easily designed.

[0022] In addition to the light emission control signal, the combination of the shift register circuit and the plurality of latch circuits may generate and output a data write signal. Each shift register unit outputs a control signal for the data write period for the corresponding pixel circuit row. Each latch circuit receives data write control signals from two different shift register units and outputs a light emission control signal for the corresponding pixel circuit row.

[0023] [Configuration of Display Device] Hereinafter, embodiments of the present specification will be described more specifically. FIG. 1 schematically shows a configuration example of a TFT (Thin Film Transistor) substrate of an OLED display device and a control circuit mounted on the TFT substrate. In FIG. 1, only one of a plurality of like elements is indicated by reference numerals. The OLED display device 1 includes a TFT substrate 10 on which an OLED element and a pixel circuit are formed, and a thin film encapsulation structure (TFE: Thin Film Encapsulation) that seals an organic light emitting element (not shown).

[0024] The thin film encapsulation structure is one of the encapsulation structure parts. As another example, the encapsulation structure part can include an encapsulation substrate that seals the organic light emitting element, and a joining part (glass frit seal part) that joins the TFT substrate and the encapsulation substrate. For example, dry nitrogen is enclosed between the TFT substrate and the encapsulation substrate.

[0025] The TFT substrate 10 includes an insulating substrate, and a display area 101 for displaying an image is formed on the insulating substrate. Outside the display area 101, a first shift register (SR) circuit 111, a latch circuit group 113, a second shift register circuit 115, and a driver IC 117 are arranged. In FIG. 1, the shift register circuit 111 is arranged on the left side of the display area 101, and the shift register circuit 115 is arranged on the right side of the display area 101, and they face each other. A wiring 112 for connecting them is formed in the area between the shift register circuit 111 and the latch circuit group 113.

[0026] The driver IC 117 is connected to an external device via an FPC (Flexible Printed Circuit) not shown. The connection terminals of the FPC are interconnected with the connection terminals 139 on the TFT substrate 10.

[0027] The first shift register circuit 111 drives the S2 signal lines 132 on the TFT substrate 10. The S2 signal lines 132 extend along the X-axis from the shift register circuit 111 and are arranged along the Y-axis. In FIG. 1, the S2 signal lines 132 are represented by dotted lines. The shift register circuit 111 sequentially outputs pulses of a control signal S2 described later to the S2 signal lines 132. The latch circuit group 113 drives the S1 signal lines 131 on the TFT substrate 10. The S1 signal lines 131 extend along the X-axis from the latch circuit group 113 and are arranged along the Y-axis. The latch circuit group 113 sequentially outputs pulses of a control signal S1 described later to the S1 signal lines 131.

[0028] The second shift register circuit 115 drives the emission signal lines (Em signal lines) 133 to control the light emission period of each pixel. The Em signal lines 133 extend along the X-axis from the shift register circuit 115 and are arranged along the Y-axis. The shift register circuit 115 sequentially outputs pulses of an Em signal (light emission control signal) described later to the Em signal lines 133.

[0029] The driver IC 117 is mounted, for example, using an anisotropic conductive film (ACF). The driver IC 117 supplies power and a timing signal (control signal) to the shift register circuits 111 and 115. The driver IC 117 outputs a data signal that defines the luminance of a pixel to the data line 137. In the configuration example of FIG. 1, the data line 137 extends along the Y-axis and is arranged along the X-axis. The driver IC 117 supplies a data signal that defines the luminance of the selected OLED element to each data line 137.

[0030] The display area 101 includes a plurality of pixel circuits 107 that control the light emission of the OLED elements of each of the plurality of pixels. In the configuration example of FIG. 1, the pixel circuits are arranged in a matrix. The layout of the pixel circuits is not particularly limited. In a color OLED display device, each OLED element emits light of, for example, one of red, blue, or green. The plurality of pixel circuits constitute a pixel circuit array.

[0031] One row of pixel circuits composed of a plurality of pixel circuits is connected to the S1 signal line 131, the S2 signal line 132, and the Em signal line 133, respectively. The S1 signal line 131, the S2 signal line 132, and the Em signal line 133 transmit the control signal S1, the control signal S2, and the control signal Em to the corresponding row of pixel circuits, respectively. Each data line 137 is connected to one column of pixel circuits, and each column of pixel circuits is connected to one pixel circuit in each row of pixel circuits. The data line 137 transmits a data signal that specifies the emission luminance to the pixel circuit of the selected row of pixel circuits.

[0032] An anode power line 141 and a reset power line 142 are disposed on the TFT substrate 10. The anode power line 141 transmits the power potential applied to the anode of the OLED element. In FIG. 1, the anode power line 141 is indicated by a broken line, and its pattern includes a line extending along the X-axis and a plurality of lines connected thereto, extending along the Y-axis and arranged along the X-axis.

[0033] The reset power line 142 transmits a power supply potential for resetting the potential of a predetermined node of the pixel circuit. In FIG. 1, the reset power line 142 is shown by a broken line, and its pattern includes a line extending along the X-axis and a plurality of lines connected thereto, extending along the Y-axis and arranged along the X-axis. These power supply potentials can be supplied, for example, from an external power supply circuit or a power supply circuit within the driver IC 117. Note that in FIG. 1, a part of the power line, which will be described later with reference to FIG. 2, is omitted.

[0034] As will be described later, each pixel circuit includes a driving TFT (driving transistor) and a holding capacitor that holds a signal voltage for determining the driving current of the driving TFT. The data signal transmitted by the data line 137 is corrected and stored (written) in the holding capacitor. The voltage of the holding capacitor determines the gate voltage (Vgs) of the driving TFT. The corrected data signal analogously changes the conductance of the driving TFT and supplies a forward bias current corresponding to the emission gradation to the OLED element.

[0035] [Configuration of Pixel Circuit] FIG. 2 shows a configuration example of a pixel circuit 107 according to an embodiment of the present specification. The pixel circuit 107 is included in the N-th (N is an integer) row of pixel circuits. The pixel circuit 107 includes six transistors (TFTs) M11 to M16 having gates, sources, and drains. In this example, all the transistors M11 to M16 are P-type TFTs.

[0036] The transistor M11 is a driving transistor that controls the amount of current flowing to the OLED element E1. The driving transistor M11 controls the amount of current supplied from the anode power supply that supplies the power supply potential PVDD to the OLED element E1 according to the voltage held by the holding capacitor C10. The holding capacitor C10 holds the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to a power line 204 that transmits the power supply potential PVEE from the cathode power supply.

[0037] In the configuration example of FIG. 2, the holding capacitor C10 is composed of capacitors C11 and C12 connected in series. An anode power supply potential PVDD is applied to one end of the holding capacitor C10, and the other end is connected to the source / drain of switch transistors M13 and M14. Also, the other end of the holding capacitor C10 is connected to the gate of the driving transistor M11. More specifically, one end of the capacitor C12 is connected to the power supply line 141. One end of the capacitor C11 is connected to the source / drain of the switch transistors M13 and M14. The intermediate node between the capacitors C11 and C12 is connected to the gate of the driving transistor M11.

[0038] The voltage of the holding capacitor C10 is the voltage between the gate of the driving transistor M11 and the anode power supply line 141. The source of the driving transistor M11 is connected to the anode power supply line 141, and the source potential is the anode power supply potential PVDD. Therefore, the holding capacitor C10 holds the gate-source voltage of the driving transistor M11. In the configuration example of FIG. 2, the capacitor C12 holds the gate-source voltage of the driving transistor M11.

[0039] The transistor M15 is a switch transistor that controls the ON / OFF of the light emission of the OLED element E1. The source of the transistor M15 is connected to the drain of the driving transistor M11. The transistor M15 turns ON / OFF the current supply to the OLED element E1 connected to its drain. The gate of the transistor M15 is connected to the Em signal line (light emission control line) 133, and the transistor M15 is controlled by the light emission control signal Em input to the gate from the shift register circuit 115.

[0040] The transistor M16 operates to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor M16 is connected to the power supply line 142 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0041] The gate of transistor M16 is connected to the S1 signal line 131, and transistor M16 is controlled by the control signal S1. When transistor M16 is turned on by the control signal S1 input to the gate from the latch circuit group 113, it supplies the reset potential Vrst transmitted by the power line 142 to the anode of the OLED element E1. At the same time as supplying the reset potential Vrst to the anode of the OLED element E1, transistor M16 has a function of bypassing the current flowing in from the power supply PVDD through M11 and M15 during the reset period to prevent leakage light emission.

[0042] Transistor M12 is a switch transistor for writing a voltage for threshold correction (threshold compensation) of the driving transistor M11 into the holding capacitor C10, and is a transistor for resetting the gate potential of the driving transistor M11. The source and drain of transistor M12 connect the gate and drain of the driving transistor M11. Therefore, when transistor M12 is ON, the driving transistor M11 is in a diode-connected state.

[0043] Transistor M14 is a switch transistor for writing a voltage for threshold compensation of the driving transistor M11 into the holding capacitor C10. Transistor M14 controls the presence or absence of supply of the reference potential Vref to the holding capacitor C10. One end of the source / drain of transistor M14 is connected to the power line 202 that transmits the reference potential Vref, and the other end is connected to one end of the capacitor C11. The gate of transistor M14 is connected to the S1 signal line 131, and transistor M14 is controlled by the control signal S1 input to the gate from the latch circuit group 113.

[0044] Transistors M12, M16, and M14 are controlled by control signal S1. Therefore, these transistors M12, M16, and M14 are turned ON / OFF simultaneously. During the period when they are in the ON state, after the emission control transistor M15 is turned ON and the gate potential of the drive transistor M11 is reset, the emission control transistor M15 is turned OFF. When transistors M12 and M14 are ON, transistor M11 forms a diode-connected transistor. A threshold compensation voltage is written into the holding capacitor C10 between the power supply potential PVDD and the reference potential Vref.

[0045] Transistor M13 is a switch transistor for selecting a pixel circuit that supplies a data signal and writing the data signal (data signal voltage) into the holding capacitor C10. One end of the source / drain of transistor M13 is connected to the data line 137 that transmits the data signal Vdata, and the other end is connected to the holding capacitor C10. More specifically, one end of the source / drain of transistor M13 is connected to one end of the capacitor C11.

[0046] The gate of transistor M13 is connected to the S2 signal line 132 that transmits the control signal S2 for selecting the pixel circuit row to which the data signal is written. Transistor M13 is controlled by the control signal S2 supplied from the shift register circuit 111. When transistor M13 is ON, transistor M13 supplies the data signal Vdata supplied from the driver IC117 via the data line 137 to the holding capacitor C10.

[0047] FIG. 3 shows an example of a timing chart of signals for controlling the pixel circuit 107 shown in FIG. 2. FIG. 3 shows a timing chart for writing the threshold compensation voltage of the driving transistor M11 and the data signal Vdata to the pixel circuits in the Nth row of pixel circuits. Specifically, FIG. 3 shows the time changes in one frame of the selection signals S1_N and S2_N for the Nth row of pixel circuits to which the data signal Vdata is written, the light emission control signal Em_N for the Nth row of pixel circuits, and the selection signal S2_N-6 for the (N-6)th row of pixel circuits. FIG. 3 shows the changes in the signal potential levels. The selection signal is one of the control signals and is also called a scanning signal.

[0048] In the timing chart of FIG. 3, the 1H period is the period for writing the data signal Vdata to the pixel circuit and is the period during which the selection signal S2 is Low. The threshold compensation period is 1H or more and is 5H in the example of FIG. 3.

[0049] At time T1, the selection signal S2_N-6 changes from High to Low. As will be described later, in response to the change in the selection signal S2_N-6, the selection signal S1_N changes from High to Low. In response to the change in the selection signal S1_N, the transistors M12, M14, and M16 turn ON. At time T1, since the light emission control signal Em_N is Low, the transistor M15 is ON.

[0050] Since the transistors M12, M14 to M16 are ON, the reset potential Vrst is applied to the anode of the OLED element E1 and further applied to the gate of the driving transistor M11. At time T2, the light emission control signal Em_N changes from Low to High. The period from time T1 to T2 is the reset period of the gate voltage of the driving transistor M11. At time T2, further, the selection signal S2_N-6 changes from Low to High. The period from time T1 to T2 is the writing period of the data signal to the (N-6)th row of pixel circuits. The period from time T1 to T2 is 1H.

[0051] From time T2 to time T3, the potential levels of signals S1_N, S2_N, Em_N, and S2_N - 6 are maintained. Transistors M12, M14, and M16 are ON, and other transistors including transistor M15 are OFF. During the period from time T2 to time T3, a threshold compensation voltage is written into the holding capacitor C10. The period from time T2 to time T3 is the threshold compensation period, and its length is 5H.

[0052] At time T3, the selection signal S2_N changes from High to Low. As will be described later, in response to the change of the selection signal S2_N, the selection signal S1_N changes from Low to High. In response to the change of the selection signal S1_N, transistors M12, M14, and M16 turn OFF. After time T3, the selection signal S1_N is maintained at High.

[0053] Also, in response to the change of the selection signal S2_N, transistor M13 turns from OFF to ON. Thereby, the writing of the data signal Vdata into the holding capacitor C10 starts. At time T4, the selection signal S2_N changes from High to Low. Thereby, transistor M13 turns from ON to OFF, and the data writing to the N-th row of the pixel circuit is completed. The period from time T3 to T4 is the data writing period to the N-th row of the pixel circuit, and its length is 1H. After time T4, the selection signal S2_N is maintained at High.

[0054] At time T4, the emission control signal Em_N changes from High to Low. Thereby, transistor M15 changes from OFF to ON. Thereby, a drive current is supplied to the OLED element E1, and the OLED element starts to emit light.

[0055] FIG. 4 schematically shows the relationship between the threshold compensation period and the data writing period in four consecutive pixel circuit rows. In each pixel circuit row, the data writing period follows the threshold compensation period. The lengths of the data writing period and the threshold compensation period are common to the pixel circuit rows. The length of the data writing period is 1H, and the length of the threshold compensation period is (q - 1)*H. q is an integer of 2 or more. In order to perform more appropriate threshold compensation, q is set to an integer of 3 or more. In the example described with reference to FIG. 3, q is 6.

[0056] As will be described later, the length of the threshold compensation period changes according to the selection signal S2_N-q of the previous stage before changing the selection signal S1_N. As described above, the period during which the selection signal S1_N is Low is qH, and the threshold compensation period is (q - 1)*H. q is selected so that an appropriate threshold compensation period can be obtained in the design of the display device.

[0057] As shown in FIG. 4, the data signal is sequentially written into the pixel circuit rows. The data writing period of each pixel circuit row starts immediately after the end of the data writing period of the previous stage, and the data writing periods of different pixel circuit rows do not overlap. The threshold compensation period overlaps with a part of the immediately preceding threshold compensation period and the data writing period. The threshold compensation period can overlap with the data writing periods of the pixel circuit rows of several stages from the immediately preceding stage.

[0058] [Combination of Shift Register Circuit and Latch Circuit Group] FIG. 5 shows a configuration example of the latch circuit 300 included in the latch circuit group 113. The latch circuit 300 shown in FIG. 5 outputs the selection signal S1_N to the Nth pixel circuit row. The latch circuit 300 includes a SET terminal 301 to which a signal is input and an RST terminal 302, and includes a Q terminal 303 that outputs a signal.

[0059] The selection signal S2_N-6 of the (N-6)-th pixel circuit row from the shift register circuit 111 is input to the SET terminal 301. The selection signal S2_N of the N-th pixel circuit row is input to the RST terminal 302. The latch circuit 300 outputs the S1_N signal from the Q terminal 303 to the S1 signal line 131 of the N-th pixel circuit row.

[0060] Figure 6 shows the truth table of the latch circuit 300. In the truth table of Figure 6, L indicates a logical Low level, and H indicates a logical High level. In the configuration described with reference to Figures 3 to 5, the High potential level of the signals S1 and S2 corresponds to logical Low, and the Low potential level corresponds to logical High.

[0061] When the SET input is L and the RST input is L, the Q output is L. When the SET input is H and the RST input is L, the Q output is H, and thereafter, even if the SET input changes, the Q output is held at H. When the SET input is L and the RST input is H, the Q output is L. The state where the SET input and the RST input are H is prohibited.

[0062] As can be understood from the description with reference to Figures 3 and 5, the shift register circuit 111 sequentially outputs the pulses of the selection signal S2 to the corresponding pixel circuit rows. The pulse width is 1H. Each latch circuit 300 outputs the S1 signal to the corresponding pixel circuit row.

[0063] As described above, the latch circuit 300 of the N-th stage receives the pulse of the Low potential level (H logic level) of the selection signal S2_N-q of a predetermined previous stage at the SET terminal 301, and changes the selection signal S1_N from the Q terminal 303 to the Low potential level. Thereafter, the selection signal S2_N-q changes to the High potential level (L logic level), but the input S2_N to the RST terminal 302 is at the High potential level, and the selection signal S1_N from the Q terminal 303 is maintained at the Low potential level.

[0064] Thereafter, the latch circuit 300 receives a pulse of the Low potential level (H logic level) of the selection signal S2_N of the N-th pixel circuit row at the RST terminal 302, and changes the selection signal S1_N from the Q terminal 303 to the High potential level (L logic level). The pulse width of the S1_N signal output from the latch circuit 300 is qH.

[0065] FIG. 7 shows a circuit configuration example of the latch circuit 300. In the configuration example of FIG. 7, the latch circuit 300 is composed of four transistors and one capacitive element. The four transistors M21 to M24 are P-type transistors. The transistor M21 is in a diode-connected state, and its drain receives the input from the SET terminal 301. The transistor M22 is connected between the transistor M21 and the power supply that supplies the power potential PVEE, and its gate receives the input from the RST terminal 302.

[0066] The transistor M23 is connected between the power supply that supplies the power potential PVDD and the Q terminal 303, and its gate is connected to the intermediate node between the transistors M21 and M22. The transistor M24 is connected between the transistor M23 and the power supply that supplies the power potential PVEE, and its gate receives the RST input. The capacitive element Cb is connected between the gate of the transistor M23 and the Q terminal 303. The intermediate node between the transistors M23 and M24 is connected to the Q terminal 303.

[0067] FIG. 8 schematically shows a configuration example of the shift register circuit 111 and the latch circuit group 113 and an example of the layout of the wiring 112. The shift register circuit 111 includes a plurality of shift register units connected in series. Only one shift register unit is indicated by reference numeral 400 in FIG. 8.

[0068] FIG. 8 shows the shift register unit 400 from the (N - 6)-th stage to the (N + 3)-th stage. These shift register units 400 correspond to the pixel circuit rows of the same stage. According to two clock signals CK and CKB, data bits move from the previous shift register unit 400 to the next shift register unit 400. The shift register unit 400 that holds the data bits outputs a signal pulse.

[0069] The latch circuit group 113 includes a plurality of latch circuits 300. Only one shift-latch circuit is indicated by reference numeral 300 in FIG. 8. FIG. 8 shows the latch circuits 300 from the (N - 6)-th stage to the (N + 3)-th stage. These latch circuits 300 correspond to the pixel circuit rows of the same stage.

[0070] The shift register circuit 111 includes shift register units 400 corresponding to each pixel circuit row. The shift register unit 400 corresponding to a pixel circuit row outputs a signal pulse to the pixel circuit row and two latch circuits 300. The number of shift register units 400 is more than the number of pixel circuit rows. Some shift register units 400 (not shown) are not connected to the pixel circuit rows and output signals only to the latch circuits 300.

[0071] The two inputs of each latch circuit 300 are connected to the outputs of shift register units 400 of different stages. Specifically, the output from the previous shift register unit 400 is input to the SET terminal, and the output from the next shift register unit 400 is input to the RST terminal. In the configuration example shown in FIG. 8, the output of the (N - 6)-th stage shift register unit 400 is input to the SET terminal of the N-th stage latch circuit 300, and the output of the N-th stage shift register unit 400 is input to the RST terminal of the N-th stage latch circuit 300.

[0072] The N-th stage shift register unit 400 is the N-th stage pixel column row, the RST terminal of the N-th stage latch circuit 300, and the SET terminal of the (N + 6)-th stage latch circuit 300to Outputs the selection signal S2 for the Nth stage. The shift register unit 400 for the Nth stage outputs signal pulses to these simultaneously.

[0073] The latch circuit 300 for the Nth stage outputs the selection signal S1 from the Q terminal for the pixel circuit row of the Nth stage. As described above, the latch circuit 300 for the Nth stage starts the pulse of the selection signal S1 in response to the signal pulse from the shift register unit 400 of the (N - 6)th stage, and ends the pulse in response to the signal pulse from the shift register unit 400 of the Nth stage. The pulse from the latch circuit 300 is the first signal pulse, and the pulse from the shift register unit 400 is the second signal pulse. As shown in FIG. 3 select the signal S1_N is generated as described above from two shift register units and one latch circuit.

[0074] The above description of the shift register unit 400 and the latch circuit 300 for the Nth stage is applicable to the shift register units 400 and the latch circuits 300 for other stages corresponding to each pixel circuit row. Also, in the above example, the output of the latch circuit 300 is controlled by the outputs from two shift register units separated by 6 stages, but the positional relationship of the shift register units 400 that control the latch circuit 300 is determined according to the pulse width of the selection signal S1.

[0075] More generally stated, the output of the latch circuit 300 for the Nth stage is set by the pulse from the shift register unit of the Kth stage and reset by the signal pulse from the shift register unit of the (K + p)th stage. K is an integer and p is an integer of 2 or more. In the above example, K is (N - 6) and p is 6.

[0076] The output of the latch circuit at the (N + q)-th stage is set by a signal pulse from the shift register unit at the (K + q)-th stage and reset by a signal pulse from the shift register unit at the (K + q + p)-th stage. q is an integer of 1 or more. The pulse from the latch circuit 300 has a pulse width of p * H. Also, the pulse from the latch circuit 300 at the (N + q)-th stage has a time delay of q * H with respect to the pulse from the latch circuit 300 at the N-th stage. As described above, the threshold compensation period is (p - 1) * H.

[0077] Next, a configuration for generating the light emission control signal Em by a combination of the shift register circuit and the latch circuit group will be described. FIG. 9 shows input and output signals to the N-th stage latch circuit 350 included in the latch circuit group. The truth table of the latch circuit 350 is as described with reference to FIG. 6.

[0078] The selection signal S2_N - 5 from the (N - 5)-th stage shift register is input to the RST terminal 352 of the latch circuit 350. The selection signal S2_N + 1 from the (N + 1)-th stage shift register is input to the SET terminal 351 of the latch circuit 350. The latch circuit 350 outputs the light emission control signal Em_N to the N-th stage pixel circuit row from the Q terminal 353. When the threshold compensation period is (p - 1) * H, the selection signal S2 from the (N - (p - 1))-th stage shift register is input to the RST terminal 352 of the latch circuit 350.

[0079] FIG. 10A schematically shows an example of the configuration and wiring layout of the shift register circuit and the latch circuit group for generating the light emission control signal Em. Thereby, it becomes possible to more easily design a circuit for generating the light emission control signal Em.

[0080] The shift register circuit 451 includes a plurality of shift register units 452 connected in series. Only one shift register unit is indicated by the reference numeral 452. The configuration of the shift register unit 452 is the same as that of the shift register unit 400. The shift register circuit 451 cannot directly output a signal to the pixel circuit and outputs only to the latch circuit group 461.

[0081] The latch circuit group 461 includes latch circuits 350 corresponding to each pixel circuit row. One of the latch circuits is indicated by reference numeral 350. The configuration of the latch circuit group 461 is the same as the configuration described with reference to FIG. 8. Compared with the configuration of FIG. 8, the connection wiring 471 between the shift register circuit 451 and the latch circuit group 461 is different.

[0082] FIG. 10A shows the (N - 6)-th stage shift register unit 452 and latch circuit 350 to the (N + 3)-th stage shift register unit 452 and latch circuit 350. The latch circuit 350 corresponds to the pixel circuit row of the same stage. The number of shift register units 452 is larger than the number of pixel circuit rows.

[0083] The two inputs of each latch circuit 350 are connected to the outputs of different shift register units 452. Specifically, the output from the earlier-stage shift register unit 452 is input to the RST terminal, and the output from the later-stage shift register unit 452 is input to the SET terminal. In the configuration example shown in FIG. 10A, the output of the (N - 5)-th stage shift register unit 452 is input to the RST terminal of the N-th stage latch circuit 350, and the output of the (N + 1)-th stage shift register unit 452 is input to the SET terminal of the N-th stage latch circuit 350.

[0084] The N-th stage shift register unit 452 outputs a control signal to the SET terminal of the (N - 1)-th stage latch circuit 350 and the RST terminal of the (N + 5)-th stage latch circuit 350. The N-th stage shift register unit 452 outputs signal pulses to these simultaneously.

[0085] The N-th stage latch circuit 350 outputs a light emission control signal Em from the Q terminal to the N-th stage pixel circuit row. The N-th stage latch circuit 350 starts the pulse of the light emission control signal Em in response to the signal pulse from the (N - 5)-th stage shift register unit 452, and ends the pulse in response to the signal pulse from the (N + 1)-th stage shift register unit 452.

[0086] The direction (potential level) of the pulse of the emission control signal Em is opposite to the direction of the pulse of the selection signal S1. The timing chart of each signal is as shown in FIG. 10B. The pulse from the latch circuit 350 is the first signal pulse, and the pulse from the shift register unit 452 is the second signal pulse.

[0087] The above description regarding the Nth-stage shift register unit 452 and the Nth-stage latch circuit 350 can be applied to the latch circuits 350 of other stages corresponding to each pixel circuit row and the shift register units 452 corresponding thereto. Also, in the above example, the output from two shift register units 452 separated by six stages controls the latch circuit 350, but the positional relationship of the shift register unit 452 that controls the latch circuit 350 is determined according to the pulse width of the emission control signal Em.

[0088] More generally described, the output of the Nth-stage latch circuit is reset by the pulse from the Kth-stage shift register unit and set by the signal pulse from the (K + p)th-stage shift register unit. In the above example, K is (N - 5) and p is 6.

[0089] (N + q)th-stage latch circuit output is reset by the signal pulse from the (K + q)th-stage shift register unit and set by the signal pulse from the (K + q + p)th-stage shift register unit. The pulse from the latch circuit 350 has a pulse width of p * H. Also, the pulse from the (N + q)th-stage latch circuit 350 has a time delay of q * H with respect to the pulse from the Nth-stage latch circuit 350. As described above, the period during which the current supply to the OLED element E1 is turned off is p *H.

[0090] The configuration example described with reference to FIG. 10A generates and outputs only the emission control signal Em without generating the selection signal S2 by combining the shift register circuit and the latch circuit group. Other configuration examples may generate and output the selection signal S2 in addition to the emission control signal Em. In this case, the OLED display device includes a shift register that generates the selection signal S1 and outputs it without passing through the latch circuit.

[0091] The circuit that generates the selection signal S2 and the emission control signal Em adds a control signal line from the output of the shift register unit 452 in the configuration example of FIG. 10A to the corresponding pixel circuit row. The shift register unit 452 connected to the pixel circuit row outputs a signal pulse to the pixel circuit row in the same stage together with the two latch circuits described with reference to FIG. 10A. The driving method of the present invention is not limited to the two embodiments described above, and by changing the time sequence and time interval of the SET signal and the RST signal input to the latch circuit, pulses with an arbitrary time width can be generated, which is a highly versatile method.

[0092] FIG. 11 shows a configuration example in which the signal line 131 that transmits the selection signal S1 from the latch circuit 300 is connected to the power supply potential VOFF. This can prevent the S1 signal line from floating during the emission period.

[0093] During the emission period, since the transistors M23 and M24 connected to the S1 signal line are in the off state, the S1 signal line is in an electrically floating state. The potential of the S1 signal line is held by the electrical capacitance of the entire signal line, but it fluctuates due to the feed-through noise through the coupling capacitance between the S1 signal line and the data line that intersects the S1 signal line within the display area. If this potential fluctuation is large, it may degrade the image quality. Therefore, it is more desirable to fix the potential of the S1 signal line during the emission period.

[0094] The configuration example of FIG. 11 includes a reset switch (switch transistor) 501 that turns on and off the connection between the S1 signal line 131 and the power supply line of the power supply potential VOFF. In the configuration example of FIG. 11, the reset switch 501 is a P-type TFT. The reset switch 501 is mounted on each of the S1 signal lines 131. The power supply potential VOFF is a potential opposite to the pulse potential of the selection signal S1, and is at the High potential level in the configuration example described with reference to FIGS. 2 to 10.

[0095] The ON / OFF of the reset switch 501 is controlled by the light emission control signal Em output from the shift register circuit 115. The light emission control signal is a signal that controls the presence or absence of the supply of the drive current to the OLED element E1. Specifically, the reset switch 501 that turns on and off the supply of the power supply potential VOFF to the S1 signal line 131 of the Nth stage is turned on and off by the light emission control signal Em_N of the same Nth stage.

[0096] FIG. 12 shows the timing chart of the control signal in the circuit shown in FIG. 11. In the following, the differences from the timing chart shown in FIG. 3 will be mainly described. The light emission control signal Em_N changes from the Low level to the High level at the time T0, which is 1H before the time T1. When the light emission control signal Em_N is at the Low level, the reset switch 501 is ON, and the potential of the S1 signal line 131 of the Nth stage is fixed to the power supply potential VOFF.

[0097] In response to the change of the light emission control signal Em_N to the High level, the reset switch 501 turns OFF. The S1 signal line 131 is in a floating state. At the time T1, the latch circuit 300 starts to output a signal of the Low level to the selection signal S1_N. The light emission control signal Em_N is at the High level, and the transistor M15 is OFF. The reset potential Vrst is applied to the anode of the OLED element E1 and not applied to the gate of the drive transistor M11.

[0098] At time T5, which is 1H after time T4, the emission control signal Em_N changes from the High level to the Low level. In response to the change in the level of the emission control signal Em_N, the reset switch 501 Low becomes ON ON. The reset switch 501 turns ON, and the potential of the N-th stage S1 signal line 131 is fixed at the power supply potential VOFF.

[0099] Figure 13 shows another configuration example for applying the power supply potential VOFF to the potential of the S1 signal line. The configuration example shown in Figure 13 controls the reset switch 501 by a combination of a shift register circuit 503 and a latch circuit group, VRESET generates and outputs a signal. Figure 13 shows the N-th stage latch circuit 505 as an example, but latch circuits 505 corresponding to each of the S1 signal lines of all stages are implemented. The output of the latch circuit 505 is input to the gate of the reset switch 501 of the same stage. The pulse period of the shift register unit is 1H.

[0100] In the configuration example shown in Figure 13, the output of the (N - 6)-th stage shift register unit is input to the RST terminal of the N-th stage latch circuit 505, and the output of the N-th stage shift register unit is input to the SET terminal. The N-th stage latch circuit 505 outputs a control signal VRESET from the Q terminal to the gate of the N-th stage reset switch 501.

[0101] Figure 14 shows the timing chart of the control signal in the configuration example shown in Figure 13. The differences from the timing chart shown in Figure 3 will be mainly described. As shown in Figure 14, the control signal VRESET of the N-th stage reset switch 501 changes complementarily to the N-th stage selection signal S1. That is, when one is at the High or Low level, the other is at the Low or High level. Thereby, the potential of the S1 signal line can be stabilized.

[0102] Time T 1In this case, due to the pulse of the control signal R_N-6 applied to the RST terminal of the latch circuit 505, the output of the latch circuit 505 changes from logical H to logical L. That is, the output VRESET of the latch circuit 505 changes from the Low potential level to the High potential level. As a result, the reset switch 501 is turned off.

[0103] Thereafter, at time T3, due to the pulse of the control signal R_N applied to the SET terminal of the latch circuit 505, the output of the latch circuit 505 changes from logical L to logical H. That is, the output VRESET of the latch circuit 505 changes from the High potential level to the Low potential level. As a result, the reset switch 501 is turned on, and the power supply potential VOFF is applied to the S1 signal line.

[0104] As described with reference to FIGS. 11 to 14, the wiring for transmitting the pulses from each latch circuit to the pixel circuit row is connected to the power supply line at the High level potential after the pulse ends. Thereby, the wiring potential can be stabilized. Note that the potential level supplied to the wiring is the reference potential level of the pulse, and may be at the Low level depending on the waveform of the S1 signal.

[0105] The explanatory configuration example described with reference to FIGS. 13 and 14 includes a second shift register circuit 503 and a plurality of second latch circuits 505. Each latch circuit 505 outputs a signal pulse to the corresponding reset switch 501.

[0106] The shift register circuit 503 sequentially outputs signal pulses. Each latch circuit 505 receives a signal pulse from one shift register unit of the shift register circuit 503 and a signal pulse from a shift register unit subsequent to that shift register unit. The signal pulse from each latch circuit 505 starts in response to the signal pulse from the previous shift register unit and ends in response to the signal pulse from the subsequent shift register unit.

[0107] Each latch circuit 505 controls the corresponding reset switch 501 by a signal pulse synchronized with the S1 signal pulse, and connects the wiring for transmitting the S1 signal line pulse to the pixel circuit row to the power supply line at a high level potential after the S1 signal pulse ends.

[0108] [Other Pixel Circuit Configurations] FIG. 15 shows another configuration example of a pixel circuit. The pixel circuit 550 includes a P-type TFT and an N-type TFT. The P-type TFT is, for example, a low-temperature poly-silicon TFT, and the N-type TFT is, for example, an oxide semiconductor TFT. The pixel circuit 550 includes seven transistors (TFTs) M51 to M57. In this example, the transistors M51, M53, and M56 are P-type TFTs, and the transistors M52, M54, M55, and M57 are N-type TFTs.

[0109] The transistor M53 is a driving transistor that controls the amount of current flowing to the OLED element E1. The driving transistor M53 controls the amount of current supplied from the anode power supply to the OLED element E1 according to the voltage held by the holding capacitor Cst. The cathode of the OLED element E1 is connected to the cathode power supply. The holding capacitor Cst holds the gate-source voltage of the driving transistor M53.

[0110] The transistors M51 and M56 control the presence or absence of light emission of the OLED element E1. The transistor M51 turns on / off the current supply to the driving transistor M53 whose source terminal is connected to the anode power supply and drain terminal is connected. The transistor M56 turns on / off the current supply to the OLED element E1 whose source terminal is connected to the drain terminal of the driving transistor M53 and drain terminal is connected. The transistors M51 and M56 are controlled by the light emission control signal Em.

[0111] Transistor M57 operates to supply a reset potential to the anode of the OLED element E1. When transistor M57 is turned on by a selection signal S2 input to the gate, it supplies a reset potential Vrst from a reset power supply to the anode of the OLED element E1. The other end of the reset power supply is connected to GND.

[0112] Transistor M55 controls the presence or absence of supply of a reset potential to the gate of driving transistor M53. When transistor M55 is turned on by a selection signal S1 input to the gate, it supplies a reset potential Vrst from a reset power supply connected to the source / drain to the gate of driving transistor M53. The other end of the reset power supply is connected to GND. Note that the reset potential to the anode of the OLED element E1 and the reset potential to the gate of driving transistor M53 may be different.

[0113] Transistor M52 is a selection transistor for selecting a pixel circuit 550 that supplies a data signal. The gate voltage of transistor M52 is controlled by a selection signal S2. When the selection transistor M52 is ON, it supplies a data signal Vdata supplied from a driver IC117 via a data line to the gate (holding capacitor Cst) of driving transistor M53.

[0114] In this example, the selection transistor M52 is connected between the data line and the source of the driving transistor M53. Further, transistor M54 is connected between the drain and the gate of the driving transistor M53.

[0115] Transistor M54 operates to correct the threshold voltage of driving transistor M53. When transistor M54 is ON, the driving transistor M53 forms a transistor in a diode-connected state. The data signal Vdata from the data line is supplied to the holding capacitor Cst through the channels (source and drain) of the ON selection transistor M52, driving transistor M53, and transistor M54.

[0116] The holding capacitance Cst holds the voltage between the gate and source of the driving transistor M53, with one end connected to the gate of the driving transistor M53 and the other end connected to the node between the source of the transistor M51 and the anode power supply. The holding capacitance Cst holds the data signal (voltage) corrected according to the threshold voltage Vth of the driving transistor M53.

[0117] FIG. 16 shows a timing chart of signals for controlling the pixel circuit 550 shown in FIG. 15 in one frame period. FIG. 16 shows a timing chart for selecting the Nth row of pixel circuits and writing the data signal Vdata to the pixel circuit 550. Specifically, FIG. 16 shows the emission control signal E m _N, the selection signal S1_N, and the change of the selection signal S2_N in one frame.

[0118] At time T11, the emission control signal Em_N changes from the Low level to the High level. The transistors M51 and M56 turn OFF. At time T11, the selection signals S1_N and S2_N are Low. In response to these control signals, the transistors M52, M54, M55, and M57 are OFF. The states of these transistors are maintained until time T12 after time T11.

[0119] At time T12, the selection signal S1_N changes from the Low level to the High level. At time T12, the emission control signal Em_N is High and the selection signal S2_N is at the Low level. In response to the change of the selection signal S1_N, the transistor M55 turns ON. The transistors M51, M52, M54, M56, and M57 are OFF.

[0120] When the transistor M55 turns ON, the gate potential of the driving transistor M53 changes to the reset potential Vrst. The reset potential Vrst is applied to the gate of the driving transistor M53 from time T12 to time T13. By applying the reset potential to the gate of the driving transistor M53, the influence due to the history effect can be reduced.

[0121] At time T13, the selection signal S1_N changes from High level to Low level, and the selection signal S2_N changes from Low level to High level. The emission control signal Em_N is High. In response to the change in the selection signal S1_N, the transistor M55 turns OFF. In response to the change in the selection signal S2_N, the transistors M52, M54, and M57 turn ON. The transistors M51 and M56 are OFF.

[0122] When the transistor M57 turns ON, the reset potential Vrst of the reset power supply is applied to the anode of the OLED element E1. Since the driving transistor M53 is diode-connected because the transistor M54 is ON. Since the transistor M52 is ON, the data signal Vdata from the data line is written into the holding capacitor Cst via the transistors M52, M53, and M54.

[0123] The voltage written into the holding capacitor Cst is a voltage obtained by correcting the data signal Vdata with respect to the threshold voltage Vth of the driving transistor M53. During the period from time T13 to time T14, the data signal Vdata is written into the pixel circuit 550 and its threshold compensation is performed.

[0124] At time T14, the selection signal S2 changes from High level to Low level. At time T14, the emission control signal Em_N is at High level and the selection signal S1_N is at Low level. In response to the change in the selection signal S2_N, the transistors M52, M54, and M57 turn OFF. The transistors M51, M52, M54 to M57 are OFF. From time T14 to time T15, the states of the control signal and the transistors are maintained.

[0125] At time T15, the emission control signal Em_N changes from High level to Low level, and the transistors M51 and M56 change from OFF to ON. The selection signals S1_N and S2_N are at Low level, and the transistors M52, M54, M55, and M57 remain OFF.

[0126] The driving transistor M53 controls the driving current supplied to the OLED element E1 based on the corrected data signal held in the holding capacitance Cst. That is, the OLED element E1 emits light. In the timing chart of FIG. 16, the periods from time T11 to T12, from time T12 to T13, from time T13 to T14, and from time T14 to T15 are each 1H. In the configuration example shown in FIGS. 15 and 16, the threshold compensation and the data writing are executed in the same period and are not separated.

[0127] Hereinafter, a method for generating and outputting the control signals S1, S2, and Em in the configuration example shown in FIGS. 15 and 16 by combining the shift register circuit and the latch circuit group will be described. FIG. 17 shows a configuration example of the latch circuit 380 used in the latch circuit group. FIG. 17 shows the N-th stage latch circuit 380, but the other stage latch circuits have the same configuration.

[0128] The latch circuit 380 is composed of four transistors and one capacitive element. The four transistors M61 to M64 are N-type transistors. The transistor M61 is in a diode-connected state, and its drain receives the input from the SET terminal 381. The transistor M62 is connected between the transistor M61 and the power supply that supplies the power potential PVEE, and its gate receives the input from the RST terminal 382.

[0129] The transistor M63 is connected between the power supply that supplies the power potential PVDD and the Q terminal 383, and its gate is connected to the intermediate node between the transistors M61 and M62. The transistor M64 is connected between the transistor M63 and the power supply that supplies the power potential PVEE, and its gate receives the RST input. The capacitive element Cd is connected between the gate of the transistor M63 and the Q terminal 383. The intermediate node between the transistors M63 and M64 is connected to the Q terminal 383.

[0130] Figure 18 shows the timing charts of the input signal and output signal of the latch circuit 380. In the latch circuit 380, when the logic level of the signal is H, the potential level is the High level. The truth table of the latch circuit 380 is as shown in Figure 6.

[0131] When both the SET signal and the RST signal are at the Low potential level, the Q output is at the Low potential level. When the SET input changes to the High potential level, the Q output changes to the High potential level. After that, even if the SET input changes to the Low potential level, the Q output maintains the High potential level. After that, when the RST input changes to the High potential level, the Q output changes to the Low potential level. After that, the RST input changes to the Low potential level, and the Q output is at the Low potential level.

[0132] Figure 19 schematically shows a circuit configuration example for generating and outputting the control signals S1, S2, and Em by combining a shift register circuit and a group of latch circuits. Figure 19 shows one latch circuit 380 in the shift register circuit 507 and the group of latch circuits. The shift register circuit 507, similar to the shift register circuit 111, includes a plurality of shift register units connected in series. The circuit configuration of the shift register circuit 507 is arbitrary. In one embodiment of this specification, all the transistors included in the shift register circuit 507 are N-type TFTs.

[0133] The plurality of register units sequentially output signal pulses. The potential level of the signal pulses is High. The output S_N of the Nth stage shift register unit is input to the S2 signal line of the Nth stage pixel circuit row, the S1 signal line of the (N + 1)th stage pixel circuit row, the RST terminal of the latch circuit 380 in the (N - 2)th stage, and the SET terminal of the latch circuit 380 in the (N + 2)th stage. The S1 signal line and the S2 signal line are the first control lines.

[0134] The shift register unit outputs selection signals S1 and S2 to two pixel circuit rows respectively, and further outputs an RST signal and a SET signal to each of the two latch circuits 380. Thus, the output pulses from each shift register unit are the S2 signal pulse of one corresponding pixel circuit row and the S1 signal pulse (the third signal pulse) of the other corresponding pixel circuit row.

[0135] For example, the selection signal S1_N of the Nth pixel circuit row is the output signal S_N-1 of the (N - 1)th shift register unit. Also, the selection signal S2_N of the Nth pixel circuit row is the output signal S_N of the Nth shift register unit.

[0136] As described above, the output signal S_N-2 of the (N - 2)th shift register unit is input to the SET terminal of the Nth latch circuit 380, and the output signal S_N+2 from the (N + 2)th shift register unit is input to the RST terminal. The Nth latch circuit 380 outputs the light emission control signal Em_N of the Nth pixel circuit row from the Q terminal. The output of the Q terminal is controlled by the signal pulses to the SET terminal and the RST terminal. The Em signal line for transmitting the light emission control signal is the second control line.

[0137] Thus, this configuration example generates the light emission control signal Em_N of the Nth row from the shift register signals two rows before and two rows after. The period of the light emission control signal Em is 4H. In this configuration example, since the light emission control signal Em is supplied to the gates of the P-type transistors 51 and 56, it becomes a pulse signal having the same polarity as the selection signals S1 and S2.

[0138] Here, the same polarity means that the time of the High level of the pulse is much smaller than the Low level time. A circuit for generating such a signal can be composed of a smaller number of TFTs using N-type TFTs than using P-type TFTs, and the circuit area can be reduced. In one embodiment of this specification, all the transistors included in the latch circuit and the shift register circuit are N-type TFTs.

[0139] As described above, in the pixel circuit 550 described with reference to FIG. 15, the emission control transistors M56, M51, and the drive transistor M53 are P-type (second conductivity type) TFTs. The switch transistors M52, M54, M55, and M57 are N-type (first conductivity type) TFTs. As described with reference to FIG. 19, the control line (first control line) from the shift register circuit 507 transmits the selection signal S, latch circuit 308 and the control line (second control line) from

[0140] transmits the emission control signal Em. Also, all the transistors included in the shift register circuit 507 and the latch circuit 308 are N-type (first conductivity type) TFTs.

[0141] [Device Structure of Latch Circuit] Hereinafter, a device structure example of the latch circuit will be described. FIG. 20 is a plan view schematically showing a layout example of the latch circuit 300. As described with reference to FIG. 7, the latch circuit 300 includes transistors M21 to M24 and a capacitor element Cb. In FIG. 20, the same material layer is coated with the same pattern. Specifically, the latch circuit 300 includes a semiconductor layer SC, a first metal layer MT1, and a second metal layer MT 2 .

[0142] FIG. 21 schematically shows a cross-sectional structure taken along the cutting line XXI-XXI in FIG. 20. FIG. 21 shows the cross-sectional structure of the transistor M22. An undercoat film UC is formed on the insulating substrate SUB. The undercoat film UC is, for example, a silicon nitride film.

[0143] A semiconductor layer SC is formed on an undercoat film UC. The semiconductor layer SC is, for example, polysilicon. When the TFT is N-type, for example, an oxide semiconductor can be used. The semiconductor layer SC is covered with a gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof.

[0144] On the gate insulating film GI, a gate electrode GT and a first wiring ML1 included in a first metal layer MT1 are formed. As the material of the first metal layer MT1, for example, Mo, W, Nb, Al, etc. can be used.

[0145] The first metal layer MT1 and the gate insulating film GI where the first metal layer MT1 is exposed are covered with an interlayer insulating film ILD. The interlayer insulating film ILD is, for example, a silicon nitride film or a silicon oxide film. On the interlayer insulating film ILD, a second wiring ML2 included in a second metal layer MT2 is formed.

[0146] A part of the second wiring ML2 is in contact with the semiconductor layer SC through a contact hole formed in the interlayer insulating film ILD and the gate insulating film GI. A part of the second wiring ML2 is in contact with the semiconductor layer SC through a contact hole formed in the interlayer insulating film ILD and the gate insulating film GI, and further in contact with the first wiring ML1 through a contact hole formed in the interlayer insulating film ILD. The entire latch circuit 300 is covered with a protective insulating film PV. The protective insulating film PV is, for example, an inorganic film such as silicon nitride or a silicon oxide film.

[0147] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, and convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

Description of Reference Numerals

[0148] 1 OLED display device 101 Indicated area 107, 555 Pixel circuits 111, 115, 451, 503, 507 Shift register circuits 112, 471 Wires 113, 461 Latch circuit groups 131 S1 signal line 132 S2 signal line 133 Emission signal line 300, 350, 380, 505 Latch circuits 400, 452 Shift register units 501 Reset switch CK, CKB Clock signals E1 OLED element M11 - M15, M21 - M24, M51 - M57, M61 - M64 Transistors

Claims

1. A display area including a plurality of pixel circuit rows, A shift register including a plurality of connected shift register units, A plurality of latch circuits that output signal pulses to the plurality of pixel circuit rows according to signals input from the shift register, comprising, Each latch circuit of the plurality of latch circuits outputs a first signal pulse to a corresponding pixel circuit row, The plurality of shift register units sequentially output a second signal pulse according to an input clock signal, Each latch circuit of the plurality of latch circuits receives the second signal pulse from the first shift register unit and the second signal pulse from a second shift register unit subsequent to the first shift register unit, The signal pulses input to each latch circuit of the plurality of latch circuits are only the second signal pulse from the first shift register unit and the second signal pulse from the second shift register unit, The first signal pulse from each latch circuit of the plurality of latch circuits, changes from a first potential level to a second potential level in response to the second signal pulse from the first shift register unit, changes from the second potential level to the first potential level in response to the second signal pulse from the second shift register unit, Each shift register unit of the plurality of shift register units outputs the second signal pulse to a corresponding pixel circuit row, The shift register sequentially outputs the second signal pulse to the plurality of pixel circuit rows, and the first signal pulse controls the threshold compensation period of the driving transistor of the pixel circuit, The second signal pulse controls the data writing period for the pixel circuit, The threshold compensation period controlled by the first signal pulse is longer than the data writing period controlled by the second signal pulse, A display device.

2. The display device according to claim 1, wherein N is an integer, K is an integer, p is an integer of 2 or more, q is an integer of 1 or more, and H is the pulse width from the shift register, The output of the latch circuit in the Nth stage is set by the second signal pulse from the Kth stage shift register unit and reset by the second signal pulse from the (K + p)th stage shift register unit, The output of the latch circuit at the (N + q)-th stage is set by the second signal pulse from the shift register unit at the (K + q)-th stage and reset by the second signal pulse from the shift register unit at the (K + q + p)-th stage. The first signal pulse from each latch circuit has a pulse width of H * p. The first signal pulse from the latch circuit at the (N + q)-th stage has a time delay of H * q with respect to the first signal pulse from the latch circuit at the N-th stage. Display device.

3. The display device according to claim 1, where N is an integer, K is an integer, p is an integer of 2 or more, q is an integer of 1 or more, and H is the pulse width from the shift register. The output of the latch circuit at the N-th stage is reset by the second signal pulse from the shift register unit at the K-th stage and set by the second signal pulse from the shift register unit at the (K + p)-th stage. The output of the latch circuit at the (N + q)-th stage is reset by the second signal pulse from the shift register unit at the (K + q)-th stage and set by the second signal pulse from the shift register unit at the (K + q + p)-th stage. The first signal pulse from each latch circuit has a pulse width of H * p. The first signal pulse from the latch circuit at the (N + q)-th stage has a time delay of H * q with respect to the first signal pulse from the latch circuit at the N-th stage. Display device.

4. The display device according to claim 1, where the first signal pulse controls the supply of driving current to the light-emitting element included in the pixel circuit, and the second signal pulse controls the data writing period for the pixel circuit. Display device.

5. The display device according to claim 1, where the wiring for transmitting the first signal pulse from each latch circuit to the pixel circuit row is connected to the power supply line at the potential of the first potential level after the first signal pulse ends. Display device.

6. The display device according to claim 5, including a switch transistor between the wiring and the power supply line for supplying the potential of the first potential level, where the switch transistor is turned ON / OFF by a signal that controls the supply of driving current to the light-emitting element included in the pixel circuit. Display device.

7. The display device according to claim 1, where the plurality of latch circuits are arranged between the shift register and the display area. Display device.

8. The display device according to claim 4, wherein the output pulses from each of the plurality of shift register units are the second signal pulse of one corresponding pixel circuit row and the third signal pulse of another corresponding pixel circuit row, a display device.

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