Device surface termination using a superconducting structure and an alloy

Abstract

A method for fabricating a superconductor device includes providing a first metal layer on a substrate. Oxidation of an upper surface of the first metal layer is eliminated. A second metal layer is deposited on the first metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

Description

Technical Field

[0001] The present disclosure generally relates to quantum computing, and more particularly to superconducting structures and methods of fabricating the same.

Background Art

[0002] Superconducting quantum computing is an implementation form of a quantum computer in a superconducting electronic circuit. Quantum computing studies the application of quantum phenomena related to information processing and communication. There are various models of quantum computing, and the most prevalent model includes the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states but can be a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but a quantum gate represents the transformation that one or more qubits will experience after the gate is applied to the qubits given an initial state of the qubits. Various quantum phenomena such as superposition and entanglement have no analogs in the world of classical computing and may therefore involve special structures, technologies, and materials.

Summary of the Invention

[0003] According to an embodiment, a superconducting device includes a first metal layer on a substrate. A second metal layer is on the first metal layer. A superconducting alloy between the first metal layer and the second metal layer is between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

[0004] In one embodiment, the first metal layer is niobium (Nb), the second metal layer is aluminum (Al), and the superconducting alloy is Al3Nb.

[0005] In one embodiment, the orientation of the crystal grains of the superconducting alloy is substantially aligned with the (002) plane parallel to the surface of the substrate metal layer.

[0006] In one embodiment, there is an electrode on the second metal layer.

[0007] In one embodiment, the electrode is a Josephson junction electrode.

[0008] In one embodiment, the superconducting alloy serves to protect the first metal layer from oxidation or contamination that may affect the performance of the superconducting device.

[0009] According to an embodiment, a method of manufacturing a superconducting device includes providing a first metal layer on a substrate. Oxidation on the upper surface of the first metal layer is rejected. A second metal layer is deposited on the first metal layer. A superconducting alloy between the first metal layer and the second metal layer is fabricated between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

[0010] In one embodiment, eliminating oxidation on the upper surface of the first metal layer includes installing a second metal layer on the first metal layer after deposition of the first metal layer and before the upper surface of the first metal layer is exposed to air.

[0011] In one embodiment, eliminating oxidation on the upper surface of the first metal layer further includes maintaining the superconducting device in a vacuum between deposition of the first metal layer and deposition of the second metal layer.

[0012] In one embodiment, eliminating oxidation on the upper surface of the first metal layer includes depositing a second metal layer on the first metal layer following cleaning of the upper surface of the first metal layer after the upper surface of the first metal layer has been exposed to air in order to remove all oxidation from the first metal layer.

[0013] In one embodiment, the second metal layer is removed by etching after fabrication of the superconducting alloy.

[0014] In one embodiment, fabricating the superconducting alloy includes annealing the first metal layer and the second metal layer at a predetermined temperature.

[0015] In one embodiment, the superconducting alloy creates an electrical path from the first metal layer to the second metal layer.

[0016] In one embodiment, the lattice orientation of the superconducting alloy is (002), (112), or (101), depending on the annealing temperature of the first and second metal layers used to fabricate the superconducting alloy.

[0017] In one embodiment, an electrode is deposited on the second metal layer.

[0018] In one embodiment, the electrode is a Josephson junction electrode.

[0019] In one embodiment, the second metal layer is removed and the electrode is deposited on the superconducting alloy.

[0020] According to an embodiment, a method of manufacturing a superconductor device includes providing a first metal layer on a substrate. An initial oxide layer is provided on the upper surface of the first metal layer. A second metal layer is deposited on the initial oxide layer. A superconducting alloy of the first metal layer and the second metal layer is fabricated between the first metal layer and the second metal layer. The initial oxide layer is moved to the upper surface of the superconducting alloy during the fabrication of the superconducting alloy.

[0021] In one embodiment, the initial oxide and the second metal layer on the upper surface of the superconducting alloy are removed. An electrode is deposited on the superconducting alloy.

[0022] These and other features will become apparent from the following detailed description of the exemplary embodiments read in conjunction with the accompanying drawings.

[0023] The drawings are of exemplary embodiments. The drawings do not illustrate all embodiments. Other embodiments may be used in addition to or instead. Details that are obvious or may be unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be implemented with additional components or steps or without or both without all of the components or steps illustrated. When the same number appears in different drawings, that number refers to the same or similar components or steps.

Brief Description of the Drawings

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Modes for Carrying Out the Invention

[0025] Overview In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings may be practiced without these specific details. In other instances, well-known methods, procedures, components, or circuits, or combinations thereof, are described at a relatively high level without detail in order to avoid unnecessarily obscuring aspects of the present teachings.

[0026] In one aspect, spatially relative terms such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper,” “side,” “left,” “right,” and the like are used in connection with the orientation of the figures being described. Since components of the disclosed embodiments may be disposed in many different orientations, the directional terms are used for purposes of illustration and are in no way limiting. Thus, it is understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above as well as below. The device may be oriented in another direction (rotated 90 degrees or viewed or referenced from another orientation), and the spatially relative descriptors used herein are to be interpreted accordingly.

[0027] As used herein, the terms “lateral” and “horizontal” describe an orientation parallel to a first surface of the chip.

[0028] As used herein, the term "vertical" describes an orientation that is perpendicular to a first surface of a chip, chip carrier, or semiconductor body.

[0029] As used herein, the terms "coupled" or "electrically coupled" or both do not mean that elements must be directly coupled together - intervening elements may be provided between "coupled" elements or "electrically coupled" elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements. The term "electrically connected" refers to a low-ohmic electrical connection between elements that are electrically connected together.

[0030] The terms first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "or... or both" includes any combination and all combinations of one or more of the related listed items.

[0031] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As a result, variations from the illustrated shapes of, for example, manufacturing techniques or tolerances or both may be expected. Thus, the regions shown in the figures are essentially schematic, and their shapes need not necessarily illustrate the actual shape of the regions of the device and do not limit the scope.

[0032] Other embodiments may be used and it should be understood that structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, the elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0033] As used herein, certain terms are used to indicate what can be considered an idealized behavior, for example, "lossless", "superconductor", or "superconductivity", etc., which are intended to include functions that may not be strictly ideal but are within an acceptable margin for a given application. For example, certain levels of loss or tolerance may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms.

[0034] The concepts herein relate to quantum technology and quantum chips. With respect to quantum technology, the electromagnetic energy associated with qubits may be stored, for example, in so-called Josephson junctions as well as capacitive and inductive elements used to form qubits. In other examples, it may be a spin qubit or topological qubit coupled to a resonator, a microfabricated ion trap, etc. Other types of superconducting components, including (without limitation) circulators, isolators, amplifiers, filters, active control electronics such as rapid single flux quantum (RSFQ), etc., are similarly supported by the teachings herein.

[0035] In one example, to read out the qubit state, a microwave signal is applied to a microwave readout cavity that couples to the qubit at the cavity frequency. The transmitted (or reflected) microwave signal passes through a number of adiabatic stages and a low-noise amplifier that is used to block or reduce noise and improve the signal-to-noise ratio. The amplitude or phase or both of the return / output microwave signal carry information about the qubit state, such as whether the qubit has been displaced from the ground state or the excited state. The microwave signal that carries quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons). Various circuits and techniques may be used to measure this weak signal. For example, low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPA), may be used as preamplifiers at the output of the quantum system to boost the quantum signal while adding the minimum amount of noise as defined by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components that use Josephson amplifiers or Josephson mixers, such as Josephson circulators, Josephson isolators, and Josephson mixers, may be used in scalable quantum processors. Thus, Josephson junctions are important circuit elements in superconducting quantum computers. A Josephson junction may include a thin layer of insulator, sometimes called a barrier or tunnel barrier, between two layers of superconductor. The Josephson junction acts as a superconducting tunnel junction.

[0036] The qubit system may include one or more readout resonators coupled to the qubits. The readout resonator may include a capacitive connection to ground on one side and may be a transmission line that is shorted to ground on both sides, such as for a quarter-wavelength resonator, or may have a capacitive connection to ground, such as for a half-wavelength resonator that provides oscillation within the transmission line at a resonance frequency near the frequency of the qubit. For example, the readout resonator affects the pulses coming from the control / measurement device at the readout resonator frequency. The pulse causes decoherence in the qubit and acts as a measurement value that collapses the pulse into a "1" or "zero" state, thereby indicating a phase shift for the measurement pulse.

[0037] There may be coupling resonators between the qubits that enable different qubits to be coupled together to implement quantum logic gates. The coupling resonator is a transmission line that includes capacitive connections to ground on both sides, which also provides oscillation within the coupling resonator and is typically structurally similar to the readout resonator. When the qubits are implemented as transmon qubits, each side of the coupling resonator is appropriately close to the qubit (e.g., a capacitor of the qubit) to be capacitively or inductively coupled to the corresponding qubit. Since each side of the coupling resonator has a coupling with a different qubit, the two qubits are coupled together via the coupling resonator. In this way, there is an interdependence between the states of the coupled qubits, which allows the coupling resonator to use the state of one qubit to control the state of the other qubit. Entanglement occurs when the interaction between the two qubits is such that the states of the two cannot be specified independently but only for the overall system. In this way, the states of the two qubits are linked together such that the measurement value of one of the qubits collapses the state of the other qubit.

[0038] Typical materials for making interconnects include, without limitation, niobium (Nb), aluminum (Al), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), etc., and are sometimes referred to herein as superconductors. It will be understood that other suitable materials having superconducting properties may equally be used.

[0039] The Applicant has recognized that improvements can be made to superconductor device structures and their manufacture, generally to enhance the computing power and reliability of quantum computers, particularly superconducting architectures. Achieving a low error rate and better reliability is related, among other aspects, to accurately manipulating the state of qubits and performing continuous operations that provide consistent results and do not simply provide unreliable data. Quantum technology is still a developing field, with high predictability, and it is rewarding to provide structures with even more ideal performance.

[0040] In one aspect, the teachings herein are based on the Applicant's insight that protecting a particular interface of a superconductor used in a superconducting quantum circuit from oxidation can improve the decoherence and signal integrity of superconducting qubits. The Applicant further recognizes that directly applying conventional integrated circuit techniques for protecting materials from oxidation to superconducting quantum circuits may not be effective due to the unique challenges presented by quantum circuits that do not exist in classical computing architectures. Thus, embodiments of the present disclosure are further based on the recognition that issues specific to quantum circuits have been considered when evaluating the applicability of conventional integrated circuit techniques for selecting materials and processes used to construct superconducting quantum circuits, particularly for protecting the superconducting materials of such circuits from oxidation.

[0041] The surface of the superconductor of the quantum circuit contains potentially lossy materials due to oxide growth or surface contamination that degrades resonator quality. In this regard, FIG. 1(A) illustrates a first superconductor layer 104 on a substrate 102. A surface oxide 106 may grow naturally and is thus sometimes referred to herein as a native oxide. As illustrated in FIG. 1(B), there is remaining residual oxide 107 when another superconductor layer 108 is placed on top (e.g., in the formation of Josephson junctions).

[0042] Contacts between superconducting elements, such as capacitor pads and Josephson junction electrodes that may be implemented by superconducting layers 104 and 108, are important for excellent qubit performance. However, residual oxide or surface contamination 107 within the contact area may reduce qubit coherence. For example, semiconductor processes often include different chambers for different depositions and the vacuum is often broken, which can immediately result in the native oxide 107 discussed herein. One way to remove the native oxide 107 is to use in-situ cleaning (e.g., ion milling, sputter cleaning, vacuum bake, vapor HF, etc.). However, there are limits to the level of cleanliness that can be achieved. For example, vapor HF is not typically performed in a vacuum (although it may be), so oxide removal sometimes follows in the atmosphere before loading into the deposition chamber. Oxide formation is thus limited but not eliminated. With regard to ion milling, although it is performed in a vacuum, since ion milling is sputter removal of the oxide, ion milling may also lead to some re-deposition.

[0043] Accordingly, the teachings herein provide methods and systems for reducing the impairment of contact between superconductors of a quantum circuit. The techniques described herein may be implemented in a number of ways. Exemplary implementations are provided below with reference to the following figures.

[0044] Exemplary superconducting structures Reference is now made to FIG. 2, which is a simplified cross-sectional view of a superconducting structure 200 that is consistent with an exemplary embodiment. The superconducting structure 200 may be used to implement various superconducting circuits, including, without limitation, Josephson junctions (JJs), superconducting capacitors, circulators, isolators, amplifiers, filters, etc. For ease of discussion, the superconducting structures herein will sometimes be discussed in the context of JJs, while it will be understood that other superconducting structures are equally supported.

[0045] The superconducting structure 200 may include a substrate 202. In various embodiments, the substrate 202 may include any suitable material or combination of materials, such as doped or undoped silicon, glass, dielectric, etc. For example, the substrate may include, for example, a silicon-on-insulator (SOI) structure having a buried insulator layer, or, for example, a bulk material substrate having appropriately doped regions typically referred to as wells. In another embodiment, the substrate may be silicon having a silicon oxide, nitride, or other insulating film thereon.

[0046] Other materials that may be used for the substrate include, without limitation, any of sapphire, aluminum oxide, germanium, gallium arsenide (GaAs) or other Group III-V compounds, indium phosphide (InP), silicon carbide (SiC), superconducting alloys of silicon and germanium, quartz, etc. Thus, as used herein, the term substrate 202 refers to a base upon which various superconducting structures may be constructed.

[0047] There is a first metal layer 204 on the substrate 202. In one embodiment, the first metal layer 204 is niobium (Nb). There is a second metal layer 208 on the first metal layer 204. In one embodiment, the second metal layer 208 is aluminum (Al). There is a superconducting alloy 206 between the first metal layer 204 and the second metal layer 208. For example, the superconducting alloy may be niobium aluminide Al3Nb. As used herein, the term niobium aluminide includes all stable aluminides present in the Nb-Al phase diagram. Niobium aluminide refers to any alloy of Al and Nb. Here, three phases are possible: Al3Nb, AlNb2, and Nb3Al (i.e., only three niobium aluminide phases are present in the binary Nb-Al equilibrium phase diagram). It should be noted that in embodiments with very thin films, metastable Al-Nb phases can be formed with crystal structures and compositions not found in the bulk phase.

[0048] In various embodiments, different grain orientations of Al3Nb may be formed based on temperature and time conditions, which will be discussed in more detail later. Significantly, there is no oxide layer between the first metal layer 204 and the superconducting alloy 206. Additionally, in one embodiment, there is no oxide layer between the second metal layer 208 and the superconducting alloy 206.

[0049] Without limitation, superconducting circuit elements such as JJ, resonators, coupling pads, capacitors, gate electrodes, etc. are typically capped with a second conductor. In one embodiment, the second conductor (i.e., the second metal layer 208) is deposited on the first conductor (i.e., the first metal layer 204) before the first metal layer 204 is exposed to air in order to prevent oxidation on the first metal layer.

[0050] Alternatively or in addition, the upper surface of the first metal layer 204 is sufficiently cleaned before the second metal layer 208 is deposited. The two conductive layers including the first metal layer 204 and the second metal layer 208 are alloyed at their interface to create an electrical path from the base conductor (i.e., the first metal layer 204), through the superconducting alloy 206, to the JJ electrode represented by the second metal layer 208 in FIG. 2. Thanks to having no oxide layer between the metal layers 204 and 208 and the superconducting alloy 206, the quality of the contact part (e.g., the contact part between the capacitor pad represented by the second metal layer 208 and the JJ208 lead for loss reduction) is improved, thereby further generating an ideal JJ. In various embodiments, the metal layer 208 may be a metal that is only used to create the interface alloy 206, in which case the electrode is deposited later. Alternatively, the metal layer 208 may also be a single layer (or a double-layer electrode) that is later annealed to form the superconducting alloy 206. In some embodiments, the superconducting circuit is constructed before the annealing to form the interface alloy 206.

[0051] Exemplary Process for a Superconducting Structure In the foregoing description of the exemplary superconducting structure 200, it may be helpful to discuss an exemplary process for manufacturing the superconducting structure 200. To that end, FIGS. 3(A) through 3(D) illustrate various steps in the manufacture of a superconducting structure that are consistent with the exemplary embodiments. More specifically, FIG. 3(A) illustrates a semiconductor structure 300A prior to the formation of a superconducting alloy between metal layers that is consistent with the exemplary embodiments. In various embodiments, the base first metal layer 304 is capped with a second metal layer 308 either (i) prior to any air exposure or (ii) after air exposure, and then any native metal oxide is fully removed prior to the coating of the second metal layer 308, which is referred to herein as the elimination and encapsulation of the native metal oxide. For example, in various embodiments, the second metal layer 308 is placed on top of the first metal layer 304 by a sufficient cleaning of the upper surface of the first metal layer 304 to remove any oxides on the first metal layer 304 either prior to oxidation (e.g., even when the chip goes from one deposition chamber to another while in a controlled environment such as a vacuum) or prior to the second metal layer 308 being placed on top of the first metal layer 304.

[0052] In various embodiments, this cleaning of the oxides from the upper surface of the first metal layer 304 may use wet cleaning or dry cleaning (preferably). Such dry cleaning may include, without limitation, ion milling, pre-sputtering, or another suitable technique for removing oxides from on top of the first metal layer 304. In this way, an oxide-free interface can be achieved. Thus, the interface between the first metal layer 304 and the second metal layer 308 is substantially free of oxides. A superconducting alloy is then formed between the two metal layers 304 and 308 as discussed in more detail below.

[0053] Figure 3(B) illustrates a semiconductor structure 300B after a superconducting alloy 306 is formed between a first metal layer 304 and a second metal layer 308, which is consistent with the exemplary embodiment. In one embodiment, the superconducting alloy is formed using annealing. Other methods of fabricating the superconducting alloy 306 between the first metal layer 304 and the second metal layer 308 include, without limitation, increasing the pressure or bias or both of a predetermined magnitude during the deposition of the second metal layer 308.

[0054] In one embodiment, the first metal layer 304 is niobium (Nb), the second metal layer 308 is aluminum (Al), and the alloy 306 obtained between these two metals is niobium aluminide Al3Nb(002), where (002) is the lattice orientation of the superconducting alloy 306 with respect to the 110 plane of Nb and, in this case, the surface of the substrate.

[0055] In various embodiments, depending on the various superconducting structures to be fabricated, the second metal layer 308 may be retained or etched away using wet or dry (plasma) etching. Thus, the unreacted second metal layer 308 may be left or removed, selectively leaving the exposed metal alloy 306, where the metal alloy 306 protects the first metal layer 304 from reaction with the surrounding environment. Thanks to the fabrication of the metal alloy 306, the first metal layer 304 is protected from oxidation or other elements that may affect the performance of the superconductor device of the first metal layer 304, thereby improving the device performance.

[0056] Figures 3(C) and 3(D) illustrate semiconductor structures 300C and 300D, which are consistent with the exemplary embodiments, and include an electrode 320 on a second metal layer 308 and an electrode 320 directly on a superconducting alloy 306, respectively. For example, the junction electrode 320 may belong to a JJ. The JJ may be on a capacitor (i.e., formed by subtractive etching) or on a substrate connected to the capacitor by a junction electrode (i.e., Dolan shadow junction construction). A three-layer junction process may be used, for example, for the manufacture of JJ logic devices and integrated circuits. For example, the junction electrode 320 may have a thin layer of oxide on the electrode, and this thin layer may be covered by another metal layer to provide a three-layer configuration (e.g., JJ on a capacitor).

[0057] Referring now to FIG. 4, FIG. 4 illustrates the formation of a superconducting alloy 406 having different orientations based on the annealing temperature, which is consistent with the exemplary embodiments. For purposes of discussion, and not limitation, the original semiconductor structure 400A has a first metal layer 404 containing niobium (Nb) and a second metal layer 408 containing aluminum (Al) disposed on a substrate 402. X-ray diffraction intensity charts 400C and 400D show (referring to structure 400B) that near the temperature of 500C, the superconducting alloy 406 is formed at the interface between the niobium layer 404 and the aluminum layer 408. The superconducting alloy 406 (i.e., Al3Nb) may have a lattice structure that is oriented differently from the substrate based on different annealing temperatures. The desired orientation for optimal contact may be controlled by the annealing conditions.

[0058] Different temperatures form different alloy thicknesses. For example, a thin layer of Al3Nb(002) is formed below 400°C with a long annealing time and grows with time. As the temperature is increased (e.g., 650°C), the superconducting alloy 406 begins to contain crystallites showing different orientations (Al3Nb(112) and (101)) as the crystallites in the film become more randomly oriented. In some embodiments, similar results may be achieved with different combinations of temperature and time. For example, although a long annealing time sometimes referred to as isothermal annealing in this specification, a low temperature may also be used to achieve the superconducting alloy Al3Nb(002). The applicant has determined that an annealing temperature from 350°C to 500°C with respect to the Nb / Al interface produces a superconducting alloy Al3Nb having a 002 alignment with respect to the underlying Nb110 plane.

[0059] Note that when Nb404 and Al408 are in direct contact, a superconducting alloy 406 is formed above 350°C. Alloying Nb404 and Al408 forms an electrical path from Nb to Al through the Nb-Al alloy 406. In one embodiment, oxygen is not present at the interface between Nb404 and the Nb-Al alloy 406, and only a small amount of oxygen is present on the surface of the Al layer 408. Thus, there is no residual Nb oxide causing decoherence, thereby substantially enhancing the performance of the superconductor device.

[0060] The foregoing discussion relates generally to avoiding an oxide layer between a first metal layer (e.g., Nb) and a second metal layer (e.g., Al). It should be noted that when naturally occurring niobium oxide is present between the two metal layers, a superconducting alloy can still form under certain conditions, albeit not rapidly. In this regard, referring to FIGS. 5(A) through 5(D), the figures provide different processing steps for fabricating a superconducting structure that includes an initial oxide layer between a first metal layer 504 and a second metal layer 508, which is consistent with an exemplary embodiment. As shown in FIG. 5(A), there is a first metal layer 504 (e.g., Nb) on a substrate 502. There is a second metal layer (e.g., Al) 508 on the first metal layer 504. There is a natural oxide layer (e.g., niobium oxide) 505 between the metal layers 508 and 504.

[0061] FIG. 5(B) illustrates that during alloy formation (e.g., by annealing), the natural oxide 505 moves away from the niobium surface and onto the surface of the superconducting alloy 506, represented by the oxide layer 507.

[0062] FIG. 5(C) illustrates that a selective etch can remove the second metal layer 508 and the oxide layer 507. In various embodiments, both the second metal layer 508 and the oxide layer 507 may be removed simultaneously or separately in different etch steps. An electrode (e.g., Josephson) 520 may then be deposited on the superconducting alloy 506. For example, selective etching and aluminum JJ fabrication result in an electrical path from Nb to Al through an alloy of Nb and Al that is free of niobium oxide defects.

[0063] Accordingly, Applicant has measured that superconducting alloys between metal layers without an oxide (e.g., niobium oxide) layer between the metal layers can be achieved without the active prevention or removal or both of the oxide layer between the first metal layer 504 and the second metal layer 508, while such a process takes substantially more manufacturing time or temperature or both to fabricate the protective alloy 506. While the discussion herein may refer to the idealized term "oxide-free", it will be understood to include the meaning of substantially oxygen-free such that it is very difficult to detect using known equipment.

[0064] Conclusion The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be either comprehensive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected in order to best explain the principles of the embodiments, the practical application, or a technical improvement found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0065] While the foregoing describes what is considered to be the best mode or other examples or both, it is understood that various modifications may be made, that the subject matter disclosed herein may be implemented in various forms and examples, that the teachings may be applied to numerous applications, only some of which have been described herein. It is the intention of the appended claims to claim the right to any and all applications, modifications and variations falling within the true scope of the present teachings.

[0066] The components, steps, features, objectives, advantages, and benefits discussed in this specification are merely illustrative. None of the above, or the discussions related thereto, are intended to limit the scope of protection. While various benefits have been discussed in this specification, it will be understood that not all embodiments need to include all benefits. Unless otherwise stated, all measurements, values, evaluations, positions, sizes, dimensions, and other details described in this specification, including the appended claims, are approximate rather than exact. The above is intended to have a reasonable range consistent with the functions to which they relate and what is conventional in the technical fields to which they belong.

[0067] Numerous other embodiments are also conceivable. These include embodiments having components, steps, features, objectives, advantages, and characteristics that are fewer, additional, or different, or combinations thereof. These also include embodiments in which the components or steps, or both, are arranged differently or listed in a different order, or both.

[0068] Although the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" means merely by way of example rather than being the best or optimal. Except as just described, nothing that has been described or illustrated is intended to result in, or be construed as resulting in, a dedication of any disclosed component, step, feature, objective, advantage, benefit, or equivalent.

[0069] The terms and expressions used in this specification shall be understood to have the ordinary meanings corresponding to those in the respective fields of investigation and research, unless a specific meaning is otherwise described in this specification. Related terms such as first and second, etc. may be used to simply distinguish one entity or act from another without requiring or implying any actual such relationship or order between such entities or acts. The terms "comprising", "including", or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a listing of elements may include not only those elements but also other elements not expressly listed or other elements inherent to such process, method, article, or apparatus. Elements following "a" or "an" are not, without further limitations, precluded from the presence of additional identical elements in the process, method, article, or apparatus comprising such element.

[0070] The summary of the present disclosure is provided to enable the reader to quickly confirm the essence of the technical disclosure. It is presented with the understanding that it is not used to interpret or limit the scope or meaning of the claims. Additionally, in the embodiments for carrying out the aforementioned invention, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the present disclosure. This approach of the present disclosure should not be construed as reflecting an intention that the claimed embodiments have more features than those expressly recited in each claim. Rather, as reflected by the appended claims, the subject matter of the invention lies in some of the features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the embodiments for carrying out the invention in a state based on themselves as the subject matter for which each claim individually claims rights.

Claims

1. A superconductor device, comprising: a substrate; a first metal layer on the substrate; a second metal layer on the first metal layer; a superconducting alloy between the first metal layer and the second metal layer; wherein there is no oxide layer between the superconducting alloy and the first metal layer; the first metal layer is niobium (Nb); the second metal layer is aluminum (Al); and the superconducting alloy is Al3Nb. A superconductor device.

2. A superconductor device, comprising: a substrate; a first metal layer on the substrate; a second metal layer on the first metal layer; a superconducting alloy between the first metal layer and the second metal layer; wherein there is no oxide layer between the superconducting alloy and the first metal layer; and the orientation of the crystal grains of the superconducting alloy is substantially aligned with the (002) plane parallel to the surface of the substrate. A superconductor device.

3. The superconductor device according to claim 1 or 2, further comprising an electrode on the second metal layer.

4. The superconductor device according to claim 3, wherein the electrode is a Josephson junction electrode.

5. The superconductor device according to any one of claims 1 to 4, wherein the superconducting alloy serves to protect the first metal layer from oxidation or contamination that may affect the performance of the superconductor device. ​ ​ ​ ​ ​

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