Communication device, communication system, and communication method

Abstract

[Problem] To carry out high speed serial communication with a combination of differing communication methods. [Solution] A communication device comprising a communication unit that either transmits a serial signal group, which was transmitted from a mask in sync with a clock and which is in accordance with serial peripheral interface (SPI), to a communication partner device as a single data block within one frame period of a prescribed communication protocol, or transmits the serial signal group to the communication partner device as a plurality of data blocks divided in accordance with a plurality of frame periods.

Description

Technical Field

[0001] The present disclosure relates to a communication device, a communication system, and a communication method.

Background Art

[0002] A technique for performing high-speed serial communication between a SerDes for a master and a SerDes for a slave has been proposed (see Patent Document 1).

[0003] When performing serial communication between two SerDes, for example, an FDD (Frequency Division Duplexing) method or a TDD (Time Division Duplex) method is used. When there is a large difference between the amount of data transmitted from one SerDes to the other SerDes and the amount of data transmitted from the other SerDes to the one SerDes, it is conceivable to adopt the TDD method to give a difference in data transmission capacity in the uplink and downlink directions. The TDD method is a half-duplex communication method that cannot perform communication in the uplink and downlink directions simultaneously and can only perform one-way communication.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One of the serial communication standards is called SPI (Serial Peripheral Interface). SPI is a full-duplex communication method that can perform upstream and downstream communications simultaneously. When each of the two SerDes described above communicates with other communication devices via SPI and transmits the SPI data to the communication devices connected to the opposite SerDes connected to the SerDes itself via the SerDes, assuming that communication is performed between the two SerDes in the TDD method, the full-duplex communication method SPI data cannot be directly transmitted in the half-duplex communication method TDD method.

[0006] Therefore, the present disclosure provides a communication device, a communication system, and a communication method capable of performing serial communication at high speed by combining different communication methods.

Means for Solving the Problem

[0007] In order to solve the above problems, according to the present disclosure, a communication device is provided that includes a communication unit that transmits a group of serial signals compliant with SPI (Serial Peripheral Interface) transmitted synchronously with a clock from a master to a communication partner device as a single data block within one frame period of a predetermined communication protocol, or as a plurality of data blocks divided according to a plurality of frame periods.

[0008] A memory that stores a first group of serial signals compliant with SPI transmitted synchronously with the clock from the master and a second group of serial signals compliant with SPI transmitted synchronously with the clock from a slave, A packet encoder that converts the first group of serial signals stored in the memory into a first packet of the predetermined communication protocol, And a packet decoder that converts a second packet of the predetermined communication protocol received from a communication partner device into the second group of serial signals.

[0009] The first packet may include frequency information of the clock, polarity information, and phase information of the clock with respect to the data signals of the first serial signal group conforming to the SPI.

[0010] The first packet may include information indicating that it includes a single data block within the one frame period, or information indicating that it includes a plurality of data blocks divided according to the plurality of frame periods.

[0011] When the first packet includes the plurality of data blocks, it may include the total number of the plurality of data blocks and division position information of the data blocks.

[0012] The first packet may include size information of the data block.

[0013] The first packet may include information indicating whether the data block is valid or invalid.

[0014] The first packet may include information indicating to reset the slave.

[0015] The second packet may include at least one of information indicating the operating state of the slave and interrupt information from the slave.

[0016] When the interrupt information is included in the second packet and when the second packet itself arrives at the memory from the communication partner device, the memory may determine that the slave requests to read the state of the slave and transmit an interrupt signal to the master.

[0017] The first packet may include information of a slave select signal included in the first serial signal group conforming to the SPI that selects the communication partner device or the slave.

[0018] The packet encoder may transmit the first packet with the communication partner device or the slave selected by the slave select signal as the destination.

[0019] A shift register may be provided that stores each serial signal included in the first serial signal group in the memory sequentially in synchronization with the clock, and transmits each serial signal included in the second serial signal group to the master sequentially in synchronization with the clock.

[0020] The communication unit may transmit the first packet at a first timing defined by the predetermined communication protocol and receive the second packet at a second timing defined by the predetermined communication protocol.

[0021] When the slave select signal transmitted from the master transitions from a first logic to a second logic, the packet encoder may determine that the transmission of the first serial signal group from the master has ended.

[0022] The communication unit may transmit and receive the first packet and the second packet with the communication partner device according to the communication protocol corresponding to TDD (Time Division Duplex).

[0023] According to the present disclosure, a communication device is provided that includes a communication unit that transmits, as a single data block within one frame period of a predetermined communication protocol, or as a plurality of data blocks divided according to a plurality of frame periods, a group of serial signals compliant with SPI transmitted from a slave in synchronization with a clock generated based on clock frequency information included in a packet from a communication partner device, to the communication partner device.

[0024] A packet decoder that converts a first packet of a predetermined communication protocol received from the communication partner device into a first group of serial signals compliant with SPI, A clock generator that generates the clock based on the clock frequency information included in the first serial signal group; A memory that stores the first serial signal group in synchronization with the clock and also stores a second serial signal group compliant with SPI transmitted from the slave in synchronization with the clock; A packet encoder that converts the second serial signal group stored in the memory into a second packet of the predetermined communication protocol may be provided.

[0025] The second packet may include information indicating that it includes a single data block transmitted within one frame period of the second serial signal group, or information indicating that it includes a plurality of data blocks transmitted by being divided into a plurality of frame periods.

[0026] The second packet may include information indicating whether the slave is in a busy state where it cannot receive the first serial signal group, and information indicating whether there is an error in the first serial signal group received by the slave.

[0027] The second packet may include interrupt information for requesting the master to read the state of the slave.

[0028] A shift register that stores each serial signal included in the second serial signal group in the memory and also transmits each serial signal included in the first serial signal group to the slave may be provided.

[0029] The communication unit may transmit the second packet at a first timing defined by the predetermined communication protocol and receive the first packet at a second timing defined by the predetermined communication protocol.

[0030] The communication unit may transmit and receive the first packet and the second packet with the communication partner device using the communication protocol corresponding to TDD (Time Division Duplex).

[0031] According to the present disclosure, there are provided a first communication device and a second communication device that transmit and receive packets according to a predetermined communication protocol. The first communication device transmits a first serial signal group compliant with SPI (Serial Peripheral Interface) transmitted in synchronization with a clock from a master to the second communication device as a single data block within one frame period of the predetermined communication protocol, or transmits the first serial signal group to the second communication device as a plurality of data blocks divided according to a plurality of frame periods, and has a first communication unit. The second communication device synchronizes with a clock generated based on clock frequency information included in a packet from the first communication device, and transmits a second serial signal group compliant with SPI transmitted from a slave to the first communication device as a single data block within one frame period of the predetermined communication protocol, or transmits the second serial signal group to the first communication device as a plurality of data blocks divided according to a plurality of frame periods, and a communication system is provided.

[0032] The first communication device stores the first serial signal group transmitted in synchronization with a first clock from a master, and stores the second serial signal group transmitted in synchronization with the first clock from a slave, and a first memory; a first packet encoder that converts the first serial signal group stored in the first memory into a first packet of the predetermined communication protocol; a first packet decoder that converts a second packet of the predetermined communication protocol received from the second communication device into the second serial signal group; and a first communication unit that transmits the first packet at a timing defined by the predetermined communication protocol and receives the second packet at a timing defined by the predetermined communication protocol. The second communication device has a second packet decoder that converts the received first packet into the first serial signal group; A clock generator that generates a second clock based on the clock frequency information included in the first serial signal group; A second memory that stores the first serial signal group in synchronization with the second clock and stores the second serial signal group transmitted from the slave in synchronization with the second clock; A packet encoder that converts the second serial signal group stored in the second memory into the second packet; A second communication unit that transmits the second packet at a timing defined by the predetermined communication protocol and receives the first packet at a timing defined by the predetermined communication protocol may be included.

[0033] According to the present disclosure, there is provided a communication method including a communication unit that transmits a serial signal group compliant with SPI transmitted from a master in synchronization with a clock to a communication partner device as a single data block within one frame period of a predetermined communication protocol, or transmits the serial signal group to the communication partner device as a plurality of data blocks divided according to a plurality of frame periods.

Brief Description of Drawings

[0034]

Figure 1

Figure 2

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Figure 4

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Figure 7A

Figure 7B

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Figure 9

Figure 10A

Figure 10B

Figure 10C

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0035] Hereinafter, embodiments of a communication device, a communication system, and a communication method will be described with reference to the drawings. Hereinafter, the main components of the communication device, the communication system, and the communication method will be mainly described, but there may be components and functions that are not shown or described in the communication device, the communication system, and the communication method. The following description does not exclude components and functions that are not shown or described.

[0036] (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a communication system 2 including communication devices 1a and 1b according to the first embodiment. The communication system 2 in FIG. 1 includes an SPI / Master 11, a Master SerDes (M_SerDes) 31, an SPI / Slave 12, and a Slave SerDes (S_SerDes) 41. Among these, the M_SerDes 31 corresponds to the communication device 1a, and the S_SerDes 41 corresponds to the communication device 1b.

[0037] SPI / Master11 and M_SerDes31 perform serial communication compliant with SPI (hereinafter sometimes referred to as SPI communication). Similarly, SPI / Slave12 and S_SerDes41 perform serial communication (SPI communication) compliant with SPI. M_SerDes31 and S_SerDes41 perform high-speed serial communication in the TDD mode. In FIG. 1, the signal transmission path from M_SerDes31 to S_SerDes41 is called the UP Link, and the signal transmission path from S_SerDes41 to M_SerDes31 is called the Down Link. In SPI communication, serial communication is performed according to a protocol compliant with the SPI standard (hereinafter referred to as the SPI protocol). Also, in this specification, the serial data transmitted and received in SPI communication may be referred to as SPI data.

[0038] As will be described later, M_SerDes31 includes a communication unit (DLL31-4) that transmits a group of serial signals compliant with SPI (Serial Peripheral Interface) transmitted in synchronization with a clock from a master (SPI_Master11) to a communication partner device (S_SerDes41) as a single data block within one frame period of a predetermined communication protocol, or transmits the signals to the communication partner device (S_SerDes41) as a plurality of data blocks divided according to a plurality of frame periods. Also, S_SerDes41 includes a communication unit (DLL41-4) that transmits a group of serial signals compliant with SPI transmitted from a slave (SPI_Slave12) to a communication partner device (M_SerDes31) as a single data block within one frame period of a predetermined communication protocol in synchronization with a clock generated based on the clock frequency information included in a packet from the communication partner device (M_SerDes31), or transmits the signals to the communication partner device (M_SerDes31) as a plurality of data blocks divided according to a plurality of frame periods.

[0039] Figure 2 is a block diagram of the part related to the SPI communication between SPI / Master11 and SPI / Slave12. In Figure 2, for the sake of simplicity of explanation, an example is shown where SPI / Master11 and SPI / Slave12 directly perform serial communication compliant with SPI.

[0040] As shown in Figure 2, SPI / Master11 has a shift register 11-1 and a buffer / memory 11-2. Similarly, SPI / Slave12 has a shift register 12-1 and a buffer / memory 12-2.

[0041] The shift register 12-1 in SPI / Slave12 operates in synchronization with the clock SCK supplied from SPI / Master11. The shift register 11-1 in SPI / Master11 outputs serial data in order from the MSB (Most Significant Bit) side in synchronization with SCK. The output serial data is input to the LSB (Least Significant Bit) side of the shift register 12-1 in SPI / Slave12 via the MOSI pin. The serial data output from the MSB side of the shift register 12-1 in SPI / Slave12 is input to the LSB side of the shift register 11-1 in SPI / Master11 via the MISO pin. The data held by the shift register 11-1 in SPI / Master11 can be stored in the buffer / memory 11-2. Also, the shift register 11-1 can hold the data stored in the buffer / memory 11-2. Similarly, the data held by the shift register 12-1 in SPI / Slave12 can be stored in the buffer / memory 12-2. Also, the shift register 12-1 can hold the data stored in the buffer / memory 12-2.

[0042] Figure 3 is a basic signal waveform diagram of the SPI protocol. In the SPI protocol, there are four combinations of the polarity of SCK at idle (high level in Figure 3) of the slave selector signal (CS signal) output by SPI / Master11 and the edge (rising edge or falling edge) of the clock (SCK) that latches data when the CS signal becomes active (low level in Figure 3). These four combinations are called SPI modes. SPI / Master11 can arbitrarily select one of the four SPI modes. SPI / Master11 needs to know in advance the SPI modes that SPI / Slave can support and select the corresponding mode.

[0043] Figures 3A to 3D are signal waveform diagrams of the four SPI modes. For SPI mode = 0 shown in Figure 3A, SCK is Low when the CS signal is idle, and data is held on the rising edge of SCK. For SPI mode = 1 shown in Figure 3B, SCK is Low when the CS signal is idle, and data is held on the falling edge of SCK. For SPI mode = 2 shown in Figure 3C, SCK is High when the CS signal is idle, and data is held on the falling and rising edges of SCK. For SPI mode = 3 shown in Figure 3D, SCK is High when the CS signal is idle, and data is held on the rising edge of SCK.

[0044] The frequency of SCK is not defined in the SPI protocol and varies for each individual device performing SPI communication. Therefore, SPI / Master11 selects the frequency of SCK for each individual device performing SPI communication. For this reason, SPI / Master11 needs to know in advance the SCK frequencies that each device performing SPI communication can support.

[0045] Hereinafter, a communication method using the SPI protocol will be described. In the example of FIG. 2, communication by the SPI protocol is performed between SPI / Master11 and SPI / Slave12. There may be one or more SPI / Slaves12 connected to SPI / Master11. When a plurality of SPI / Slaves12 are connected to SPI / Master11, SPI / Master11 has a plurality of CS signals corresponding to the plurality of SPI / Slaves12, and can select the Slave to communicate with using the corresponding CS signal to perform communication. The CS signal for SPI / Master11 to select the SPI / Slave12 to communicate with is included in the SPI control information as will be described later. SPI / Master11 includes the SPI control information in the SPI data and transmits it to M_SerDes31.

[0046] When performing SPI communication, SPI / Master11 sets the CS signal connected to the SPI / Slave12 to be communicated with to the active state (Low in FIGS. 3A to 3D). In this specification, setting various signals to the active state may be referred to as asserting, and setting to the idle state may be referred to as deasserting.

[0047] SPI / Master11 and SPI / Slave12 transfer the data to be transferred from their respective buffer / memory11-2 and 12-2 to shift registers 11-1 and 12-1. SPI / Master11 generates SCK and supplies it to its own shift register 11-1 and also to the shift register 12-1 in SPI / Slave12. Each of the shift registers 11-1 and 12-1 shifts the held data by 1 bit with the toggling of SCK. When SCK toggles for the number of stages of the shift registers 11-1 and 12-1, the data in the shift registers 11-1 and 12-1 are swapped. Thereafter, SPI / Master11 transitions the CS signal to the idle state (High in FIGS. 3A to 3D). SPI / Master11 and SPI / Slave12 can obtain the data from buffer / memory11-2 and 12-2 by transferring the data in the shift registers 11-1 and 12-1 at that time to buffer / memory11-2 and 12-2, thereby ending the SPI communication.

[0048] In FIG. 2, an example in which SPI / Master11 and SPI / Slave12 directly perform SPI communication is shown. In FIG. 1, between SPI / Master11 and M_SerDes31, M_SerDes31 and S_SerDes41 are arranged. In FIG. 1, SPI / Master11 and M_SerDes31 perform SPI communication, M_SerDes31 and S_SerDes41 perform serial communication by the TDD method, and SPI / Slave12 and S_SerDes41 perform SPI communication.

[0049] FIG. 4 is a diagram for explaining the TDD method performed between M_SerDes31 and S_SerDes41 in FIG. 1. In FIG. 4, the internal configurations of SPI / Master11 and SPI / Slave12 shown in FIG. 1 are illustrated in a simplified manner. Also, in FIG. 4, an example in which peripheral devices 32 and 42 are respectively connected to M_SerDes31 and S_SerDes41 is shown.

[0050] M_SerDes31 and S_SerDes41 are connected to each other via a cable 103 of, for example, several tens of meters to about one hundred meters. Through this cable 103, M_SerDes31 and S_SerDes41 perform high-speed serial communication. Note that there may be two or more devices that perform serial communication with M_SerDes31. In this case, each device has the same configuration as S_SerDes41 in FIG. 4. Also, a plurality of sets of two devices having the same configuration as M_SerDes31 and S_SerDes41 in FIG. 4 may be provided, and high-speed serial communication may be performed for each set. M_SerDes31 and S_SerDes41 in FIG. 4 can be widely applied to applications that transmit and receive a large amount of data, such as in-vehicle camera modules.

[0051] M_SerDes31 and S_SerDes41 perform high-speed serial communication by the TDD method. The timing and frequency band of the TDD method are shown in the lower right of FIG. 4. In the TDD method, as shown on the right side of FIG. 4, within one TDD cycle, an uplink signal transmission period and a downlink signal transmission period are provided so as not to overlap in time. In the example of the TDD timing diagram in FIG. 4, an example is shown in which the signal transmission period of the uplink signal (referred to as UP Link) from M_SerDes31 to S_SerDes41 is extremely shorter than the signal transmission period of the downlink signal (referred to as Down Link) from S_SerDes41 to M_SerDes31, that is, an example in which the signal ratio of UP Link is extremely smaller than the signal ratio of Downlink. For example, when transmitting a video signal captured by a sensor in S_SerDes41 to M_SerDes31, the signal ratio is as shown in the TDD timing diagram of FIG. 4.

[0052] On the right side of FIG. 4, the frequency band used for the uplink signal transmission and the frequency band used for the downlink signal transmission in the TDD mode are shown. As shown in the figure, in the TDD mode, in the uplink signal transmission and the downlink signal transmission, most of the frequency bands overlap. For example, when the video signal captured by the sensor in S_SerDes41 is transmitted to M_SerDes31, since the downlink signal transmission with a large signal amount requires a wider frequency band than the uplink signal transmission, it is performed using a wider frequency band including the frequency band used for the uplink signal transmission. In the TDD mode, since the downlink signal transmission period does not overlap with the uplink signal transmission period, an echo canceler circuit for separating the two signals becomes unnecessary.

[0053] Although M_SerDes31 and S_SerDes41 according to this embodiment assume signal transmission in the TDD mode, in some cases, signal transmission may also be possible in the FDD mode. The timing and frequency band of the FDD mode are shown in the lower left of FIG. 4. In the FDD mode, the frequency band used for the signal transmission from M_SerDes31 to S_SerDes41 is different from the frequency band used for the signal transmission from S_SerDes41 to M_SerDes31. Therefore, the signal transmission from M_SerDes31 to S_SerDes41 and the signal transmission from S_SerDes41 to M_SerDes31 can be performed at the same timing, and the uplink signal transmission and the downlink signal transmission can be performed using the entire period within one FDD cycle.

[0054] Also, in the FDD mode, the uplink signal transmission with a large signal volume is performed using a wide frequency band on the high-frequency side. The downlink signal transmission with a small signal volume is performed using a narrow frequency band on the low-frequency side. In the example at the lower left of FIG. 4, in order to improve the frequency utilization efficiency, the frequency band used for uplink signal transmission and the frequency band used for downlink signal transmission are partially overlapped. Due to this overlapping part, an echo cancellation circuit is required. The echo cancellation circuit is a circuit that accurately separates the uplink signal and the downlink signal.

[0055] Hereinafter, an example will be described in which M_SerDes31 and S_SerDes41 perform high-speed serial communication in the TDD mode, and M_SerDes31 performs serial communication compliant with SPI with SPI / Master11, and S_SerDes41 performs serial communication compliant with SPI with SPI / Slave12.

[0056] Since serial communication by the TDD mode is performed between M_SerDes31 and S_SerDes41 instead of SPI, it is necessary to perform protocol conversion inside M_SerDes31 and S_SerDes41. In addition, while serial communication by SPI is a full-duplex communication mode, serial communication by the TDD mode is a half-duplex communication mode. Therefore, data from SPI / Master11 or SPI_Slave cannot be transmitted and received in the TDD mode at the same timing as it is.

[0057] Hereinafter, the configuration of the communication system 2 in FIG. 1 will be described in detail. As shown in FIG. 4, the SPI / Master11 in FIG. 1 includes a controller 11-3 and an SCK generator 11-4 in addition to a shift register 11-1 and a buffer / memory 11-2.

[0058] The controller 11-3 supplies a slave select signal (CS signal) for activating the SPI communication to M_SerDes31 through the M_CSn pin. The CS signal is provided for the number of devices that perform SPI communication with SPI / Master11. For example, in FIG. 1, different M_CSn pins are assigned to M_SerDes31, S_SerDes41, and SPI / Slave12 respectively. In this specification, the pin that outputs the CS signal output from SPI / Master11 may be denoted as M_CSn(x). For example, M_CSn(0) is assigned to M_SerDes31 and M_CSn(1) is assigned to SPI / Slave12.

[0059] The controller 11-3 controls the operation of the SCK generator 11-4. The SCK generator 11-4 outputs SCK when any of the CS signals is in the active state. The shift register 11-1 performs a shift operation in synchronization with the SCK.

[0060] The controller 11-3 detects that SPI / Slave12 has output the interrupt signal S_INT by the interrupt signal M_INT from M_SerDes31, and starts the SPI communication of the next frame using this interrupt signal M_INT as a trigger. Alternatively, when the controller 11-3 itself wants to transmit SPI data, it also starts the SPI communication in the same way (at time t5 of M_CSn(1) in FIG. 6 described later).

[0061] M_SerDes31 is connected to SPI / Master11. M_SerDes31 has an SPI block 31-1 for data communication with SPI / Master11 according to the SPI protocol. The SPI block 31-1 has a shift register 31-1-1 and a buffer / memory 31-1-2. When the controller 11-3 in SPI / Master11 activates the CS signal corresponding to M_SerDes31 and the SCK generator 41-1-3 outputs SCK, in synchronization with this SCK, the shift register 31-1-1 outputs SPI data and supplies it to SPI / Master11 via the MISO pin. Also, the shift register 31-1-1 captures the SPI data output from SPI / Master11 via the MOSI pin in synchronization with SCK.

[0062] When the CS signal becomes idle, the controller 11-3 stops the output of SCK to the SCK generator 11-4. As a result, the shift register 31-1-1 holds the state just before SCK is stopped.

[0063] When the CS signal transitions to the idle state, the SPI block 31-1 in M_SerDes31 transfers all the data in the shift register 31-1-1 to the buffer / memory 31-1-2. Thereby, the data transfer process according to the SPI protocol from SPI / Master11 to M_SerDes31 ends.

[0064] Note that the data transfer from the shift register 31-1-1 to the buffer / memory 31-1-2 in M_SerDes31 depends on the amount of data that SPI / Master11 wants to transfer and the data capacity of the shift register 31-1-1. Therefore, if there is a risk that the data in the shift register 31-1-1 will overflow during the active state of the CS signal, data loss can be prevented by transferring the data in the shift register 31-1-1 to the buffer / memory 31-1-2 before it overflows.

[0065] In addition, M_SerDes31 includes a packet encoder (ECP) 31-2, a packet decoder (DCP) 31-3, a DLL 31-4, and a PHY layer block (PHY) 31-5. The ECP 31-2 in M_SerDes31 converts the SPI data stored in the buffer / memory 31-1-2 into packets compliant with the TDD mode (SPI packets). The DLL 31-4 combines the SPI packets generated by the ECP 31-2 with other transmission packets other than the SPI packets to generate UP Link packets. The PHY 31-5 transmits the UP Link packets to S_SerDes41 via the UP Link.

[0066] The S_SerDes41 in FIG. 1 is connected to SPI / Slave12. The S_SerDes41 has an SPI block 41-1 to transmit and receive data according to the SPI protocol with SPI / Slave12. The SPI block 41-1 has a controller (CNTR) 41-1-4, an SCK generator 41-1-3, a shift register 41-1-1, and a buffer / memory 41-1-2. The controller 41-1-4 controls the timing and frequency of the SCK output from the SCK generator 41-1-3 based on the SPI control information from SPI / Master11. When the controller 41-1-4 activates the CS signal corresponding to SPI / Slave12 and the SCK generator 41-1-3 outputs the SCK, in synchronization with this SCK, the shift register 41-1-1 outputs SPI data and supplies it to SPI / Slave12 via the S_MOSI pin. Also, SPI data output from SPI / Slave12 via the S_MISO pin is input to the shift register 41-1-1 in synchronization with the SCK. In addition, the S_SerDes41 has a packet encoder (ECP) 41-2, a packet decoder (DCP) 41-3, a DLL 41-4, and a PHY layer block (PHY) 41-5. The ECP 41-2 in the S_SerDes41 converts the SPI data stored in the buffer / memory 41-1-2 into a packet (SPI packet) compliant with the TDD method. The DLL 41-4 combines the SPI packet generated by the ECP 41-2 with other transmission packets other than the SPI packet to generate an UP Link packet. The PHY 41-5 transmits the UP Link packet to the S_SerDes41 via the UP Link.

[0067] FIG. 5 is a diagram for explaining information included in transmission packets generated by ECP31-2 and 41-2. In FIG. 5, for each piece of information in the transmission packet, an identification symbol, an information name, a function in the transmission packet for data transmission from SPI / Master11 to SPI / Slave12, a function in the transmission packet for data transmission from SPI / Slave12 to SPI / Master11, and an explanation are associated with each other.

[0068] C-1 is a transmission mode, which is commanded by SPI / Master11 as a command. The transmission mode included in the packet from SPI / Slave12 is used for SPI / Master11 to monitor the state. If C-1 is 0, a single data block is transmitted within one frame period of TDD. If C-1 is 1, a plurality of data blocks divided according to a plurality of frame periods are transmitted.

[0069] C-2 is a slave selector signal (CSn signal), which is commanded by SPI / Master11 as a command. The CSn signal included in the packet from SPI / Slave12 is used for SPI / Master11 to monitor the state. The CSn signal is a signal for SPI / Master11 to select the SPI / Slave12 with which it wants to communicate. With the CSn signal, not only can individual SPI / Slave12 be selected, but SerDes (M_SerDes31 or S_SerDes41) can also be selected.

[0070] C-3 is the SCK frequency, which is commanded by SPI / Master11 as a command. The SCK frequency included in the packet from SPI / Slave12 is used for SPI / Master11 to monitor the state. C-3 is for SPI / Master11 to specify the SCK frequency on the SPI / Slave12 side.

[0071] C-4 is in SPI mode, and SPI / Master11 commands it as a command. The SPI mode included in the packet from SPI / Slave12 is used for SPI / Master11 to monitor the status. For example, if C-4 is 0, mode=0 in Figure 3A is selected; if it is 1, mode=1 in Figure 3B is selected; if it is 2, mode=2 in Figure 3C is selected; if it is 3, mode=3 in Figure 3D is selected.

[0072] C-5 is the total number of data blocks DB, and SPI / Master11 provides it as information. The total number of DBs included in the packet from SPI / Slave12 is used for SPI / Master11 to monitor the status. When C-1 is 0 (during the transmission of split DBs), C-5 is 1. SPI / Slave12 returns the number of received DBs since the start of SPI communication.

[0073] C-6 is the position of the current data block DB, and SPI / Master11 provides it as information. It is not included in the packet from SPI / Slave12. If C-6 is 0, it indicates invalid information. When C-1 is 0, it becomes 0. If C-6 is 1, it indicates the first split data. If it is 2, it indicates the split data other than the first and the last. If it is 3, it indicates the last split data.

[0074] C-7 is the status of the current data block DB, and both SPI / Master11 and SPI / Slave12 provide it as information. If C-7 is 0, it indicates dummy data; if it is 1, it indicates valid data.

[0075] C-8 is the size of the data block DB, and SPI / Master11 provides it as information. The data transmission size included in the packet from SPI / Slave12 is used for SPI / Master11 to monitor the status. C-8 represents the data transmission size in bytes, and the maximum size is 511 bytes.

[0076] C-9 is the interrupt information of SPI / Slave12, not included in the packets sent by SPI / Master11, and is the interrupt flag included in the packets sent by SPI / Slave12. If C-9 is 0, it indicates no interrupt; if it is 1, it indicates an interrupt.

[0077] C-10 is the operating state on the SPI / Slave12 side, not included in the packets sent by SPI / Master11, and is included in the packets from SPI / Slave12. If C-10 is 0, it indicates the normal state; if it is 1, it indicates busy (DCP31-3 is not empty); if it is 2, it indicates that an error has occurred (SPI data is corrupted).

[0078] C-11 is the reset of SPI block 41-1, commanded by SPI / Master11 as a command. It is not included in the packets of SPI / Slave12. If C-11 is 0, it does not perform a reset; if it is 1, it resets the SPI block 41-1 of S_SerDes41.

[0079] D-1 is the SPI data transmitted together with the above-mentioned C-1 to C-11. The SPI data transmitted by SPI / Master11 is output from the M_MOSI pin, and the SPI data transmitted by SPI / Slave12 is output from the S_MISO pin.

[0080] E-1 is the CRC transmitted together with the above-mentioned C-1 to C-11 and D-1, and is included in both the SPI data transmitted from SPI / Master11 and the SPI data transmitted from SPI / Slave12. The CRC is used for error detection of the control data C-1 to C-11 and the SPI data.

[0081] FIG. 6 is a timing diagram showing the communication between SPI / Master11 and SPI / Slave12, and FIGS. 7A and 7B are flowcharts showing the processing procedures for the communication between SPI / Master11 and SPI / Slave12. FIG. 8 is a diagram schematically showing the packets transmitted and received in the UP Link and the Down Link. FIGS. 6 to 8 show the processing procedures for transmitting and receiving a single data block within one frame period of TDD.

[0082] First, SPI / Master11 performs the process of generating the SPI control information used in ECP31-2 and DCP31-3 within M_SerDes31 and transmitting it to M_SerDes31 (Steps S1 to S4, times t1 to t4). The SPI control information includes, for example, the SPI transmission mode, the SCK frequency information, the SPI mode, and the size and number of the data block DB during SPI communication. SPI / Master11 stores the SPI control information in buffer / memory11-2 in advance.

[0083] The controller 11-3 within SPI / Master11 asserts M_CSn(0) to the active state (Low) in order to perform SPI communication with M_SerDes31 (Step S1, time t1).

[0084] The controller 11-3 within SPI / Master11 controls the SCK generator 11-4 to output the clock M_SCK (step S2, time t2). Synchronized with the clock M_SCK, the SPI control information stored in the buffer / memory 11-2 is sequentially read out and transferred to the shift register 11-1. The transferred SPI control information includes the transmission mode, SCK frequency information, SPI mode, transmission data size, number of data blocks, etc. The shift register 11-1 outputs the SPI control information sequentially in synchronization with the clock M_SCK (steps S2~S3, time t2~t3). This SPI control information is input to M_SerDes31 via the M_MOSI pin. The shift register 31-1-1 within M_SerDes31 captures the SPI control information from SPI / Master11 in synchronization with M_SCK.

[0085] In parallel with capturing the SPI control information from SPI / Master11, the shift register 31-1-1 transmits the data held in the shift register 31-1-1 to SPI / Master11 via the M_MISO pin in synchronization with M__SCK. Since this data is invalid data, it is shown by a dashed line at times t2~t3 in Figure 6. SPI / Master11 discards this data after receiving it.

[0086] When the data transfer of SPI / Master11 is completed, the controller 11-3 within SPI / Master11 stops the generation of M_SCK for the SCK generator 11-4 and de-asserts M_CSn(0) to the idle state (step S4, time t4). When M_SCK stops, the shift register 31-1-1 within M_SerDes31 transfers the held SPI control information from SPI / Master11 to the buffer / memory 31-1-2.

[0087] The buffer / memory 31-1-2 within M_SerDes31 transfers the SPI control information from SPI / Master11 to the ECP31-2. The ECP31-2 converts the SPI control information into an SPI packet.

[0088] Next, for the purpose of performing data transmission to SPI / Slave12, SPI / Master11 transmits SPI data to M_SerDes31. Specifically, the controller 11-3 in SPI / Master11 transitions (asserts) M_CSn(1) corresponding to SPI / Slave12 from the idle state to the active state (step S5, time t5).

[0089] Also, the controller 11-3 causes M_SCK to be output to SCK generator 11-4 (step S6, time t6). Buffer / memory 11-2 reads out the data to be transmitted to SPI / Slave12 by the amount of the transmission data size and inputs it to the shift register 11-1. The shift register 11-1 sequentially outputs data for SPI / Slave12 via the M_MOSI pin in synchronization with M_SCK (step S7, time t7).

[0090] The shift register 31-1-1 in M_SerDes31 sequentially captures the data output from SPI / Master11 into the shift register 31-1-1 in synchronization with SCK. When the data transfer for the amount of the transmission data size is completed, the controller 11-3 in SPI / Master11 stops the output of M_SCK to SCK generator 11-4 (step S8, time t8). Thereafter, the controller 11-3 of SPI / Master11 sets M_CSn(1) to the idle state (de-asserts) and ends the SPI communication (step S9, time t9).

[0091] When M_SCK stops, M_SerDes31 transfers the data held in shift register 31-1-1 to buffer / memory 31-1-2. Buffer / memory 31-1-2 transfers the data transferred from shift register 31-1-1 to ECP31-2. ECP31-2 generates data including the SPI control information received in the communication from time t1 to t3, the CS signal (M_CSn(1)) corresponding to SPI / Slave12, and the Data for SPI / Slave12. ECP31-2 adds a flag indicating that the packet is valid to the generated data to generate a transmission packet.

[0092] ECP31-2 transmits the generated transmission packet as SPI packet 51 to DLL31-4 as shown in FIG. 8. DLL31-4 combines the SPI packet 51 from ECP31-2 and other transmission packets to generate an UP Link packet 52 and outputs it to PHY layer block 31-5. PHY layer block 31-5 outputs the received UP Link packet 52 to cable 103 according to the UP Link output timing by TDD (step S10, time t10).

[0093] S_SerDes41 communicates with M_SerDes31 in a TDD mode and performs SPI communication with SPI / Slave12. The PHY layer block 41-5 in S_SerDes41 receives the UP Link Packet from M_SerDes31 via cable 103 and outputs it to the Link layer block (DLL) 41-4.

[0094] The Link layer block 41-4 within S_SerDes41 extracts an SPI packet containing SPI data from the UP Link Packet and outputs it to the packet decoder (DCP) 41-3. Based on the CSn information (C-2) within the received SPI packet, DCP 41-3 detects that SPI / Slave12 is the SPI communication target. Then, in order to initiate SPI communication with SPI / Slave12, the controller 41-1-4 detects that all of the SPI data has been transmitted based on the transmission mode information (C-1) within the SPI packet, and after obtaining the number of SCK cycles required for one SPI communication based on the number (C-5) and size (C-8) of the SPI data, it activates (asserts) the Slave select signal S_CS (step S11, time t11).

[0095] Next, the controller 41-1-4 within S_SerDes41 obtains the SCK frequency information (C-3) contained in the SPI packet and causes S_SCK to be output to the SCK generator 41-1-3 at the obtained frequency (step S12, time t12). At this time, the phase relationship between S_CS and SCK follows the SPI mode (C-4) within the SPI packet. As a result, S_SerDes41 becomes capable of transferring SPI data with SPI / Slave12. The data transferred to SPI / Slave12 is the SPI packet (D-1) and is stored in the buffer / memory 41-1-2.

[0096] The shift register 41-1-1 within S_SerDes41 sequentially outputs the SPI data transferred from the buffer / memory 41-1-2 from the S_MOSI pin by means of the SCK supplied from the SCK generator 41-1-3 (step S13, time t13). In parallel with this, the SPI data output from the SPI / Slave12 to the S_MISO pin is stored in the shift register 41-1-1 and then transferred to the buffer / memory 41-1-2 in a timely manner.

[0097] SPI / Slave12 captures the SPI data from the S_MOSI pin of S_SerDes41 into the sequential shift register 12-1 in synchronization with S_SCK, and sequentially outputs the data held by the shift register 12-1 from the S_MISO pin (step S14, time t14).

[0098] After driving S_SCK for the set size (C-8) of the SPI data, the controller (41-1-4) stops SCK and returns S_CS to the idle state (de-asserts it) to end the SPI communication (step S15, time t15). In parallel, while receiving SPI data from the S_MOSI pin of S_SerDes41, SPI / Slave12 transfers the SPI data from the S_MOSI pin from the shift register 12-1 to buffer / memory12-2 in a timely manner, and finally completes the reception of the data from SPI / Master11.

[0099] buffer / memory41-1-2 transfers the SPI data received from SPI / Slave12 to the packet encoder (ECP) 41-2 for transmission to SPI / Master11. ECP41-2 adds the SPI control information it obtained in the SPI packet, together with the received SPI data, to the SPI packet 53. In addition, ECP41-2 adds the information indicating the operating state of SPI / Slave12 in (C-10) of FIG. 5 and the CRC in (E-1) to the SPI packet.

[0100] Also, when SPI / Slave12 outputs an interrupt signal (C-9), ECP41-2 also includes the information of the interrupt signal in the SPI packet 53. In this case, the SPI packet 53 does not transmit the SPI data from SPI / Slave12. The reason for providing the interrupt signal is that in the SPI protocol, only SPI / Master11 controls the CS signal and SCK, and SPI / Slave12 cannot actively output data, so it issues an interrupt signal and waits for an instruction from SPI / Master11.

[0101] The Link layer block (DLL) 41-4 combines the SPI packet 53 received from the ECP 41-2 with other transmission packets to generate a Down Link packet 54 and outputs it to the PHY layer block 41-5. The PHY layer block 41-5 outputs the received Down Link packet 54 to the cable 103 according to the Down Link output timing (step S16, time t16).

[0102] The PHY layer block 31-5 of the M_SerDes 31 receives a Down Link packet including the SPI packet 53 from the SPI / Slave 12 output from the S_SerDes 41 and outputs it to the DLL 31-4. The DLL 31-4 extracts the SPI packet 53 from the received Down Link packet 54 and outputs it to the packet decoder (DCP) 31-3.

[0103] The DCP 31-3 in the M_SerDes 31 receives a packet including the I_DB#1 transmitted to the Master 11 simultaneously when receiving the SPI data O_DB#1 from the Master 11 and stores it in the buffer / memory 31-1-2. In order to indicate that the valid SPI data I_DB#1 has returned from the SPI / Slave 12, the buffer / memory 31-1-2 asserts the interrupt signal M_INT (step S17, time t17). The controller 11-3 of the SPI / Master 11 that receives the interrupt signal M_INT starts SPI communication to read the SPI data from the SPI / Slave 12 from the M_SerDes 31 and activates (asserts) the M_CSn(1) (step S18, time t18).

[0104] The controller 11-3 of SPI / Master11 controls the SCK generator 11-4 to output M_SCK (11-10-2) (step S19, time t19). The shift register 11-1 sequentially fetches data from the M_MISO pin by the amount of the transmission data size (c-8) set in Frame#1 in synchronization with the SCK. At this time, the buffer / memory 31-1-2 in M_SerDes31 transfers the data from SPI / Slave12 to the shift register 31-1-1 in a timely manner, and the shift register 31-1-1 sequentially outputs the data in synchronization with the SCK generator 11-4 as described above. This data is fetched from the M_MISO pin (step S20, time t20). In parallel with this, SPI / Master11 reads the SPI data to be transferred to SPI / Slave12 next from the buffer / memory 11-2, fetches it into the shift register 11-1, and sequentially outputs it from the shift register 11-1 to the M_MOSI pin (step S21, time t21). After the necessary data is read, the buffer / memory 31-1-2 returns the interrupt signal M_INT to the idle state (deasserts it) (step S22, time t22).

[0105] With the operations up to this point, the transfer of SPI data between SPI / Master11 and SPI / Slave12 is completed. The above series of operations is repeated the number of times of the transfer of the necessary SPI data (step S23, time t23).

[0106] When SPI / Master11 reads the last SPI data from SPI / Slave12, SPI / Master11 asserts M_CSn(1) to output dummy data (step S24, time t24). Since this dummy data is invalid data and does not need to be transferred to the SPI slave, it is discarded without being transferred from the shift register 31-1-1 of M_SerDes31 to buffer / memory31-1-2 (step S25, time t25). The last data from SPI / Slave12 is output from the shift register 31-1-1 in M_SerDes31 through the M_MISO pin and captured into the shift register 11-1 in SPI / Master11 (step S26, time t26).

[0107] In this way, in the first embodiment, a block of data transmitted by SPI / Master11 to M_SerDes31 in SPI communication can be transmitted to S_SerDes41 via the UP Link within one frame period of the TDD system, and a block of data transmitted by SPI / Slave12 to S_SerDes41 in SPI communication can be transmitted to M_SerDes31 via the Down Link. Thereby, by combining full-duplex SPI communication and half-duplex TDD communication, serial communication can be performed between SPI / Master11 and SPI / Slave12 via M_SerDes31 and S_SerDes41.

[0108] (Second Embodiment) The second embodiment divides the data transmitted and received in SPI communication into a plurality of frame periods of the TDD system for transmission and reception.

[0109] The communication system 2 according to the second embodiment is configured in the same manner as in FIG. 1, but the SPI control information transmitted by SPI / Master11 to M_SerDes31 is different.

[0110] FIG. 9 is a timing diagram when the process of transmitting the divided data within one frame period is repeated over a plurality of frames. FIGS. 10A, 10B, and 10C are flowcharts showing the processing procedures of the communication system 2 operating at the timing of FIG. 9.

[0111] Steps S31 to S38 (times t31 to t38) in FIG. 10A are the same as steps S1 to S8 (times t1 to t8) in FIG. 7. SPI / Master11 generates SPI control information and sets it in ECP31-2 and DCP31-3 in M_SerDes31. The processing operations after step S39 are basically the same as those in FIGS. 7A and 7B. However, in FIGS. 9, 10A, 10B, and 10C, the data transmitted within one SPI frame is divided into a plurality of pieces, and each of the plurality of divided data is transmitted during one frame period of TDD. The signal transmitted during one frame period of TDD is called a TDD burst signal.

[0112] Until the transfer of all the divided data within the SPI frame is completed, the Slave Select signal M_CSn(1) between SPI / Master11 and M_SerDes31 and the Slave Select signal S_CS between S_SerDes41 and SPI / Slave12 remain in the active state.

[0113] SPI / Master11 asserts the CS signal (M_CSn(1)) to start the transmission of SPI data (step S35, time t35). SPI / Master11 causes SCK generator11-4 to output M_SCK for the purpose of transmitting one divided data (data block DB) (step S36, time t36).

[0114] Next, SPI / Master11 outputs SPI data from shift register 11-1 in sequence in synchronization with SCK and outputs it from the M_MOSI pin (step S37, time t37). Also, SPI / Master11 outputs the CS signal corresponding to SPI / Slave12 which is the communication target to M_SerDes31 (step S38, time t38). Next, ECP31-2 in M_SerDes31 generates a packet including the SPI data and the CS signal (step S39, time t39). This packet is combined with other transmission packets in PHY layer block31-5 to generate an UP Link packet. This UP Link packet is transmitted to S_SerDes41 via the UP Link.

[0115] SPI / Master11 continues to assert the CS signal until all the divided data is transmitted (step S40, time t40). SPI / Master11 stops the output of M_SCK from SCK generator11-4 until the next divided data is transmitted (step S41, time t41).

[0116] S_SerDes41 acquires the CS signal and the SPI data from the received packet and asserts S_CS (step S42, time t42). The controller 41-1-4 in S_SerDes41 causes S_SCK to be output to SCK generator41-1-3 (step S43, time t43). S_SerDes41 temporarily stores the SPI data in the received packet in buffer / memory41-1-2 and then transfers it to shift register 41-1-1. Shift register 41-1-1 outputs the data in sequence in synchronization with S_SCK. The output data is input to SPI / Slave12 from the S_MOSI pin (step S44, time t44). Also, the data output from shift register 12-1 in SPI / Slave12 in synchronization with S_SCK is input to S_SerDes41 from the S_MISO pin (step S45, time t45).

[0117] The DLL 41-4 within S_SerDes41 generates a transmission packet containing data from the S_MISO pin. The PHY layer block 41-5 transmits the transmission packet to the Down Link at the timing defined by the TDD method (step S46, time t46).

[0118] The DLL 31-4 within M_SerDes31 transmits the SPI packet contained in the transmission packet transmitted from S_SerDes41 to DCP31-3. DCP31-3 receives a packet containing I_DB#1 that is transmitted to Master11 simultaneously when receiving SPI data O_DB#1 from Master11, and stores it in buffer / memory 31-1-2. To indicate that valid SPI data I_DB#1 has returned from SPI / Slave12, buffer / memory 31-1-2 asserts an interrupt signal M_INT (step S47, time t47).

[0119] When SPI / Master11 detects that M_INT has been asserted, it causes M_SCK to be output to the SCK generator 11-4 (step S48, time t48). Buffer / memory 11-2 transfers the data to be transmitted next to the shift register 11-1, and the shift register 11-1 outputs the SPI data from the M_MOSI pin synchronized with M_SCK (step S49, time t49). In parallel with this, the data output from M_SerDes31 via the M_MISO pin is taken into the shift register 11-1 (step S50, time t50).

[0120] When SPI / Master11 reads all the data from M_SerDes31, it returns M_INT to the idle state (de-asserts it) (step S51, time t51).

[0121] S_SerDes41 maintains the active state (assert) of S_CS until all the split data is transmitted (step S52, time t52). Also, the SCK generator 41-1-3 in S_SerDes41 stops the output of S_SCK until the next SPI data is transmitted from M_SerDes31 (step S53, time t53).

[0122] Thereafter, the processing operations of steps S40 to S53 are repeated (step S54, time t54). When M_SerDes31 transmits the last split packet on the UP Link (step S55, time t55), S_SerDes41 outputs S_SCK (step S56, time t56). Then, S_SerDes41 outputs SPI data via the S_MOSI pin (step S57, time t57) and receives the last SPI data from SPI / Slave12 via the S_MISO pin (step S58, time t58).

[0123] When S_SerDes41 finishes receiving the last SPI data, it sets S_CS to the idle state (de-assert) (step S59, time t59). Also, S_SerDes41 transmits the transmission packet including the last SPI data to M_SerDes31 on the Down Link (step S60, time t60).

[0124] M_SerDes31 activates M_INT in the same way as in step S47 (step S61, time t61). Also, M_SerDes31 causes the SCK generator 11-4 in SPI / Master11 to output M_SCK (step S62, time 62). Synchronized with M_SCK, the data output from the shift register 31-1-1 via the M_MISO pin is captured into the shift register 11-1 in SPI / Master 11 (steps S63 - S64, times t63 - t64). When SPI / Master11 has captured all the data, it sets the CS signal to the idle state (step S65, time t65). Also, since the data output from the shift register 11-1 in step S63 is dummy data, it is discarded (step S66, time t66).

[0125] In this way, in the second embodiment, each split data obtained by splitting a set of data transmitted from SPI / Master11 to M_SerDes31 by SPI communication is transmitted to S_SerDes41 via the UP Link in a plurality of frame periods of the TDD system, and each split data obtained by splitting a set of data transmitted from SPI / Slave12 to S_SerDes41 by SPI communication can be transmitted to M_SerDes31 via the Down Link in a plurality of frame periods of the TDD system.

[0126] (Third Embodiment) In the third embodiment, SPI / Master11 performs serial communication with a plurality of SPI / Slaves12.

[0127] FIG. 11 is a block diagram of the main part of a communication system 2 including a communication device according to the third embodiment. In FIG. 11, S_SerDes41 and a plurality of SPI / Slaves12 are shown. Since the internal configurations of SPI / Slave12 and M_SerDes31 are the same as those in FIG. 1, they are omitted in FIG. 11. Also, in FIG. 11, the same reference numerals are given to the components common to FIG. 1.

[0128] SPI / Master11 specifies the CSn signal of the SPI / Slave12 with which communication is to be performed using the SPI control information transmitted to M_SerDes31. The controller 41-1-4 in S_SerDes41 activates the CSn signal specified by SPI / Master11. FIG. 11 shows an example in which two SPI / Slaves 12_1 and 12_2 are connected to S_SerDes41.

[0129] When SPI / Master11 wants to perform data communication with SPI / Slave12_1, it sets the CSn signal in the SPI control signal to CS1. As a result, the controller 41-1-4 in S_SerDes41 activates the S_CS1 pin that outputs the CS1 signal. Since the CS1 signal from the S_CS1 pin is input to SPI / Slave12_1, SPI / Slave12_1 receives SPI data synchronized with S_SCK from S_SerDes41 and transmits SPI data synchronized with S_SCK to S_SerDes41.

[0130] Also, when SPI / Master11 wants to perform data communication with SPI / Slave12_2, it sets the CSn signal in the SPI control signal to CS2. As a result, the controller 41-1-4 in S_SerDes41 activates the S_CS2 pin that outputs the CS2 signal. Since the CS2 signal from the S_CS2 pin is input to SPI / Slave12_2, SPI / Slave12_2 receives SPI data synchronized with S_SCK from S_SerDes41 and transmits SPI data synchronized with S_SCK to S_SerDes41.

[0131] In the communication system 2 of FIG. 11, an example is shown in which the SPI / Slave12 with which SPI / Master11 wants to communicate is specified by the CSn signal in the SPI control signal. However, as shown in FIG. 12, a plurality of SPI / Slaves 12 may be daisy-chain connected.

[0132] FIG. 12 is a block diagram of a main part of a communication system 2 including a communication device according to a modified example of FIG. 11. In FIG. 12, two SPI / Slaves 12 capable of performing serial communication simultaneously with SPI / Master 11 are illustrated, but three or more SPI / Slaves 12 may be enabled to perform serial communication simultaneously with SPI / Master 11.

[0133] The shift registers 12-1 in the two SPI / Slaves 12_1 and 12_2 in FIG. 12 are daisy-chained. The data output from the MSB of the shift register 12-1 in SPI / Slave 12_2 synchronized with SCK is input to the LSB of the shift register 12-1 in SPI / Slave 12_1, and the data output from the MSB is transmitted to S_SerDes41 by SPI communication.

[0134] In the communication device of FIG. 12, it is necessary to repeat the processes of steps S24 to S26 in FIG. 6 for the number of SPI / Slaves 12.

[0135] Thus, in the third embodiment, SPI / Master 11 can perform bidirectional serial communication with a plurality of SPI / Slaves 12 by designating individual SPI / Slaves 12 with the CSn signal in the SPI control information. Also, by daisy-chaining a plurality of SPI / Slaves 12, SPI / Master 11 can perform serial communication with a plurality of SPI / Slaves 12 simultaneously.

[0136] Note that the present technology can adopt the following configuration. (1) A communication device including a communication unit that transmits a group of serial signals compliant with SPI (Serial Peripheral Interface) transmitted synchronously with a clock from a master to a communication partner device as a single data block within one frame period of a predetermined communication protocol, or as a plurality of data blocks divided according to a plurality of frame periods. (2) A memory that stores a first serial signal group compliant with SPI transmitted from the master in synchronization with the clock, and stores a second serial signal group compliant with SPI transmitted from the slave in synchronization with the clock, A packet encoder that converts the first serial signal group stored in the memory into a first packet of the predetermined communication protocol, A packet decoder that converts the second packet of the predetermined communication protocol received from the communication partner device into the second serial signal group, and the communication device according to (1). (3) The first packet includes frequency information of the clock, polarity information, and phase information of the clock with respect to the data signal of the first serial signal group compliant with SPI, and the communication device according to (2). (4) The first packet includes information indicating that it includes a single data block within the one frame period, or information indicating that it includes a plurality of data blocks divided according to the plurality of frame periods, and the communication device according to (2) or (3). (5) When the first packet includes the plurality of data blocks, the first packet includes the total number of the plurality of data blocks and the division position information of the data blocks, and the communication device according to (4). (6) The first packet includes size information of the data block, and the communication device according to (4) or (5). (7) The first packet includes information indicating whether the data block is valid or invalid, and the communication device according to any one of (2) to (6). (8) The first packet includes information indicating that the slave is to be reset, and the communication device according to any one of (2) to (7). (9) The second packet includes at least one of information indicating the operating state of the slave and interrupt information from the slave, and the communication device according to any one of (2) to (8). (10) The communication device according to (9), wherein when the interrupt information is included in the second packet and when the second packet itself arrives at the memory from the communication partner device, the slave determines that the slave is requesting a read of the slave state and transmits an interrupt signal to the master. (11) The communication device according to any one of (2) to (10), wherein the first packet includes information on a slave select signal included in the first serial signal group conforming to the SPI that selects the communication partner device or the slave. (12) The communication device according to (11), wherein the packet encoder transmits the first packet with the communication partner device or the slave selected by the slave select signal as a destination. (13) The communication device according to any one of (2) to (12), further comprising a shift register that sequentially stores each serial signal included in the first serial signal group in the memory in synchronization with the clock and sequentially transmits each serial signal included in the second serial signal group to the master in synchronization with the clock. (14) The communication device according to any one of (2) to (13), wherein the communication unit transmits the first packet at a first timing defined by the predetermined communication protocol and receives the second packet at a second timing defined by the predetermined communication protocol. (15) The communication device according to any one of (2) to (14), wherein when the slave select signal transmitted from the master transitions from a first logic to a second logic, the packet encoder determines that the transmission of the first serial signal group from the master has ended. (16) The communication device according to any one of (2) to (15), wherein the communication unit transmits and receives the first packet and the second packet using the communication protocol according to TDD (Time Division Duplex) with the communication partner device. A communication device comprising a communication unit that transmits, as a single data block within one frame period of a predetermined communication protocol or as a plurality of data blocks divided according to a plurality of frame periods, a group of serial signals compliant with SPI transmitted from a slave in synchronization with a clock generated based on clock frequency information included in a packet from a communication partner device. (18) A packet decoder that converts a first packet of a predetermined communication protocol received from the communication partner device into a first group of serial signals compliant with SPI, A clock generator that generates the clock based on the clock frequency information included in the first group of serial signals, A memory that stores the first group of serial signals in synchronization with the clock and stores a second group of serial signals compliant with SPI transmitted from a slave in synchronization with the clock, A packet encoder that converts the second group of serial signals stored in the memory into a second packet of the predetermined communication protocol, the communication device according to (17). (19) The second packet includes information indicating that it includes a single data block transmitted within one frame period of the second group of serial signals or information indicating that it includes a plurality of data blocks divided and transmitted over a plurality of frame periods, the communication device according to (18). (20) The second packet includes information indicating whether the slave is in a busy state where it cannot receive the first group of serial signals and information indicating whether there is an error in the first group of serial signals received by the slave, the communication device according to (18) or (19). (21) The second packet includes interrupt information requesting that the master read the state of the slave, the communication device according to any one of (18) to (20). (22) A communication device according to any one of (18) to (21), comprising a shift register that stores each serial signal included in the second serial signal group in the memory and transmits each serial signal included in the first serial signal group to the slave. (23) The communication unit transmits the second packet at a first timing defined by the predetermined communication protocol and receives the first packet at a second timing defined by the predetermined communication protocol. A communication device according to any one of (18) to (22). (24) The communication unit transmits and receives the first packet and the second packet using the communication protocol corresponding to TDD (Time Division Duplex) with the communication partner device. A communication device according to any one of (18) to (23). (25) A communication system comprising a first communication device and a second communication device that transmit and receive packets using a predetermined communication protocol. The first communication device transmits a first group of serial signals compliant with SPI (Serial Peripheral Interface) transmitted in synchronization with a clock from a master to the second communication device as a single data block within one frame period of a predetermined communication protocol, or as a plurality of data blocks divided according to a plurality of frame periods. It has a first communication unit that transmits to the second communication device. The second communication device synchronizes with a clock generated based on the clock frequency information included in the packet from the first communication device, and a second group of serial signals compliant with SPI transmitted from a slave is transmitted as a single data block within one frame period of the predetermined communication protocol. Or a communication system that transmits to the first communication device as a plurality of data blocks divided according to a plurality of frame periods. (26) The first communication device A first memory that stores the first group of serial signals transmitted in synchronization with the first clock from the master and stores the second group of serial signals transmitted in synchronization with the first clock from the slave. A first packet encoder that converts the first serial signal group stored in the first memory into a first packet of the predetermined communication protocol; A first packet decoder that converts the second packet of the predetermined communication protocol received from the second communication device into the second serial signal group; A first communication unit that transmits the first packet at a timing defined by the predetermined communication protocol and receives the second packet at a timing defined by the predetermined communication protocol; The second communication device A second packet decoder that converts the received first packet into the first serial signal group; A clock generator that generates a second clock based on the clock frequency information included in the first serial signal group; A second memory that stores the first serial signal group in synchronization with the second clock and stores the second serial signal group transmitted from the slave in synchronization with the second clock; A packet encoder that converts the second serial signal group stored in the second memory into the second packet; A second communication unit that transmits the second packet at a timing defined by the predetermined communication protocol and receives the first packet at a timing defined by the predetermined communication protocol; The communication system according to (25). A communication method comprising a communication unit that transmits a serial signal group conforming to SPI transmitted in synchronization with a clock from a master to a communication partner device as a single data block within one frame period of a predetermined communication protocol, or as a plurality of data blocks divided according to a plurality of frame periods.

[0137] Aspects of the present disclosure are not limited to the individual embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described content. That is, various additions, changes, and partial deletions are possible without departing from the conceptual ideas and spirit of the present disclosure derived from the content defined in the claims and their equivalents.

Explanation of Reference Numerals

[0138] 1a communication device, 1b communication device, 2 communication system, 11 SPI / Master, 11-1 sequential shift register, 11-1 shift register, 11-2 buffer / memory, 11-3 controller, 11-4 SCK generator, 12 SPI / Slave, 12-1 shift register, 12-2 buffer / memory, 31 M_SerDes, 31-1 SPI block, 31-1-1 shift register, 31-1-2 buffer / memory, 31-3 packet decoder (DCP), 31-5 PHY layer block, 32 peripheral devices, 41 S_SerDes, 41-1 SPI block, 41-1-1 shift register, 41-1-2 buffer / memory, 41-1-3 SCK generator, 41-1-4 controller, 41-2 packet encoder (ECP), 41-3 packet decoder (DCP), 41-4 Link layer block (DLL), 41-5 PHY layer block, 42 peripheral devices, 51 SPI packet, 52 UP Link packet, 53 SPI packet, 54 Down Link packet, 103 cable

Claims

1. A communication unit that transmits a group of serial signals compliant with SPI (Serial Peripheral Interface) transmitted in synchronization with a clock from a master to a communication partner device as a single data block within one frame period of a predetermined communication protocol, or transmits the group of serial signals to the communication partner device as a plurality of data blocks divided according to a plurality of frame periods, A memory that stores a first group of serial signals compliant with SPI transmitted in synchronization with the clock from the master and stores a second group of serial signals compliant with SPI transmitted in synchronization with the clock from a slave, A packet encoder that converts the first group of serial signals stored in the memory into a first packet of the predetermined communication protocol, A communication device comprising: a packet decoder that converts a second packet of the predetermined communication protocol received from a communication partner device into the second group of serial signals.

2. The communication device according to claim 1, wherein the first packet includes frequency information of the clock, polarity information, and phase information of the clock with respect to a data signal of the first group of serial signals compliant with SPI.

3. The communication device according to claim 1 or 2, wherein the first packet includes information indicating that the first packet includes a single data block within the one frame period, or information indicating that the first packet includes a plurality of data blocks divided according to the plurality of frame periods.

4. The communication device according to claim 3, wherein when the first packet includes the plurality of data blocks, the first packet includes the total number of the plurality of data blocks and division position information of the data blocks.

5. The communication device according to claim 3 or 4, wherein the first packet includes size information of the data block.

6. The communication device according to any one of claims 1 to 5, wherein the first packet includes information indicating whether the data block is valid or invalid.

7. The communication device according to any one of claims 1 to 6, wherein the first packet includes information indicating that the slave is reset.

8. The communication device according to any one of claims 1 to 7, wherein the second packet includes at least one of information indicating an operating state of the slave and interrupt information from the slave.

9. The communication device according to claim 8, wherein when the interrupt information is included in the second packet and when the second packet itself arrives at the memory from the communication partner device, the slave determines that the slave is requesting reading of the slave state, and transmits an interrupt signal to the master.

10. The communication device according to any one of claims 1 to 9, wherein the first packet includes information on a slave select signal included in the first serial signal group conforming to the SPI that selects the communication partner device or the slave.

11. The communication device according to claim 10, wherein the packet encoder transmits the first packet to the communication partner device or the slave selected by the slave select signal as a destination.

12. The communication device according to any one of claims 1 to 11, further comprising a shift register that stores each serial signal included in the first serial signal group in the memory sequentially in synchronization with the clock, and transmits each serial signal included in the second serial signal group to the master sequentially in synchronization with the clock.

13. The communication device according to any one of claims 1 to 12, wherein the communication unit transmits the first packet at a first timing defined by the predetermined communication protocol and receives the second packet at a second timing defined by the predetermined communication protocol.

14. The communication device according to any one of claims 1 to 13, wherein the packet encoder determines that transmission of the first serial signal group from the master has ended when the slave select signal transmitted from the master transitions from a first logic to a second logic.

15. The communication device according to any one of claims 1 to 14, wherein the communication unit transmits and receives the first packet and the second packet using the communication protocol corresponding to TDD (Time Division Duplex) with the communication partner device.

16. Synchronizing with a clock generated based on clock frequency information included in a packet from a communication partner device, a group of serial signals compliant with SPI transmitted from a slave is transmitted to the communication partner device as a single data block within one frame period of a predetermined communication protocol, or is transmitted to the communication partner device as a plurality of data blocks divided according to a plurality of frame periods. A communication unit, A packet decoder that converts a first packet of a predetermined communication protocol received from the communication partner device into a first group of serial signals compliant with SPI, A clock generator that generates the clock based on the clock frequency information included in the first group of serial signals, A memory that stores the first group of serial signals in synchronization with the clock and stores a second group of serial signals compliant with SPI transmitted from the slave in synchronization with the clock, A packet encoder that converts the second group of serial signals stored in the memory into a second packet of the predetermined communication protocol. A communication device comprising:

17. The communication device according to claim 16, wherein the second packet includes information indicating that it includes a single data block transmitted within one frame period of the second group of serial signals, or information indicating that it includes a plurality of data blocks transmitted divided into a plurality of frame periods.

18. The communication device according to claim 16 or 17, wherein the second packet includes information indicating whether the slave is in a busy state where it cannot receive the first group of serial signals, and information indicating whether there is an error in the first group of serial signals received by the slave.

19. The communication device according to any one of claims 16 to 18, wherein the second packet includes interrupt information requesting that the master read the state of the slave.

20. The communication device according to any one of claims 16 to 19, further comprising a shift register that stores each serial signal included in the second group of serial signals in the memory and transmits each serial signal included in the first group of serial signals to the slave.

21. The communication unit transmits the second packet at a first timing defined by the predetermined communication protocol and receives the first packet at a second timing defined by the predetermined communication protocol. The communication device according to any one of claims 16 to 20.

22. The communication unit transmits and receives the first packet and the second packet to and from the communication partner device according to the communication protocol corresponding to TDD (Time Division Duplex). The communication device according to any one of claims 16 to 21.

23. A first communication device and a second communication device that transmit and receive packets according to a predetermined communication protocol are provided. The first communication device transmits a first group of serial signals compliant with SPI (Serial Peripheral Interface) transmitted in synchronization with a clock from a master to the second communication device as a single data block within one frame period of the predetermined communication protocol, or transmits the signals to the second communication device as a plurality of data blocks divided according to a plurality of frame periods. The first communication device has a first communication unit. The second communication device transmits a second group of serial signals compliant with SPI transmitted from a slave to the first communication device as a single data block within one frame period of the predetermined communication protocol, or transmits the signals to the first communication device as a plurality of data blocks divided according to a plurality of frame periods, in synchronization with a clock generated based on the clock frequency information included in the packet from the first communication device. The first communication device has a first memory that stores the first group of serial signals transmitted in synchronization with a first clock from a master and stores the second group of serial signals transmitted in synchronization with the first clock from a slave; a first packet encoder that converts the first group of serial signals stored in the first memory into a first packet of the predetermined communication protocol; a first packet decoder that converts the second packet of the predetermined communication protocol received from the second communication device into the second group of serial signals; and a first communication unit that transmits the first packet at a timing defined by the predetermined communication protocol and receives the second packet at a timing defined by the predetermined communication protocol. The second communication device A second packet decoder that converts the received first packet into the first serial signal group; A clock generator that generates a second clock based on the clock frequency information included in the first serial signal group; A second memory that stores the first serial signal group in synchronization with the second clock and stores the second serial signal group transmitted from the slave in synchronization with the second clock; A packet encoder that converts the second serial signal group stored in the second memory into the second packet; A communication system comprising: a second communication unit that transmits the second packet at a timing defined by the predetermined communication protocol and receives the first packet at a timing defined by the predetermined communication protocol.

24. Transmit a serial signal group compliant with SPI transmitted from the master in synchronization with the clock as a single data block within one frame period of a predetermined communication protocol, or transmit it to the communication partner device as a plurality of data blocks divided according to a plurality of frame periods, Store the first serial signal group compliant with SPI transmitted from the master in synchronization with the clock, and store the second serial signal group compliant with SPI transmitted from the slave in synchronization with the clock in the memory, Convert the first serial signal group stored in the memory into a first packet of the predetermined communication protocol, A communication method for converting a second packet of the predetermined communication protocol received from a communication partner device into the second serial signal group.

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