Multi-channel frequency-adjustable signal generation system based on FPGA (Field Programmable Gate Array)
By using generate block statements and location register technology, the resource usage and control logic of the FPGA multi-channel adjustable frequency signal generation system are optimized, solving the problems of resource waste and synchronization complexity in the existing technology, and realizing efficient and flexible multi-channel signal output.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-04-10
AI Technical Summary
Existing FPGA-based multi-channel adjustable frequency signal generation designs suffer from problems such as wasted hardware resources, high code complexity, complex synchronization control, and poor flexibility.
Employing generate block statements and location register technology, multiple signals are output in parallel through the top-level module. A set of register resources is used to control multiple outputs, simplifying the register configuration process. Remote parameter adjustment is achieved through the SPI communication module.
It significantly reduces FPGA resource consumption, simplifies code structure, improves system maintainability and flexibility, and enables synchronous output and high-precision control of multiple signals.
Smart Images
Figure CN121841508A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal generation technology, and in particular to a multi-channel adjustable frequency signal generation system based on FPGA. Background Technology
[0002] In the field of signal communication and control, adjustable frequency signal generation technology has significant application value. Traditional signal output modules mostly use fixed-frequency pulse signal output, which has obvious limitations in practical applications. As application scenarios continue to expand, systems often need to dynamically adjust parameters such as the frequency and duty cycle of the output signal according to different operating conditions. This necessitates the design of solutions that can provide multiple adjustable frequency signals.
[0003] Currently, FPGA-based adjustable frequency signal generation designs typically employ a module-based repetitive instantiation approach to achieve multiple outputs. Specifically, when generating N adjustable frequency signals, designers need to instantiate the same functional module multiple times in the FPGA code. While intuitive, this method suffers from significant efficiency issues. Each module's repeated instantiation requires declaring multiple sets of functionally identical register variables and configuring multiple independent register addresses in the upper-layer interface (such as the SPI communication module). This design approach leads to wasted hardware resources, increased code complexity, and reduced system maintainability.
[0004] like Figure 2 As shown, from a resource optimization perspective, without using generate blocks and location registers, assuming a single adjustable frequency signal output module requires M regularization statements and K configurable feature variables (such as high pulse width, low pulse width, frequency, etc.), then N outputs require a total of N×M regularization statements and N×K register configurations. This linear growth relationship significantly impacts the FPGA's resource utilization efficiency when N is large. Each generated functional module requires independent register configuration, making register resource sharing impossible.
[0005] Furthermore, existing technologies also have shortcomings in the synchronous control of multiple signal outputs. When it is necessary to update the parameters of multiple output signals simultaneously, traditional methods require writing to the registers of each module separately. This not only increases the complexity of the control logic but may also lead to asynchrony problems when updating the signals.
[0006] Therefore, there is an urgent need for a new technical solution that can effectively optimize FPGA resource utilization, simplify control logic, and improve system maintainability and flexibility while maintaining the function of multiple adjustable frequency signal outputs. This invention is an innovative solution proposed based on this need. Summary of the Invention
[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-channel adjustable frequency signal generation system based on FPGA.
[0008] The objective of this invention is achieved through the following technical solution: a multi-channel adjustable frequency signal generation system based on FPGA, comprising a top-level module, an SPI communication module, an FPGA register read / write control module, an adjustable frequency signal generation module, and an adjustable frequency signal output module; the SPI communication module is connected to the FPGA, CPU, and FPGA register read / write control module; the FPGA register read / write control module is connected to the adjustable frequency signal generation module; and the adjustable frequency signal generation module is connected to the adjustable frequency signal output module. The top-level module uses the for statement in the generate block statement to instantiate the required number of adjustable frequency signal generation modules, realizing the parallel output of multiple signals; the system matches the target output channel in the FPGA register read and write control module through the positioning register, so that a set of register resources controls multiple outputs, reducing the use of register resources and repeated declaration steps.
[0009] Preferably, the adjustable frequency signal generation module includes an adjustable variable frequency signal period, a high pulse width of the frequency signal, a low pulse width of the frequency signal, a positioning register, a control enable signal, a synchronization signal, and an input signal that needs to be aligned with the trigger edge. When the adjustable frequency signal generation module receives the input signal, it buffers or performs a time-lapse process on the input signal to capture the trigger edge and determine the data update flag. When the channel matches and the data update flag is valid, the adjustable frequency signal is generated through internal timing logic, and the control signal output is updated according to the positioning register, sending the feature value to the corresponding output channel.
[0010] Preferably, the SPI communication module includes SCLK, MOSI, MISO and CS signal lines, used to realize communication between the CPU and FPGA through the SPI protocol, control the timing of the FPGA register read / write control module, and enable the CPU to remotely configure the FPGA internal registers.
[0011] Preferably, the FPGA register read / write control module uses a case statement to map registers corresponding to different addresses, receives instructions from the SPI communication module, and locates the target output channel based on the positioning register. Address mapping simplifies the register access process and improves the accuracy of multi-output configuration.
[0012] Preferably, the data update judgment process of the adjustable frequency signal generation module includes the following steps: buffering or shifting the input signal, and obtaining the trigger edge by pausing the D flip-flop; when the positioning register matches the output channel and the data update flag is valid, updating the high pulse width, low pulse width and periodic characteristic values.
[0013] The beneficial effects of this invention are: 1) This invention fundamentally changes the traditional design pattern of multi-channel signal output by using the `generate` block statement to instantiate repetitive modules. Compared to the traditional method of instantiating modules one by one, the `generate` block statement can automatically generate multiple modules with the same function through a loop structure, greatly reducing the amount of code to be written. This design method not only significantly shortens development time but also makes the code structure clearer and more concise, greatly improving the maintainability of the design. When it is necessary to modify the module function or increase the number of output channels, only a few parameters need to be modified, avoiding repetitive work and human error.
[0014] 2) By introducing a location register when using the `generate` block statement, multiple outputs can be controlled by changing only the values of one set of registers, reducing resource consumption and redundant declaration steps, thus achieving the goal of controlling multiple outputs using a single set of register resources. Traditional multiplexed designs require configuring an independent register set for each output channel, causing register resources to grow linearly with the number of channels. However, the location register technology of this invention, through address mapping and channel selection mechanisms, allows the same set of registers to serve multiple output channels, significantly reducing the occupation of internal FPGA register resources.
[0015] 3) The adjustable frequency signal generation capability provided by this invention enables the system to adapt to diverse application requirements. Compared with traditional fixed-frequency output systems, this invention allows users to dynamically adjust parameters such as the frequency and duty cycle of the output signal according to the actual application scenario, achieving a "one-machine-multiple-uses" effect. This flexibility is of great value in fields such as test and measurement, industrial control, and communication systems, and can meet the signal requirements under different operating conditions. Especially in scenarios where frequent adjustments to output parameters are required, this invention achieves remote real-time parameter adjustment through seamless integration with the upper-level control system via the SPI communication interface, greatly improving the system's practicality and applicability.
[0016] 4) This invention fully utilizes the high-speed processing capabilities of FPGAs, operating at clock frequencies up to 100MHz, ensuring high precision and low error in the output signals. The parallel processing capabilities of FPGAs enable synchronous output of multiple signals, avoiding timing deviations inherent in traditional serial processing methods. Through precise timing control and triggering mechanisms, the system ensures consistency between output signals, performing excellently in multi-channel applications requiring strict synchronization. Furthermore, the buffering and timing techniques employed in this invention effectively eliminate signal jitter, improving the system's anti-interference capabilities. Attached Figure Description
[0017] Figure 1 This is a system principle block diagram of the present invention; Figure 2 This is a schematic diagram illustrating the design optimization process of the present invention compared to existing technologies; Figure 3 A flowchart for inputting instructions. Detailed Implementation
[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] See Figures 1-3 The present invention provides a technical solution: a multi-channel adjustable frequency signal generation system based on FPGA, comprising a top-level module, an SPI communication module, an FPGA register read / write control module, an adjustable frequency signal generation module, and an adjustable frequency signal output module; the SPI communication module is connected to the FPGA, CPU, and FPGA register read / write control module, the FPGA register read / write control module is connected to the adjustable frequency signal generation module, and the adjustable frequency signal generation module is connected to the adjustable frequency signal output module; The top-level module uses the for statement in the generate block statement to instantiate the required number of adjustable frequency signal generation modules, realizing the parallel output of multiple signals; the system matches the target output channel in the FPGA register read and write control module through the positioning register, so that a set of register resources controls multiple outputs, reducing the use of register resources and repeated declaration steps.
[0020] In this embodiment, devices with multiple adjustable outputs in real-world applications often involve numerous repetitive steps in their design. For instance, when using an FPGA to output multiple signals with the same function, the same module is repeatedly instantiated, leading to the declaration of multiple variables with different functions and the need to build multiple registers for communication configuration at higher layers (such as SPI). This consumes significant resources to handle repetitive steps. This problem can be optimized by using the `generate` block statement in the FPGA to generate repetitive modules. Furthermore, in FPGA-based designs, by introducing a register to locate the specific number of output channels when using the `generate` block statement, multiple channel output configurations can be performed using only the register resources of a single module.
[0021] Following the above optimized routine, assuming the output of N adjustable frequency signals is required, a single module requires M instantiation statements, and there are K characteristic variables that need to be configured (such as high pulse width, low pulse width, frequency, etc.). The number of registers and statements after introducing the generate block and location registers is as follows: Figure 2 As shown, introducing generate blocks and positioning registers in FPGAs for multi-channel adjustable frequency signal output can save register resources, optimize control flow, improve code flexibility, and reduce repetitive steps.
[0022] This invention is based on FPGA and requires upper-level control (such as CPU controlling FPGA internal registers via SPI) to control the output signal. The entire design module consists of an adjustable frequency signal generation module, an FPGA register read / write control module, and an SPI communication module. A top-level module is then constructed for signal connection. In the top-level module, the generate block statement is used to instantiate the required number of frequency signal output modules. At the same time, when instantiating the generate block statement, a for statement is used to instantiate multiple repeatable adjustable frequency generation modules, and the declared variables are connected in the top-level module.
[0023] In some embodiments, the adjustable frequency signal generation module includes an adjustable variable frequency signal period, a high pulse width of the frequency signal, a low pulse width of the frequency signal, a positioning register, a control enable signal, a synchronization signal, and an input signal that needs to be aligned with the trigger edge. When the adjustable frequency signal generation module receives the input signal, it buffers or performs a time-lapse process on the input signal to capture the trigger edge and determine the data update flag. When the channel matches and the data update flag is valid, the adjustable frequency signal is generated through internal timing logic, and the control signal output is updated according to the positioning register, sending the feature value to the corresponding output channel.
[0024] In this embodiment, the adjustable frequency signal generation module contains controllable variables such as frequency signal period, high pulse width, low pulse width, positioning register, control enable signal, synchronization signal, and input signal that needs to be aligned with the trigger edge. When called, the corresponding value of the frequency signal to be generated is written, thereby generating the required frequency signal. It can be changed according to actual needs, and the control function can also be turned off by controlling the control enable signal.
[0025] In some embodiments, the SPI communication module includes SCLK, MOSI, MISO and CS signal lines, used to realize communication between the CPU and the FPGA through the SPI protocol, control the timing of the FPGA register read / write control module, and enable the CPU to remotely configure the FPGA internal registers.
[0026] In some embodiments, the FPGA register read / write control module uses a case statement to map registers corresponding to different addresses, receives instructions from the SPI communication module, and locates the target output channel based on the positioning register. Address mapping simplifies the register access process and improves the accuracy of multi-output configuration.
[0027] In some embodiments, the data update judgment process of the adjustable frequency signal generation module includes the following steps: buffering or shifting the input signal, obtaining the trigger edge by pausing the D flip-flop; when the positioning register matches the output channel and the data update flag is valid, updating the high pulse width, low pulse width and periodic characteristic values.
[0028] In this embodiment, the characteristic values corresponding to different frequency signal outputs are not necessarily the same. Different output frequency signals need to be generated through a positioning register and an update control register. The frequency signal generation module consists of multiple parallel timing logics, containing multiple flag bits and trigger judgments. The frequency signal generation process is as follows: 1. Buffer or shift register some input signals (such as trigger signals, data update flags, etc.), and use D flip-flops to set a timer, so as to facilitate the capture of the rising edge of the trigger signal (trigger edge) and provide some functions (data update judgment) flags.
[0029] 2. When the characteristic corresponding to the channel needs to be generated, the internal register will match the number of channels of the generation module with the number of channels to be controlled by the upper layer. When the channel is determined and the data update flag is valid (update data includes high pulse width, low pulse width, period, etc.), the value corresponding to the channel will be sent to the corresponding channel to avoid control channel confusion, thereby achieving the effect of controlling multiple outputs using only one set of register resources.
[0030] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A multi-channel adjustable frequency signal generation system based on FPGA, characterized in that: It includes a top-level module, an SPI communication module, an FPGA register read / write control module, an adjustable frequency signal generation module, and an adjustable frequency signal output module; the SPI communication module is connected to the FPGA, CPU, and FPGA register read / write control module; the FPGA register read / write control module is connected to the adjustable frequency signal generation module; and the adjustable frequency signal generation module is connected to the adjustable frequency signal output module. The top-level module uses the for statement in the generate block statement to instantiate the required number of adjustable frequency signal generation modules, realizing the parallel output of multiple signals; the system matches the target output channel in the FPGA register read and write control module through the positioning register, so that a set of register resources controls multiple outputs, reducing the use of register resources and repeated declaration steps.
2. The FPGA-based multi-channel adjustable frequency signal generation system according to claim 1, characterized in that: The adjustable frequency signal generation module includes an adjustable variable frequency signal period, a high pulse width of the frequency signal, a low pulse width of the frequency signal, a positioning register, a control enable signal, a synchronization signal, and an input signal that needs to be aligned with the trigger edge. When the adjustable frequency signal generation module receives the input signal, it buffers or performs a time-lapse process on the input signal to capture the trigger edge and determine the data update flag. When the channel matches and the data update flag is valid, the adjustable frequency signal is generated through internal timing logic, and the control signal output is updated according to the positioning register, sending the feature value to the corresponding output channel.
3. The FPGA-based multi-channel adjustable frequency signal generation system according to claim 1, characterized in that: The SPI communication module includes SCLK, MOSI, MISO and CS signal lines, which are used to realize communication between the CPU and FPGA through the SPI protocol, control the timing of the FPGA register read and write control module, and enable the CPU to remotely configure the FPGA internal registers.
4. The FPGA-based multi-channel adjustable frequency signal generation system according to claim 1, characterized in that: The FPGA register read / write control module uses a case statement to map registers corresponding to different addresses, receives instructions from the SPI communication module, and locates the target output channel based on the positioning register. Address mapping simplifies the register access process and improves the accuracy of multi-output configuration.
5. The FPGA-based multi-channel adjustable frequency signal generation system according to claim 2, characterized in that: The data update judgment process of the adjustable frequency signal generation module includes the following steps: buffering or shifting the input signal, and obtaining the trigger edge by pausing the D flip-flop; when the positioning register matches the output channel and the data update flag is valid, updating the high pulse width, low pulse width and periodic characteristic values.