Improvements in or relating to quantum computing

Abstract

1. A surface ion trap comprising a plurality of electrodes and DACs, each electrode controlled by a DAC, a first set of DACs controlling electrodes configured to trap ions in a first region and a second set of DACs controlling electrodes configured to trap ions in a second region, the first set of DACs configured to operate with low noise and low bandwidth and the second set of DACs configured to operate with high bandwidth and high noise.

Description

Technical Field

[0001] The present invention relates to improvements in or related to quantum computing, and more particularly to an improved digital / analog converter (DAC) for an optimized surface ion trap.

Background Art

[0002] Generally, unlike so-called "classical computing," quantum computing relies on the quantum mechanical properties of particles or matter to generate or modify data. The data may be represented by qubits or "qubits," which are two-state quantum mechanical systems. Unlike classical computing, qubits may be in a superposition of quantum states. Another feature of quantum computing is the entanglement between qubits where the state of one particle or atom is affected by another particle or atom.

[0003] Quantum mechanical qubits can simultaneously encode information as a combination of zero and one. Such a property enables many complex numerical applications that have traditionally been difficult on classical computers. Examples include artificial intelligence, image processing and recognition, cryptography, or secure communication.

[0004] Within the ion hyperfine electronic state (Zeeman split state), it can be revealed by the use of a magnetic field, and different electronic levels used as different qubit states, and electrons that move between levels using microwave radiation or a laser.

[0005] In an ion trap quantum computer, a surface ion trap is used to control the ions used in quantum computing, and surface electrodes are used to generate an electric field for manipulating and trapping ions floating in free space. The surface electrode potential of the ion trap is successively controlled by a DAC. State-of-the-art quantum computers use many DACs of the same type, for example, 16-bit DACs with an update rate exceeding 1 MHz.

[0006] The performance of a surface ion trap can be considered in terms of meeting the requirements for noise, bandwidth, power, and resolution, and the DAC is selected for use that best meets these requirements across the surface ion trap.

Summary of the Invention

[0007] However, different functions executed by a quantum computer require different requirements. For example, gate operations require a DAC with low noise and low bandwidth, while shuttling operations require a faster DAC that can tolerate more noise.

[0008] Ion traps currently use the same DAC across the ion trap and have characteristics that are sufficient across the entire ion trap. They have sufficient bandwidth in the shuttling region and have low enough noise to enable the execution of gate operations.

[0009] It is difficult to meet the various requirements for executing different functions with a single type of DAC, and in addition to a large portion of the power budget, it requires a large amount of space.

[0010] Therefore, there is a need for an improved surface ion trap that can better meet the requirements of each function executed in a quantum computer while minimizing power consumption and the use of precious space on a silicon chip.

[0011] The present invention has arisen from such a background.

[0012] According to the present invention, there is provided an ion trap including a plurality of electrodes and a DAC, wherein each electrode is controlled by the DAC, a first set of DACs controls electrodes configured to capture ions in a first region, a second set of DACs controls electrodes configured to capture ions in a second region, the first set of DACs is configured to operate with low noise, and the second set of DACs is configured to operate with high bandwidth. By having different types of DACs for different regions, the DACs can be selected to have characteristics suitable for the purposes of the regions in which they are located. The first set of DACs may be a different type of DAC from the second set of DACs.

[0013] The first set of DACs may be configured to operate with low noise and low bandwidth, and the second set of DACs may be configured to operate with high bandwidth, but as a result, have a larger noise profile.

[0014] The low-noise DAC may have less than 10 nV / rtHz, or more specifically less than 5 nV / rtHz. The high-bandwidth DAC may have a bandwidth of one million updates per second (1 MSPS).

[0015] By selecting a DAC for a particular region, a DAC with the most suitable characteristics can be selected. This also helps to minimize space because smaller DACs can be used in regions where minimizing noise is not as important. Larger-footprint DACs can be used in regions where minimizing noise is more important.

[0016] Also, there may be a set of additional electrodes configured to capture ions in the first region, a set of third DACs, and each additional electrode controlled by one of the set of third DACs, where the set of third DACs is configured to operate with high bandwidth and high noise. The additional electrodes may be interleaved with the plurality of electrodes. Thus, the additional electrodes can be used for high-speed applications, and the original first electrodes can be used for low-noise and low-bandwidth applications.

[0017] The set of first DACs may be of the same type as the set of second DACs, and each DAC has two operating modes: a first mode with low noise and low bandwidth, and a second mode with high noise and high bandwidth. Thus, different operating modes can be used for different applications.

[0018] Each DAC has an output and may include a first sub-DAC and a second sub-DAC. The output of the DAC is selected by an output switch connected to one or more of the sub-DACs, a power switch connected to one or more of the sub-DACs, and / or one or more of the analog additions of the sub-DACs.

[0019] The first sub-DAC may include a capacitive architecture, and the second sub-DAC may include a resistive architecture. In particular, the first sub-DAC can have no or minimal resistive elements so as to operate with very low noise. The second sub-DAC can have no or minimal capacitive elements. Thus, the second sub-DAC can operate at high speed and occupy only a small area, but as a result, generate more noise.

[0020] The first sub-DAC and the second sub-DAC can take different formats. The DAC may include a precision code portion for operating in a first mode with low noise and low bandwidth, and a second high-speed code portion for operating in a second mode with high noise and high bandwidth, and the surface ion trap may further include a switch for switching between the precision code portion and the high-speed code portion.

[0021] The first mode may include a feedback loop that avoids drift in low-noise, low-bandwidth applications. The feedback loop may include a proportional-integral-derivative controller configured to control the output to a reference output. The DAC may use selectable compensation and / or variable gain stages.

[0022] The ion trap may be a surface ion trap.

[0023] According to the present invention, an ion trap quantum computer including the above-described ion trap is provided.

[0024] According to the present invention, the DAC can be selected according to the purpose of the region and design requirements (such as installation area size, noise, and speed). There is a balance among noise, bandwidth, power, and installation area size. For example, in a gate region where noise reduction is important, a low-noise DAC can be used. Low-noise DACs often have a larger installation area. Conversely, in a shuttling region, only a small area may be available, and a high-bandwidth DAC can be used. There may be higher noise associated with such DACs, but in the shuttling region, this may be acceptable.

[0025] Here, the present invention will be described more specifically with reference to the accompanying drawings, although only as examples.

Brief Description of the Drawings

[0026]

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[0027] Here, the present invention will be described more specifically with reference to the accompanying drawings, although only as examples.

[0028] The present invention enables adjusting the DAC performance towards specific requirements for the use of surface ion traps in a given area of a quantum computer. Referring to FIG. 1, there is an embodiment showing different DACs used in different areas of a quantum computer according to the present invention. FIG. 1 shows an x-junction device 12 in a trapped ion quantum computer 10. The x-junction device 12 is divided into areas. The areas of the x-junction device 12 can be divided into a crystal operation 14, a junction shuttering 16, a logic area / gate zone 18, and a linear shuttering 20 according to the functions executed in each area. Each area of the x-junction device 12 has different requirements for noise, bandwidth, drift, linearity, resolution, and power consumption.

[0029] The x-junction 12 comprises a plurality of electrodes 22 configured to trap ions in the areas of the x-junction device 12. Each electrode 22 is driven by a DAC to execute the functions of the areas of the x-junction device 12.

[0030] Dividing the x-junction device 12 into areas according to the requirements of that area of the device facilitates the selection of a DAC that can achieve the best performance in each area of the device. An x-shaped junction is shown here, but the junction does not have to be x-shaped and can simply be divided into areas by the functions of the electrodes.

[0031] For example, the logic area 18 of the x-junction device 12 requires a 16-bit DAC with low noise and high resolution, and a low noise level, for example, less than 100 nV / rtHz, preferably less than 10 nV / rtHz, or particularly less than 5 nV / rtHz. The level can be selected to meet the requirements of this area of the x-junction device 12. An exemplary DAC is the AD5791, which has a noise spectral density of 7.5 nV / rtHz, which is 7.5 μV RMS over a 1 MHz bandwidth, and a 20-bit resolution. The AD5791 stabilizes within 1 μs to within 0.02% and has a 1 MSPS update rate.

[0032] For the low-noise region, there can be a total RMS noise of less than 10 μV with a 10 V full-scale deflection over one hour.

[0033] On the other hand, the linear shuttling 20 and the junction shuttling 16 regions of the x-junction device 12 require high bandwidth and low resolution. These regions may preferably have an update rate exceeding one million updates per second. One example is an 8-bit DAC with a 100 MHz bandwidth that can be most appropriately selected to meet the requirements for electrode control in these regions of the device. An example DAC for the linear shuttling region or junction shuttling can be the LTC1668 with a 50 MSPS update rate, 16-bit resolution, and 50 pA / rtHz noise and a 10 ns settling.

[0034] Dividing the x-junction device 12 into regions with a set of DACs configured to operate with specific performance characteristics can reduce the power consumption of the quantum computer while optimizing the use of space on the silicon chip. However, shuttling still occurs in the logic regions, and thus it is desirable to optimize the characteristics.

[0035] Referring to FIG. 2, there is a scheme for combining the effects of two different DACs in the same region. Using the scheme shown in FIG. 2, a further increase in the performance of a surface ion trap that requires dual functions such as shuttling speed and low-noise quantum operation can be achieved. The scheme shown in FIG. 2 can be implemented in the gate zone / logic region 18 of the device, which requires shuttling in the gate zone region and thus requires a high bandwidth for shuttling in addition to low noise and high resolution.

[0036] FIG. 2 shows two DACs 26 and 28 with independent DAC outputs. The selection mechanism 24 can meet the requirements of the task being performed and enable the selection of the DAC that can achieve the best control over the position of the ions.

[0037] The first DAC 26 may have a capacitive architecture and, thus, may be used for applications where low noise is required. In particular, the first DAC has no resistive part and is thus very quiet. The second DAC may have a resistive architecture and, thus, may be used for applications where high bandwidth is required.

[0038] The selection mechanism 24 enables an electric field at the ion position to be generated from either or both of the two independent DAC outputs.

[0039] The selection mechanism 24 can be part of the DAC design itself, such as an output that connects or disconnects the DAC as needed, a power switch that enables or disables the DAC output as needed, an analog addition circuit with appropriately weighted DAC outputs, an e-field addition that divides the electrode region into two separate interleaved regions, or a hybrid DAC, but is not limited thereto.

[0040] As another method or additionally, the selection mechanism 24 may combine one or more of these mechanisms.

[0041] FIG. 3 shows a potential energy plot of a scheme having two independently operable DACs shown in FIG. 2. FIG. 3A shows an embodiment in which the first DAC "DAC" 1 is a high-speed DAC and is set to 0V everywhere. The second DAC "DAC2", which is a low-noise DAC, provides a potential well of the total potential in the gate zone / logic region 18.

[0042] FIG. 3B shows a potential energy plot when shuttling in and out of the gate zone / logic region 18 by adjusting the DAC1 output. The total potential shifts to the right. Since the potential well created by DAC2 does not change, there is no bandwidth requirement imposed on DAC2.

[0043] In the embodiment shown in FIG. 2, it is important that the performance of the DACs does not interfere with each other. When the selection mechanism 24 is an output switch, unused DACs can be temporarily switched off or disconnected from the ions to avoid noise contributions. Alternatively, a power switch can be used to disconnect the power supply of unused DACs. Alternatively, the DAC selection mechanism 24 can be included in the DAC design itself, which can prevent the need to silence inactive DACs separately and independently. The DAC can have internal switches that change the DAC architecture to prevent the contribution of unused DACs.

[0044] In some embodiments, switches are undesirable due to switching noise or charge injection. The DAC can be configured such that the noise output is code-dependent and the idle state during quantum operation is at the lowest noise level. This is typical of DACs where the output noise is dominated by the input reference noise and is thus reduced for codes that generate a smaller fraction of the reference as an output.

[0045] FIG. 4 shows a scheme in which a shuttling control DAC is implemented as a series of high-speed switches to a reference and a gated-zone DAC is implemented as a reference voltage with a static filter. The electrodes are arranged such that the qubit sees the electric field sum of two outputs. By shorting the electrodes to GND for the shuttling DAC to output 0 V, noise on the potential well during quantum operation is minimized.

[0046] FIG. 5 shows a surface view of a surface ion trap having several pairs of axial electrodes.

[0047] FIG. 6 shows a surface view of a surface ion trap having a single axial position electrode replaced by interleaved electrode pairs. Alternatively, any other arbitrary electrode shape that achieves the desired effect of e-field addition with the ions can be used.

[0048] FIG. 7 shows a scheme of a hybrid DAC with a custom architecture where the selection mechanism is included in the DAC design itself. FIG. 7 shows examples where locations require an accurate or high-speed DAC at various times. A single hybrid DAC architecture is created by combining precision codes and high-speed codes.

[0049] FIG. 8 shows another scheme of a hybrid DAC architecture for locations that require high speed or low drift at various times. This scheme includes a proportional-integral-derivative (PID) controller and a low-speed feedback loop. The low-speed feedback loop checks the level returning to the reference input and facilitates adjustment.

[0050] If a low-noise bandwidth / high-speed device is required at different times, the bandwidth can be dynamically adjusted within the DAC output buffer.

[0051] FIG. 9 shows an additional scheme of a hybrid DAC architecture using selectable compensation at the output stage. FIG. 10 shows a method of using a variable gain stage within a feedback loop (using the open-loop gain of the amplifier). This is also possible using a switchable filter.

[0052] Various further aspects and embodiments of the present invention will be apparent to those skilled in the art in view of the present disclosure.

[0053] As used herein, "and / or" should be taken as a specific disclosure of each of two specific features or components, with or without the other. For example, "A and / or B" should be taken as a specific disclosure of each of (i) A, (ii) B, and (iii) A and B, as if each were individually described herein.

[0054] Unless the context otherwise indicates, the descriptions and definitions of the above features are not limited to any specific aspect or embodiment of the present invention and apply equally to all aspects and embodiments described.

[0055] Those skilled in the art will further understand that the present invention has been described by way of example with reference to several embodiments. Without being limited to the disclosed embodiments, alternative embodiments may be constructed without departing from the scope of the present invention as defined in the appended claims.

Claims

1. An ion trap comprising a plurality of electrodes and a DAC, each electrode being controlled by the DAC, a first set of DACs controlling the electrodes configured to capture ions in a first region, a second set of DACs controlling the electrodes configured to capture ions in a second region, the first set of DACs being configured to operate with low noise, and the second set of DACs being configured to operate with high bandwidth.

2. The ion trap according to claim 1, wherein the first set of DACs is configured to operate with low noise and low bandwidth, and the second set of DACs is configured to operate with high bandwidth and high noise.

3. The ion trap according to claim 1 or 2, wherein the first set of DACs is a different type of DAC from the second set of DACs.

4. A further set of additional electrodes configured to also capture ions in the first region, and a third set of DACs, each additional electrode being controlled by one of the third set of DACs, the third set of DACs being configured to operate with high bandwidth and high noise.

5. The ion trap according to claim 4, wherein the additional electrodes are interleaved with at least some of the plurality of electrodes.

6. The ion trap according to claim 1 or 2, wherein the first set of DACs is the same type as the second set of DACs, and each DAC has two operating modes: a first mode with low noise and low bandwidth, and a second mode with high noise and high bandwidth.

7. Each DAC has an output and includes a first sub-DAC and a second sub-DAC, and the output of the DAC is an output switch connected to one or more of the sub-DACs, a power switch connected to one or more of the sub-DACs, selected by one or more of analog addition of the sub-DACs.

8. The ion trap according to claim 7, wherein the first sub-DAC includes a capacitive architecture and the second sub-DAC includes a resistive architecture.

9. The DAC includes a precision code portion for operating in the first mode with low noise and low bandwidth, and a second high-speed code portion for operating in the second mode with high noise and high bandwidth, and the surface ion trap further includes a switch for switching between the precision code portion and the high-speed code portion. The ion trap according to claim 6.

10. The ion trap according to claim 7, wherein the first mode includes a feedback loop.

11. The ion trap according to claim 10, wherein the feedback loop includes a proportional-integral-derivative controller configured to control the output to a reference output.

12. The ion trap according to claim 6, wherein the DAC uses selectable compensation.

13. The ion trap according to claim 10, wherein the feedback loop includes a variable gain stage.

14. The ion trap according to claim 1 or 2, wherein the ion trap is a surface ion trap.

15. An ion trap quantum computer comprising the ion trap according to claim 1 or 2.

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