Indicating device

Abstract

In the present invention, a transistor (9a) is connected to a transistor (9b) via first wiring (17c); the gate electrode of a transistor (9d) is connected to the first wiring (17c) via second wiring (21c); in each sub-pixel, a first scan signal line (PS) of the gate electrode of a transistor (9c), a second scan signal line (NS) of the gate electrode of the transistor (9b), and a second scan signal line (NS) of the gate electrode of the transistor (9a) are disposed so as to extend parallel to each other; a third wiring (16c) is connected to the second wiring (21c); and the first wiring (17c) is provided on the first scan signal line (PS) so as to cover the third wiring (16c).

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] In recent years, as a display device replacing a liquid crystal display device, a self-emitting organic EL display device using an organic electroluminescence (hereinafter also referred to as "EL") element has been attracting attention. In this organic EL display device, a plurality of thin film transistors (hereinafter also referred to as "TFTs") are provided for each sub-pixel which is the minimum unit of an image. Here, as a semiconductor layer constituting the TFT, for example, a semiconductor layer made of polysilicon having high mobility, a semiconductor layer made of an oxide semiconductor such as In-Ga-Zn-O having a small leakage current, etc. are well known.

[0003] For example, Patent Document 1 discloses a display device having a hybrid structure in which a first TFT using a polysilicon semiconductor and a second TFT using an oxide semiconductor are respectively formed on a substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, in an organic EL display device in which six TFTs, namely an initialization transistor, a threshold voltage compensation transistor, a write control transistor, a drive transistor, a power supply control transistor, and a light emission control transistor, are provided for each sub-pixel, it has been proposed to use an oxide semiconductor for the initialization transistor and the threshold voltage compensation transistor, and polysilicon for the write control transistor, the drive transistor, the power supply control transistor, and the light emission control transistor. Here, since the threshold voltage compensation transistor using an oxide semiconductor is an N-channel type, the voltage of the gate electrode (node G) of the drive transistor electrically connected to the threshold voltage compensation transistor is pulled to the negative side by the feed-through that occurs when the threshold voltage compensation transistor is off, and an N-type capacitor formed at the intersection of the wiring connected to the gate electrode of the drive transistor and the scan signal line for transmitting the scan signal to the N-channel type transistor. As a result, in the drive transistor of that sub-pixel, it becomes difficult to obtain the black potential in the off state, resulting in display unevenness. Therefore, a means is taken to raise the voltage of node G by forming a P-type capacitor using the scan signal line for transmitting the scan signal to the P-channel type transistor and electrically connecting the P-type capacitor to the gate electrode of the drive transistor. However, since the P-type capacitor is formed separately into a portion where the scan signal line and the metal layer overlap and a portion where the scan signal line and the wiring layer made of an oxide semiconductor overlap, the capacitance varies due to manufacturing variations (for example, variations in the line width of the metal layer). As a result, since the voltage of node G cannot be stably raised, display unevenness occurs, and there is room for improvement.

[0006] The present invention has been made in view of such a point, and an object thereof is to suppress variations in the capacitance of the P-type capacitor and stably raise the voltage of the gate electrode of the drive transistor.

Means for Solving the Problem

[0007] In order to achieve the above object, a display device according to the present invention includes a base substrate, and a first semiconductor film made of polysilicon, a first inorganic insulating film, a first metal film, a second inorganic insulating film, a second metal film, a second semiconductor film made of an oxide semiconductor, a third inorganic insulating film, a third metal film, a fourth inorganic insulating film, and a fourth metal film are sequentially stacked on the base substrate. In the thin film transistor layer, a first conductor region and a second conductor region are defined so as to be separated from each other, and a first semiconductor layer formed by the first semiconductor film in which a first channel region is defined between the first conductor region and the second conductor region, and a first gate electrode formed by the first metal film so as to overlap the first channel region. A first transistor having a first gate electrode, a second semiconductor layer formed by the second semiconductor film in which a third conductor region and a fourth conductor region are defined so as to be separated from each other and a second channel region is defined between the third conductor region and the fourth conductor region, and a second gate electrode formed by the third metal film so as to overlap the second channel region. A second transistor having a second gate electrode is provided for each sub-pixel constituting the display region. As the first transistor, a write control transistor, a drive transistor, a power supply control transistor, and a light emission control transistor are provided. As the second transistor, an initialization transistor and a threshold voltage compensation transistor are provided. The third conductor region in the initialization transistor and the third conductor region in the threshold voltage compensation transistor are electrically connected via a first wiring formed by the second semiconductor film. The first gate electrode in the drive transistor is electrically connected to the first wiring via a second wiring formed by the fourth metal film. Each sub-pixel is electrically connected to the first gate electrode in the write control transistor, a first scanning signal line formed by the first metal film, and the second gate electrode in the threshold voltage compensation transistor on one side of the first scanning signal line. A second scanning signal line formed by the third metal film is electrically connected, and another second scanning signal line formed by the third metal film is electrically connected to the second gate electrode in the initialization transistor on the other side of the first scanning signal line, and they are provided so as to extend in parallel with each other. The second wiring hasA display device in which a third wiring formed by the second metal film is electrically connected, wherein the first wiring is provided so as to cover the third wiring at least on the first scanning signal line.

Advantages of the Invention

[0008] According to the present invention, it is possible to suppress variations in the capacitance of the P-type capacitor and stably raise the voltage of the gate electrode of the driving transistor.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Modes for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments.

[0011] <<First Embodiment>> Figs. 1 to 7 show a first embodiment of a display device according to the present invention. In each of the following embodiments, an organic EL display device including an organic EL element layer is exemplified as a display device including a light-emitting element layer. Here, Fig. 1 is a block diagram of the overall configuration of the organic EL display device 100 of the present embodiment. Fig. 2 is an equivalent circuit diagram of a pixel circuit of the TFT layer 30a constituting the organic EL display device 100. Fig. 3 is a plan view of the TFT layer 30a. Fig. 4 is a cross-sectional view of the organic EL display device 100. Fig. 5 is a cross-sectional view schematically showing the structure of a stacked film of the TFT layer 30a. Fig. 6 is a cross-sectional view of the TFT layer 30a taken along line VI-VI in Fig. 3. Fig. 7 is a timing chart for explaining the operation of the pixel circuit of the organic EL display device 100. In the cross-sectional views of Figs. 4 and 5, the same hatching as that in the plan view of Fig. 3 is used for the components corresponding to those in the plan view of Fig. 3.

[0012] As shown in Fig. 1, the organic EL display device 100 includes a display area 50 in which a plurality of sub-pixels P are provided in a matrix, and a gate driver 60, an emission driver 70, and a source driver 80 provided in a frame area around the display area 50. Note that, as shown in Fig. 1, a display control circuit 150 electrically connected to the gate driver 60, the emission driver 70, and the source driver 80 is provided outside the organic EL display device 100.

[0013] Further, as shown in Fig. 4, the organic EL display device 100 includes a resin substrate 10 provided as a base substrate, a TFT layer 30a provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30a, and a sealing film 45 provided on the organic EL element layer 40.

[0014] The resin substrate 10 is made of, for example, polyimide resin or the like.

[0015] As shown in FIG. 4, the TFT layer 30a includes a base coat film 11 provided on the resin substrate 10, four P-channel type first transistors 9A provided for each sub-pixel P on the base coat film 11, three N-channel type second transistors 9B, and one capacitor 9h (see FIG. 2), and a planarization film 22 provided on each of the first transistors 9A, the second transistors 9B, and the capacitor 9h. Further, in the TFT layer 30a, as shown in FIG. 5, a base coat film 11, a first semiconductor film 12, a first gate insulating film 13, a first metal film 14, a first interlayer insulating film 15, a second metal film 16, a second semiconductor film 17, a second gate insulating film 18, a third metal film 19, a second interlayer insulating film 20, a fourth metal film 21, and a planarization film 22 are sequentially laminated on the resin substrate 10. Here, the base coat film 11, the first gate insulating film 13 provided as the first inorganic insulating film, the first interlayer insulating film 15 provided as the second inorganic insulating film, the third gate insulating film 18 provided as the third inorganic insulating film, and the second interlayer insulating film 20 provided as the fourth inorganic insulating film are made of, for example, a single-layer film or a laminated film of silicon nitride, silicon oxide, silicon oxynitride, or the like. Note that at least the side of the second semiconductor layer 17a, which will be described later, of the first interlayer insulating film 15 and the third gate insulating film 18 is made of a silicon oxide film. The first semiconductor film 12 is made of polysilicon and is, for example, a film for forming the first semiconductor layer 12a or the like, which will be described later. The first metal film 14 is, for example, a film for forming the first gate electrode 14a or the like, which will be described later. The second metal film 16 is, for example, a film for forming the third wiring 16c or the like, which will be described later. The second semiconductor film 17 is made of an oxide semiconductor and is, for example, a film for forming the second semiconductor layer 17a, the first wiring 17c, or the like, which will be described later, and its film thickness (for example, about 30 nm) is smaller than the film thickness of the second metal film 16 (for example, about 250 nm). The third metal film 19 is, for example, a film for forming the second gate electrode 19a or the like, which will be described later. The fourth metal film 21 is, for example, a film for forming the second wiring 21c or the like, which will be described later.

[0016] In the display area 50 of the TFT layer 30a, as shown in FIG. 1, i first scanning signal lines PS(1) to PS(i), (i + 1) second scanning signal lines NS(0) to NS(i), i emission control lines EM(1) to EM(i), and j data signal lines D(1) to D(j) are provided. Here, i and j are integers of 2 or more, n is an integer of 1 or more and i or less, and m is an integer of 1 or more and j or less. Also, in FIG. 1, the illustration of the first scanning signal lines PS, the second scanning signal lines NS, and the data signal lines D within the display area 50 is omitted. Here, the first scanning signal lines PS(1) to PS(i) are signal lines for transmitting the first scanning signal which is a control signal for P-channel type transistors. Also, the second scanning signal lines NS(0) to NS(i) are signal lines for transmitting the second scanning signal which is a control signal for N-channel type transistors. Also, the emission control lines EM(1) to EM(i) are signal lines for transmitting the emission control signal. Note that the first scanning signal lines PS(1) to PS(i), the second scanning signal lines NS(0) to NS(i), and the emission control lines EM(1) to EM(i) are provided parallel (in parallel) to each other as shown in FIG. 3. Also, the first scanning signal lines PS(1) to PS(i) and the data signal lines D(1) to D(j) are provided so as to be orthogonal to each other as shown in FIG. 3. Also, in the timing chart of FIG. 7 described later, the first scanning signals respectively applied to the first scanning signal lines PS(1) to PS(i) are also given the symbols PS(1) to PS(i), the second scanning signals respectively applied to the second scanning signal lines NS(0) to NS(i) are also given the symbols NS(0) to NS(i), the emission control signals respectively applied to the emission control lines EM(1) to EM(i) are also given the symbols EM(1) to EM(i), and the data signals (data voltages) respectively applied to the data signal lines D(1) to D(j) are also given the symbols D(1) to D(j).

[0017] Furthermore, in the display region 50 of the TFT layer 30a, there are provided a power line (hereinafter referred to as "high-level power line") for supplying a high-level power supply voltage ELVDD for driving the organic EL element 35 described later, a power line (hereinafter referred to as "low-level power line") for supplying a low-level power supply voltage ELVSS for driving the organic EL element 35, and a power line (hereinafter referred to as "initialization power line") for supplying an initialization voltage Vini. In this embodiment, as necessary, the high-level power line is also labeled with the symbol ELVDD, the low-level power line is also labeled with the symbol ELVSS, and the initialization power line is also labeled with the symbol Vini. Also, the high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from a power supply circuit (not shown).

[0018] As shown in FIG. 4, the first transistor 9A includes a first semiconductor layer 12a provided on the base coat film 11 and a first gate electrode 14a provided on the first semiconductor layer 12a via a first gate insulating film 13.

[0019] The first semiconductor layer 12a is formed of a first semiconductor film 12 made of polysilicon such as LTPS (low temperature polysilicon), and as shown in FIG. 4, includes a first conductor region 12aa and a second conductor region 12ab defined so as to be spaced apart from each other, and a first channel region 12ac defined between the first conductor region 12aa and the second conductor region 12ab.

[0020] The first gate electrode 14a is formed in the first metal film 14, and as shown in FIG. 4, is provided so as to overlap the first channel region 12ac of the first semiconductor layer 12a, and is configured to control the conduction between the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a.

[0021] Note that, as necessary, the first transistor 9A is electrically connected to the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a through two contact holes formed in the stacked film of the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 18, and the second interlayer insulating film 20, and the first terminal electrode and the second terminal electrode formed on the second interlayer insulating film 20 are provided.

[0022] As shown in FIG. 4, the second transistor 9B includes a second semiconductor layer 17a provided on the first interlayer insulating film 15 and a second gate electrode 19a provided on the second semiconductor layer 17a with the second gate insulating film 18 interposed therebetween.

[0023] The second semiconductor layer 17a is formed of, for example, an oxide semiconductor such as an In-Ga-Zn-O system, and as shown in FIG. 4, includes a third conductor region 17aa and a fourth conductor region 17ab defined to be spaced apart from each other, and a second channel region 17ac defined between the third conductor region 17aa and the fourth conductor region 17ab. Here, the In-Ga-Zn-O system semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratios (composition ratios) of In, Ga, and Zn are not particularly limited. Further, the In-Ga-Zn-O system semiconductor may be amorphous or crystalline. Note that, as the crystalline In-Ga-Zn-O system semiconductor, a crystalline In-Ga-Zn-O system semiconductor in which the c-axis is oriented substantially perpendicular to the layer plane is preferable. Further, instead of the In-Ga-Zn-O system semiconductor, other oxide semiconductors may be included. Examples of other oxide semiconductors may include an In-Sn-Zn-O system semiconductor (for example, In2O3-SnO2-ZnO; InSnZnO). Here, the In-Sn-Zn-O system semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Further, examples of other oxide semiconductors include an In-Al-Zn-O system semiconductor, an In-Al-Sn-Zn-O system semiconductor, a Zn-O system semiconductor, an In-Zn-O system semiconductor, a Zn-Ti-O system semiconductor, a Cd-Ge-O system semiconductor, a Cd-Pb-O system semiconductor, CdO (cadmium oxide), a Mg-Zn-O system semiconductor, an In-Ga-Sn-O system semiconductor, an In-Ga-O system semiconductor, a Zr-In-Zn-O system semiconductor, a Hf-In-Zn-O system semiconductor, an Al-Ga-Zn-O system semiconductor, a Ga-Zn-O system semiconductor, an In-Ga-Zn-Sn-O system semiconductor, InGaO3(ZnO)5, magnesium zinc oxide (Mg x Zn 1-x O), cadmium zinc oxide (Cd x Zn 1-x O), etc. may be included. Note that, as the Zn-O system semiconductor, an amorphous (amorphous) state of ZnO to which one or more impurity elements among group 1 elements, group 13 elements, group 14 elements, group 15 elements, group 17 elements, etc. are added, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.

[0024] The second gate electrode 19a is formed of the third metal film 19, and as shown in FIG. 4, is provided so as to overlap with the second channel region 17ac of the second semiconductor layer 17a, and is configured to control conduction between the third conductor region 17aa and the fourth conductor region 17ab of the second semiconductor layer 17a.

[0025] Note that, in the second transistor 9B, if necessary, two contact holes formed in the stacked film of the second gate insulating film 18 and the second interlayer insulating film 20, and the second semiconductor layer 17a are electrically connected to the third conductor region 17aa and the fourth conductor region 17ab thereof via a conductive layer formed of the second metal film 16 so as to be in contact with the third conductor region 17aa and the fourth conductor region 17ab, respectively, and a third terminal electrode and a fourth terminal electrode formed on the second interlayer insulating film 20 are provided.

[0026] In this embodiment, as four P-channel type first transistors 9A formed of polysilicon, a write control transistor 9c, a drive transistor 9d, a power supply control transistor 9e, and a light emission control transistor 9f, which will be described later, are provided, and as three N-channel type second transistors 9B formed of an oxide semiconductor and having a second semiconductor layer 17a, an initialization transistor 9a, a threshold voltage compensation transistor 9b, and an anode discharge transistor 9g, which will be described later, are provided (see FIG. 2). In the equivalent circuit diagram of FIG. 2, the first terminal electrodes (first conductor regions 12aa) and the second terminal electrodes (second conductor regions 12ab) of the respective transistors 9c, 9d, 9e, 9f are indicated by circled numbers 1 and 2, the third terminal electrodes (third conductor regions 17aa) and the fourth terminal electrodes (fourth conductor regions 17ab) of the respective transistors 9a, 9b, 9g are indicated by circled numbers 3 and 4, and the first capacitance electrode and the second capacitance electrode of a capacitor 9h, which will be described later, are indicated by circled numbers 5 and 6.

[0027] As shown in FIGS. 2 and 3, the initialization transistor 9a is electrically connected to the second scanning signal line NS(n - 1) because its second gate electrode 19a is a part of the second scanning signal line NS(n - 1) in the (n - 1)-th row. Its third terminal electrode (third conductor region 17aa) is connected to the third terminal electrode (third conductor region 17aa) of the threshold voltage compensation transistor 9b, the first gate electrode 14a of the driving transistor 9d, and the second capacitive electrode of the capacitor 9h. Its fourth terminal electrode (fourth conductor region 17ab) is electrically connected to the initialization power supply line Vini. Here, as shown in FIG. 3, the third conductor region 17aa of the initialization transistor 9a and the third conductor region 17aa of the threshold voltage compensation transistor 9b are electrically connected via the first wiring 17c formed by the second semiconductor film 17. Note that the first wiring 17c is composed of the third conductor regions 17aa of the initialization transistor 9a and the threshold voltage compensation transistor 9b. Also, the fourth conductor region 17ab of the initialization transistor 9a is electrically connected to the initialization power supply line Vini formed by the first metal film 14 via a conductive layer formed by the second metal film 16 laminated thereunder and a contact hole formed in the first interlayer insulating film 15 under the conductive layer. Further, the second scanning signal line NS that functions as the second gate electrode 19a of the initialization transistor 9a is formed by the third metal film 19.

[0028] As shown in FIG. 3, the first wiring 17c forms a P-type capacitor Cgp in a portion overlapping with the first scanning signal line PS(n). Here, as shown in FIG. 6, the P-type capacitor Cgp includes a first scanning signal line PS composed of a wiring layer 14b formed by the first metal film 14, a first interlayer insulating film 15 provided to cover the first scanning signal line PS, a third wiring 16c provided by the second metal film 16 on the first interlayer insulating film 15, and a first wiring 17c provided directly on the third wiring 16c so as to cover the third wiring 16c at least on the first scanning signal line PS. Also, the P-type capacitor Cgp is configured to raise the voltage of the first gate electrode 14a of the driving transistor 9d, that is, the voltage of the node G (NG in FIG. 2), when the first scanning signal line PS(n) changes from a low level to a high level.

[0029] As shown in FIGS. 2 and 3, the threshold voltage compensation transistor 9b is electrically connected to the second scanning signal line NS(n) because its second gate electrode 19a is a part of the second scanning signal line NS(n) in the n-th row. Its third terminal electrode (third conductor region 17aa) is electrically connected to the third terminal electrode of the initialization transistor 9a, the first gate electrode 14a of the drive transistor 9d, and the second capacitive electrode of the capacitor 9h. Its fourth terminal electrode (fourth conductor region 17ab) is electrically connected to the second terminal electrode (second conductor region 12ab) of the drive transistor 9d and the first terminal electrode (first conductor region 12aa) of the light emission control transistor 9f. Here, the fourth conductor region 17ab of the threshold voltage compensation transistor 9b is electrically connected to the second conductor region 12ab of the drive transistor 9d through a conductive layer formed by the second metal film 16 laminated thereunder and a contact hole formed in a laminated film of the first interlayer insulating film 15 and the first gate insulating film 13 under the conductive layer.

[0030] As shown in FIGS. 2 and 3, the write control transistor 9c is electrically connected to the first scanning signal line PS(n) because its first gate electrode 14a is a part of the first scanning signal line PS(n) in the n-th row. Its first terminal electrode (first conductor region 12aa) is electrically connected to the data signal line D(m) in the m-th column. Its second terminal electrode (second conductor region 12ab) is electrically connected to the first terminal electrode (first conductor region 12aa) of the drive transistor 9d and the second terminal electrode (second conductor region 12ab) of the power supply control transistor 9e. Here, the first scanning signal line PS that functions as the first gate electrode 14a of the write control transistor 9c is formed by the first metal film 14.

[0031] As shown in FIGS. 2 and 3, for the drive transistor 9d, its first gate electrode 14a is electrically connected to the third terminal electrode (third conductor region 17aa) of the initialization transistor 9a, the third terminal electrode (third conductor region 17aa) of the threshold voltage compensation transistor 9b, and the second capacitive electrode of the capacitor 9h. Its first terminal electrode (first conductor region 12aa) is electrically connected to the second terminal electrode (second conductor region 12ab) of the write control transistor 9c and the second terminal electrode (second conductor region 12ab) of the power supply control transistor 9e. Its second terminal electrode (second conductor region 12ab) is electrically connected to the fourth terminal electrode (fourth conductor region 17ab) of the threshold voltage compensation transistor 9b and the first terminal electrode (first conductor region 12aa) of the light emission control transistor 9f. Note that a high-level power supply voltage ELVDD is input to the first terminal electrode (first conductor region 12aa) of the drive transistor 9d during the period when the organic EL element 35 emits light, and a data signal D(m) is input during the period when writing to the capacitor 9h is performed. Here, the first gate electrode 14a of the drive transistor 9d and each of the third conductor regions 17aa of the initialization transistor 9a and the threshold voltage compensation transistor 9b, that is, the first wiring 17c, are electrically connected via a second wiring 21c formed of a fourth metal film 21. Note that the first conductor region 12aa of the drive transistor 9d is provided integrally with the second conductor region 12ab of the write control transistor 9c and the second conductor region 12ab of the power supply control transistor 9e, and thus is electrically connected to the second conductor region 12ab of the write control transistor 9c and the second conductor region 12ab of the power supply control transistor 9e. Also, the second conductor region 12ab of the drive transistor 9d is provided integrally with the first conductor region 12aa of the light emission control transistor 9f, and thus is electrically connected to the first conductor region 12aa of the light emission control transistor 9f.

[0032] As shown in FIG. 3, the second wiring 21c is provided so as to intersect (orthogonally) with the second scanning signal line NS(n) disposed on one side (the lower side in the figure) of the first scanning signal line PS(n), and forms an N-type capacitor Cgn in a portion overlapping with the second scanning signal line NS(n). Here, the N-type capacitor Cgn includes the second scanning signal line NS formed by the third metal film 19, the second interlayer insulating film 20 provided so as to cover the second scanning signal line NS, and the second wiring 21c provided on the second interlayer insulating film 20. Further, the N-type capacitor Cgn is configured to lower the voltage of the first gate electrode 14a of the driving transistor 9d, that is, the voltage of the node G(NG), when the second scanning signal line NS(n) changes from a high level to a low level. Note that the capacitance of the N-type capacitor Cgn is designed to be smaller than the capacitance of the P-type capacitor Cgp. Further, as shown in FIG. 6, a contact hole H formed in a stacked film of the second gate insulating film 18 and the second interlayer insulating film 20 and the third wiring 16c are electrically connected to the second wiring 21c via the first wiring 17c. Then, as shown in FIG. 6, the contact hole H may be disposed on the first scanning signal line PS and provided so as to penetrate the first wiring 17c. That is, as shown in FIGS. 3 and 6, the contact hole H is provided in a region overlapping the third wiring 16c in plan view and in a region where the first wiring 17c and the third wiring 16c overlap in plan view, and may be provided so as to penetrate the first wiring 17c.

[0033] As shown in FIGS. 2 and 3, since the first gate electrode 14a of the power supply control transistor 9e is a part of the light emission control line EM(n) in the n-th row, the power supply control transistor 9e is electrically connected to the light emission control line EM(n). The first terminal electrode (the first conductor region 12aa) thereof is electrically connected to the high-level power supply line ELVDD and the first capacitive electrode of the capacitor 9h, and the second terminal electrode (the second conductor region 12ab) thereof is electrically connected to the second terminal electrode (the second conductor region 12ab) of the write control transistor 9c and the first terminal electrode (the first conductor region 12aa) of the driving transistor 9d. Note that as shown in FIG. 3, the light emission control line EM includes a wiring layer formed by the first metal film 14 and a wiring layer formed by the third metal film 19.

[0034] As shown in FIGS. 2 and 3, the emission control transistor 9f is electrically connected to the emission control line EM(n) because its first gate electrode 14a is a part of the emission control line EM(n) in the n-th row. Its first terminal electrode (first conductor region 12aa) is electrically connected to the fourth terminal electrode (fourth conductor region 17ab) of the threshold voltage compensation transistor 9b and the second terminal electrode (second conductor region 12ab) of the drive transistor 9d. Its second terminal electrode (second conductor region 12ab) is electrically connected to the fourth terminal electrode (fourth conductor region 17ab) of the anode discharge transistor 9g and the first electrode 31 (to be described later) of the organic EL element 35. Here, the second conductor region 12ab of the emission control transistor 9f is laminated under the fourth conductor region 17ab of the anode discharge transistor 9g and is electrically connected to the fourth conductor region 17ab of the anode discharge transistor 9g through a conductive layer formed by the second metal film 16 and a contact hole formed in a laminated film of the first interlayer insulating film 15 and the first gate insulating film 13 under the conductive layer.

[0035] As shown in FIGS. 2 and 3, the anode discharge transistor 9g has its second gate electrode 19a being a protruding portion to the side of the light emission control line EM(n) in the n-th row, and thus is electrically connected to the light emission control line EM(n). Its third terminal electrode (third conductor region 17aa) is electrically connected to the initialization power supply line Vini, and its fourth terminal electrode (fourth conductor region 17ab) is electrically connected to the second terminal electrode (second conductor region 12ab) of the light emission control transistor 9f and the first electrode 31 of the organic EL element 35. Here, the third conductor region 17aa of the anode discharge transistor 9g is electrically connected to the initialization power supply line Vini through a conductive layer formed by the second metal film 16 laminated thereunder and a contact hole formed in the first interlayer insulating film 15 under the conductive layer. Also, the fourth conductor region 17ab of the anode discharge transistor 9g is electrically connected to the first electrode 31 through a conductive layer formed by the second metal film 16 laminated thereunder, a contact hole formed in a laminated film of the second gate insulating film 18 and the second interlayer insulating film 20, a conductive layer formed by the fourth metal film 21, and a contact hole formed in the planarization film 22.

[0036] The capacitor 9h includes, for example, a first capacitive electrode formed by the second metal film 16, a second capacitive electrode formed by the first metal film 14, and a first interlayer insulating film 15 provided between the first capacitive electrode and the second capacitive electrode. Here, for the capacitor 9h, its first capacitive electrode is electrically connected to the high-level power supply line ELVDD and the first terminal electrode (the first conductor region 12aa) of the power supply control transistor 9e, and its second capacitive electrode is electrically connected to the third terminal electrode (the third conductor region 17aa) of the initialization transistor 9a, the third terminal electrode (the third conductor region 17aa) of the threshold voltage compensation transistor 9b, and the first gate electrode 14a of the drive transistor 9d. Note that the first capacitive electrode of the capacitor 9h is electrically connected to the high-level power supply line ELVDD formed by the fourth metal film through a contact hole formed in the stacked film of the second gate insulating film 18 and the second interlayer insulating film 20. In addition, the second capacitive electrode of the capacitor 9h is electrically connected to the first gate electrode 14a of the drive transistor 9d by being provided integrally with the first gate electrode 14a of the drive transistor 9d. Further, in addition to the first capacitor including the first capacitive electrode formed by the second metal film 16 described above, the second capacitive electrode formed by the first metal film 14, and the first interlayer insulating film 15 provided between the first capacitive electrode and the second capacitive electrode, a second capacitor including the first capacitive electrode formed by the second metal film 16, the third capacitive electrode formed by the third metal film 19, and the second gate insulating film 18 provided between the first capacitive electrode and the third capacitive electrode may be provided.

[0037] The planarization film 22 has a flat surface in the display region 50 and is formed of, for example, an organic resin material such as a polyimide resin or an acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0038] As shown in FIG. 4, the organic EL element layer 40 includes a plurality of organic EL elements 35 provided as a plurality of light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P, and an edge cover 32 provided in a grid pattern in common to all the sub-pixels P so as to cover the peripheral end portions of the first electrode 31, which will be described later, of each organic EL element 35.

[0039] As shown in FIG. 4, each organic EL element 35 includes a first electrode (anode) 31 provided on the planarization film 22 of the TFT layer 30a, an organic EL layer 33 provided on the first electrode 31, and a second electrode (cathode) 34 provided on the organic EL layer 33 in each sub-pixel P.

[0040] The first electrode 31 is electrically connected to the second conductor region of the light-emitting control transistor 9f of each sub-pixel P through a contact hole formed in the planarization film 22. Further, the first electrode 31 has a function of injecting holes (positive holes) into the organic EL layer 33. Also, the first electrode 31 is more preferably formed of a material having a large work function in order to improve the hole injection efficiency into the organic EL layer 33. Here, examples of the material constituting the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), tin (Sn). Further, the material constituting the first electrode 31 may be an alloy such as astatine (At) / astatine oxide (AtO2). Furthermore, the material constituting the first electrode 31 may be a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO). Also, the first electrode 31 may be formed by laminating a plurality of layers made of the above materials. Note that examples of the compound material having a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0041] The organic EL layer 33 includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, which are sequentially provided on the first electrode 31. Here, the hole injection layer is also called an anode buffer layer and has a function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer and improving the hole injection efficiency from the first electrode 31 to the organic EL layer 33. Examples of the material constituting the hole injection layer include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, etc. Further, the hole transport layer has a function of improving the hole transport efficiency from the first electrode 31 to the organic EL layer 33. Examples of the material constituting the hole transport layer include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylene vinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, zinc selenide, etc. Further, the light-emitting layer is a region where holes and electrons are respectively injected from the first electrode 31 and the second electrode 34 and holes and electrons recombine when a voltage is applied by the first electrode 31 and the second electrode 34.Examples of materials constituting the light-emitting layer include metal oxynoid compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, tristyrilbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylene vinylene, polysilane, and the like. Further, the electron transport layer has a function of efficiently moving electrons to the light-emitting layer. Examples of materials constituting the electron transport layer include, as organic compounds, oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, metal oxynoid compounds, and the like. Further, the electron injection layer has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer and improving the efficiency of injecting electrons from the second electrode 34 into the organic EL layer 33. By this function, the driving voltage of the organic EL element 35 can be lowered. Examples of materials constituting the electron injection layer include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), barium fluoride (BaF2), aluminum oxide (Al2O3), strontium oxide (SrO), and the like.

[0042] As shown in FIG. 4, the second electrode 34 is provided in common to all sub-pixels P so as to cover each organic EL layer 33 and the edge cover 32. Further, the second electrode 34 has a function of injecting electrons into the organic EL layer 33. Further, the second electrode 34 is more preferably made of a material having a small work function in order to improve the electron injection efficiency into the organic EL layer 33. Further, as shown in FIG. 2, the second electrode 34 is electrically connected to the low-level power line ELVSS. Here, examples of the material constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), lithium fluoride (LiF), and the like. Further, the second electrode 34 may be formed of an alloy such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), or the like. Further, the second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), or the like. Further, the second electrode 34 may be formed by laminating a plurality of layers made of the above materials. Examples of the material having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), and the like.

[0043] The edge cover 32 is made of, for example, an organic resin material such as a polyimide resin or an acrylic resin, or a polysiloxane-based SOG material.

[0044] As shown in FIG. 4, the sealing film 45 is provided to cover the second electrode 34, and includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 that are sequentially laminated on the second electrode 34, and has a function of protecting the organic EL layer 33 of the organic EL element layer 35 from moisture and oxygen.

[0045] The first inorganic sealing film 41 and the second inorganic sealing film 43 are made of an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, for example.

[0046] The organic sealing film 42 is made of an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin, for example.

[0047] Next, the operation of the organic EL display device 100 having the above configuration will be described.

[0048] <Operation of Peripheral Circuit> As shown in FIG. 1, the display control circuit 150 receives an input image signal DIN and a timing signal group (horizontal synchronization signal, vertical synchronization signal, etc.) TG sent from the outside, and outputs a digital video signal DV, a gate control signal GCTL for controlling the operation of the gate driver 60, an emission driver control signal EMCTL for controlling the operation of the emission driver 70, and a source control signal SCTL for controlling the operation of the source driver 80. Here, the gate control signal GCTL includes a gate start pulse signal, a gate clock signal, etc. Also, the emission driver control signal EMCTL includes an emission start pulse signal, an emission clock signal, etc. Also, the source control signal SCTL includes a source start pulse signal, a source clock signal, a latch strobe signal, etc.

[0049] The gate driver 60 is electrically connected to the first scanning signal lines PS(1) to PS(i) and the second scanning signal lines NS(0) to NS(i). Then, based on the gate control signal GCTL output from the display control circuit 150, the gate driver 60 applies a first scanning signal to the first scanning signal lines PS(1) to PS(i) and a second scanning signal to the second scanning signal lines NS(0) to NS(i).

[0050] The emission driver 70 is electrically connected to the emission control lines EM(1) to EM(i). Then, based on the emission driver control signal EMCTL output from the display control circuit 150, the emission driver 70 applies an emission control signal to the emission control lines EM(1) to EM(i).

[0051] The source driver 80 includes a j-bit shift register (not shown), a sampling circuit, a latch circuit, and j D / A converters, etc. Here, the shift register has j serially connected registers, and based on the source clock signal, it sequentially transfers the pulse of the source start pulse signal supplied to the first-stage register from the input end to the output end. In response to the transfer of the pulse, a sampling pulse is output from each stage of the register. Then, the sampling circuit stores the digital video signal DV based on the sampling pulse. And the latch circuit takes in and holds the digital video signal DV for one line stored in the sampling circuit according to the latch strobe signal. And the D / A converters are provided corresponding to each of the data signal lines D(1) to D(j), convert the digital video signal DV held in the latch circuit into an analog voltage, and simultaneously apply the converted analog voltage as a data signal (data voltage) to all the data signal lines D(1) to D(j).

[0052] As described above, data signals are applied to the data signal lines D(1) to D(j), first scan signals are applied to the first scan signal lines PS(1) to PS(i), second scan signals are applied to the second scan signal lines NS(0) to NS(i), and emission control signals are applied to the emission control lines EM(1) to EM(i), whereby an image based on the input image signal DIN is displayed in the display area 50.

[0053] <Operation of Pixel Circuit in Display Area> Hereinafter, with reference to the timing chart of FIG. 7, the operation of the pixel circuit of the organic EL display device 100 of the present embodiment will be described. Note that the operation of this pixel circuit is an example and is not limited thereto.

[0054] First, before time t01, the first scan signal PS(n) is at a high level, and the second scan signals NS(n - 1), NS(n), and the emission control signal EM(n) are at a low level. At this time, the power supply control transistor 9e and the emission control transistor 9f are in an on state, and the anode discharge transistor 9g is in an off state. Therefore, before time t01, a drive current corresponding to the charging voltage of the capacitor 9h is supplied to the organic EL element 35, and the organic EL element 35 emits light according to the magnitude of the drive current.

[0055] When time t01 arrives, the emission control signal EM(n) changes from a low level to a high level, so that the power supply control transistor 9e and the emission control transistor 9f are turned off. As a result, the supply of the drive current to the organic EL element 35 is cut off, and the organic EL element 35 is turned off. Further, when the emission control signal EM(n) changes from a low level to a high level, the anode discharge transistor 9g is turned on. Thereby, the voltage of the first electrode 31 of the organic EL element 35 is initialized based on the initialization voltage Vini.

[0056] When time t02 arrives, the second scanning signal NS(n - 1) changes from a low level to a high level, causing the initialization transistor 9a to turn on. As a result, the gate voltage of the driving transistor 9d is initialized. That is, the gate voltage of the driving transistor 9d becomes equal to the initialization voltage Vini.

[0057] When time t03 arrives, the second scanning signal NS(n - 1) changes from a high level to a low level, causing the initialization transistor 9a to turn off. Also, at time t03, the second scanning signal NS(n) changes from a low level to a high level. Thereby, the threshold voltage compensation transistor 9b turns on.

[0058] When time t04 arrives, the first scanning signal PS(n) changes from a high level to a low level, causing the write control transistor 9c to turn on. Here, since the threshold voltage compensation transistor 9b is on at time t03, when the write control transistor 9c turns on at time t04, the data signal D(m) is input to the second capacitive electrode of the capacitor 9h through the write control transistor 9c, the driving transistor 9d, and the threshold voltage compensation transistor 9b. Thereby, the capacitor 9h is charged.

[0059] When time t05 arrives, the first scanning signal PS(n) changes from a low level to a high level, causing the write control transistor 9c to turn off.

[0060] When time t06 arrives, the second scanning signal NS(n) changes from a high level to a low level, causing the threshold voltage compensation transistor 9b to turn off.

[0061] When time t07 is reached, the emission control signal EM(n) changes from high level to low level, causing the anode discharge transistor 9g to turn off and the power supply control transistor 9e and the emission control transistor 9f to turn on. As a result, a drive current corresponding to the charging voltage of the capacitor 9h is supplied to the organic EL element 35, and the organic EL element 35 emits light according to the magnitude of the drive current.

[0062] In this way, in the organic EL display device 100, in each sub-pixel P, the organic EL element 35 emits light with a luminance corresponding to the drive current, and image display is performed.

[0063] Here, the behavior of the gate voltage (the voltage of node G(NG)) of the drive transistor 9d in the organic EL display device 100 will be described. In the timing chart of FIG. 7, Ga shows the behavior of the voltage of node G(NG) when no P-type capacitor is added to node G(NG), Gb shows the behavior of the voltage of node G(NG) in the case of this embodiment where a stable P-type capacitor is added to node G(NG), and Gc shows the behavior of the voltage of node G(NG) when an unstable P-type capacitor is added to node G(NG) (when the display unevenness described in the problem to be solved by the above invention occurs).

[0064] Specifically, before time t02, the voltage of node G (Ga, Gb, Gc) is at the black potential.

[0065] When time t02 is reached, as described above, the gate voltage of the drive transistor 9d is initialized, and at Ga, Gb, and Gc, the voltage of node G(NG) becomes equal to the initialization voltage Vini.

[0066] When time t05 arrives, the first scanning signal PS(n) changes from the low level to the high level, causing the voltage of the node G (NG) to rise in Ga, Gb, and Gc. Here, when no P-type capacitor is added (Ga), the voltage of the node G (NG) only rises to a potential lower than the black potential. Also, when a stable P-type capacitor is added (Gb), the voltage of the node G (NG) rises to a potential higher than the black potential. Further, when an unstable P-type capacitor is added (Gc), the voltage of the node G (NG) rises to about the same level as the black potential.

[0067] When time t06 arrives, the second scanning signal NS(n) changes from the high level to the low level, causing the voltage of the node G (NG) to drop in Ga, Gb, and Gc. Here, when no P-type capacitor is added (Ga), the voltage of the node G (NG), which is lower than the black potential, further decreases. Also, when a stable P-type capacitor is added (Gb), even though the voltage of the node G (NG) drops, since it was previously raised, the voltage of the node G (NG) becomes the black potential. Further, when an unstable P-type capacitor is added (Gc), the voltage of the node G (NG) becomes lower than the black potential.

[0068] As described above, in the organic EL display device 100 of the present embodiment, by adding a P-type capacitor with a stable capacitance, the voltage of the gate electrode of the driving transistor 9d can be stably raised to secure the black potential.

[0069] Next, a method for manufacturing the organic EL display device 100 of the present embodiment will be described. The manufacturing method of the organic EL display device 100 includes a TFT layer formation step, an organic EL element layer formation step, and a sealing film formation step.

[0070] <TFT layer formation step> First, for example, a base coat film 11 is formed by depositing a silicon oxide film (with a thickness of about 100 nm) on a resin substrate 10 formed on a glass substrate by, for example, the plasma CVD (Chemical Vapor Deposition) method.

[0071] Subsequently, on the surface of the substrate on which the base coat film 11 is formed, for example, by plasma CVD method, an amorphous silicon film (about 50 nm thick) is formed, and the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film 12 made of polysilicon. After that, the first semiconductor film 12 is patterned to form a first semiconductor layer 12a and the like.

[0072] Thereafter, on the surface of the substrate on which the first semiconductor layer 12a and the like are formed, for example, by plasma CVD method, a silicon oxide film (about 100 nm thick) is formed to form a first gate insulating film 13.

[0073] Furthermore, on the surface of the substrate on which the first gate insulating film 13 is formed, for example, by sputtering method, a molybdenum film (about 250 nm thick) or the like is formed to form a first metal film 14. After that, the first metal film 14 is patterned to form a first gate electrode 14a and the like. Here, the variation in the line width in the manufacture of the first scanning signal line PS formed by patterning the first metal film 14 is larger than the variation in the line width of the first wiring 17c formed by patterning the second semiconductor film 17 later.

[0074] Subsequently, using the first gate electrode 14a as a mask, impurity ions are doped to conduct a part of the first semiconductor layer 12a, and a first conductor region 12aa, a second conductor region 12ab, and a first channel region 12ac are formed in the first semiconductor layer 12a.

[0075] Thereafter, on the surface of the substrate on which a part of the first semiconductor layer 12a is conducted, for example, by plasma CVD method, a silicon nitride film (about 100 nm thick) is formed to form a first interlayer insulating film 15.

[0076] Furthermore, on the surface of the substrate on which the first interlayer insulating film 15 is formed, for example, by sputtering, a molybdenum film (with a thickness of about 250 nm) or the like is formed to form the second metal film 16. After that, the second metal film 16 is patterned to form the third wiring 16c and the like. Here, the variation in the line width in the manufacture of the third wiring 16c formed by patterning the second metal film 16 is larger than the variation in the line width of the first wiring 17c formed by patterning the second semiconductor film 17 later.

[0077] Subsequently, on the surface of the substrate on which the third wiring 16c and the like are formed, for example, by sputtering, InGaZnO4 (with a thickness of about 30 nm) or the like is formed to form the second semiconductor film 17 made of an oxide semiconductor. After that, the second semiconductor film 17 is patterned to form the second semiconductor layer 17a and the like.

[0078] Thereafter, on the surface of the substrate on which the second semiconductor layer 17a and the like are formed, for example, by plasma CVD, a silicon oxide film (with a thickness of about 100 nm) is formed to form the second gate insulating film 18.

[0079] Furthermore, on the surface of the substrate on which the second gate insulating film 18 is formed, for example, by sputtering, a molybdenum film (with a thickness of about 250 nm) or the like is formed to form the third metal film 19. After that, the third metal film 19 is patterned to form the second gate electrode 19a and the like.

[0080] Subsequently, on the surface of the substrate on which the second gate electrode 19a and the like are formed, for example, by plasma CVD, a silicon oxide film (with a thickness of about 300 nm) and a silicon nitride film (with a thickness of about 150 nm) are sequentially formed to form the second interlayer insulating film 20. Note that, by heat treatment after forming the second interlayer insulating film 20, a part of the second semiconductor layer 17a is made conductive, and a third conductor region 17aa (first wiring 17c), a fourth conductor region 17ab, and a second channel region 17ac are formed in the second semiconductor layer 17a.

[0081] Subsequently, on the substrate surface on which the second interlayer insulating film 20 is formed, contact holes are formed by appropriately patterning the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 18, and the second interlayer insulating film 20.

[0082] Furthermore, on the substrate surface on which the contact holes are formed, for example, by sputtering, a titanium film (about 50 nm thick), an aluminum film (about 400 nm thick), a titanium film (about 50 nm thick), etc. are sequentially formed to form the fourth metal film 21. After that, the fourth metal film 21 is patterned to form the second wiring 21c, etc.

[0083] Finally, on the substrate surface on which the second wiring 21c, etc. are formed, for example, by spin coating or slit coating, a polyimide-based photosensitive resin film (about 2 μm thick) is applied. Then, pre-baking, exposure, development, and post-baking are performed on the applied film to form the planarization film 22.

[0084] In the above manner, the TFT layer 30a can be formed.

[0085] <Organic EL element layer formation process> On the planarization film 22 of the TFT layer 30a formed in the above TFT layer formation process, a first electrode 31, an edge cover 32, an organic EL layer 33, and a second electrode 34 are formed using a well-known method to form an organic EL element layer 40.

[0086] <Sealing film formation process> First, on the substrate surface on which the organic EL element layer 40 formed in the above organic EL element layer formation process is formed, using a mask, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD to form the first inorganic sealing film 41.

[0087] Subsequently, on the substrate surface on which the first inorganic sealing film 41 is formed, for example, an organic resin material such as an acrylic resin is formed by inkjet method to form the organic sealing film 42.

[0088] Thereafter, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD on the surface of the substrate on which the organic sealing film 42 is formed using a mask, and the second inorganic sealing film 43 is formed to form the sealing film 45.

[0089] Finally, after attaching a protective sheet (not shown) to the surface of the substrate on which the sealing film 45 is formed, laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the lower surface of the resin substrate 10, and a protective sheet (not shown) is attached to the lower surface of the resin substrate 10 from which the glass substrate has been peeled.

[0090] In the above manner, the organic EL display device 100 of the present embodiment can be manufactured.

[0091] As described above, according to the organic EL display device 100 of the present embodiment, the P-type capacitor Cgp electrically connected to the first gate electrode 14a of the driving transistor 9d via the second wiring 21c includes the first scanning signal line PS formed by the first metal film 14, the first interlayer insulating film 15 provided so as to cover the first scanning signal line PS, the third wiring 16c provided by the second metal film 16 on the first interlayer insulating film 15, and the first wiring 17c provided on the third wiring 16c. Here, since the first wiring 17c is provided so as to cover the third wiring 16c at least on the first scanning signal line PS, even if the variation in the width of the third wiring 16c is large in the P-type capacitor Cgp, the variation in the width of the first wiring 17c provided so as to cover the third wiring 16c is small. Therefore, the width of the conductive layer overlapping the first scanning signal line PS via the first interlayer insulating film 15 becomes the width of the first wiring 17c with small variation. As a result, the variation in the capacitance of the P-type capacitor Cgp can be suppressed, and the voltage of the first gate electrode 14a of the driving transistor 9d can be stably pulled up. And in each sub-pixel P, since the voltage of the first gate electrode 14a of the driving transistor 9d is stably pulled up, the occurrence of display unevenness can be suppressed in the organic EL display device 100.

[0092] Further, according to the organic EL display device 100 of the present embodiment, since the third wiring 16c formed of the second metal film 16 is disposed below the first wiring 17c formed of the oxide semiconductor film, when forming a contact hole reaching the first wiring 17c in the laminated film of the second gate insulating film 18 and the second interlayer insulating film 20, it is possible to suppress the contact hole from penetrating through the first wiring 17c and also penetrating through the first interlayer insulating film 15. Here, if the contact hole penetrates through the first interlayer insulating film 15, the second wiring 21c and the first scanning signal line PS will be short-circuited, and thus the P-type capacitor Cgp cannot be formed.

[0093] Further, according to the organic EL display device 100 of the present embodiment, since the base coat film 11 made of an inorganic insulating film is provided between the resin substrate 10 and the first semiconductor layer 12a, it is possible to suppress the peeling of the first semiconductor layer 12a.

[0094] 《Second Embodiment》 FIG. 8 shows a second embodiment of the display device according to the present invention. Here, FIG. 8 is a plan view of the TFT layer 30b constituting the organic EL display device of the present embodiment, and is a figure corresponding to FIG. 3 described in the first embodiment above. In the following embodiments, the same parts as those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0095] In the first embodiment above, the organic EL display device 100 including the TFT layer 30a provided with the first scanning signal line PS having a certain width was exemplified. However, in the present embodiment, an organic EL display device including the TFT layer 30b provided with the first scanning signal line PS having the wide portion W is exemplified.

[0096] The organic EL display device of this embodiment, similar to the organic EL display device 100 of the first embodiment, includes a display area 50 in which a plurality of sub-pixels P are provided in a matrix, and a gate driver 60, an emission driver 70, and a source driver 80 provided in a frame area around the display area 50. Note that, outside the organic EL display device of this embodiment, similar to the organic EL display device 100 of the first embodiment, a display control circuit 150 electrically connected to the gate driver 60, the emission driver 70, and the source driver 80 is provided.

[0097] The organic EL display device of this embodiment includes a resin substrate 10 provided as a base substrate, a TFT layer 30b provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30b, and a sealing film 45 provided on the organic EL element layer 40.

[0098] Similar to the TFT layer 30a of the first embodiment, the TFT layer 30b includes a base coat film 11 provided on the resin substrate 10, four P-channel type first transistors 9A provided for each sub-pixel P on the base coat film 11, three N-channel type second transistors 9B, and one capacitor 9h, and a planarization film 22 provided on each of the first transistors 9A, the second transistors 9B, and the capacitor 9h. Also, in the TFT layer 30b, similar to the TFT layer 30a of the first embodiment, the base coat film 11, the first semiconductor film 12, the first gate insulating film 13, the first metal film 14, the first interlayer insulating film 15, the second metal film 16, the second semiconductor film 17, the second gate insulating film 18, the third metal film 19, the second interlayer insulating film 20, the fourth metal film 21, and the planarization film 22 are sequentially laminated on the resin substrate 10.

[0099] In the display region 50 of the TFT layer 30b, similar to the TFT layer 30a of the first embodiment, i first scanning signal lines PS(1) to PS(i), (i + 1) second scanning signal lines NS(0) to NS(i), i emission control lines EM(1) to EM(i), and j data signal lines D(1) to D(j), a high-level power supply line, a low-level power supply line, and an initialization power supply line are provided. Here, as shown in FIG. 8, each of the first scanning signal lines PS has a wide portion W that is wider than adjacent portions at the portion where the first wiring 17d in each sub-pixel P covers the third wiring 16c.

[0100] In the TFT layer 30b, similar to the TFT layer 30a of the first embodiment, four P-channel first transistors 9A having a first semiconductor layer 12a formed of polysilicon are provided as a write control transistor 9c, a drive transistor 9d, a power supply control transistor 9e, and an emission control transistor 9f, and three N-channel second transistors 9B having a second semiconductor layer 17a formed of an oxide semiconductor are provided as an initialization transistor 9a, a threshold voltage compensation transistor 9b, and an anode discharge transistor 9g.

[0101] In the TFT layer 30b, the third conductor region 17aa of the initialization transistor 9a and the third conductor region 17aa of the threshold voltage compensation transistor 9b are electrically connected via the first wiring 17d formed of the second semiconductor film 17, as shown in FIG. 8.

[0102] As shown in FIG. 8, the first wiring 17d is provided such that a portion overlapping with the wide portion W extends in a direction orthogonal to the first scanning signal line PS. Here, the length La (for example, about 10 μm) of the portion of the first wiring 17d overlapping with the wide portion W along the direction orthogonal to the first scanning signal line PS is larger than the length Lb (for example, about 5 μm) of the portion of the first wiring 17d overlapping with the wide portion W along the extending direction of the first scanning signal line PS. Further, similar to the first wiring 17c of the first embodiment, the first wiring 17d forms a P-type capacitor Cgp in a portion overlapping with the first scanning signal line PS(n). Here, the P-type capacitor Cgp includes the first scanning signal line PS formed by the first metal film 14, the first interlayer insulating film 15 provided so as to cover the first scanning signal line PS, the third wiring 16c provided by the second metal film 16 on the first interlayer insulating film 15, and the first wiring 17d provided so as to cover the third wiring 16c at least on the first scanning signal line PS. Note that the numerical values of the lengths La and Lb described above vary depending on the fineness and configuration of the panel, and are merely examples.

[0103] Similar to the operation of the organic EL display device 100 of the first embodiment, in each sub-pixel P of the organic EL display device of this embodiment, the organic EL element 35 emits light with a luminance corresponding to the drive current, and image display is performed.

[0104] The organic EL display device of this embodiment can be manufactured by changing the shape when patterning the first metal film 14 and the shape when patterning the second semiconductor film 17 in the TFT layer formation process in the manufacturing method of the organic EL display device 100 of the first embodiment.

[0105] As described above, according to the organic EL display device of the present embodiment, the P-type capacitor Cgp electrically connected to the first gate electrode 14a of the driving transistor 9d via the second wiring 21c includes the first scanning signal line PS formed by the first metal film 14, the first interlayer insulating film 15 provided so as to cover the first scanning signal line PS, the third wiring 16c provided by the second metal film 16 on the first interlayer insulating film 15, and the first wiring 17d provided on the third wiring 16c. Here, since the first wiring 17d is provided so as to cover the third wiring 16c at least on the first scanning signal line PS, even if there is a large variation in the width of the third wiring 16c in the P-type capacitor Cgp, the variation in the width of the first wiring 17d provided so as to cover the third wiring 16c is small. Therefore, the width of the conductive layer overlapping the first scanning signal line PS via the first interlayer insulating film 15 becomes the width of the first wiring 17d with small variation. Thereby, the variation in the capacitance of the P-type capacitor Cgp can be suppressed, and the voltage of the first gate electrode 14a of the driving transistor 9d can be stably pulled up. And in each sub-pixel P, since the voltage of the first gate electrode 14a of the driving transistor 9d is stably pulled up, the occurrence of display unevenness can be suppressed in the organic EL display device.

[0106] Further, according to the organic EL display device of the present embodiment, the length La of the portion overlapping the wide portion W of the first wiring 17d along the direction orthogonal to the first scanning signal line PS is larger than the length Lb of the portion overlapping the wide portion W of the first wiring 17d along the extending direction of the first scanning signal line PS. Here, the variation in the width direction (X direction) of the first wiring 17d made of the oxide semiconductor film 17 made of an oxide semiconductor tends to be smaller than the variation in the width direction (Y direction) of the first scanning signal line PS formed by the first metal film 14. Therefore, assuming that the variation in the X direction of the first wiring 17d is ±1 μm, the variation in the Y direction of the first scanning signal line PS is ±2 μm, and the length La > length Lb, when the length La is 10 μm and the length Lb is 5 μm, the area of La×Lb proportional to the capacitance of the P-type capacitor Cgp is 32 - 72 μm of (8 - 12 μm)×(4 - 6 μm). 2It becomes so. On the contrary, when the relationship of the lengths is such that length La < length Lb, with length La being 5 μm and length Lb being 10 μm, the area of La×Lb, which is proportional to the capacitance of the P-type capacitor Cgp, is 27 to 77 μm² of (3 to 7 μm)×(9 to 11 μm). 2 Therefore, if the relationship of the lengths is such that length La > length Lb, variations in the capacitance of the P-type capacitor Cgp can be suppressed.

[0107] Further, according to the organic EL display device of the present embodiment, since the third wiring 16c formed by the second metal film 16 is disposed below the first wiring 17d formed by the second semiconductor film 17 made of an oxide semiconductor, when forming a contact hole reaching the first wiring 17d in the laminated film of the second gate insulating film 18 and the second interlayer insulating film 20, it is possible to suppress the contact hole from penetrating through the first wiring 17d and also through the first interlayer insulating film 15. Here, if the contact hole penetrates through the first interlayer insulating film 15, the second wiring 21c and the first scanning signal line PS will be short-circuited, and thus the P-type capacitor Cgp cannot be formed.

[0108] Further, according to the organic EL display device of the present embodiment, since the base coat film 11 made of an inorganic insulating film is provided between the resin substrate 10 and the first semiconductor layer 12a, peeling of the first semiconductor layer 12a can be suppressed.

[0109] 《Other Embodiments》 In each of the above embodiments, an organic EL layer having a five-layer laminated structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer is exemplified. However, the organic EL layer may have, for example, a three-layer laminated structure of a hole injection layer and hole transport layer combined, a light-emitting layer, and an electron transport layer and electron injection layer combined.

[0110] Also, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the laminated structure of the organic EL layer is inverted, the first electrode is a cathode, and the second electrode is an anode.

[0111] In each of the above embodiments, an organic EL display device has been described as an example of the display device. However, the present invention can be applied to a display device including a plurality of light-emitting elements driven by current, and for example, can be applied to a display device including a QLED (Quantum-dot light emitting diode) which is a light-emitting element using a quantum dot-containing layer.

Industrial Applicability

[0112] As described above, the present invention is useful for a flexible display device.

Explanation of Signs

[0113] H Contact hole NS Second scanning signal line NG Node G P Sub-pixel PS First scanning signal line W Wide portion 9A First transistor 9B Second transistor 9C Third transistor 9a Initialization transistor (second transistor) 9b Threshold voltage compensation transistor (second transistor) 9c Write control transistor (first transistor) 9d Drive transistor (first transistor) 9e Power supply control transistor (first transistor) 9f Light emission control transistor (first transistor) 9g Anode discharge transistor (second transistor) 10 Resin substrate (base substrate) 11 Base coat film 12 First semiconductor film 12a First semiconductor layer 12aa First conductor region 12ab Second conductor region 12ac First channel region 13 First gate insulating film (first inorganic insulating film) 14 First metal film 14a First gate electrode 15 First interlayer insulating film (second inorganic insulating film) 16 Second metal film 16c Third wiring 17 Second semiconductor film 17a Second semiconductor layer 17aa Third conductor region 17ab Fourth conductor region 17ac Second channel region 17c, 17d First wiring 18 Second gate insulating film (third inorganic insulating film) 19 Third metal film 19a Second gate electrode 20 Second interlayer insulating film (fourth inorganic insulating film) 21 Fourth metal film 21c Second wiring 30a, 30b TFT layer (thin film transistor layer) 35 Organic EL element (organic electroluminescence element, light-emitting element) 40 Organic EL element layer (light-emitting element layer) 45 Encapsulation film 50 Display area 100 Organic EL display device

Claims

1. a base substrate; a thin film transistor layer provided on the base substrate, in which a first semiconductor film made of polysilicon, a first inorganic insulating film, a first metal film, a second inorganic insulating film, a second metal film, a second semiconductor film made of an oxide semiconductor, a third inorganic insulating film, a third metal film, a fourth inorganic insulating film, and a fourth metal film are laminated in this order; in the thin film transistor layer, a first semiconductor layer formed of the first semiconductor film in which a first conductor region and a second conductor region are defined so as to be separated from each other and a first channel region is defined between the first conductor region and the second conductor region, and a first gate electrode formed of the first metal film so as to overlap the first channel region, and a first transistor having the first gate electrode; a second semiconductor layer formed of the second semiconductor film in which a third conductor region and a fourth conductor region are defined so as to be separated from each other and a second channel region is defined between the third conductor region and the fourth conductor region, and a second gate electrode formed of the third metal film so as to overlap the second channel region, and a second transistor having the second gate electrode are provided for each sub-pixel constituting a display region; as the first transistor, a write control transistor, a drive transistor, a power supply control transistor, and a light emission control transistor are provided; as the second transistor, an initialization transistor and a threshold voltage compensation transistor are provided; the third conductor region in the initialization transistor and the third conductor region in the threshold voltage compensation transistor are electrically connected via a first wiring formed of the second semiconductor film; the first gate electrode in the drive transistor is electrically connected to the first wiring via a second wiring formed of the fourth metal film; in each sub-pixel, a first scanning signal line electrically connected to the first gate electrode in the write control transistor and formed of the first metal film, a second scanning signal line electrically connected to the second gate electrode in the threshold voltage compensation transistor on one side of the first scanning signal line and formed of the third metal film, and another second scanning signal line electrically connected to the second gate electrode in the initialization transistor on the other side of the first scanning signal line and formed of the third metal film are provided so as to extend in parallel with each other; A display device in which a third wiring formed by the second metal film is electrically connected to the second wiring, wherein the first wiring is provided so as to cover the third wiring at least on the first scanning signal line. The display device is characterized by this. **Claim 2** In the display device according to claim 1, The display device is characterized in that the film thickness of the second semiconductor film is smaller than the film thickness of the second metal film. **Claim 3** In the display device according to claim 1 or 2, The display device is characterized in that the second wiring is provided so as to intersect with the second scanning signal line provided on one side of the first scanning signal line. **Claim 4** In the display device according to claim 1 or 2, The display device is characterized in that the first wiring is provided directly on the third wiring. **Claim 5** In the display device according to claim 1 or 2, The second wiring is electrically connected to the first wiring via contact holes formed in the third inorganic insulating film and the fourth inorganic insulating film, The display device is characterized in that the contact holes are provided in a region overlapping the third wiring in plan view. **Claim 6** In the display device according to claim 5, The display device is characterized in that the contact holes are provided in a region where the first wiring and the third wiring overlap in plan view. **Claim 7** In the display device according to claim 6, The display device is characterized in that the contact holes are provided so as to penetrate the first wiring. **Claim 8** In the display device according to claim 5, The display device is characterized in that the contact holes are provided on the first scanning signal line. **Claim 9** In the display device according to claim 1 or 2, The display device is characterized in that the second metal film is composed of a molybdenum film. **Claim 10** In the display device according to claim 1 or 2, The display device is characterized in that an anode discharge transistor is provided as the second transistor. **Claim 11** In the display device according to claim 1 or 2, The first scanning signal line has a widened portion that is wider than an adjacent portion at a portion where the first wiring covers the third wiring, The first wiring is provided such that a portion overlapping the widened portion extends in a direction orthogonal to the first scanning signal line. A display device characterized in that a length of a portion of the wide portion of the first wiring overlapping with the first wiring along a direction orthogonal to the first scanning signal line is larger than a length of a portion of the wide portion of the first wiring overlapping with the first wiring along a direction in which the first scanning signal line extends.

12. In the display device according to claim 11, A display device characterized in that the first metal film is composed of a molybdenum film.

13. In the display device according to claim 1 or 2, The base substrate is a resin substrate, A base coat film is provided on the resin substrate, A display device characterized in that the first semiconductor film is provided on the base coat film.

14. In the display device according to claim 1 or 2, A light-emitting element layer provided on the thin-film transistor layer and having a plurality of light-emitting elements arranged thereon, A display device characterized by comprising a sealing film provided on the light-emitting element layer.

15. In the display device according to claim 14, A display device characterized in that each of the light-emitting elements is an organic electroluminescence element.

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