Display Panel and Display Device

Abstract

Display panel and display device, the display panel comprises a base substrate (1000), a silicon semiconductor layer (500), a first insulating layer (710), a first conductive layer (100), a second insulating layer (720), and an oxide semiconductor layer (600), the silicon semiconductor layer (500) comprises a silicon active layer of a driving transistor (T1) and a silicon active layer of an initialization transistor (T6), the silicon active layer comprises a first region (T1-S, T6-S), a second region (T1-D, T6-D) and a first region (T1-S, T6-S) and a second region (T1-D, T The oxide semiconductor layer (600) includes an oxide active layer of an oxide transistor (T8-D), the oxide active layer having a third region (T8-S), a fourth region (T8-D), and a second channel region (T8-A) disposed between the third region (T8-S) and the fourth region (T8-D), and in the same subpixel, the second region (T6-D) of the silicon active layer of the initialization transistor (T6) is electrically connected to the third region (T8-S) of the oxide active layer of the oxide transistor (T8). The fourth region (T8-D) of the oxide active layer of the oxide transistor (T8) is electrically connected to the gate (CC2a) of the drive transistor (T1).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to display panels and display devices.

[0002] [Cross - reference to Related Applications] This application claims priority based on a Chinese patent application filed with the Chinese Patent Office on May 9, 2020, with an application number of PCT / CN2020 / 089467 and an invention title of "Display Panel and Display Device", and incorporates the entire disclosure thereof herein.

Background Art

[0003] Electroluminescent diodes such as Organic Light Emitting Diode (OLED) and Quantum Dot Light Emitting Diodes (QLED) are one of the hotspots in the applied research field of electroluminescent display devices, which have the advantages of self - emission and low energy consumption.

Summary of the Invention

Means for Solving the Problems

[0004] The display panel provided by an embodiment of the present disclosure includes a base substrate, a silicon semiconductor layer, a first conductive layer, an oxide semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, the base substrate has a plurality of sub - pixels, at least one of the plurality of sub - pixels includes a pixel circuit, and the pixel circuit includes a driving transistor, an oxide transistor, and a storage capacitor, the silicon semiconductor layer is disposed on the base substrate, and the silicon semiconductor layer includes the silicon active layer of the driving transistor, The first conductive layer is disposed on the side of the silicon semiconductor layer away from the base substrate, and the first conductive layer includes the gate of the driving transistor. The oxide semiconductor layer is disposed on the side of the first conductive layer away from the base substrate, and the oxide semiconductor layer includes the oxide active layer of the oxide transistor. The second conductive layer is disposed on the side of the first conductive layer away from the base substrate, and the second conductive layer includes a memory conductive portion. The third conductive layer is disposed on the side of the second conductive layer away from the base substrate, and the third conductive layer includes a first power line portion and a second connection portion arranged at intervals. In the same sub-pixel, the second electrode of the oxide transistor is electrically connected to the gate of the driving transistor via the second connection portion, and the first power line portion is electrically connected to the memory conductive portion. The fourth conductive layer is disposed on the side of the third conductive layer away from the base substrate, and the fourth conductive layer includes a second power line portion. In the same sub-pixel, the first power line portion is electrically connected to the second power line portion. Here, in the same sub-pixel, the orthographic projection of the second power line portion on the base substrate covers the orthographic projection of the second connection portion on the base substrate, and the orthographic projection of the second power line portion on the base substrate extends beyond the edges on both sides in the second direction of the orthographic projection of the gate of the driving transistor on the base substrate, and extends beyond the edges on both sides in the second direction of the orthographic projection of the memory conductive portion on the base substrate.

[0005] Optionally, in an embodiment of the present disclosure, the first conductive layer further includes a plurality of third scanning lines arranged at intervals, the third scanning lines extend in a first direction and are arranged in a second direction. The sub-pixel further includes a data writing transistor, and the gate of the data writing transistor is electrically connected to the third scanning line. The orthographic projection of the third scanning line on the base substrate and the orthographic projection of the second power line portion on the base substrate have an overlapping region.

[0006] Optionally, in an embodiment of the present disclosure, the second conductive layer further includes a plurality of auxiliary scanning lines arranged at intervals. In the same subpixel, the orthographic projection of the auxiliary scanning line on the base substrate and the orthographic projection of the oxide active layer of the oxide transistor on the base substrate have a sixth overlapping region, and the orthographic projection of the second power line portion on the base substrate overlaps with the sixth overlapping region.

[0007] Optionally, in an embodiment of the present disclosure, the subpixel further includes a first light emission control transistor and a second light emission control transistor. The silicon semiconductor layer further includes a silicon active layer of the first light emission control transistor and a silicon active layer of the second light emission control transistor. The first conductive layer further includes a gate of the first light emission control transistor and a gate of the second light emission control transistor. In the same subpixel, the first power line portion is electrically connected to a first electrode of the first light emission control transistor, a second electrode of the first light emission control transistor is electrically connected to a first electrode of the driving transistor, a first electrode of the second light emission control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the second light emission control transistor is electrically connected to a first electrode of the light emitting device.

[0008] Optionally, in an embodiment of the present disclosure, the first conductive layer further includes a plurality of light emission control lines arranged at intervals. In the same subpixel, the orthographic projection of the light emission control line on the base substrate is arranged on the side of the orthographic projection of the gate of the driving transistor on the base substrate away from the orthographic projection of the auxiliary scanning line on the base substrate. The light emission control line is electrically connected to the gate of the first light emission control transistor and the gate of the second light emission control transistor. Optionally, in an embodiment of the present disclosure, a region where a positive projection of the second power line portion on the base substrate overlaps with a positive projection of the light emission control line on the base substrate is provided.

[0009] Optionally, in an embodiment of the present disclosure, the second connection portion includes a first conductive portion and a first main body portion that are electrically connected to each other, and the first conductive portion is electrically connected to an oxide active layer of the oxide transistor. A region where a positive projection of the first main body portion on the base substrate overlaps with a positive projection of a gate of the driving transistor on the base substrate is provided, and a positive projection of the first main body portion on the base substrate does not overlap with a positive projection of the third scanning line on the base substrate.

[0010] Optionally, in an embodiment of the present disclosure, in the same sub-pixel, a minimum linear distance between a positive projection of the first main body portion on the base substrate and a positive projection of the first power line portion on the base substrate is smaller than a minimum linear distance between a positive projection of the first main body portion on the base substrate and a positive projection of a gate of the first light emission control transistor on the base substrate.

[0011] Optionally, in an embodiment of the present disclosure, the third conductive layer further includes a first connection portion that is disposed at an interval from the first power line portion and the second connection portion. In the same sub-pixel, the first connection portion is electrically connected to an oxide active layer of the oxide transistor.

[0012] Optionally, in an embodiment of the present disclosure, a distance between the first connection portion and the first conductive portion is greater than a threshold value.

[0013] On the other hand, a display panel provided by an embodiment of the present disclosure includes a base substrate, a silicon semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer. The base substrate has a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes a pixel circuit. The pixel circuit includes a driving transistor, an initialization transistor, and an oxide transistor. The silicon semiconductor layer is disposed on the base substrate, and the silicon semiconductor layer includes a silicon active layer of the driving transistor. The first conductive layer is disposed on the side of the silicon semiconductor layer away from the base substrate, and the first conductive layer includes a gate of the driving transistor. The oxide semiconductor layer is disposed on the side of the first conductive layer away from the base substrate, and the oxide semiconductor layer includes an oxide active layer of the oxide transistor. The second conductive layer is disposed on the side of the first conductive layer away from the base substrate. The second conductive layer includes a plurality of auxiliary scanning lines arranged at intervals. The auxiliary scanning lines extend along a first direction and are electrically connected to the gate of the oxide transistor. The third conductive layer is disposed on the side of the first conductive layer away from the base substrate. The third conductive layer includes a first connection portion and a second connection portion. In the same sub-pixel, the oxide active layer of the oxide transistor is electrically connected to the gate of the driving transistor through the second connection portion. The first electrode of the initialization transistor is electrically connected to the gate of the driving transistor through the first connection portion and the second connection portion. The first connection portion includes a portion whose extending direction is substantially parallel to the first direction.

[0014] Optionally, in an embodiment of the present disclosure, the first connection portion includes a first sub-connection portion electrically connected to the oxide active layer of the oxide transistor. The extending direction of the first sub-connection portion is substantially parallel to the first direction and intersects the extending direction of the oxide active layer of the oxide transistor.

[0015] Optionally, in an embodiment of the present disclosure, the first connection portion further includes a second sub-connection portion electrically connected to the first sub-connection portion. The extending direction of the second sub-connection portion is substantially parallel to the extending direction of the oxide active layer of the oxide transistor.

[0016] Optionally, in an embodiment of the present disclosure, the orthographic projection of the second connection portion on the base substrate is disposed within the orthographic projection of the gate of the driving transistor on the base substrate. Optionally, in an embodiment of the present disclosure, the sub-pixel further includes an initialization line, the initialization transistor is electrically connected to the initialization line, and the initialization signal is transmitted to the gate of the driving transistor by at least the first sub-connection portion and the second connection portion.

[0017] Optionally, in an embodiment of the present disclosure, the second conductive layer further includes a memory conductive portion, the third conductive layer further includes a first power line portion disposed at an interval, and the first power line portion is electrically connected to the memory conductive portion.

[0018] Optionally, in an embodiment of the present disclosure, it further includes a fourth conductive layer disposed on the side of the third conductive layer away from the base substrate, the fourth conductive layer includes a second power line portion, and in the same sub-pixel, the first power line portion is electrically connected to the second power line portion. Here, in the same sub-pixel, the orthographic projection of the second power line portion on the base substrate covers the orthographic projection of the second connection portion on the base substrate, the orthographic projection of the second power line portion on the base substrate exceeds the edges on both sides in the second direction of the orthographic projection of the gate of the driving transistor on the base substrate, and exceeds the edges on both sides in the second direction of the orthographic projection of the memory conductive portion on the base substrate.

[0019] Optionally, in an embodiment of the present disclosure, the first conductive layer further includes a plurality of third scanning lines disposed at intervals, the third scanning lines extend along the first direction and are arranged along the second direction. The sub-pixel further includes a data writing transistor, and a gate of the data writing transistor is electrically connected to the third scanning line, A positive projection of the third scanning line on the base substrate and a positive projection of the second power line portion on the base substrate have an overlapping region.

[0020] Optionally, in an embodiment of the present disclosure, the sub-pixel further includes a first light emission control transistor and a second light emission control transistor. The silicon semiconductor layer further includes a silicon active layer of the first light emission control transistor and a silicon active layer of the second light emission control transistor. The first conductive layer further includes a gate of the first light emission control transistor and a gate of the second light emission control transistor. In the same sub-pixel, the first power line portion is electrically connected to a first electrode of the first light emission control transistor, a second electrode of the first light emission control transistor is electrically connected to a first electrode of the driving transistor, a first electrode of the second light emission control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the second light emission control transistor is electrically connected to a first electrode of the light emitting device.

[0021] Optionally, in an embodiment of the present disclosure, the first conductive layer further includes a plurality of light emission control lines arranged at intervals. In the same sub-pixel, a positive projection of the light emission control line on the base substrate is arranged on a side of a positive projection of the gate of the driving transistor on the base substrate, which is away from a positive projection of the auxiliary scanning line on the base substrate. The light emission control line is electrically connected to the gate of the first light emission control transistor and the gate of the second light emission control transistor.

[0022] Optionally, in the embodiments of the present disclosure, the orthographic projection of the second power line portion on the base substrate and the orthographic projection of the light emission control line on the base substrate have an overlapping region. On the other hand, the embodiments of the present disclosure also provide a display device including the above display panel provided by the embodiments of the present disclosure.

Brief Description of the Drawings

[0023]

Figure 1

Figure 2a

Figure 2b

Figure 2c

Figure 2d

Figure 2e

Figure 3

Figure 4a

Figure 4b

Figure 4c

Figure 4d

Figure 4e

Figure 4f

Figure 5a

Figure 5b

Figure 5c

Figure 5d

Figure 6

Embodiments for Carrying out the Invention

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of them. And, when there is no contradiction, the embodiments and features of the embodiments of the present disclosure can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present disclosure.

[0025] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar words used in this disclosure do not indicate order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and other similar words mean that the elements or items listed before the word cover the elements or items listed after the word and their equivalents, but do not exclude other elements or items. Similar words such as "connected" or "related by blood" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect.

[0026] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true ratios, and the purpose is only to illustrate the content of the present invention. Also, the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions.

[0027] As shown in FIG. 1, the display panel provided by the embodiment of the present invention may include a base substrate 1000 and a plurality of pixel units PX disposed in the display area of the base substrate 1000. The pixel unit PX may include a plurality of sub-pixels spx. Exemplarily, as shown in FIGS. 1 and 2a, at least one of the plurality of sub-pixels spx may include a pixel driving circuit 0121 and a light-emitting device 0120. Here, the pixel driving circuit 0121 has a transistor and a capacitor, generates an electrical signal by the interaction of the transistor and the capacitor, and the generated electrical signal is input to the first electrode of the light-emitting device 0120. Further, a corresponding voltage is applied to the second electrode of the light-emitting device 0120 to drive the light-emitting device 0120 to emit light.

[0028] As shown in FIG. 2a, the pixel driving circuit 0121 may include a driving control circuit 0122, a first light emission control circuit 0123, a second light emission control circuit 0124, a voltage stabilization circuit 0125, a data writing circuit 0126, a memory circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129.

[0029] The driving control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the driving control circuit 0122 is configured to provide a driving current for driving the light emitting device 0120 to emit light to the light emitting device 0120. For example, the first light emission control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the first light emission control circuit 0123 is configured to realize turning on or off the connection between the driving control circuit 0122 and the first voltage terminal VDD. The second light emission control circuit 0124 is electrically connected to the second end of the driving control circuit 0122 and the first electrode of the light emitting device 0120. And the second light emission control circuit 0124 is configured to realize turning on or off the connection between the driving control circuit 0122 and the light emitting device 0120.

[0030] The voltage stabilization circuit 0125 is electrically connected to the control terminal of the driving control circuit 0122, the reset circuit 0129, and the threshold compensation circuit 0128. The voltage stabilization circuit 0125 is configured to turn on the control terminal of the driving control circuit 0122 and the reset circuit 0129 to turn on the control circuit 0122. Reset the control terminal of the dynamic control circuit 0122. And the voltage stabilization circuit 0125 is configured to turn on the control terminal of the driving control circuit 0122 and the threshold compensation circuit 0128 to perform threshold compensation.

[0031] The data writing circuit 0126 is electrically connected to the first terminal of the driving control circuit 0122. And the second light emission control circuit 0124 is configured to write the signal on the data line VD into the memory circuit 0127.

[0032] The memory circuit 0127 is electrically connected to the control terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the memory circuit 0127 is configured to store data signals.

[0033] The threshold compensation circuit 0128 is electrically connected to the second terminal of the voltage stabilization circuit 0125 and the drive control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the drive control circuit 0122.

[0034] The reset circuit 0129 is also electrically connected to the first electrode of the light-emitting device 0120. And the reset circuit 0129 resets the first electrode of the light-emitting device 0120 and provides the signal transmitted on the initialization line VINIT to the voltage stabilization circuit 0125, so that when the voltage stabilization circuit 0125 turns on the control terminal of the drive control circuit 0122 and the reset circuit 0129, the control terminal of the drive control circuit 0122 is reset.

[0035] Here, the light-emitting device 0120 can be configured as an electroluminescent diode such as at least one of an OLED and a QLED. Here, the light-emitting device 0120 may include a stacked first electrode, a light-emitting functional layer, and a second electrode. Exemplarily, the first electrode may be an anode and the second electrode may be a cathode. The light-emitting functional layer may include a light-emitting layer. Further, the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Of course, in an actual application, the light-emitting device 0120 can be designed and determined according to the requirements of the actual application environment not limited herein.

[0036] Exemplarily, as shown in FIG. 2a, the drive control circuit 0122 includes a drive transistor T1, the control terminal of the drive control circuit 0122 includes the gate of the drive transistor T1, and the first terminal of the drive control circuit 0122 includes the first electrode of the drive transistor T1. The second terminal of the drive control circuit 0122 includes the second electrode of the drive transistor T1. Exemplarily, as shown in FIG. 2a, the data writing circuit 0126 includes a data writing transistor T2. The memory circuit 0127 includes a memory capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a first light emission control transistor T4. The second light emission control circuit 0124 includes a second light emission control transistor T5. The reset circuit 0129 includes an initialization transistor T6 and a second reset transistor T7. The voltage stabilization circuit 0125 includes an oxide transistor T8.

[0037] Specifically, the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, and the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive a data signal. The gate of the data writing transistor T2 is configured to be electrically connected to the third scanning line GA3 to receive a signal.

[0038] The first electrode of the memory capacitor CST is electrically connected to the first power supply terminal VDD, and the second electrode of the memory capacitor CST is electrically connected to the gate of the driving transistor T1.

[0039] The first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1. The second electrode of the threshold compensation transistor T3 is electrically connected to the first electrode of the oxide transistor T8. The gate of the threshold compensation transistor T3 is configured to be electrically connected to the third scanning line GA3 to receive a signal. The first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the threshold compensation transistor T3 is electrically connected to the first electrode of the oxide transistor T8. The compensation transistor T3 is configured to be electrically connected to the third scanning line GA3 to receive a signal.

[0040] The first electrode of the second reset transistor T7 is configured to be electrically connected to the initialization line VINIT to receive a reset signal, and the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device 0120. The gate of the second reset transistor T7 is configured to be electrically connected to the fourth scanning line GA4 to receive a signal.

[0041] The first electrode of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light-emitting control transistor T4 is electrically connected to the light-emitting control line EM and configured to receive a light-emitting control signal.

[0042] The first electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the second light-emitting control transistor T5 is electrically connected to the first electrode of the light-emitting device 0120. The gate of the second light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0043] The second electrode of the oxide transistor T8 is electrically connected to the gate of the driving transistor T1, and the gate of the oxide transistor T8 is configured to be electrically connected to the first scanning line GA1 to receive a signal.

[0044] The second electrode of the light-emitting device 0120 is electrically connected to the second power supply terminal VSS. Here, the first electrode and the second electrode of the above transistor can be determined as the source electrode or the drain electrode according to the actual use not limited to this specification.

[0045] For example, one of the first power supply terminal VDED and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. For example, in the embodiment shown in FIG. 2a, the first power supply terminal VDED is a voltage source that outputs a constant first voltage, the first voltage is a positive voltage, and the second power supply terminal VSS can be a voltage source that outputs a constant second voltage. The second voltage can be a negative voltage or the like. For example, in some examples, the second power supply terminal VSS can be grounded.

[0046] Several signal timing diagrams corresponding to the pixel driving circuit shown in FIG. 2a are shown in FIG. 2b. In one frame of the display time, the operation process of the pixel driving circuit has three stages: a T10 stage, a T20 stage, and a T30 stage. Here, ga1 represents the signal transmitted on the first scanning line GA1, ga2 represents the signal transmitted on the second scanning line GA2, ga3 represents the signal transmitted on the third scanning line GA3, and ga4 represents the signal transmitted on the fourth scanning line GA4. em represents the signal transmitted on the emission control line EM.

[0047] In the T10 stage, since the signal ga1 controls the initialization transistor T6 and the signal ga2 controls the oxide transistor T8 to turn on, the signal transmitted on the initialization line VINIT can be supplied to the gate of the driving transistor T1 to reset the gate of the driving transistor T1. The signal ga4 controls the second reset transistor T7, which is turned on, to turn on, so that the signal transmitted on the initialization line VINIT is provided to the first electrode of the light emitting device 0120 to reset the first electrode of the light emitting device 0120. Also, in this stage, the signal ga3 controls both the data writing transistor T2 and the threshold compensation transistor T3 to turn off. The signal em controls both the first emission control transistor T4 and the second emission control transistor T5 to turn off.

[0048] In the T20 stage, the signal ga3 turns on both the data write transistor T2 and the threshold compensation transistor T3. Further, since the signal ga2 controls the oxide transistor T8 to turn on, the data signal transmitted on the data line VD can charge the gate of the drive transistor T1, and as a result, the voltage of the gate of the drive transistor T1 becomes Vdata + Vth. Here, Vth represents the threshold voltage of the drive transistor T1, and Vdata represents the voltage of the data signal. Further, in this stage, the signal ga1 controls the initialization transistor T6 to turn off, and the signal ga4 controls the second reset transistor T7 to turn off. The signal em controls both the first light emission control transistor T4 and the second light emission control transistor T5, which are turned off, to turn off.

[0049] In the T30 stage, the signal em controls both the first light emission control transistor T4 and the second light emission control transistor T5 to turn on. The turned-on first light emission control transistor T4 provides the voltage V of the first power supply terminal VDED to the first electrode of the drive transistor T1, and as a result, the voltage of the first electrode of the drive transistor T1 is V. vdd The drive transistor T1 generates a drive current according to its gate voltage Vdata + Vth and the first electrode voltage V. vdd The drive current is provided to the light emitting device 0120 through the turned-on second light emission control transistor T5 to drive the light emitting device 0120 to emit light. Further, in this stage, the signal ga1 controls the initialization transistor T6 to turn off, and the signal ga4 controls the second reset transistor T7 to turn off. The signal ga3 controls both the data write transistor T2 and the threshold compensation transistor T3 to turn off. The signal ga2 controls the oxide transistor T8 to turn off. vdd

[0050] In some examples, another signal timing diagram corresponding to the pixel driving circuit shown in FIG. 2a is shown in FIG. 2c. In one frame of the display time, the operation process of the pixel driving circuit has three stages: a T10 stage, a T20 stage, and a T30 stage. Here, ga1 represents the signal transmitted on the first scanning line GA1, ga2 represents the signal transmitted on the second scanning line GA2, ga3 represents the signal transmitted on the third scanning line GA3, and ga4 represents the signal transmitted on the fourth scanning line GA4. em represents the signal transmitted on the emission control line EM.

[0051] In the T10 stage, the signal ga4 controls the second reset transistor T7 to turn off, and the remaining operation process can refer to the above embodiment and will not be repeated here.

[0052] In the T20 stage, the signal ga4 controls the second reset transistor T7 to turn on, provides the signal transmitted on the initialization line VINIT to the first electrode of the light-emitting device 0120, and resets the first electrode of the light-emitting device 0120. The remaining operation process can refer to the above embodiment and will not be repeated here. In the T30 stage, the operation process of this stage can refer to the above embodiment and will not be repeated here.

[0053] In some examples, some other signal timing diagrams corresponding to the pixel driving circuit shown in FIG. 2a are as shown in FIG. 2d. In one frame of the display time, the operation process of the pixel driving circuit has four stages: a T10 stage, a T20 stage, a T30 stage, and a T40 stage. Here, ga1 represents the signal transmitted on the first scanning line GA1, ga2 represents the signal transmitted on the second scanning line GA2, ga3 represents the signal transmitted on the third scanning line GA3, and ga4 represents the signal transmitted on the fourth scanning line GA4. GA4. em represents the signal transmitted on the emission control line EM.

[0054] At the T10 stage, the signal ga4 turns on the second reset transistor T7 and provides the signal transmitted on the initialization line VINIT to the first electrode of the light-emitting device 0120 to reset the first electrode of the light-emitting device 0120. Also at this stage, the signal ga1 turns off the initialization transistor T6, and the signal ga3 turns off both the data writing transistor T2 and the threshold compensation transistor T3. The signal em turns off both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 that are turned off. The signal ga2 controls the oxide transistor T8 to turn off.

[0055] At the T20 stage, since the signal ga1 turns on the initialization transistor T6 and the signal ga2 turns on the oxide transistor T8, the signal transmitted on the initialization line VINIT can be supplied to the gate of the driving transistor to reset the gate of the driving transistor T1 so that the polarity can be reset. Further at this stage, the signal ga4 turns off the second reset transistor T7, and the signal ga3 turns off both the data writing transistor T2 and the threshold compensation transistor T3. The signal em turns off both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 that are turned off.

[0056] At the T30 stage, the signal ga3 turns on both the data write transistor T2 and the threshold compensation transistor T3. Further, since the signal ga2 controls the oxide transistor T8 to turn on, the data signal transmitted on the data line VD can charge the gate of the drive transistor T1, and as a result, the voltage of the gate of the drive transistor T1 becomes Vdata+Vth. Here, Vth represents the threshold voltage of the drive transistor T1, and Vdata represents the voltage of the data signal. Further, at this stage, the signal ga1 controls the initialization transistor T6 to turn off, and the signal ga4 controls the second reset transistor T7 to turn off. The signal em controls both the first light emission control transistor T4 and the second light emission control transistor T5, which are turned off, to turn off.

[0057] At the T40 stage, the signal em controls both the first light emission control transistor T4 and the second light emission control transistor T5 to turn on. The turned-on first light emission control transistor T4 supplies the voltage V of the first power supply terminal VDED to the first electrode of the drive transistor T1, and as a result, the voltage of the first electrode of the drive transistor T1 is V. vdd is provided to the first electrode of the drive transistor T1, and as a result, the voltage of the first electrode of the drive transistor T1 is V. vdd The drive transistor T1 generates a drive current according to its gate voltage Vdata + Vth and the first electrode voltage V. vdd The drive current is provided to the light emitting device 0120 through the turned-on second light emission control transistor T5 to drive the light emitting device 0120 to emit light. Further, at this stage, the signal ga1 controls the initialization transistor T6 to turn off, and the signal ga4 controls the second reset transistor T7 to turn off. The signal ga3 controls both the data write transistor T2 and the threshold compensation transistor T3 to turn off. The signal ga2 controls the oxide transistor T8 to turn off.

[0058] In some examples, several other signal timing diagrams corresponding to the pixel driving circuit shown in FIG. 2a are shown in FIG. 2e. In one frame of the display time, there are three stages in the operation process of the pixel driving circuit: the T10 stage, the T20 stage, and the T30 stage. Here, ga1 represents the signal transmitted on the first scanning line GA1, ga2 represents the signal transmitted on the second scanning line GA2, ga3 represents the signal transmitted on the third scanning line GA3, and ga4 represents the signal transmitted on the fourth scanning line GA4. Em represents the signal transmitted on the emission control line EM.

[0059] In the T10 stage, the signal ga1 controls the initialization transistor T6 to turn on, and the signal ga2 controls the oxide transistor T8 to turn on, so that the signal transmitted on the initialization line VINIT can be provided to the gate of the driving transistor. Thereby, the gate of the driving transistor T1 can be reset. Further, in this stage, the signal ga4 controls the second reset transistor T7 to turn off, and the signal ga3 controls both the data writing transistor T2 and the threshold compensation transistor T3 to turn off. The signal em controls both the first emission control transistor T4 and the second emission control transistor T5 to turn off.

[0060] In the T20 stage, the signal ga4 controls the second reset transistor T7 to turn on, provides the signal transmitted on the initialization line VINIT to the first electrode of the light emitting device 0120, and resets the first electrode of the light emitting device 0120. Also, in this stage, the signal ga1 controls the initialization transistor T6 to turn off, and the signal ga3 controls both the data writing transistor T2 and the threshold compensation transistor T3 to turn off. The signal em controls both the first emission control transistor T4 and the second emission control transistor T5 to turn off.

[0061] At the T30 stage, the signal ga3 turns on both the data writing transistor T2 and the threshold compensation transistor T3. Further, since the signal ga2 controls the oxide transistor T8 to turn on, the data signal transmitted on the data line VD can charge the gate of the driving transistor T1. As a result, the voltage of the gate of the driving transistor T1 becomes Vdata + Vth. Here, Vth represents the threshold voltage of the driving transistor T1, and Vdata represents the voltage of the data signal. Further, at this stage, the signal ga1 controls the initialization transistor T6 to turn off, and the signal ga4 controls the second reset transistor T7 to turn off. The signal em controls both the first light emission control transistor T4 and the second light emission control transistor T5 to turn off.

[0062] It should be noted that in the embodiments of the present disclosure, the pixel driving circuit in the sub-pixel may not only have the structure shown in FIG. 2a, but also have a structure including other numbers of transistors. It is not limited in the embodiments of the present disclosure.

[0063] FIG. 3 is a schematic diagram of the layout structure of a pixel driving circuit provided by some embodiments of the present disclosure. FIGS. 4a to 4f are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the present disclosure. Here, in the examples shown in FIGS. 3 to 4f, the pixel driving circuit of the sub-pixel spx is taken as an example. FIGS. 3 to 4f also show the first scanning line GA1, the second scanning line GA2, the third scanning line GA3, the fourth scanning line GA4, the initialization line VINIT, the light emission control line EM, the data line VD, and the light emission control line electrically connected to the first power line portion Vdd of the pixel driving circuit 0121. Here, the first power line portion Vdd is configured to input a driving voltage (i.e., the first voltage) to the first power terminal VDD. Exemplarily, a plurality of data lines VD may be arranged along the first direction F1.

[0064] Exemplarily, as shown in FIGS. 3, 4a, and 5a to 6, the silicon semiconductor layer 500 of the pixel driving circuit 0121 is shown. The silicon semiconductor layer 500 can be formed by patterning amorphous silicon and low temperature poly-silicon (LTPS) materials. Using the silicon semiconductor layer 500, the silicon active layers of the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, initialization transistor T6, and second reset transistor T7 can be fabricated. Also, each silicon active layer may include a first region, a second region, and a first channel region located between the first region and the second region. For example, FIG. 4a shows the first channel region T1-A of the driving transistor T1, the first channel region T2-A of the data writing transistor T2, the first channel region T3-A of the threshold compensation transistor T3, the first channel region T4-A of the first light emission control transistor T4, the first channel region T5-A of the second light emission control transistor T5, the first channel region T6-A of the initialization transistor T6, and the first channel region T7-A of the second reset transistor T7. It should be noted that the above-mentioned first region and second region can be regions of the silicon semiconductor layer 500 doped with n-type impurities or p-type impurities to form conductive regions. Therefore, the first region and the second region can be used as the source electrode region and drain electrode region of the silicon active layer for electrical connection.

[0065] Exemplarily, as shown in FIGS. 3 and 4a, the silicon active layer of the initialization transistor T6 can extend substantially linearly along the second direction F2. For example, the extending direction of the silicon active layer of the initialization transistor T6 is substantially parallel to the second direction F2. In the actual process, due to limitations of process conditions and the like, the extending direction of the silicon active layer of the initialization transistor T6 may not be completely parallel to the second direction, and there may be some deviation. Therefore, as long as the extending direction of the silicon active layer of the above-mentioned initialization transistor T6 satisfies the substantially parallel condition with the second direction, all of these belong to the protection scope of the present invention. For example, the above identity can enable parallel processing within the allowable error range.

[0066] Exemplarily, as shown in FIGS. 3 and 4a, the silicon active layer of the threshold compensation transistor T3 can extend substantially linearly along the second direction F2. For example, the extending direction of the silicon active layer of the threshold compensation transistor T3 is substantially parallel to the second direction F2. In the actual process, due to limitations of process conditions and the like, the extending direction of the silicon active layer of the threshold compensation transistor T3 may not be completely parallel to the second direction, and there may be some deviation. Therefore, as long as the extending direction of the silicon active layer of the above-mentioned threshold compensation transistor T3 and the second direction satisfy the substantially parallel condition, they are all within the protection scope of the present invention. For example, the above identity can enable parallel processing within the allowable error range.

[0067] Exemplarily, as shown in FIGS. 5a and 5b, the first insulating layer 710 is formed on the silicon semiconductor layer 500 to protect the silicon semiconductor layer 500. As shown in FIGS. 3, 4b, and 5a to 6, the first conductive layer 100 of the pixel driving circuit 0121 is shown. The first conductive layer 100 is disposed on the side of the first insulating layer 710 away from the base substrate 1000 so as to be insulated from the silicon semiconductor layer 500. The first conductive layer 100 may include a plurality of scanning lines arranged at intervals, a plurality of emission control lines EM arranged at intervals, the gate CC2a of the driving transistor T1, the gate T2-G of the data writing transistor T2, the gate T3-G of the threshold compensation transistor T3, the gate T4-G of the first emission control transistor T4, the gate T5-G of the second emission control transistor T5, the gate T6-G of the initialization transistor T6, the gate T7-G of the second reset transistor T7, and the first gate T8-G1 of the oxide transistor T8. Exemplarily, the plurality of scanning lines may include, for example, a plurality of first scanning lines GA1 arranged at intervals, a plurality of second scanning lines GA2, a plurality of third scanning lines GA3, and a plurality of fourth scanning lines GA4. For example, one row of sub-pixels corresponds to one first scanning line GA1, one second scanning line GA2, one third scanning line GA3, one fourth scanning line GA4, and one emission control line EM.

[0068] For example, as shown in FIGS. 3 to 4b, the gate T2-G of the data write transistor T2 may be a first portion where the third scanning line GA3 overlaps the silicon semiconductor layer 500. The orthographic projection of the third scanning line GA3 on the base substrate 1000 and the orthographic projection of the first channel region T3-A of the silicon active layer of the threshold compensation transistor T3 on the base substrate 1000 have a third overlapping region, and the portion of the scanning line GA3 located in the third overlapping region is between the gate T3-G of the threshold compensation transistor T3 and the third scanning line GA3. That is, the gate T3-G of the threshold compensation transistor T3 may be a second portion where the third scanning line GA3 overlaps the silicon semiconductor layer 500. The orthographic projection of the light emission control line EM on the base substrate 1000 and the first channel region T4-A of the silicon active layer of the first light emission control transistor T4 have a fourth overlapping region, and the portion of the light emission control line EM located in the fourth overlapping region is the gate T4-G of the first light emission control transistor T4. That is, the gate T4-G of the first light emission control transistor T4 is a first portion where the light emission control line EM overlaps the silicon semiconductor layer 500. The orthographic projection of the light emission control line EM on the base substrate 1000 and the first channel region T5-A of the silicon active layer of the second light emission control transistor T5 have a fifth overlapping region, and the portion of the light emission control line EM located in the fifth overlapping region is the gate T5-G of the second light emission control transistor T5, that is, the gate T5-G of the second light emission control transistor T5 is a second portion where the light emission control line EM overlaps the silicon semiconductor layer 500.

[0069] Furthermore, the orthographic projection of the first scanning line GA1 on the base substrate 1000 and the orthographic projection of the first channel region T6-A of the silicon active layer of the initialization transistor T6 on the base substrate 1000 have a first overlapping region. The portion of the first scanning line GA1 located in the first overlapping region is the gate T6-G of the initialization transistor T6. That is, the gate T6-G of the initialization transistor T6 is the first portion where the first scanning line GA1 overlaps with the silicon semiconductor layer 500, and the gate T7-G of the second reset transistor T7 is the first portion where the fourth scanning line GA4 overlaps with the silicon semiconductor layer 500. The first gate T8-G1 of the oxide transistor T8 is the first portion where the second scanning line GA2 overlaps with the silicon semiconductor layer 500. Also, the gate CC2a of the driving transistor T1 can be set as an electrode plate of the storage capacitor CST. It can also be said that the gate CC2a of the driving transistor T1 and one electrode plate of the storage capacitor CST are integrated. Furthermore, the orthographic projection of the second scanning line GA2 on the base substrate 1000 and the orthographic projection of the second channel region T8-A of the oxide active layer of the oxide transistor T8 on the base substrate 1000 have a second overlapping region. And the portion of the second scanning line GA2 located in the second overlapping region is the gate of the oxide transistor T8-A.

[0070] Exemplarily, as shown in FIGS. 3 and 4b, the first scanning line GA1, the second scanning line GA2, the third scanning line GA3, the emission control line EM, and the fourth scanning line GA4 extend along the first direction F1. Also, the first scanning line GA1, the second scanning line GA2, the third scanning line GA3, the emission control line EM, and the fourth scanning line GA4 are arranged along the second direction F2. Here, in the same sub-pixel, the orthographic projection of the second scanning line GA2 on the base substrate 1000 is located between the orthographic projection of the first scanning line GA1 on the base substrate 1000 and the orthographic projection of the third scanning line GA3 on the base substrate 1000. On the base substrate 1000. The orthographic projection of the third scanning line GA3 on the base substrate 1000 is located between the orthographic projection of the second scanning line GA2 on the base substrate 1000 and the orthographic projection of the emission control line EM on the base substrate 1000. The orthographic projection of the fourth scanning line GA4 on the base substrate 1000 is arranged on the side of the orthographic projection of the emission control line EM on the base substrate 1000 that is away from the orthographic projection of the third scanning line GA3 on the base substrate 1000. Further, in the same sub-pixel, the orthographic projection of the oxide active layer of the oxide transistor T8 on the base substrate 1000 is located between the orthographic projections of the first scanning line GA1 and the third scanning line GA3 on the base substrate 1000. And the orthographic projection of the second scanning line GA2 on the base substrate 1000 does not overlap with the orthographic projection of the silicon active layer of the threshold compensation transistor T3 on the base substrate 1000 and the orthographic projection of the silicon active layer of the initialization transistor T6 on the base substrate 1000, respectively. Of course, the orthographic projection of the second scanning line GA2 on the base substrate 1000 may also overlap with the orthographic projection of the first region of the silicon active layer of the threshold compensation transistor T3 on the base substrate 1000. It is also possible to overlap the orthographic projection of the second scanning line GA2 on the base substrate 1000 with the orthographic projection of the second region of the silicon active layer of the initialization transistor T6 on the base substrate 1000. Of course, these setting methods can be designed and determined according to the actual application requirements and are not limited herein.

[0071] Exemplarily, as shown in FIGS. 3 and 4b, in the same sub-pixel, the orthographic projection of the radiation control line EM on the base substrate 1000 is disposed on the side of the orthographic projection of the third scanning line GA3 on the base substrate 1000 away from the orthographic projection of the second scanning line GA2 on the base substrate 1000. The orthographic projection of the fourth scanning line GA3 on the base substrate 1000 is disposed on the side of the orthographic projection of the light emission control line EM on the base substrate 1000 away from the orthographic projection of the second scanning line GA2 on the base substrate 1000. The orthographic projections of both the silicon active layer and the gate of the driving transistor T1 on the base substrate 1000 are disposed between the orthographic projection of the light emission control line EM on the base substrate 1000 and the orthographic projection of the third scanning line GA2.

[0072] Exemplarily, as shown in FIGS. 3 and 4b, in the second direction F2, the orthographic projection of the gate CC2a of the driving transistor T1 on the base substrate 1000 is disposed between the orthographic projection of the third scanning line GA3 on the base substrate 1000 and the orthographic projection of the light emission control line EM on the base substrate 1000. And in the second direction F2, the gates T2-G of the data writing transistor T2, the gates T3-G of the threshold compensation transistor T3, the gates T6-G of the initialization transistor T6, and the first gate T8-G1 of the oxide transistor T8 are all disposed on the gate side of the driving transistor T1 away from the light emission control line EM, and the gates T7-G of the second reset transistor T7, the gates T4-G of the first light emission control transistor T4, and the gates T5-G of the second light emission control transistor T5 are all disposed on the side of the gate of the driving transistor T1 away from the first scanning line GA1.

[0073] For example, in some embodiments, as shown in FIGS. 3 and 4b, in the first direction F1, both the gate T2-G of the data writing transistor T2 and the gate T4-G of the first light emission control transistor T4 are disposed on the third side of the gate of the driving transistor T1. The gate T3-G of the threshold compensation transistor T3, the gate T5-G of the second light emission control transistor T5, the gate T6-G of the initialization transistor T6, and the gate T7-G of the second reset transistor T7 are all disposed on the fourth side of the gate of the driving transistor T1. Here, the third side and the fourth side of the gate of the driving transistor T1 are on the opposite side of the first direction F1 of the gate of the driving transistor T1. Also, the first gate T8-G1 of the oxide transistor T8 and the gate of the driving transistor T1 are linearly arranged along the first direction F1. For example, the center of the first gate T8-G1 of the oxide transistor T8 and the center of the gate of the driving transistor T1 are arranged on a straight line along the first direction F1.

[0074] Exemplarily, as shown in FIGS. 5a and 5b, the second insulating layer 720 is formed on the first conductive layer 100 to protect the first conductive layer 100. As shown in FIGS. 3, 4c, and 5a - 6, the oxide semiconductor layer 600 of the pixel driving circuit 0121 is shown. The oxide semiconductor layer 600 is disposed on the side of the second insulating layer 720 away from the base substrate 1000. Here, the oxide semiconductor layer 600 can be formed by patterning an oxide semiconductor material. Exemplarily, the oxide semiconductor material can be, for example, Indium Gallium Zinc Oxide (IGZO).

[0075] Further, the oxide semiconductor layer 600 may include the oxide active layer of the oxide transistor T8. Here, the oxide active layer has a third region, a fourth region, and a second channel region T8-A located between the third region and the fourth region. For example, FIG. 4c shows the second channel region T8-A of the oxide transistor T8. It should be noted that the above-mentioned third region and fourth region may be regions of the oxide semiconductor layer 600 doped with n-type impurities or p-type impurities for forming a conductive region. Therefore, the third region and the fourth region can be used as the source electrode region and the drain electrode region of the oxide active layer for electrical connection.

[0076] Exemplarily, as shown in FIGS. 3 and 4c, the oxide active layer of the oxide transistor T8 extends substantially linearly along the second direction F2. For example, the extending direction of the oxide active layer of the oxide transistor T8 is substantially parallel to the second direction F2. In an actual process, due to limitations of process conditions, etc., the extending direction of the oxide active layer of the oxide transistor T8 may not be completely parallel to the second direction, and there may be some deviation. Therefore, the extending direction of the oxide active layer of the above-mentioned oxide material transistor T8 and the second direction only need to satisfy the substantially parallel condition, and both are within the protection scope of the present invention. For example, the above identity can enable parallel processing within an allowable error range.

[0077] Exemplarily, as shown in FIGS. 3, 4d, and 5a to 6, in the same sub-pixel, the orthographic projection of the auxiliary scanning line FGA on the base substrate 1000 and the orthographic projection of the second scanning line GA2 on the base overlap. And the auxiliary scanning line FGA and the second scanning line GA2 within the same sub-pixel are electrically connected.

[0078] Exemplarily, the auxiliary scanning line FGA and the second scanning line GA2 within the same sub-pixel can be electrically connected at the edge of the effective display area via a via hole. For example, they can be electrically connected in the effective display area via a via hole.

[0079] Exemplarily, as shown in FIGS. 5a and 5b, a fourth insulating layer 740 is formed on the second conductive layer 200 described above to protect the second conductive layer 200. As shown in FIGS. 3, 4e, and 5a to 6, a third conductive layer 300 of the pixel driving circuit 0121 is shown. The third conductive layer 300 is disposed on the side of the fourth insulating layer 740 away from the base substrate 1000. The third conductive layer 300 may include a plurality of data lines VD, a plurality of first power line portions Vdd, a plurality of first connection portions 310, a plurality of second connection portions 320, a plurality of third connection portions 330, and a plurality of fourth connection portions 340 disposed at intervals. Here, the data lines VD, the first power line portions Vdd, the first connection portions 310, the second connection portions 320, the third connection portions 330, and the fourth connection portions 340 are disposed at intervals from each other.

[0080] Exemplarily, as shown in FIGS. 3, 4e, and 5a to 6, the data line VD and the first power line portion Vdd are arranged along the first direction, and the data line VD and the first power line extend along the first direction. One sub-pixel is provided with one first connection portion 310, one second connection portion 320, a third connection portion 330, and one fourth connection portion 340. For example, one column of sub-pixels corresponds to one first power line portion Vdd, and one column of sub-pixels corresponds to one data line VD. Further, in the same sub-pixel, the orthographic projection of the first power line portion Vdd on the base substrate 1000 is located between the orthographic projection of the data line VD on the base substrate 1000 and the orthographic projection of the second connection portion 320 on the base substrate 1000. And in the same column of sub-pixels, the orthographic projections of the silicon active layer of the initialization transistor T6 and the silicon active layer of the threshold compensation transistor T3 on the base substrate 1000 are both arranged on the side of the orthographic projection of the oxide active layer of the oxide transistor T8 on the base substrate 1000 that is away from the orthographic projection of the data line VD on the base substrate 1000. For example, the orthographic projection of the silicon active layer of the initialization transistor T6 on the base substrate 1000 is the first orthographic projection, and the orthographic projection of the silicon active layer of the threshold compensation transistor T3 on the base substrate 1000 is the second orthographic projection. The orthographic projection of the oxide active layer of the oxide transistor T8 on the base substrate 1000 is the third orthographic projection, and the orthographic projection of the data line VD on the base substrate 1000 is the fourth orthographic projection. The first orthographic projection is arranged on the side of the third orthographic projection away from the fourth orthographic projection. The second orthographic projection is also arranged on the side of the third orthographic projection away from the fourth orthographic projection. In this way, the first orthographic projection and the second orthographic projection can be arranged on the side of the third orthographic projection away from the fourth orthographic projection.

[0081] Exemplarily, as shown in FIGS. 5a and 5b, a fifth insulating layer 750 is formed on the third conductive layer 300 described above to protect the third conductive layer 300. As shown in FIGS. 3, 4f, and 5a - 6, a fourth conductive layer 400 of the pixel driving circuit 0121 is shown. The fourth conductive layer 400 is disposed on the side of the fifth insulating layer 750 away from the base substrate 1000. The fourth conductive layer 400 may include a plurality of initialization lines VINIT arranged at intervals from each other, a plurality of second power line portions 410 arranged at intervals from each other, and a plurality of transfer portions 420. Here, the initialization line VINIT, the second power line portion 410, and the transfer portion 420 are arranged at intervals from each other. Here, one sub - pixel includes the second power line portion 410 and the transfer portion 420. One row of sub - pixels corresponds to one initialization line VINIT. Exemplarily, in the same sub - pixel, the orthographic projection of the initialization line VINIT on the base substrate 1000 is located on the orthographic projection side of the first scanning line GA1 on the base substrate 1000 away from the orthographic projection of the second scanning line GA2 on the side surface of the base substrate 1000.

[0082] FIG. 5a is a schematic cross - sectional view of the layout structure shown in FIG. 3 along the AA' direction. FIG. 5b is a schematic cross - sectional view of the layout structure shown in FIG. 3 along the BB' direction. FIG. 5c is a schematic cross - sectional view of the layout structure shown in FIG. 3 along the CC' direction. FIG. 5d is a schematic partial cross - sectional structure view of the schematic layout structure shown in FIG. 3. FIG. 6 is a schematic view of the layout structure of a two - row and two - column pixel driving circuit of sub - pixels in an embodiment of the present invention. Here, FIG. 5d shows only the oxide transistor T8 and the second light emission control transistor T5 in the pixel driving circuit 0121.

[0083] As shown in FIGS. 5A to 6, the first buffer layer 810 is provided between the silicon semiconductor layer 500 and the base substrate 1000, the first insulating layer 710 is provided between the silicon semiconductor layer 500 and the first conductive layer 100, the second insulating layer 720 is provided between the first conductive layer 100 and the oxide semiconductor layer 600, the third insulating layer 730 is provided between the oxide semiconductor layer 600 and the second conductive layer 200, the fourth insulating layer 740 is provided between the second conductive layer 200 and the third conductive layer 300, and the fifth insulating layer 750 is provided between the third conductive layer 300 and the fourth conductive layer 400. Further, the first planarization layer 760 is provided on the side of the fourth conductive layer 400 away from the base substrate 1000, and the first electrode layer is provided on the side of the first planarization layer 760 away from the base substrate 1000. The pixel definition layer 770, the light-emitting functional layer 781, and the second electrode layer 782 are sequentially arranged on the side of the first electrode layer away from the base substrate 1000. Here, the first electrode layer may include a plurality of first electrodes 783 arranged at intervals from each other. Further, the first electrode 783 is electrically connected to the transfer portion 420 through a via hole penetrating the first planarization layer 760. It should be noted that FIGS. 5A and 5B do not show the via hole penetrating the first planarization layer 760.

[0084] Exemplarily, the insulating layer may be an organic material or an inorganic material (such as SiOx, SiNx, etc.) not limited to this specification.

[0085] Exemplarily, as shown in FIG. 5d, the first buffer layer 810 may include stacked first sub-buffer layer 811, second sub-buffer layer 812, and third sub-buffer layer 813. Here, the first sub-buffer layer 811 is disposed between the base substrate 1000 and the second sub-buffer layer 812, and the third sub-buffer layer 813 is disposed between the second sub-buffer layer 812 and the silicon semiconductor layer 500. Exemplarily, at least one of the first sub-buffer layer 811, the second sub-buffer layer 812, and the third sub-buffer layer 813 may be configured as an inorganic material or may be configured as an organic material. For example, the first sub-buffer layer 811 may be configured as an organic material such as polyimide (PI), and the second sub-buffer layer 812 and the third sub-buffer layer 813 may be configured as inorganic materials such as SiOx, SiNx, etc.

[0086] Exemplarily, as shown in FIG. 5d, the second insulating layer 720 may include stacked second sub-insulating layer 721 and second buffer layer 722. The second sub-insulating layer 721 is disposed between the first conductive layer 100 and the second buffer layer 722, and the second buffer layer 722 is disposed between the second sub-insulating layer 721 and the oxide semiconductor layer 600. Exemplarily, the second sub-insulating layer 721 may be made of an inorganic material such as silicon nitride, silicon oxide, and silicon nitride, and may be used in a specific implementation. The second buffer layer 722 can be configured as an inorganic material such as silicon nitride, silicon oxide, etc., and silicon oxide can be used in a specific implementation.

[0087] Exemplarily, as shown in FIG. 5d, the fifth insulating layer 750 may include a stacked passivation layer (PVX) 751 and a second planarization layer 752, where the passivation layer 752 is disposed between the third conductive layer 300 and the second planarization layer 752. The second planarization layer 752 is disposed between the passivation layer 752 and the fourth conductive layer 400. Exemplarily, the material of the passivation layer 751 may be an inorganic material such as silicon oxide or silicon nitride, and the second planarization layer 752 may be an organic material.

[0088] Exemplarily, the sub-pixel spx includes first connection through-holes 511, 512, 513, 514, 515, and 516. The sub-pixel spx includes a second connection through-hole 521. The sub-pixel spx includes third connection through-holes 531 and 532. The sub-pixel spx includes a fourth connection through-hole 541. The sub-pixel spx includes fifth connection through-holes 551, 552, and 553. Here, the first connection through-holes 511, 512, 513, 514, 515, and 516 penetrate through the first insulating layer 710, the second insulating layer 720, the third insulating layer 730, and the fourth insulating layer 740. The second connection through-hole 521 penetrates through the second insulating layer 720, the third insulating layer 730, and the fourth insulating layer 740. The third connection through-holes 531 and 532 penetrate through the third insulating layer 730 and the fourth insulating layer 740. The fourth connection through-hole 541 penetrates through the fourth insulating layer 740. The fifth connection through-holes 551, 552, and 553 penetrate through the fifth insulating layer 750. Also, the above-mentioned connection through-holes are arranged at intervals. Exemplarily, the third connection through-hole 531 functions as the first via hole, the first connection through-hole 513 functions as the second via hole, and the first connection through-hole 512 functions as the third via hole.

[0089] At least one fifth connection through-hole 551. Exemplarily, the first connection through-holes 511, 512, 513, 514, 515, and 516 in the sub-pixel may each be provided with one, or two or more may be provided respectively. In an actual application, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0090] Exemplarily, the second connection through-hole 521 of the sub-pixel may be provided with one, or two or more may be provided. In an actual application, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0091] Exemplarily, the third connection through-holes 531 and 532 in the sub-pixel may each have one, or each may have two or more. In an actual application, the design can be determined according to the requirements of the actual application environment, and is not limited thereto. Exemplarily, the fourth connection through-hole 541 of the sub-pixel may each be provided with one, or two or more may be provided respectively. In an actual application, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0092] Exemplarily, the fifth connection through-holes 551, 552, and 553 of the sub-pixel may each be provided with one, or two or more may be provided respectively. In an actual application, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0093] Note that the positional arrangement relationship of the transistors in each sub-pixel spx is not limited to the examples shown in FIGS. 3 to 4f, and the positions of the above transistors can be specifically set according to the actual application requirements.

[0094] It should be noted that the first direction F1 can be the row direction of the sub-pixels, and the second direction F2 can be the column direction of the sub-pixels. Alternatively, the first direction F1 can also be the column direction of the sub-pixels, and the second direction F2 can be the row direction of the sub-pixels. In actual applications, it can be set according to the actual application requirements and is not limited thereto.

[0095] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, the first region T6-S of the silicon active layer of the initialization transistor T6 functions as the first electrode of the initialization transistor T6, and the second region T6-D of the silicon active layer of the initialization transistor T6 functions as the second electrode of the initialization transistor T6. The third region T8-S of the oxide active layer of the oxide transistor T8 functions as the first electrode of the oxide transistor T8, and the fourth region T8-S of the oxide active layer of the oxide transistor T8 functions as the second electrode of the oxide transistor T8. Further, in the same sub-pixel, the second region T6-D of the silicon active layer of the initialization transistor T6 is electrically connected to the third region T8-S of the oxide active layer of the oxide transistor T8, and the fourth region T8-D of the oxide transistor T8 active layer is electrically connected to the gate of the driving transistor T1. In this way, an oxide active layer can be provided between the gate of the driving transistor and the second region T6-D of the silicon active layer of the initialization transistor T6, and the signal flow path between the gate of the driving transistor and the second region T6-D of the silicon active layer of the initialization transistor T6 flows through the oxide active layer. Since the leakage current of a transistor using a metal oxide semiconductor material as the active layer is small, the off-state current of the oxide transistor T8 is small or can be ignored. Therefore, the influence of the leakage current on the gate voltage of the driving transistor can be reduced, and the stability of the gate voltage of the driving transistor can be improved.

[0096] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, a first region T3-S of the silicon active layer of the threshold compensation transistor T3 functions as a first electrode of the threshold. A second region T3-D of the silicon active layer of the threshold compensation transistor T3 functions as a second electrode of the threshold compensation transistor T3. A first region T1-S of the silicon active layer of the drive transistor T1-D functions as a first electrode of the drive transistor T1. A second region T1-D of the silicon active layer of the drive transistor T1-D functions as a second electrode of the drive transistor T1. Further, in the same sub-pixel, the second region T3-D of the silicon active layer of the threshold compensation transistor T3 is electrically connected to a third region T8-S of the oxide active layer of the oxide transistor T8. The first region T3-S of the silicon active layer of the threshold compensation transistor T3 is electrically connected to the second region T1-D of the silicon active layer of the drive transistor T1-D. In this way, since an oxide active layer can be provided between the gate of the drive transistor and the second region T3~D of the silicon active layer of the threshold compensation transistor T3, the signal flow path between the gate of the drive transistor and the second region T3-D of the silicon active layer of the threshold compensation transistor T3 flows through the oxide active layer. Since the leakage current of a transistor using a metal oxide semiconductor material as the active layer is small, the off-state current of the oxide transistor T8 is small or negligible. Therefore, the influence of the leakage current on the gate voltage of the drive transistor can be reduced, and the stability of the gate voltage of the drive transistor can be improved.

[0097] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3, 4e, and 5a to 6, the first connection portion 310 may include a first sub-connection portion 311 and a second sub-connection portion 312 that are electrically connected to each other. Here, the first terminal of the first sub-connection portion 311 is electrically connected to the third region T8-S of the oxide active layer of the oxide transistor T8 through a first via hole (i.e., the third connection through hole 531). The second terminal of the first sub-connection portion 311 is electrically connected to the second region T6-D of the silicon active layer of the initialization transistor T6 through a second via hole (i.e., the first connection through hole 513). The first terminal of the second sub-connection portion 312 is electrically connected to the second region T3-D of the silicon active layer of the threshold compensation transistor T3 through a third via hole (i.e., the first connection through hole 512). The second terminal of the second sub-connection portion 312 is connected to the first sub-connection portion.

[0098] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 and 4e, the first sub-connection portion 311 may extend in a first direction. For example, the first sub-connection portion 311 can be linearly extended along the first direction. That is, the extending direction of the first sub-connection portion 311 can be substantially parallel to the first direction F1. In the actual process, due to restrictions on process conditions and the like, the extending direction of the first sub-connection portion 311 may not be completely parallel to the first direction F1, and there may be some deviation. As long as the extending direction of the first sub-connection portion 311 and the first direction F1 satisfy the condition of being substantially parallel, they all belong to the protection scope of the present invention. For example, the above identity can enable parallel processing within an allowable error range.

[0099] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 and 4e, the second sub-connection portion 312 can extend in the second direction F2. For example, the second sub-connection portion 312 can extend linearly along the second direction F2. That is, the extending direction of the second sub-connection portion 312 can be substantially parallel to the second direction F2. In actual processes, due to restrictions such as process conditions, the extending direction of the second sub-connection portion 312 cannot be completely parallel to the second direction F2, and there may be some deviation. As long as the extending direction of the second sub-connection portion 312 and the second direction F2 satisfy the condition of being substantially parallel, both of them belong to the protection scope of the present invention. For example, the above identity can enable parallel processing within an allowable error range.

[0100] In a specific implementation, in an embodiment of the present invention, as shown in FIG. 3, the shape of the orthographic projection of the first connection portion 310 on the base substrate 1000 can also be substantially T-shaped. Alternatively, the third connection through-hole 531 functions as the first through-hole, the first connection through-hole 513 functions as the second via hole, and the first connection through-hole 512 functions as the third via hole. In the same sub-pixel, the first via hole, the second via hole, and the third via hole can be arranged in a substantially triangular shape. Further, in the same sub-pixel, the first via hole and the second via hole extend substantially linearly along the first direction F1. The orthographic projection of the third via hole on the straight line where the first via hole and the second via hole are arranged is near the second via hole. In actual processes, due to restrictions of process conditions or other factors, the shape of the orthographic projection of the first connection portion 310 on the base substrate 1000 is not completely T-shaped, and the first via and the second via hole do not extend completely linearly along the first direction F1, so there may be some deviation. Therefore, as long as the above method satisfies the condition of being substantially parallel, it belongs to the protection scope of the present invention. For example, the above method may be permitted within the allowable range.

[0101] In a specific implementation, in an embodiment of the present invention, as shown in FIG. 3, in the same row of sub-pixels, the orthographic projection of the first sub-connection portion 311 on the base substrate 1000 is disposed between the orthographic projection of the first scanning line GA1 on the base substrate 1000 and the orthographic projection of the second scanning line GA2 on the base substrate 1000, and the orthographic projection of the second sub-connection portion 312 on the base substrate 1000 and the orthographic projection of the second scanning line GA2 on the base substrate 1000 have an overlapping region. Exemplarily, in the sub-pixels of the same row, the orthographic projection of the first via hole (i.e., the third connection through hole 531) on the base substrate 1000 and the orthographic projection of the second via hole (i.e., the first connection through hole 513) on the base substrate 1000 are disposed substantially linearly along the first direction F1.

[0102] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3, 4d, and 5a to 6, the first region T4-S of the silicon active layer of the first light emission control transistor T4 functions as the first electrode of the first light emission control transistor T4, the second region T4-D of the silicon active layer of the first light emission control transistor T4 functions as the second electrode of the first light emission control transistor T4, the first region T4-S of the silicon active layer of the second light emission control transistor T5 functions as the first electrode of the second light emission control transistor T5, and the second region T4-D of the silicon active layer of the second light emission control transistor T5 functions as the second electrode of the second light emission control transistor T5. Exemplarily, the second region T4-D of the silicon active layer of the first light emission control transistor T4 is electrically connected to the first region T1-S of the silicon active layer of the driving transistor T1. The first region T5-S of the silicon active layer of the second light emission control transistor T5 is electrically connected to the second region T1-D of the silicon active layer of the driving transistor T1. The second region T5-D of the silicon active layer of the second light emission control transistor T5 is electrically connected to the first electrode of the light emitting device through the fifth via hole.

[0103] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, the second connection portion 320 may include a first conductive portion 321 and a first main body portion 322. Here, the first conductive portion 321 is electrically connected to a fourth region T8-D of the oxide active layer of the oxide transistor T8 through a sixth via hole (i.e., the third connection through hole 532). Also, the orthographic projection of the first conductive portion 321 on the base substrate 1000 has a region that overlaps with the orthographic projection of the third scanning line GA3 on the base substrate 1000 and the orthographic projection of the fourth region T8-D of the oxide active layer of the oxide transistor T8 on the base substrate 1000, respectively. Further, the orthographic projection of the first main body portion 322 on the base substrate 1000 has a region that overlaps with the orthographic projection of the gate of the driving transistor T1 on the base substrate 1000, and the orthographic projection of the first main body portion 322 on the base substrate 1000 does not overlap with the orthographic projection of the third scanning line GA3 on the base substrate 1000.

[0104] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, in the same sub-pixel, the orthographic projection of the first main body portion 322 on the base substrate 1000 and the orthographic projection of the first region T5-S of the second light emission control transistor T5 on the base substrate 1000 do not overlap at least partially. Exemplarily, the orthographic projection of the first main body portion 322 on the base substrate 1000 and the orthographic projection of the first region T5-S of the second light emission control transistor T5 on the base substrate 1000 may be tangent. Also, it is possible that the orthographic projection of the first main body portion 322 on the base substrate 1000 and the orthographic projection of the first region T5-S of the second light emission control transistor T5 on the base substrate 1000 do not overlap. Of course, the present disclosure includes but is not limited to this.

[0105] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, in the same sub-pixel, the orthographic projection of the first main body portion 322 on the base substrate 1000 and the orthographic projection of the emission control line EM on the base substrate 1000 are tangent, the orthographic projection of the first main body portion 322 on the base substrate 1000 is close to the orthographic projection of the first power line portion Vdd on the base substrate 1000, and the orthographic projection of the first main body portion 322 on the base substrate 1000 is close to the orthographic projection of the third scanning line GA3 on the base substrate 1000.

[0106] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, in the same sub-pixel, the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 respectively covers the orthographic projection of the gate of the driving transistor T1 on the base substrate 1000 and the orthographic projection of the first main body portion 322 on the base substrate 1000. And, the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 and the orthographic projection of the seventh via hole (i.e., the second connection through hole 521) on the base substrate 1000 do not overlap. And, the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 and the orthographic projection of the third scanning line GA3 on the base substrate 1000 do not overlap.

[0107] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, in the same sub-pixel, the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 and the orthographic projection of the first power line portion Vdd on the base substrate 1000 have an overlapping region, and the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 and the orthographic projection of the data line VD on the base substrate 1000 do not overlap. Thereby, it is possible to prevent the signal transmitted on the data line VD from interfering with the signal of the storage conductive portion CC1a. Also, since the first power line portion Vdd transmits a fixed voltage, the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 and the orthographic projection of the first power line portion Vdd on the base substrate 1000 have an overlapping region. By expanding the region of the storage conductive portion CC1a, signal interference can also be reduced.

[0108] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, in the same sub-pixel, the orthographic projections of the eighth via hole (i.e., the fourth connection through hole 541) on the base substrate 1000, the fourth via hole (i.e., the first connection through hole 515), and the fifth via hole (i.e., the first connection through hole 516) are all located between the orthographic projection of the emission control line EM on the base substrate 1000 and the orthographic projection of the fourth scanning line GA4 on the base substrate 1000.

[0109] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, in the same row of sub-pixels, the orthographic projections of the eighth via hole (i.e., the fourth connection through hole 541) on the base substrate 1000, the fourth via hole (i.e., the first connection through hole 515), and the fifth via hole (i.e., the first connection through hole 516) are arranged on the same straight line substantially along the first direction F1.

[0110] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, the second power cord portion 410 may include a second conductive portion 411 and a second main body portion 412 that are electrically connected to each other. Here, the second conductive portion 411 is electrically connected to the first power line portion Vdd through at least one fifth connection through hole 551. Also, the orthographic projection of the second main body portion 412 on the base substrate 1000 covers the orthographic projection of the first main body portion 322 on the base substrate 1000. In this way, the second power line portion within the same sub-pixel can be electrically connected to the memory conductive portion CC1a.

[0111] In a specific implementation, in an embodiment of the present invention, as shown in FIGS. 3 to 6, the sub-pixel may further include a tenth via hole (i.e., the fifth through hole 551 for connection), and the second conductive portion 411 may further include a first sub-conductive portion 4111 and a second sub-conductive portion 4112. Here, the first sub-conductive portion 4111 extends along a first direction F1, and the second sub-conductive portion 4112 extends along a second direction F2. Here, the first terminal of the first sub-conductive portion 4111 is electrically connected to the first power line portion Vdd through the tenth via hole (i.e., the fifth through hole 551 for connection). The second terminal of the first sub-conductive portion 4111 is electrically connected to the first terminal of the second sub-conductive portion 4112. The second terminal of the second sub-conductive portion 4112 is electrically connected to the second main body portion 412. Further, the orthographic projection of the third scanning line GA3 on the base substrate 1000 and the orthographic projection of the first sub-conductive portion 4111 on the base substrate 1000 have an overlapping region, and the orthographic projection of the second terminal of the first sub-conductive portion 4111 on the base substrate 1000 and the orthographic projection of the second channel region T8-A of the oxide semiconductor layer of the oxide transistor T8 on the base substrate 1000 have an overlapping region. And the orthographic projection of the second sub-conductive portion 4112 on the base substrate 1000 has an overlapping region with the orthographic projection of the sixth via hole on the base substrate 1000 and the orthographic projection of the third scanning line GA3 on the base substrate 1000.

[0112] Note that the second power line part 410, the memory conductive part CC1a, and the first power line part Vdd within the same subpixel are electrically connected to form the first electrode of the memory capacitor CST. The potentials of the second power line part 410 and the memory conductive part CC1a are the same, and both are the potential of the first power supply line part Vdd. Also, the gate CC2a of the driving transistor T1 is electrically connected to the second connection part 320 to form the second electrode of the memory capacitor CST, so the potential of the gate CC2a of the driving transistor T1 and the potential of the second connection part 320 are the same. And both are the potential of the gate of the driving transistor T1. In this way, since the storage capacitor can include four stacked substrates, the area of the memory capacitor CST can be increased without increasing the occupation, and the capacitance value of the memory capacitor CST can be increased.

[0113] In a specific embodiment, the second planarization layer 752 at the corresponding positions of the second power line part 410 and the second connection part 320 can be thinned or removed, and as a result, the capacitance value of the memory capacitor CST can be improved.

[0114] Based on the same inventive concept, an embodiment of the present invention also provides a display device including the above display panel provided by the embodiment of the present invention. The implementation of the display device can refer to the embodiment of the above display panel, and the description will not be repeated here.

[0115] In a specific embodiment, in an embodiment of the present invention, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, etc. A navigator, etc. Other essential components of the display device should be understood by those skilled in the art and will not be repeated here and should not be used as a limitation of the present invention.

[0116] Preferred embodiments of the present invention have been described. Those skilled in the art can make additional changes and modifications to these embodiments once they have acquired the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications within the scope of the present invention.

[0117] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, these modifications and variations of the embodiments of the present invention are intended to be included in the present invention if they are within the scope of the claims of the present invention and their equivalent technologies.

Claims

1. A display panel, wherein the display panel includes a base substrate, a silicon semiconductor layer, a first conductive layer, an oxide semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, the base substrate has a plurality of sub-pixels, at least one of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit includes a driving transistor, an oxide transistor, and a storage capacitor, the silicon semiconductor layer is disposed on the base substrate, and the silicon semiconductor layer includes a silicon active layer of the driving transistor, the first conductive layer is disposed on a side of the silicon semiconductor layer away from the base substrate, and the first conductive layer includes a gate of the driving transistor, the oxide semiconductor layer is disposed on a side of the first conductive layer away from the base substrate, and the oxide semiconductor layer includes an oxide active layer of the oxide transistor, the second conductive layer is disposed on a side of the first conductive layer away from the base substrate, and the second conductive layer includes a storage conductive portion, the third conductive layer is disposed on a side of the second conductive layer away from the base substrate, and the third conductive layer includes a first power line portion disposed at intervals and a second connection portion. In the same sub-pixel, a second electrode of the oxide transistor is electrically connected to a gate of the driving transistor through the second connection portion, and the first power line portion is electrically connected to the storage conductive portion, the fourth conductive layer is disposed on a side of the third conductive layer away from the base substrate, and the fourth conductive layer includes a second power line portion. In the same sub-pixel, the first power line portion is electrically connected to the second power line portion, In the same sub-pixel, a positive projection of the second power line portion on the base substrate covers a positive projection of the second connection portion on the base substrate, and the positive projection of the second power line portion on the base substrate extends beyond edges on both sides in a second direction of a positive projection of a gate of the driving transistor on the base substrate and extends beyond edges on both sides in the second direction of a positive projection of the storage conductive portion on the base substrate. A display panel characterized by this.

2. The first conductive layer further includes a plurality of third scanning lines disposed at intervals, the third scanning lines extend in a first direction and are arranged in a second direction, The sub-pixel further includes a data writing transistor, and a gate of the data writing transistor is electrically connected to the third scanning line. The display panel according to claim 1, wherein a positive projection of the third scanning line on the base substrate and a positive projection of the second power line portion on the base substrate have an overlapping region. **Claim 3** The second conductive layer further includes a plurality of auxiliary scanning lines arranged at intervals. In the same sub-pixel, a positive projection of the auxiliary scanning line on the base substrate and a positive projection of an oxide active layer of the oxide transistor on the base substrate have a sixth overlapping region, and a positive projection of the second power line portion on the base substrate overlaps with the sixth overlapping region. The display panel according to claim 2, characterized in that. **Claim 4** The sub-pixel further includes a first light emission control transistor and a second light emission control transistor. The silicon semiconductor layer further includes a silicon active layer of the first light emission control transistor and a silicon active layer of the second light emission control transistor. The first conductive layer further includes a gate of the first light emission control transistor and a gate of the second light emission control transistor. In the same sub-pixel, the first power line portion is electrically connected to a first electrode of the first light emission control transistor, a second electrode of the first light emission control transistor is electrically connected to a first electrode of the driving transistor, and a first electrode of the second light emission control transistor is electrically connected to a second electrode of the driving transistor. A second electrode of the second light emission control transistor is electrically connected to a first electrode of a light emitting device. The display panel according to claim 3, characterized in that. **Claim 5** The first conductive layer further includes a plurality of light emission control lines arranged at intervals. In the same sub-pixel, a positive projection of the light emission control line on the base substrate is arranged on a side of a positive projection of a gate of the driving transistor on the base substrate, which is away from a positive projection of the auxiliary scanning line on the base substrate. The display panel according to claim 4, wherein the light emission control line is electrically connected to the gate of the first light emission control transistor and the gate of the second light emission control transistor. **Claim 6** The orthographic projection of the second power line portion on the base substrate and the orthographic projection of the light emission control line on the base substrate have an overlapping region, and the display panel according to claim 5 is characterized in that.

7. The second connection portion includes a first conductive portion and a first main body portion that are electrically connected to each other, and the first conductive portion is electrically connected to the oxide active layer of the oxide transistor. The orthographic projection of the first main body portion on the base substrate and the orthographic projection of the gate of the drive transistor on the base substrate have an overlapping region, and the orthographic projection of the first main body portion on the base substrate and the orthographic projection of the third scanning line on the base substrate do not overlap, and the display panel according to claim 6 is characterized in that.

8. In the same sub-pixel, the minimum straight-line distance between the orthographic projection of the first main body portion on the base substrate and the orthographic projection of the first power line portion on the base substrate is smaller than the minimum straight-line distance between the orthographic projection of the first main body portion on the base substrate and the orthographic projection of the gate of the first light emission control transistor on the base substrate, and the display panel according to claim 7 is characterized in that.

9. The third conductive layer further includes a first connection portion disposed at an interval from the first power line portion and the second connection portion. In the same sub-pixel, the first connection portion is electrically connected to the oxide active layer of the oxide transistor, and the display panel according to claim 7 or claim 8 is characterized in that.

10. The distance between the first connection portion and the first conductive portion is greater than a threshold value, and the display panel according to claim 9 is characterized in that.

11. A display panel, The display panel includes a base substrate, a silicon semiconductor layer, a first conductive layer, an oxide semiconductor layer, a second conductive layer, and a third conductive layer. The base substrate has a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit includes a drive transistor, an initialization transistor, and an oxide transistor. The silicon semiconductor layer is disposed on the base substrate, and the silicon semiconductor layer includes a silicon active layer of the drive transistor. The first conductive layer is disposed on the side of the silicon semiconductor layer away from the base substrate, and the first conductive layer includes a gate of the driving transistor. The oxide semiconductor layer is disposed on the side of the first conductive layer away from the base substrate, and the oxide semiconductor layer includes an oxide active layer of the oxide transistor. The second conductive layer is disposed on the side of the first conductive layer away from the base substrate, and the second conductive layer includes a plurality of auxiliary scanning lines arranged at intervals. The auxiliary scanning lines extend along a first direction and are electrically connected to the gate of the oxide transistor. The third conductive layer is disposed on the side of the first conductive layer away from the base substrate, and the third conductive layer includes a first connection portion and a second connection portion. In the same sub-pixel, the oxide active layer of the oxide transistor is electrically connected to the gate of the driving transistor via the second connection portion, and the first electrode of the initialization transistor is electrically connected to the gate of the driving transistor via the first connection portion and the second connection portion. The first connection portion includes a portion whose extending direction is substantially parallel to the first direction. A display panel characterized by this.

12. The first connection portion includes a first sub-connection portion electrically connected to the oxide active layer of the oxide transistor. The extending direction of the first sub-connection portion is substantially parallel to the first direction and intersects the extending direction of the oxide active layer of the oxide transistor. The display panel according to claim 11, characterized by this.

13. The first connection portion further includes a second sub-connection portion electrically connected to the first sub-connection portion. The extending direction of the second sub-connection portion is substantially parallel to the extending direction of the oxide active layer of the oxide transistor. The display panel according to claim 12, characterized by this.

14. The orthographic projection of the second connection portion on the base substrate is disposed within the orthographic projection of the gate of the driving transistor on the base substrate. The display panel according to claim 13, characterized by this.

15. The sub-pixel further includes an initialization line, the initialization transistor is electrically connected to the initialization line, and the initialization signal is transmitted to the gate of the driving transistor by at least the first sub-connection portion and the second connection portion. The display panel according to claim 14, characterized in that.

16. The second conductive layer further includes a memory conductive portion, the third conductive layer further includes a first power line portion arranged at intervals, and the first power line portion is electrically connected to the memory conductive portion. The display panel according to claim 15, characterized in that.

17. Further includes a fourth conductive layer disposed on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a second power line portion, and in the same sub-pixel, the first power line portion is electrically connected to the second power line portion. In the same sub-pixel, the orthographic projection of the second power line portion on the base substrate covers the orthographic projection of the second connection portion on the base substrate, and the orthographic projection of the second power line portion on the base substrate exceeds the edges on both sides in the second direction of the orthographic projection of the gate of the driving transistor on the base substrate, and exceeds the edges on both sides in the second direction of the orthographic projection of the memory conductive portion on the base substrate. The display panel according to claim 16, characterized in that.

18. The first conductive layer further includes a plurality of third scanning lines arranged at intervals, the third scanning lines extend along the first direction and are arranged along the second direction. The sub-pixel further includes a data writing transistor, and the gate of the data writing transistor is electrically connected to the third scanning line. The orthographic projection of the third scanning line on the base substrate and the orthographic projection of the second power line portion on the base substrate have an overlapping region. The display panel according to claim 17, characterized in that.

19. The sub-pixel further includes a first light emission control transistor and a second light emission control transistor. The silicon semiconductor layer further includes a silicon active layer of the first light emission control transistor and a silicon active layer of the second light emission control transistor. The first conductive layer further includes a gate of the first light emission control transistor and a gate of the second light emission control transistor. In the same sub-pixel, the first power line portion is electrically connected to the first electrode of the first light emission control transistor, the second electrode of the first light emission control transistor is electrically connected to the first electrode of the drive transistor, the first electrode of the second light emission control transistor is electrically connected to the second electrode of the drive transistor, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting device. The display panel according to claim 18, characterized in that.

20. The first conductive layer further includes a plurality of light emission control lines arranged at intervals. In the same sub-pixel, the orthographic projection of the light emission control line on the base substrate is arranged on the side of the orthographic projection of the gate of the drive transistor on the base substrate, which is away from the orthographic projection of the auxiliary scanning line on the base substrate. The light emission control line is electrically connected to the gate of the first light emission control transistor and the gate of the second light emission control transistor. The display panel according to claim 19, characterized in that.

21. The orthographic projection of the second power line portion on the base substrate and the orthographic projection of the light emission control line on the base substrate have an overlapping region. The display panel according to claim 20, characterized in that.

22. A display device including the display panel according to any one of claims 1 to 21.

Images