Indicating device

Abstract

To provide a display device capable of improving a level of electromagnetic interference (EMI).SOLUTION: The display device comprises: a display panel including a display area in which a plurality of pixels are arranged and a non-display area except the display area; a gate driver that is disposed in the non-display area of the display panel and provides the plurality of pixels with a gate signal; a data driver that provides the plurality of pixels with a data voltage and provides the gate driver with a clock signal through a clock line; and a clock noise compensation line that is disposed in the non-display area of the display panel and to which a clock pseudo signal with a phase inverted from that of the clock signal is applied. The electromagnetic interference by the clock signal can be effectively removed.SELECTED DRAWING: Figure 2a

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] As the information age has arrived, the display field has been developing rapidly. In response, various display devices with excellent performance in terms of thinning, weight reduction, and low power consumption have been developed. Examples of such display devices include liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), and the like.

[0003] A display device can include a display panel on which pixels for displaying an image are arranged, a data driving unit that supplies a data voltage to data wirings arranged on the display panel, a gate driving unit that sequentially supplies gate signals to gate wirings arranged on the display panel, and a driving circuit such as a timing control unit that controls the data driving unit and the gate driving unit.

[0004] In an electronic device such as a display device, electromagnetic interference (EMI) can occur due to various signals for driving the driving circuit.

[0005] And the performance of the display device can be problematic due to the above-mentioned electromagnetic interference and the like.

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved in this specification is to provide a display device capable of improving the level of electromagnetic interference (EMI).

[0007] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned may be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] In order to solve the problems as described above, a display device according to an embodiment of this specification includes a display panel including a display area where a plurality of pixels are arranged and a non-display area excluding the display area, a gate driving unit arranged in the non-display area of the display panel and providing a gate signal to the plurality of pixels, a data driving unit providing a data voltage to the plurality of pixels and providing a clock signal to the gate driving unit through a clock wiring, and a clock noise compensation wiring arranged in the non-display area of the display panel and to which a clock pseudo signal having a phase inverted from that of the clock signal is applied, and electromagnetic interference caused by the clock signal can be effectively removed.

[0009] Specific matters of other embodiments are included in the detailed description and the drawings.

Advantages of the Invention

[0010] In the display device according to the embodiment of this specification, the electromagnetic wave of the clock signal can be completely canceled by the clock pseudo signal, and the electromagnetic interference caused by the clock signal can be effectively removed.

[0011] In the display device according to the embodiment of this specification, the electromagnetic wave of the multiplexer control signal can be completely canceled by the multiplexer pseudo signal, and the electromagnetic interference caused by the multiplexer control signal can be effectively removed.

[0012] The effects according to this specification are not limited to the contents exemplified above, and more various effects are included in this specification.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2a

Figure 2b

Figure 3

Figure 4

Figure 5

Figure 6a

Figure 6b

Figure 7

Figure 8

Figure 9a

Figure 9b

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Mode for Carrying Out the Invention

[0014] The advantages and features of the present specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and is embodied in various different shapes. Merely, these embodiments are provided so that the disclosure of the present specification becomes complete and fully informs those with ordinary knowledge in the technical field to which the present specification pertains of the scope of the invention. The present specification is only defined by the scope of the claims.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, and thus this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining this specification, if it is determined that a detailed description of related known technologies may obscure the gist of this specification, the detailed description thereof will be omitted. When terms such as "including", "having", "being made" are used in this specification, unless "only" is used, other parts may be added. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0016] When interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0017] When it is an explanation about a positional relationship, for example, when a positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0018] What an element or layer is referred to as "on" another element or layer includes both the case where it is immediately above another element and the case where another layer or another element is interposed in the middle.

[0019] And when it is described as "connected" or "coupled", unless "immediately" or "directly" is used, it can include being "connected" or "coupled" through one or more other components located between the two components.

[0020] Also, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0021] Throughout the specification, the same reference numerals refer to the same components.

[0022] The areas and thicknesses of the respective configurations shown in the drawings are shown for convenience of explanation, and this specification is not necessarily limited to the areas and thicknesses of the shown configurations.

[0023] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various technical linkages and drives, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0024] In the following, with reference to the accompanying drawings, various embodiments of this specification will be described in detail.

[0025] FIG. 1 is a block diagram showing a display device according to an embodiment of this specification.

[0026] Referring to FIG. 1, the display device 1000 according to an embodiment of this specification can include a display panel 100, a gate driving unit 200, a data driving unit 300, and a timing control unit 400.

[0027] The display panel 100 can include a display area DA (for example, an active area) where an image is displayed and a non-display area NA (for example, a non-active area). The non-display area NA can be located adjacent to the display area DA and does not overlap with the display area DA. In one example, the non-display area NA can entirely or partially surround the display area DA.

[0028] Pixels PX for displaying an image can be arranged on the display area DA of the display panel 100. Also, a plurality of gate wirings GL and a plurality of data wirings DL can be arranged on the display area DA of the display panel 100. The gate wirings GL can be arranged in one direction (for example, the first direction DR1 (see FIG. 2a)), and the data wirings DL can be arranged in a direction different from the one direction (for example, the second direction DR2 (see FIG. 2a)).

[0029] Each pixel PX can be connected to a corresponding gate wiring among the gate wirings GL and a corresponding data wiring among the data wirings DL. Thereby, a gate signal and a data voltage can be applied to each pixel PX through the gate wiring and the data wiring. And each pixel PX can embody gradation by the applied gate signal and data voltage, and finally, an image can be displayed on the display area DA of the display panel 100 according to the gradation displayed by each pixel PX.

[0030] On the non-display area NA of the display panel 100, various signal wirings, power supply wirings, and the gate driving unit 200 for transmitting signals for controlling the operation of the pixels PX arranged in the display area DA can be arranged.

[0031] That is, the gate driving unit 200 can be arranged in a gate in panel (GIP) form arranged inside the display panel 100.

[0032] Specifically, in the non-display area NA of the display panel 100, a clock wiring CL connected to the gate driving unit 200 and providing a clock signal to the gate driving unit 200 can be arranged. And on the non-display area NA of the display panel 100, a clock noise compensation wiring (Clock Pseudo Line) CPL arranged outside the gate driving unit 200 and to which a clock pseudo signal whose phase is inverted with respect to the clock signal is applied can be arranged. The above-described clock pseudo signal can be referred to as an inverted clock signal.

[0033] The timing control unit 400 (or, timing control circuit) can receive an input video signal DATA1 and an input control signal CS from the outside (for example, a host system).

[0034] The timing control unit 400 can generate video data DATA2 corresponding to the operation conditions of the pixels PX based on the input video signal DATA1 and provide it to the data driving unit 300.

[0035] The timing control unit 400 can generate control signals for controlling the gate driving unit 200 and the data driving unit 300 based on the input control signal CS. For example, the input control signal CS can include timing signals such as a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal. Here, the horizontal synchronization signal is a signal indicating the time required to display one horizontal line of the screen, the vertical synchronization signal is a signal indicating the time required to display one frame of the screen, and the data enable signal can correspond to a signal indicating the period during which a data voltage is supplied to the pixel PX.

[0036] The timing control unit 400 can generate a gate control signal GCS for controlling the operation timing of the gate driving unit 200 by using the timing signals included in the input control signal CS and provide it to the gate driving unit 200.

[0037] Also, the timing control unit 400 can generate a data control signal DCS for controlling the operation timing of the data driving unit 300 by using the timing signals included in the input control signal CS and provide it to the data driving unit 300.

[0038] The data driving unit 300 (or data driving circuit) can receive the data control signal DCS from the timing control unit 400 and convert the video data DATA2 into an analog data voltage (e.g., data voltage) in response to the data control signal DCS. The data driving unit 300 can output the data voltage to the data wiring DL and supply it to the pixel PX.

[0039] Then, the data driving unit 300 receives a clock signal from the timing control unit 400 and provides the clock signal to the gate driving unit 200 through the clock wiring CL.

[0040] The gate driving unit 200 (or gate driving circuit, scan driving unit, scan driving circuit) receives a gate control signal GCS from the timing control unit 400 and a clock signal from the data driving unit 300, and can sequentially provide gate signals to the gate wiring GL in response to the gate control signal GCS and the clock signal. For this purpose, each of the gate driving units 200 can include a shift register, a level shifter, etc. The gate control signal GCS can include a gate start signal and a gate enable signal for generating the gate signal.

[0041] On the other hand, the display device 1000 according to the embodiments of the present specification may be various types of display devices such as a liquid crystal display device, an organic light emitting display device, a plasma display device, and a quantum dot display device.

[0042] For example, when the display device 1000 according to the embodiments of the present specification is a liquid crystal display device, the display panel 100 includes a liquid crystal layer formed between two substrates (for example, an upper substrate and a lower substrate), and can operate in any known mode such as a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, and an FFS (Fringe Field Switching) mode.

[0043] A black matrix, a color filter, etc. are formed on the upper substrate of the display panel 100, and a thin film transistor, a pixel PX, etc. can be formed on the lower substrate of the display panel 100. The display panel 100 can be embodied in a COT (Color filter On TFT) structure. In this case, the black matrix and the color filter can be formed on the lower substrate of the display panel 100.

[0044] In addition, the common electrode to which the common voltage is supplied may be formed on the upper substrate or the lower substrate of the display panel 100. Polarizing plates may be attached to the upper substrate and the lower substrate of the display panel 100, respectively, and an alignment film for setting the tilt angle of the liquid crystal may be formed on the inner surface in contact with the liquid crystal.

[0045] Between the upper substrate and the lower substrate of the display panel 100, a column spacer for maintaining the cell gap of the liquid crystal cell may be formed. In the case of a liquid crystal display device, a backlight unit is disposed below the back of the lower polarizing plate of the display panel 100, and the backlight unit may be implemented in an edge type or a direct type or the like.

[0046] Here, in the liquid crystal display device, the plurality of touch electrodes disposed on the display panel 100 and for sensing a user's touch or the like may be the common electrodes to which a common voltage for display driving is applied.

[0047] As another example, when the display device 1000 according to the embodiment of the present specification is an organic light emitting display device, it may include a first electrode (anode electrode) constituting an organic light emitting diode, an organic light emitting layer, a second electrode (cathode electrode), an encapsulation layer having a sealing function, and a touch sensor metal layer.

[0048] Here, in the organic light emitting display device, the plurality of touch electrodes disposed on the display panel 100 and for sensing a user's touch or the like may be formed on the touch sensor metal layer or may be formed on the second electrode layer constituting the cathode electrode of the organic light emitting diode.

[0049] On the one hand, the common voltage applied to the common electrode or the touch electrode can be set to a DC voltage applied at a specific voltage level for a certain period of time when the level of the data voltage supplied to the display panel 100 changes during the driving period of the display device 1000. Also, the common voltage applied to the common electrode or the touch electrode may be used under other names such as display voltage depending on the type of liquid crystal display device or organic light emitting display device.

[0050] On the other hand, as noise that can occur within the display device 1000, there may be electromagnetic waves generated by the clock signal provided to the gate driving unit 200, which are electromagnetic waves generated by the display panel 100, and / or electromagnetic waves generated by the multiplexer control signal that controls the multiplexer connected to the source driving integrated circuit of the data driving unit described later.

[0051] Thus, due to the influence of the noise that can occur within the display device 1000, that is, electromagnetic interference (EMI), the system stability of the display device 1000 may decrease. In this case, it may affect other signals (voltages) necessary for video display of the display device 1000 and reduce the display performance.

[0052] Accordingly, the display device 1000 according to the embodiments of the present specification arranges a plurality of compensation wirings (Pseudo Lines) in the non-display area NA of the display panel 100 in order to cancel out the noise that can occur within the display device 1000. Then, a clock pseudo signal for canceling out the electromagnetic waves generated by the clock signal and a multiplexer pseudo signal for canceling out the electromagnetic waves generated by the multiplexer control signal are applied to each of the plurality of compensation wirings. Thereby, the level of electromagnetic interference of the display device 1000 can be improved.

[0053] This will be described more specifically with reference to FIG. 2a and below.

[0054] FIG. 2A and FIG. 2B are diagrams showing a clock wiring and a clock noise compensation wiring arranged in a non-display area of the display device of FIG. 1.

[0055] Referring to FIGS. 1, 2A and 2B, as described with reference to FIG. 1, the display panel 100 can include a display area DA where an image is displayed and a non-display area NA.

[0056] The display area DA can be parallel to a plane defined by a first direction axis (for example, an axis extending in the first direction DR1) and a second direction axis (for example, an axis extending in the second direction DR2). However, the first and second directions DR1 and DR2 shown herein are merely examples, and the first and second directions DR1 and DR2 are relative concepts and can be converted to other directions.

[0057] A plurality of pixels PX can be arranged on the display area DA. Each pixel PX can be connected to a corresponding gate wiring among the gate wirings GL and a corresponding data wiring among the data wirings DL. According to an embodiment, each pixel PX can include a driving transistor, at least one switching transistor, a light-emitting element, a storage capacitor, and the like.

[0058] Referring to FIG. 1, the display panel 100 can include a gate wiring GL, a data wiring DL, a clock wiring CL, and a clock noise compensation wiring CPL.

[0059] In one embodiment, in the display area DA of the display panel 100, the gate wiring GL can extend in the first direction DR1, and the data wiring DL can extend in the second direction DR2. And in the non-display area NA of the display panel 100, the clock wiring CL and the clock noise compensation wiring CPL can extend in the second direction DR2.

[0060] And referring further to FIGS. 2A and 2B, the data driving unit can include a plurality of source driving integrated circuits D-IC#1,..., D-IC#6 arranged in the first direction DR1.

[0061] A plurality of source driving integrated circuits D-IC#1, ..., D-IC#6 can supply data voltages to data wiring DL. Also, the plurality of source driving integrated circuits D-IC#1, ..., D-IC#6 can provide clock signals to a gate driving unit GIP through clock wiring CL. And the plurality of source driving integrated circuits D-IC#1, ..., D-IC#6 can provide clock pseudo signals to clock noise compensation wiring CPL.

[0062] In one embodiment, the plurality of source driving integrated circuits D-IC#1, ..., D-IC#6 are constituted by integrated circuits (ICs) and can be attached to a display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, an ultrasonic bonding method, or the like.

[0063] Referring to FIGS. 2a and 2b, the clock wiring CL can include a first clock wiring CLa and a second clock wiring CLb that are arranged on both sides of a display area DA with respect to a first direction DR1 and extend in a second direction DR2.

[0064] Each of the first clock wiring CLa and the second clock wiring CLb can be electrically connected to the outermost source driving integrated circuits D-IC#1 and D-IC#6 among the plurality of source driving integrated circuits D-IC#1, ..., D-IC#6.

[0065] Specifically, the first clock wiring CLa is connected to the first source driving integrated circuit D-IC#1 that is closest to the first clock wiring CLa and can receive the application of a clock signal. And the second clock wiring CLb is connected to the sixth source driving integrated circuit D-IC#6 that is closest to the second clock wiring CLb and can receive the application of a clock signal.

[0066] Then, the clock wiring CL can further include a third clock wiring CLc that extends in the first direction DR1 in the display area DA and connects the first clock wiring CLa and the second clock wiring CLb. Therefore, the first clock wiring CLa and the second clock wiring CLb are electrically connected by the third clock wiring CLc, and a clock signal can be stably supplied.

[0067] On the other hand, the clock noise compensation wiring CPL can include a first clock noise compensation wiring CPLa and a second clock noise compensation wiring CPLb that are disposed outside the first clock wiring CLa and the second clock wiring CLb.

[0068] Specifically, the first clock noise compensation wiring CPLa is disposed on one side (one side) of the first clock wiring CLa with respect to the first direction DR1 and extends in the second direction DR2. The second clock noise compensation wiring CPLb is disposed on the other side (the other side) of the second clock wiring CLb with respect to the first direction DR1 and extends in the second direction DR2.

[0069] As shown in FIG. 2a, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb may be in a linear form. However, it is not limited thereto. As shown in FIG. 2b, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb may be in a bent form. For example, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb may be in a square wave form or a sine wave form. Therefore, the total length of each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be extended. In addition, the shapes of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb are not limited thereto. For example, the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb may have a zigzag wave shape.

[0070] On the one hand, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be connected to source driver integrated circuits D-IC#2, ..., D-IC#4 arranged between source driver integrated circuits D-IC#1 and D-IC#6 connected to the clock wiring CL.

[0071] That is, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be connected to any one of the second to fourth source driver integrated circuits D-IC#2, ..., D-IC#4 arranged between the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6, and can receive the application of a clock pseudo signal.

[0072] As an example, the first clock noise compensation wiring CPLa can be connected to the third source driver integrated circuit D-IC#3 arranged between the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6. And the first clock noise compensation wiring CPLa can receive the application of a clock pseudo signal from the third source driver integrated circuit D-IC#3.

[0073] And the second clock noise compensation wiring CPLb can be connected to the fourth source driver integrated circuit D-IC#4 arranged between the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6. And the second clock noise compensation wiring CPLb can receive the application of a clock pseudo signal from the fourth source driver integrated circuit D-IC#4.

[0074] That is, as shown in Fig. 2a, by connecting each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb to the source driver integrated circuits D-IC#2, ..., D-IC#4 arranged between the source driver integrated circuits D-IC#1 and D-IC#6 connected to the clock wiring CL, the length of each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be longer than that of each of the first clock wiring CLa and the second clock wiring CLb.

[0075] Furthermore, as shown in FIG. 2b, by forming each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb in a non-linear bent form, the length of each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be longer than that of each of the first clock wiring CLa and the second clock wiring CLb.

[0076] Source driver integrated circuits D-IC#1, D-IC#2, D-IC#3, D-IC#4, D-IC#5, and D-IC#6 are shown in FIGS. 2a and 2b, but the number of source driver integrated circuits is not limited thereto. For example, the number of source driver integrated circuits is n, where n is an integer of 4 or more.

[0077] FIG. 3 is a graph for explaining the radiation amount of the clock pseudo signal according to the length of the clock noise compensation wiring.

[0078] Specifically, graph (a) of FIG. 3 is a graph showing the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring with a relatively short length. And graph (b) of FIG. 3 is a graph showing the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring with a relatively long length. The X-axis of graphs (a) and (b) shown in FIG. 3 means the frequency of the clock pseudo signal, and the Y-axis means the radiation amount.

[0079] When the length of the clock noise compensation wiring becomes longer, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring can increase.

[0080] For example, as shown in graph (a) of FIG. 3, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring with a relatively short length is measured to be 36.9 dB. And as shown in graph (b) of FIG. 3, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring with a relatively long length is measured to be 43.8 dB. That is, it can be confirmed that the radiation amount of the clock pseudo signal increases by about 6.9 dB as the length of the clock noise compensation wiring becomes longer.

[0081] FIG. 3 shows only the examples in which the radiation amounts of the clock pseudo signals applied to the clock noise compensation wiring were measured to be 36.9 dB and 43.8 dB. However, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring is not limited to this, and the measured value of the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring varies depending on the length of the clock noise compensation wiring.

[0082] To summarize, the longer the length of the clock noise compensation wiring, the greater the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring.

[0083] FIGS. 4 and 5 are graphs for explaining the cancellation interference of electromagnetic wave interference generated in the display device.

[0084] Specifically, FIG. 4 is a graph for explaining the electromagnetic wave interference when the total length of the clock noise compensation wiring CPL is shorter than the length of the clock wiring CL. And FIG. 5 is a graph for explaining the electromagnetic wave interference when the total length of the clock noise compensation wiring CPL is at the same level as the length of the clock wiring CL.

[0085] As shown in FIGS. 2A and 2B, as the display device is enlarged, in order to stably transmit the clock signal, a third clock wiring CLc for connecting the first clock wiring CLa and the second clock wiring CLb may be further formed. Therefore, a phenomenon occurs in which the total length of the clock wiring CL becomes longer than the total length of the clock noise compensation wiring CPL, and the total length of the clock noise compensation wiring CPL becomes relatively shorter compared to the total length of the clock wiring CL.

[0086] Since the radiation amount of the signal is proportional to the length of the wiring to which the signal is applied, as shown in FIG. 4, the radiation amount A (GCLK) of the clock signal can be greater than the radiation amount B (Pseudo) of the clock pseudo signal.

[0087] Therefore, since the electromagnetic waves of the clock signal are not completely canceled out by the clock pseudo-signal, there is a problem that electromagnetic interference A + B (EMI) still exists.

[0088] Therefore, in the display device according to an embodiment of the present specification, as shown in FIG. 2a, the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb are respectively connected to the clock wiring CL between the source drive integrated circuits D-IC#1 and D-IC#6, and are connected to the source drive integrated circuits D-IC#2,..., D-IC#4 arranged therebetween. By doing so, the lengths of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be longer than the lengths of the first clock wiring CLa and the second clock wiring CLb, respectively.

[0089] Furthermore, as shown in FIG. 2b, by forming the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb in a bent form that is not straight, the lengths of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be longer than the lengths of the first clock wiring CLa and the second clock wiring CLb, respectively.

[0090] As a result, in the display device according to an embodiment of the present specification, the total length of the clock noise compensation wiring CPL can be at the same level as the total length of the clock wiring CL.

[0091] Since the radiation amount of the signal is proportional to the length of the wiring to which the signal is applied, as shown in FIG. 5, the radiation amounts of the clock signal A (GCLK) and the clock pseudo-signal B (Pseudo) can be at the same level.

[0092] Therefore, the electromagnetic waves of the clock signal can be completely canceled out by the clock pseudo-signal, and the electromagnetic interference A + B (EMI) can be effectively removed.

[0093] Hereinafter, a display device according to another embodiment of the present specification will be described. Since the only difference between the display device according to one embodiment of the present specification and the display device according to another embodiment of the present specification lies in the clock noise compensation wiring CPL, it will be specifically described below.

[0094] For convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to another embodiment of the present specification, duplicate descriptions of the same components are omitted, and the same reference numerals are used for the same components.

[0095] FIGS. 6A and 6B are diagrams showing clock wiring and clock noise compensation wiring arranged in a non-display area of a display device according to another embodiment of the present specification.

[0096] In the display device according to another embodiment of the present specification, the clock noise compensation wiring CPL arranged in the non-display area NA not only includes a first clock noise compensation wiring CPLa and a second clock noise compensation wiring CPLb, but may further include a third clock noise compensation wiring CPLc that connects the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb.

[0097] As shown in FIGS. 6A and 6B, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can be connected to a source drive integrated circuit connected to the clock wiring CL.

[0098] That is, the first clock noise compensation wiring CPLa can be connected to the first source drive integrated circuit D-IC#1. And the first clock noise compensation wiring CPLa can receive an application of a clock pseudo signal from the first source drive integrated circuit D-IC#1.

[0099] And the second clock noise compensation wiring CPLb can be connected to the sixth source drive integrated circuit D-IC#6. And the second clock noise compensation wiring CPLb can receive an application of a clock pseudo signal from the sixth source drive integrated circuit D-IC#6.

[0100] And, as shown in FIG. 6a, the third clock noise compensation wiring CPLc is disposed on one side (one side) (the upper side in FIG. 6a) in the second direction DR2, extends in the first direction DR1, and can electrically connect the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb. For example, the third clock noise compensation wiring CPLc can extend in the first direction DR1 and be disposed on one side (for example, the upper side in FIG. 6a) of the non-display area NA away from the source drive integrated circuit.

[0101] In some embodiments, as shown in FIG. 6b, the third clock noise compensation wiring CPLc is disposed on the other side (the other side) (the lower side in FIG. 6a) in the second direction DR2, extends in the first direction DR1, and can electrically connect the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb. For example, the third clock noise compensation wiring CPLc can extend in the first direction DR1 and be disposed on the other side (the other side) (for example, the lower side in FIG. 6a) of the non-display area NA close to the source drive integrated circuit.

[0102] And, as shown in FIGS. 6a and 6b, the length of the third clock noise compensation wiring CPLc can be the same as or substantially the same as the length of the third clock wiring CLc that connects the first clock wiring CLa and the second clock wiring CLb.

[0103] As a result, in the display device according to other embodiments of the present specification, the total length of the clock noise compensation wiring CPL can be at the same level as the total length of the clock wiring CL.

[0104] Since the radiation amount of the signal is proportional to the length of the wiring to which the signal is applied, the radiation amount of the clock signal applied to the clock wiring CL and the radiation amount of the clock pseudo-signal applied to the clock noise compensation wiring CPL can be at the same level.

[0105] Therefore, the electromagnetic wave of the clock signal can be effectively canceled by the clock pseudo-signal, and electromagnetic interference can be effectively removed.

[0106] Hereinafter, a display device according to another embodiment (the third embodiment) of the present specification will be described. Since the display device according to one embodiment of the present specification and the display device according to another embodiment (the third embodiment) of the present specification differ only in the clock noise compensation wiring CPL_1, it will be specifically described.

[0107] For convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to another embodiment (the third embodiment) of the present specification, duplicate descriptions of the same components are omitted, and the same reference numerals are used for the same components.

[0108] FIG. 7 is a diagram showing clock wiring and clock noise compensation wiring arranged in a non-display area of a display device according to another embodiment (the third embodiment) of the present specification.

[0109] In the display device according to another embodiment (the third embodiment) of the present specification, the width of the clock noise compensation wiring CPL_1 arranged in the non-display area NA may be wider than the width of the clock wiring CL.

[0110] As shown in FIG. 7, the width of each of the first clock noise compensation wiring CPLa_1 and the second clock noise compensation wiring CPLb_1 may be wider than the width of each of the first clock wiring CLa and the second clock wiring CLb.

[0111] On the other hand, each of the first clock noise compensation wiring CPLa_1 and the second clock noise compensation wiring CPLb_1 can be connected to a source drive integrated circuit connected to the clock wiring CL.

[0112] That is, the first clock noise compensation wiring CPLa_1 can be connected to the first source drive integrated circuit D-IC#1. And the first clock noise compensation wiring CPLa_1 can receive the application of a clock pseudo signal from the first source drive integrated circuit D-IC#1.

[0113] The second clock noise compensation wiring CPLb_1 can be connected to the sixth source drive integrated circuit D-IC#6. And the second clock noise compensation wiring CPLb_1 can receive the application of a clock pseudo signal from the sixth source drive integrated circuit D-IC#6.

[0114] FIG. 8 is a graph for explaining the radiation amount of a clock pseudo signal according to the width of clock noise compensation wiring.

[0115] Specifically, graph (a) in FIG. 7 is a graph showing the radiation amount of a clock pseudo signal applied to relatively narrow clock noise compensation wiring. And graph (b) in FIG. 7 is a graph showing the radiation amount of a clock pseudo signal applied to relatively wide clock noise compensation wiring CPL_1. The X-axis of graph (a) and graph (b) shown in FIG. 7 means the frequency of the clock pseudo signal, and the Y-axis means the radiation amount.

[0116] When the width of the clock noise compensation wiring CPL_1 becomes wider, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring CPL_1 can increase.

[0117] For example, as shown in graph (a) of FIG. 7, the radiation amount of the clock pseudo signal applied to relatively narrow clock noise compensation wiring is measured to be 24.6 dB. And as shown in graph (b) of FIG. 7, the radiation amount of the clock pseudo signal applied to relatively wide clock noise compensation wiring CPL_1 is measured to be 37.8 dB. That is, it can be confirmed that the radiation amount of the clock pseudo signal increases by about 13.2 dB as the width of the clock noise compensation wiring CPL_1 becomes wider.

[0118] FIG. 8 shows only the embodiments in which the radiation amounts of the clock pseudo signals applied to the clock noise compensation wiring CPL_1 are measured to be 24.6 dB and 37.8 dB. However, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring CPL_1 is not limited to this, and the measured value of the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring CPL_1 varies depending on the width of the clock noise compensation wiring.

[0119] To summarize, as the width of the clock noise compensation wiring CPL_1 increases, the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring CPL_1 can increase.

[0120] Therefore, the radiation amount of the clock signal applied to the clock wiring CL and the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring CPL_1 can be at the same level.

[0121] Therefore, the electromagnetic waves of the clock signal can be efficiently canceled by the clock pseudo signal, and electromagnetic interference can be effectively removed.

[0122] In the following, a display device according to another embodiment (Embodiment 4) of the present specification will be described. Since the display device according to one embodiment of the present specification and the display device according to another embodiment (Embodiment 4) of the present specification differ only in the clock noise compensation wiring CPL_2, it will be specifically described.

[0123] For convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to another embodiment (Embodiment 4) of the present specification, duplicate descriptions of the same components are omitted, and the same drawing reference numerals are used for the same components.

[0124] FIGS. 9A and 9B are diagrams showing the clock wiring and the clock noise compensation wiring arranged in the non-display area of the display device according to another embodiment (Embodiment 4) of the present specification.

[0125] In the display device according to another embodiment (the fourth embodiment) of the present specification, a plurality of first clock noise compensation wirings CPLa_2 may be arranged outside the first clock wiring CLa, and a plurality of second clock noise compensation wirings CPLb_2 may be arranged outside the second clock wiring CLb.

[0126] As an example, three first clock noise compensation wirings CPLa_2 may be arranged on one side (one side) of the first clock wiring CLa with respect to the first direction DR1. And three second clock noise compensation wirings CPLb_2 may be arranged on the other side (the other side) of the second clock wiring CLb with respect to the first direction DR1. However, the number of the first clock noise compensation wiring CPLa_2 and the second clock noise compensation wiring CPLb_2 is not limited to this. For example, the number of each of the first clock noise compensation wiring CPLa_2 and the second clock noise compensation wiring CPLb_2 can be m, where m is an integer of 2 or more.

[0127] The number of the clock noise compensation wirings CPL_2 arranged in the non-display area NA may be the same as the number of the source drive integrated circuits D-IC#1,..., D-IC#6 included in the display panel 100. However, the present disclosure is not limited to this, and the number of the clock noise compensation wirings CPLb_2 arranged in the non-display area NA may not be equal to the number of the source drive integrated circuits D-IC#1,..., D-IC#6 included in the display panel 100.

[0128] And as shown in FIG. 9a, each of the plurality of first clock noise compensation wirings CPLa_2 may be connected to different source drive integrated circuits D-IC#1, D-IC#2, D-IC#3, and each of the plurality of second clock noise compensation wirings CPLb_2 may be connected to different source drive integrated circuits D-IC#4, D-IC#5, D-IC#6.

[0129] As an example, any one of the three first clock noise compensation wirings CPLa_2, CPLa_2(1), can be connected to the first source drive integrated circuit D-IC#1, another one of the three first clock noise compensation wirings CPLa_2, CPLa_2(2), can be connected to the second source drive integrated circuit D-IC#2, and the remaining one of the three first clock noise compensation wirings CPLa_2, CPLa_2(3), can be connected to the third source drive integrated circuit D-IC#3.

[0130] Therefore, each of the three first clock noise compensation wirings CPLa_2 can receive an applied clock pseudo-signal from each of the first to third source drive integrated circuits D-IC#1, D-IC#2, and D-IC#3.

[0131] And, any one of the three second clock noise compensation wirings CPLb_2, CPLb_2(1), can be connected to the sixth source drive integrated circuit D-IC#6, another one of the three second clock noise compensation wirings CPLb_2, CPLb_2(2), can be connected to the fifth source drive integrated circuit D-IC#5, and the remaining one of the three second clock noise compensation wirings CPLb_2, CPLb_2(3), can be connected to the fourth source drive integrated circuit D-IC#4.

[0132] Therefore, each of the three second clock noise compensation wirings CPLb_2 can receive an applied clock pseudo-signal from each of the fourth to sixth source drive integrated circuits D-IC#4, D-IC#5, and D-IC#6.

[0133] That is, in FIG. 9a, different clock noise compensation wirings can be connected to different source drive integrated circuits.

[0134] In contrast, in some embodiments, as shown in FIG. 9b, each of the plurality of first clock noise compensation wirings CPLa_2 can be connected to one source drive integrated circuit, and each of the plurality of second clock noise compensation wirings CPLb_2 can be connected to another one source drive integrated circuit.

[0135] As an example, each of the three first clock noise compensation wirings CPLa_2(1), CPLa_2(2), and CPLa_2(3) is connected to the first source drive integrated circuit D-IC#1 and can receive an application of a clock pseudo signal from each of the first source drive integrated circuits D-IC#1. Alternatively, the three first clock noise compensation wirings CPLa_2(1), CPLa_2(2), and CPLa_2(3) are each connected to the second source drive integrated circuit D-IC#2 and can receive an application of a clock pseudo signal from the second source drive integrated circuit D-IC#2, or the three first clock noise compensation wirings CPLa_2(1), CPLa_2(2), and CPLa_2(3) are each connected to the third source drive integrated circuit D-IC#3 and can receive an application of a clock pseudo signal from the third source drive integrated circuit D-IC#3, but the present disclosure is not limited thereto.

[0136] And each of the three second clock noise compensation wirings CPLb_2(1), CPLb_2(2), and CPLb_2(3) is connected to the sixth source drive integrated circuit D-IC#6 and can receive an application of a clock pseudo signal from each of the sixth source drive integrated circuits D-IC#6. Alternatively, the three second clock noise compensation wirings CPLb_2(1), CPLb_2(2), and CPLb_2(3) are each connected to the fifth source drive integrated circuit D-IC#5 and can receive an application of a clock pseudo signal from the fifth source drive integrated circuit D-IC#5, or the three second clock noise compensation wirings CPLb_2(1), CPLb_2(2), and CPLb_2(3) are each connected to the fourth source drive integrated circuit D-IC#4 and can receive an application of a clock pseudo signal from the fourth source drive integrated circuit D-IC#4, but the present disclosure is not limited thereto.

[0137] Referring to FIGS. 9A and 9B, the number of the first clock noise compensation wirings CPLa_2 located on one side of the display panel 100 may be the same as the number of the second clock noise compensation wirings CPLb_2 located on the other side of the display panel 100. However, it is not limited thereto, and the number of the first clock noise compensation wirings CPLa_2 located on one side of the display panel 100 and the number of the second clock noise compensation wirings CPLb_2 located on the other side of the display panel 100 may be different. On the other hand, the number of each of the first clock noise compensation wirings CPLa_2 and the second clock noise compensation wirings CPLb_2 is not limited to 3. For example, the number of the first clock noise compensation wirings CPLa_2 may be m, and the number of the second clock noise compensation wirings CPLb_2 may be p, where m and p are each an integer of 1 or more. Considering the design of the pixels and circuits arranged on the display panel 100, such as the position of the gate driving unit GIP, the arrangement of the clock noise compensation wiring CPL_2 may be appropriately changed.

[0138] FIG. 10 is a graph for explaining the radiation amount of the clock pseudo signal according to the number of the clock noise compensation wirings.

[0139] Specifically, graph (a) of FIG. 10 is a graph showing the radiation amount of the clock pseudo signal when one first clock noise compensation wiring CPLa_2 and one second clock noise compensation wiring CPLb_2 are arranged. And graph (b) of FIG. 10 is a graph showing the radiation amount of the clock pseudo signal when two first clock noise compensation wirings CPLa_2 and two second clock noise compensation wirings CPLb_2 are arranged. The X-axis of graph (a) and graph (b) shown in FIG. 10 means the frequency of the clock pseudo signal, and the Y-axis means the radiation amount.

[0140] When the number of the first clock noise compensation wirings CPLa_2 and the number of the second clock noise compensation wirings CPLb_2 increase, the radiation amount of the clock pseudo signal may increase.

[0141] For example, as shown in graph (a) of FIG. 10, when one first clock noise compensation wiring CPLa_2 and one second clock noise compensation wiring CPLb_2 are arranged, the radiation amount of the clock pseudo signal is measured to be 16.2 dB. And as shown in graph (b) of FIG. 10, when two first clock noise compensation wirings CPLa_2 and two second clock noise compensation wirings CPLb_2 are arranged, the radiation amount of the clock pseudo signal is measured to be 22.0 dB. That is, it can be confirmed that by increasing the number of the first clock noise compensation wirings CPLa_2 and the number of the second clock noise compensation wirings CPLb_2, the radiation amount of the clock pseudo signal increases by about 5.8 dB.

[0142] FIG. 10 shows only the embodiments in which the radiation amounts of the clock pseudo signals are measured to be 16.2 dB and 22.0 dB, but the radiation amounts of the clock pseudo signals are not limited thereto, and the measured values of the radiation amounts of the clock pseudo signals vary depending on the number of the clock noise compensation wirings.

[0143] To summarize, the larger the number of the clock noise compensation wirings, the greater the radiation amount of the clock pseudo signal applied to the clock noise compensation wirings.

[0144] Therefore, the radiation amount of the clock signal applied to the clock wiring CL (for example, the first clock wiring CLa and the second clock wiring CLb) and the radiation amount of the clock pseudo signal applied to the clock noise compensation wiring (for example, the first clock noise compensation wiring CPLa_2 and the second clock noise compensation wiring CPLb_2) can be at the same level.

[0145] Therefore, the electromagnetic wave of the clock signal can be effectively canceled by the clock pseudo signal, and the electromagnetic interference can be effectively removed.

[0146] FIG. 11 is a graph for explaining the cancellation interference of the electromagnetic interference generated in the display device according to still another embodiment (the fourth embodiment) of the present specification.

[0147] By increasing the number of the first clock noise compensation wirings CPLa_2 and the number of the second clock noise compensation wirings CPLb_2, it is possible to increase the radiation amount of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2 and the radiation amount of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2.

[0148] In other words, the number of the first clock noise compensation wirings CPLa_2 and the number of the second clock noise compensation wirings CPLb_2 can be adjusted, and the radiation amount of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2 and the radiation amount of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2 can be adjusted.

[0149] As shown in FIG. 11, the radiation amount B(Pseudo1) of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2 and the radiation amount C(Pseudo2) of the clock pseudo signal applied to the plurality of second clock noise compensation wirings CPLb_2 can increase to a half level of the radiation amount A(GCLK) of the clock signal.

[0150] In other words, it can be matched so that the sum of the radiation amount B(Pseudo1) of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2 and the radiation amount C(Pseudo2) of the clock pseudo signal applied to the plurality of second clock noise compensation wirings CPLb_2 can reach a level equivalent to the radiation amount A(GCLK) of the clock signal.

[0151] Therefore, the radiation amount A(GCLK) of the clock signal can be completely canceled out by the radiation amount B(Pseudo1) of the clock pseudo signal applied to the plurality of first clock noise compensation wirings CPLa_2 and the radiation amount B(Pseudo2) of the clock pseudo signal applied to the plurality of second clock noise compensation wirings CPLb_2.

[0152] That is, the electromagnetic wave of the clock signal can be completely canceled by the clock pseudo signals applied by the plurality of first clock noise compensation wirings CPLa_2 and the plurality of second clock noise compensation wirings CPLb_2, and the electromagnetic interference A + B + C (EMI) can be effectively removed.

[0153] Hereinafter, a display device according to another embodiment (the fifth embodiment) of the present specification will be described. The display device according to one embodiment of the present specification and the display device according to another embodiment (the fifth embodiment) of the present specification differ only in the clock noise compensation switch CPS connected to the clock noise compensation wiring CPL, and thus will be specifically described.

[0154] For convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to another embodiment (the fifth embodiment) of the present specification, duplicate descriptions of the same components are omitted, and the same reference numerals are used for the same components.

[0155] FIG. 12 is a diagram showing a clock wiring, a clock noise compensation wiring, and a clock noise compensation switch arranged in a non-display area of a display device according to another embodiment (the fifth embodiment) of the present specification.

[0156] In the display device according to another embodiment (the fifth embodiment) of the present specification, a plurality of clock noise compensation switches CPS can be included between the clock noise compensation wiring CPL arranged in the non-display area NA and the plurality of source drive integrated circuits D-IC#1,..., D-IC#6.

[0157] And the plurality of clock noise compensation switches CPS can control the electrical connection state between the clock noise compensation wiring CPL and the plurality of source drive integrated circuits D-IC#1,..., D-IC#6.

[0158] As shown in FIG. 12, the plurality of clock noise compensation switches CPS can include a first clock noise compensation switch CPS1 to a sixth clock noise compensation switch CPS6.

[0159] Specifically, the first clock noise compensation switch CPS1 is connected between the first clock noise compensation wiring CPLa and the first source drive integrated circuit D-IC#1, and can control the connection state between the first clock noise compensation wiring CPLa and the first source drive integrated circuit D-IC#1.

[0160] And the second clock noise compensation switch CPS2 is connected between the first clock noise compensation wiring CPLa and the second source drive integrated circuit D-IC#2, and can control the connection state between the first clock noise compensation wiring CPLa and the second source drive integrated circuit D-IC#2.

[0161] And the third clock noise compensation switch CPS3 is connected between the first clock noise compensation wiring CPLa and the third source drive integrated circuit D-IC#3, and can control the connection state between the first clock noise compensation wiring CPLa and the third source drive integrated circuit D-IC#3.

[0162] Therefore, the number of source drive integrated circuits connected to the first clock noise compensation wiring CPLa can be adjusted through the first clock noise compensation switch CPS1 to the third clock noise compensation switch CPS3. For example, any one of the first clock noise compensation switch CPS1, the second clock noise compensation switch CPS2, and the third clock noise compensation switch CPS3 can be selectively and independently turned on.

[0163] And the fourth clock noise compensation switch CPS4 is connected between the second clock noise compensation wiring CPLb and the fourth source drive integrated circuit D-IC#4, and can control the connection state between the second clock noise compensation wiring CPLb and the fourth source drive integrated circuit D-IC#4.

[0164] And the fifth clock noise compensation switch CPS5 is connected between the second clock noise compensation wiring CPLb and the fifth source drive integrated circuit D-IC#5, and can control the connection state between the second clock noise compensation wiring CPLb and the fifth source drive integrated circuit D-IC#5.

[0165] The sixth clock noise compensation switch CPS6 is connected between the second clock noise compensation wiring CPLb and the sixth source drive integrated circuit D-IC#6, and can control the connection state between the second clock noise compensation wiring CPLb and the sixth source drive integrated circuit D-IC#6.

[0166] Therefore, the number of source drive integrated circuits connected to the second clock noise compensation wiring CPLb can be adjusted through the fourth clock noise compensation switch CPS4 to the sixth clock noise compensation switch CPS6. For example, any one of the fourth clock noise compensation switch CPS4, the fifth clock noise compensation switch CPS5, and the sixth clock noise compensation switch CPS6 can be selectively and independently turned on.

[0167] FIG. 13 is a graph for explaining the radiation amount of the clock pseudo signal according to the number of source drive integrated circuits connected to the clock noise compensation wiring.

[0168] Specifically, graph (a) in FIG. 13 is a graph showing the radiation amount of the clock pseudo signal when one source drive integrated circuit is connected to each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb. And graph (b) in FIG. 13 is a graph showing the radiation amount of the clock pseudo signal when two source drive integrated circuits are connected to each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb. And graph (c) in FIG. 13 is a graph showing the radiation amount of the clock pseudo signal when three source drive integrated circuits are connected to each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb. The X-axis of graphs (a) to (c) shown in FIG. 13 represents time, and the Y-axis represents the radiation amount.

[0169] As the number of source drive integrated circuits connected to each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb increases, the radiation amount of the clock pseudo signal may increase.

[0170] For example, when one of the first to third source drive integrated circuits D-IC#1, D-IC#2, and D-IC#3 is connected to the first clock noise compensation wiring CPLa, or when one of the fourth to sixth source drive integrated circuits D-IC#4, D-IC#5, and D-IC#6 is connected to the second clock noise compensation wiring CPLb, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can receive an application of a clock pseudo signal from one source drive integrated circuit.

[0171] In such a case, as shown in graph (a) of FIG. 13, the slope of the radiation amount graph of the clock pseudo signal can be the gentlest.

[0172] When two of the first to third source drive integrated circuits D-IC#1, D-IC#2, and D-IC#3 are connected to the first clock noise compensation wiring CPLa, or when two of the fourth to sixth source drive integrated circuits D-IC#4, D-IC#5, and D-IC#6 are connected to the second clock noise compensation wiring CPLb, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can receive an application of a clock pseudo signal from two source drive integrated circuits.

[0173] In such a case, as shown in graph (b) of FIG. 13, the slope of the radiation amount graph of the clock pseudo signal can be steeper than that of graph (a) of FIG. 13.

[0174] When all of the first to third source drive integrated circuits D-IC#1, D-IC#2, and D-IC#3 are connected to the first clock noise compensation wiring CPLa, or when all of the fourth to sixth source drive integrated circuits D-IC#4, D-IC#5, and D-IC#6 are connected to the second clock noise compensation wiring CPLb, each of the first clock noise compensation wiring CPLa and the second clock noise compensation wiring CPLb can receive an application of a clock pseudo signal from three source drive integrated circuits.

[0175] In such a case, as shown in graph (c) of FIG. 13, the slope of the radiation amount graph of the clock pseudo-signal can be steeper than that of graph (b) of FIG. 13. That is, the slope of the radiation amount graph of the clock pseudo-signal can be the steepest. That is, the meaning that the slope of the radiation amount graph of the clock pseudo-signal is the steepest means that the radiation amount of the clock pseudo-signal is the highest.

[0176] Ultimately, the display device according to another embodiment of the present specification can adjust the radiation amount of the clock pseudo-signal by controlling the number of source drive integrated circuits connected to the clock noise compensation wiring CPL through a plurality of clock noise compensation switches CPS.

[0177] Thereby, the radiation amount of the clock pseudo-signal can be adjusted according to the radiation amount of the electromagnetic wave of the clock signal through a plurality of clock noise compensation switches CPS.

[0178] Therefore, the display device according to another embodiment (the fifth embodiment) of the present specification can match the radiation amount of the clock signal electromagnetic wave and the radiation amount of the clock pseudo-signal, and electromagnetic interference can be effectively removed.

[0179] In the following, the display device according to another embodiment of the present specification will be described.

[0180] For convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to another embodiment of the present specification, duplicate descriptions of the same components are omitted, and the same reference numerals are used for the same components.

[0181] FIG. 14 is a diagram showing a multiplexer and a multiplexer noise compensation wiring arranged in a non-display area according to another embodiment (the sixth embodiment) of the present specification.

[0182] Referring to FIG. 14, in the non-display area NA of the display panel, a plurality of source driver integrated circuits D-IC#1, ..., D-IC#6, a multiplexer MUX, a multiplexer control signal wiring MCL, and a multiplexer noise compensation wiring MPL may be arranged.

[0183] The plurality of source driver integrated circuits D-IC#1, ..., D-IC#6 can supply data voltages to the link wiring. And the plurality of source driver integrated circuits D-IC#1, ..., D-IC#6 and the multiplexer MUX are connected through the link wiring, and a data voltage can be provided to the multiplexer MUX.

[0184] And the multiplexer MUX includes a plurality of first switching elements SW1 and a plurality of second switching elements SW2. Each of the plurality of first switching elements SW1 connects one of the link wiring and the plurality of data wirings by a first control signal applied to the first multiplexer control wiring MCL1. And each of the plurality of second switching elements SW2 connects another one of the link wiring and the plurality of data wirings by a second control signal applied to the second multiplexer control wiring MCL2.

[0185] Specifically, the first switching element SW1 includes a gate electrode connected to the first multiplexer control wiring MCL1, a drain electrode connected to the link wiring, and a source electrode connected to one of the plurality of data wirings.

[0186] Therefore, when the first multiplexer control signal applied to the first multiplexer control wiring MCL1 is at a high level, the first switching element SW1 is turned on, and the link wiring is electrically connected to one of the plurality of data wirings. In contrast, when the first multiplexer control signal applied to the first multiplexer control signal wiring MCL1 is at a low level, the first switching element SW1 is turned off, and the link wiring is electrically separated from one of the plurality of data wirings.

[0187] The second switching element SW2 includes a gate electrode connected to the second multiplexer control wiring MCL2, a drain electrode connected to the link wiring, and a source electrode connected to another one of the plurality of data wirings.

[0188] Therefore, when the second multiplexer control signal applied to the second multiplexer control wiring MCL2 is at a high level, the second switching element SW2 is turned on, and the link wiring is electrically connected to another one of the plurality of data wirings. In contrast, when the second multiplexer control signal applied to the second multiplexer control signal wiring MCL2 is at a low level, the second switching element SW2 is turned off, and the link wiring is electrically separated from another one of the plurality of data wirings.

[0189] Also, the plurality of source drive integrated circuits D-IC#1,..., D-IC#6 can provide the first multiplexer control signal and the second multiplexer control signal to the first multiplexer control wiring MCL1 and the second multiplexer control wiring MCL2 described above, respectively. And the plurality of source drive integrated circuits D-IC#1,..., D-IC#6 can provide a multiplexer pseudo signal to the multiplexer noise compensation wiring MPL. The phase of the multiplexer pseudo signal described above can be inverted with respect to the phase of the first multiplexer control signal. Alternatively, the phase of the multiplexer pseudo signal can be inverted with respect to the phase of the second multiplexer control signal. That is, the phase of the multiplexer pseudo signal can be inverted with respect to the phases of the plurality of multiplexer control signals. The multiplexer pseudo signal described above can be referred to as an inverted multiplexer control signal.

[0190] Referring to FIG. 14, each of the first multiplexer control wiring MCL1 to which the first multiplexer control signal is applied and the second multiplexer control wiring MCL2 to which the second multiplexer control signal is applied is connected to the outermost source drive integrated circuits D-IC#1 and D-IC#6 among the plurality of source drive integrated circuits D-IC#1,..., D-IC#6, and can form a loop configuration.

[0191] Specifically, the first multiplexer control wiring MCL1 is connected to the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6, and can receive the application of the first multiplexer control signal from the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6. And the second multiplexer control wiring MCL2 is also connected to the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6, and can receive the application of the first multiplexer control signal.

[0192] On the other hand, the multiplexer noise compensation wiring MPL can include a first multiplexer noise compensation wiring MPLa, a second multiplexer noise compensation wiring MPLb, and a third multiplexer noise compensation wiring MPLc that are arranged adjacent to the first multiplexer control wiring MCL1 and the second multiplexer control wiring MCL2.

[0193] And each of the first multiplexer noise compensation wiring MPLa, the second multiplexer noise compensation wiring MPLb, and the third multiplexer noise compensation wiring MPLc can be connected to at least one of the plurality of source driver integrated circuits D-IC#1,... D-IC#6.

[0194] Specifically, the first multiplexer noise compensation wiring MPLa is connected to the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6, and a multiplexer pseudo signal whose phase is inverted from the first multiplexer control signal or the second multiplexer control signal can be applied from the first source driver integrated circuit D-IC#1 and the sixth source driver integrated circuit D-IC#6.

[0195] The second multiplexer noise compensation wiring MPLb is connected to the second source driver integrated circuit D-IC#2 and the fifth source driver integrated circuit D-IC#5, and a multiplexer pseudo signal whose phase is inverted from the first multiplexer control signal or the second multiplexer control signal can be applied from the second source driver integrated circuit D-IC#2 and the fifth source driver integrated circuit D-IC#5.

[0196] The third multiplexer noise compensation wiring MPLc is connected to the third source driver integrated circuit D-IC#3 and the fourth source driver integrated circuit D-IC#4, and a multiplexer pseudo signal whose phase is inverted from the first multiplexer control signal or the second multiplexer control signal can be applied from the third source driver integrated circuit D-IC#3 and the fourth source driver integrated circuit D-IC#4.

[0197] As shown in FIG. 14, each of the first multiplexer noise compensation wiring MPL a to the third multiplexer noise compensation wiring MPL c may be in a linear form. However, it is not limited thereto, and each of the first multiplexer noise compensation wiring MPL a to the third multiplexer noise compensation wiring MPL c may be in a bent form. For example, each of the first multiplexer noise compensation wiring MPL a to the third multiplexer noise compensation wiring MPL c may be in a square wave form or a sine wave form. Alternatively, the first multiplexer noise compensation wiring MPL a to the third multiplexer noise compensation wiring MPL c may have a zigzag waveform. Therefore, the total length of each of the first multiplexer noise compensation wiring MPL a to the third multiplexer noise compensation wiring MPL c can be extended.

[0198] As described above, the display device according to the present specification and another embodiment (the sixth embodiment) arranges the multiplexer noise compensation wiring MPL so as to be adjacent to a plurality of multiplexer control signal wirings MCL, and a multiplexer pseudo signal whose phase is inverted from the multiplexer control signal can be applied to the multiplexer noise compensation wiring MPL.

[0199] Therefore, the electromagnetic waves generated by the multiplexer control signal in the plurality of multiplexer control signal wirings MCL can be canceled by the multiplexer pseudo signal.

[0200] Ultimately, the display device according to still another embodiment (the sixth embodiment) of the present specification can significantly reduce the interference caused by the electromagnetic wave of the multiplexer control signal, and has the effect of preventing abnormal driving of the display device.

[0201] Hereinafter, a display device according to still another embodiment (the seventh embodiment) of the present specification will be described. The display device according to one embodiment of the present specification and the display device according to still another embodiment (the seventh embodiment) of the present specification differ only in the multiplexer noise compensation switch MPS connected to the multiplexer noise compensation wiring MPL, and thus will be specifically described.

[0202] For convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to still another embodiment (the seventh embodiment) of the present specification, duplicate descriptions of the same components are omitted, and the same reference numerals are used for the same components.

[0203] FIG. 15 is a diagram showing a multiplexer control wiring, a multiplexer noise compensation wiring, and a multiplexer noise compensation switch arranged in a non-display area of a display device according to still another embodiment (the seventh embodiment) of the present specification.

[0204] In the display device according to still another embodiment (the seventh embodiment) of the present specification, a plurality of multiplexer noise compensation switches MPS arranged between a plurality of multiplexer noise compensation wirings MPL arranged in the non-display area NA and a plurality of source drive integrated circuits D-IC#1,..., D-IC#6 can be further included.

[0205] And the plurality of multiplexer noise compensation switches MPS can control the electrical connection states of the plurality of multiplexer noise compensation wirings MPL and the plurality of source drive integrated circuits D-IC#1,..., D-IC#6.

[0206] As shown in FIG. 15, the plurality of multiplexer noise compensation switches MPS can include a first multiplexer noise compensation switch MPS1 to a sixth multiplexer noise compensation switch MPS6.

[0207] Specifically, the first multiplexer noise compensation switch MPS1 is connected between the first multiplexer noise compensation wiring MPL a and the first source drive integrated circuit D-IC #1, and can control the connection state between the first multiplexer noise compensation wiring MPL a and the first source drive integrated circuit D-IC #1.

[0208] And the second multiplexer noise compensation switch MPS2 is connected between the second multiplexer noise compensation wiring MPL b and the second source drive integrated circuit D-IC #2, and can control the connection state between the second multiplexer noise compensation wiring MPL b and the second source drive integrated circuit D-IC #2.

[0209] And the third multiplexer noise compensation switch MPS3 is connected between the third multiplexer noise compensation wiring MPL c and the third source drive integrated circuit D-IC #3, and can control the connection state between the third multiplexer noise compensation wiring MPL c and the third source drive integrated circuit D-IC #3.

[0210] And the fourth multiplexer noise compensation switch MPS4 is connected between the third multiplexer noise compensation wiring MPL c and the fourth source drive integrated circuit D-IC #4, and can control the connection state between the third multiplexer noise compensation wiring MPL c and the fourth source drive integrated circuit D-IC #4.

[0211] And the fifth multiplexer noise compensation switch MPS5 is connected between the second multiplexer noise compensation wiring MPL b and the fifth source drive integrated circuit D-IC #5, and can control the connection state between the second multiplexer noise compensation wiring MPL b and the fifth source drive integrated circuit D-IC #5.

[0212] The sixth multiplexer noise compensation switch MPS6 is connected between the first multiplexer noise compensation wiring MPL a and the sixth source drive integrated circuit D-IC#6, and can control the connection state between the first multiplexer noise compensation wiring MPL a and the sixth source drive integrated circuit D-IC#6.

[0213] Therefore, the number of source drive integrated circuits connected to the first multiplexer noise compensation wiring MPL a can be adjusted through the first multiplexer noise compensation switch MPS1 and the sixth multiplexer noise compensation switch MPS6. The number of source drive integrated circuits connected to the second multiplexer noise compensation wiring MPL b can be adjusted through the second multiplexer noise compensation switch MPS2 and the fifth multiplexer noise compensation switch MPS5. The number of source drive integrated circuits connected to the third multiplexer noise compensation wiring MPL c can be adjusted through the third multiplexer noise compensation switch MPS3 and the fourth multiplexer noise compensation switch MPS4.

[0214] For example, any one of the first multiplexer noise compensation switch MPS1, the second multiplexer noise compensation switch MPS2, the third multiplexer noise compensation switch MPS3, the fourth multiplexer noise compensation switch MPS4, the fifth multiplexer noise compensation switch MPS5, and the sixth multiplexer noise compensation switch MPS6 can be selectively and independently turned on.

[0215] As described above with reference to FIG. 13, the amount of radiation of the clock pseudo signal may increase as the number of source drive integrated circuits connected to each of the clock noise compensation wirings CPL increases.

[0216] Based on the same technical logic, the amount of radiation of the multiplexer pseudo signal may increase as the number of source drive integrated circuits connected to each of the plurality of multiplexer noise compensation wirings MPL increases.

[0217] Therefore, in the display device according to still another embodiment (the seventh embodiment) of the present specification, the radiation amount of the inverted multiplexer signal can also be adjusted through a plurality of multiplexer noise compensation switches MPS.

[0218] Accordingly, the radiation amount of the multiplexer pseudo signal can be adjusted through a plurality of multiplexer noise compensation switches MPS in accordance with the radiation amount of the electromagnetic wave of the multiplexer control signal.

[0219] Therefore, the display device according to still another embodiment (the seventh embodiment) of the present specification can match the radiation amount of the electromagnetic wave of the multiplexer control signal and the radiation amount of the multiplexer pseudo signal, and electromagnetic interference can be effectively removed.

[0220] Hereinafter, the display device according to still another embodiment (the eighth embodiment) of the present specification will be described.

[0221] For the sake of convenience of explanation, in the display device according to one embodiment of the present specification and the display device according to another embodiment of the present specification, duplicate descriptions of the same components are omitted, and the same drawing reference numerals are used for the same components.

[0222] FIG. 16 is a diagram showing a multiplexer control wiring, a multiplexer noise compensation wiring, and a multiplexer noise compensation switch arranged in a non-display area of a display device according to still another embodiment (the eighth embodiment) of the present specification.

[0223] In the display device according to still another embodiment (the eighth embodiment) of the present specification, the multiplexer noise compensation wiring MPL_1 may include first to fifth multiplexer noise compensation wirings MPLa_1, MPLb_1, MPLc_1, MPLd_1, MPLe_1 arranged adjacent to the first multiplexer control wiring MCL1 and the second multiplexer control wiring MCL2.

[0224] Then, each of the first to fifth multiplexer noise compensation wirings MPL a_1, MPL b_1, MPL c_1, MPL d_1, and MPL e_1 can be electrically connected to at least one of a plurality of source drive integrated circuits D-IC#1, ..., D-IC#6 through a plurality of multiplexer noise compensation switches MPS_1.

[0225] That is, the plurality of multiplexer noise compensation switches MPS_1 can control the connection states of the first to fifth multiplexer noise compensation wirings MPL a_1, MPL b_1, MPL c_1, MPL d_1, and MPL e_1 and the plurality of source drive integrated circuits D-IC#1, ..., D-IC#6.

[0226] As shown in FIG. 16, the plurality of multiplexer noise compensation switches MPS_1 can include a first multiplexer noise compensation switch MPS1_1 to a tenth multiplexer noise compensation switch MPS10_1.

[0227] Specifically, the first multiplexer noise compensation switch MPS1_1 is connected between the first multiplexer noise compensation wiring MPL a_1 and the first source drive integrated circuit D-IC#1, and can control the connection state between the first multiplexer noise compensation wiring MPL a_1 and the first source drive integrated circuit D-IC#1.

[0228] And the second multiplexer noise compensation switch MPS2_1 is connected between the first multiplexer noise compensation wiring MPL a_1 and the second source drive integrated circuit D-IC#2, and can control the connection state between the first multiplexer noise compensation wiring MPL a_1 and the second source drive integrated circuit D-IC#2.

[0229] And the third multiplexer noise compensation switch MPS3_1 is connected between the second multiplexer noise compensation wiring MPL b_1 and the second source drive integrated circuit D-IC#2, and can control the connection state between the second multiplexer noise compensation wiring MPL b_1 and the second source drive integrated circuit D-IC#2.

[0230] The fourth multiplexer noise compensation switch MPS4_1 is connected between the second multiplexer noise compensation wiring MPLb_1 and the third source drive integrated circuit D-IC#3, and can control the connection state between the second multiplexer noise compensation wiring MPLb_1 and the third source drive integrated circuit D-IC#3.

[0231] The fifth multiplexer noise compensation switch MPS5_1 is connected between the third multiplexer noise compensation wiring MPLc_1 and the third source drive integrated circuit D-IC#3, and can control the connection state between the third multiplexer noise compensation wiring MPLc_1 and the third source drive integrated circuit D-IC#3.

[0232] The sixth multiplexer noise compensation switch MPS6_1 is connected between the third multiplexer noise compensation wiring MPLc_1 and the fourth source drive integrated circuit D-IC#4, and can control the connection state between the third multiplexer noise compensation wiring MPLc_1 and the fourth source drive integrated circuit D-IC#4.

[0233] The seventh multiplexer noise compensation switch MPS7_1 is connected between the fourth multiplexer noise compensation wiring MPLd_1 and the fourth source drive integrated circuit D-IC#4, and can control the connection state between the fourth multiplexer noise compensation wiring MPLd_1 and the fourth source drive integrated circuit D-IC#4.

[0234] The eighth multiplexer noise compensation switch MPS8_1 is connected between the fourth multiplexer noise compensation wiring MPLd_1 and the fifth source drive integrated circuit D-IC#5, and can control the connection state between the fourth multiplexer noise compensation wiring MPLd_1 and the fifth source drive integrated circuit D-IC#5.

[0235] The ninth multiplexer noise compensation switch MPS9_1 is connected between the fifth multiplexer noise compensation wiring MPLe_1 and the fifth source drive integrated circuit D-IC#5, and can control the connection state between the fifth multiplexer noise compensation wiring MPLe_1 and the fifth source drive integrated circuit D-IC#5.

[0236] The first multiplexer noise compensation switch MPS10_1 is connected between the fifth multiplexer noise compensation wiring MPLe_1 and the sixth source driver integrated circuit D-IC#6, and can control the connection state between the fifth multiplexer noise compensation wiring MPLe_1 and the sixth source driver integrated circuit D-IC#6.

[0237] Therefore, the first multiplexer noise compensation wiring MPLa_1 is connected to at least one of the first source driver integrated circuit D-IC#1 and the second source driver integrated circuit D-IC#2 in the first source driver integrated circuit D-IC#1, and a multiplexer pseudo signal whose phase is inverted from at least one of the first source driver integrated circuit D-IC#1 and the second source driver integrated circuit D-IC#2 to the first multiplexer control signal or the second multiplexer control signal can be applied.

[0238] The second multiplexer noise compensation wiring MPLb_1 is connected to at least one of the second source driver integrated circuit D-IC#2 and the third source driver integrated circuit D-IC#3 in the second source driver integrated circuit D-IC#2, and a multiplexer pseudo signal whose phase is inverted from at least one of the second source driver integrated circuit D-IC#2 and the third source driver integrated circuit D-IC#3 to the first multiplexer control signal or the second multiplexer control signal can be applied.

[0239] The third multiplexer noise compensation wiring MPLc_1 is connected to at least one of the third source driver integrated circuit D-IC#3 and the fourth source driver integrated circuit D-IC#4 in the third source driver integrated circuit D-IC#3, and a multiplexer pseudo signal whose phase is inverted from at least one of the third source driver integrated circuit D-IC#3 and the fourth source driver integrated circuit D-IC#4 to the first multiplexer control signal or the second multiplexer control signal can be applied.

[0240] The fourth multiplexer noise compensation wiring MPLd_1 is connected to at least one of the fifth source driver integrated circuits D-IC#5 in the fourth source driver integrated circuit D-IC#4, and a multiplexer pseudo signal whose phase is inverted from the first multiplexer control signal or the second multiplexer control signal can be applied to at least one of the fifth source driver integrated circuits D-IC#5 in the fourth source driver integrated circuit D-IC#4.

[0241] The fifth multiplexer noise compensation wiring MPLe_1 is connected to at least one of the sixth source driver integrated circuits D-IC#6 in the fifth source driver integrated circuit D-IC#5, and a multiplexer pseudo signal whose phase is inverted from the first multiplexer control signal or the second multiplexer control signal can be applied to at least one of the sixth source driver integrated circuits D-IC#6 in the fifth source driver integrated circuit D-IC#5.

[0242] As shown in FIG. 16, each of the first multiplexer noise compensation wiring MPLa_1 to the fifth multiplexer noise compensation wiring MPLe_1 may be in a linear form. However, it is not limited thereto, and each of the first multiplexer noise compensation wiring MPLa_1 to the fifth multiplexer noise compensation wiring MPLe_1 may be in a bent form. For example, each of the first multiplexer noise compensation wiring MPLa_1 to the fifth multiplexer noise compensation wiring MPLe_1 may be in a square wave form or a sine wave form.

[0243] Alternatively, the first multiplexer noise compensation wiring MPLa_1 to the fifth multiplexer noise compensation wiring MPLe_1 may have a zigzag wave shape.

[0244] In other words, the number of source driver integrated circuits connected to the first to fifth multiplexer noise compensation wirings MPLa_1, MPLb_1, MPLc_1, MPLd_1, and MPLe_1 through the first multiplexer noise compensation switch MPS1_1 and the tenth multiplexer noise compensation switch MPS10_1 can be adjusted.

[0245] As described above with reference to FIG. 13, as the number of source driver integrated circuits connected to each of the clock noise compensation wirings CPL increases, the amount of radiation of the clock pseudo signal can increase.

[0246] By the same technical logic, as the number of source driver integrated circuits connected to each of the plurality of multiplexer noise compensation wirings MPL_1 increases, the amount of radiation of the multiplexer pseudo signal can increase.

[0247] Therefore, also in the display device according to another embodiment (the eighth embodiment) of the present specification, the amount of radiation of the inverted multiplexer signal can be adjusted through a plurality of multiplexer noise compensation switches MPS_1.

[0248] Accordingly, by controlling the plurality of multiplexer noise compensation switches MPS_1, the amount of radiation of the multiplexer pseudo signal can be adjusted in accordance with the amount of radiation of the electromagnetic wave of the multiplexer control signal.

[0249] Therefore, the display device according to another embodiment (the eighth embodiment) of the present specification can match the amount of radiation of the electromagnetic wave of the multiplexer control signal and the amount of radiation of the multiplexer pseudo signal, and electromagnetic interference can be effectively removed.

[0250] The display device according to various embodiments of the present specification can be described as follows.

[0251] Embodiments of the present invention can also be described as follows.

[0252] According to an aspect of the present invention, a display device according to an embodiment of the present specification includes a display panel including a display area where a plurality of pixels are arranged and a non-display area excluding the display area, a gate driving unit arranged in the non-display area of the display panel to provide a gate signal to the plurality of pixels, a data driving unit that provides a data voltage to the plurality of pixels and provides a clock signal to the gate driving unit through a clock wiring, and a clock noise compensation wiring arranged in the non-display area of the display panel to which a clock pseudo signal having a phase inverted from the clock signal is applied, and electromagnetic interference caused by the clock signal can be effectively removed.

[0253] According to another feature of the present invention, the data driving unit includes a plurality of source driving integrated circuits arranged in a first direction, the clock wiring includes a first clock wiring and a second clock wiring arranged on both sides of the first direction and extending in a second direction, and each of the first clock wiring and the second clock wiring can be connected to a source driving integrated circuit arranged on the outermost side among the plurality of source driving integrated circuits.

[0254] According to still another feature of the present invention, the clock wiring can further include a third clock wiring extending in the second direction to connect the first clock wiring and the second clock wiring.

[0255] According to still another feature of the present invention, the clock noise compensation wiring can include a first clock noise compensation wiring and a second clock noise compensation wiring arranged outside the first clock wiring and the second clock wiring.

[0256] According to still another feature of the present invention, each of the first clock noise compensation wiring and the second clock noise compensation wiring can be connected to a source driving integrated circuit arranged between the source driving integrated circuits connected to the clock wiring among the plurality of source driving integrated circuits.

[0257] According to still another feature of the present invention, the clock noise compensation wiring can have a bent shape.

[0258] According to another feature of the present invention, at least one clock noise compensation switch can be arranged between the clock noise compensation wiring and each of the plurality of source drive integrated circuits.

[0259] According to another feature of the present invention, the clock noise compensation wiring can further include a third clock noise compensation wiring that extends in a first direction and connects the first clock noise compensation wiring and the second clock noise compensation wiring.

[0260] According to another feature of the present invention, the width of the clock noise compensation wiring may be wider than the width of the clock wiring.

[0261] According to another feature of the present invention, the first clock noise compensation wiring may be composed of a plurality, and the second clock noise compensation wiring may be composed of a plurality.

[0262] According to another feature of the present invention, each of the plurality of first clock noise compensation wirings is connected to a different source drive integrated circuit, and each of the plurality of second clock noise compensation wirings may be connected to a different source drive integrated circuit.

[0263] According to another feature of the present invention, the plurality of first clock noise compensation wirings are all connected to one source drive integrated circuit, and the plurality of second clock noise compensation wirings may all be connected to another one source drive integrated circuit.

[0264] According to another feature of the present invention, the display device further includes a multiplexer that is connected to the plurality of source drive integrated circuits and is controlled by a multiplexer control signal applied through a multiplexer control wiring to provide a data voltage to the plurality of pixels, and a multiplexer noise compensation wiring that is arranged in a non-display area of the display panel and to which a multiplexer pseudo signal having a phase inverted from the multiplexer control signal is applied from the plurality of source drive integrated circuits.

[0265] According to another feature of the present invention, at least one multiplexer noise compensation switch may be disposed between the multiplexer noise compensation wiring and each of the plurality of source driver integrated circuits.

[0266] According to another feature of the present invention, the multiplexer noise compensation wiring includes a plurality of multiplexer noise compensation wirings, and each of the plurality of multiplexer noise compensation wirings may be connected to at least one of the plurality of source driver integrated circuits through the at least one multiplexer noise compensation switch.

[0267] The length of the clock noise compensation wiring is the same as the length of the clock wiring.

[0268] The radiation amount of the clock signal is equivalent to the radiation amount of the clock pseudo signal.

[0269] The first clock noise compensation wiring and one of the plurality of first clock noise compensation wirings are connected to the same source driver integrated circuit, and the second clock noise compensation wiring and one of the plurality of second clock noise compensation wirings are connected to the same source driver integrated circuit.

[0270] The first clock noise compensation wiring and all of the plurality of first clock noise compensation wirings are connected to the same source driver integrated circuit, and the second clock noise compensation wiring and all of the plurality of second clock noise compensation wirings are connected to the same source driver integrated circuit.

[0271] Although the embodiments of this specification have been described in more detail, this specification is not necessarily limited to such embodiments, and various modifications can be made within the scope not departing from the technical idea of this specification. Therefore, the embodiments disclosed in this specification are not for limiting the technical idea of this specification, but for explanation, and the scope of the technical idea of this specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not limiting. The protection scope of this specification should be interpreted by the following claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of this specification.

Claims

1. A display panel including a display area where a plurality of pixels are arranged and a non-display area excluding the display area; A gate driving unit arranged in the non-display area of the display panel to provide a gate signal to the plurality of pixels; A data driving unit that provides a data voltage to the plurality of pixels and provides a clock signal to the gate driving unit through a clock wiring; and Including a clock noise compensation wiring arranged in the non-display area of the display panel to which a clock pseudo signal having a phase inverted from the clock signal is applied, The data driving unit includes a plurality of source driving integrated circuits arranged in a first direction, The clock wiring includes a first clock wiring and a second clock wiring arranged on both sides in the first direction and extending in a second direction, Each of the first clock wiring and the second clock wiring is connected to a source driving integrated circuit arranged on the outermost side among the plurality of source driving integrated circuits, a display device.

2. The clock wiring, Further includes a third clock wiring extending in the second direction and connecting the first clock wiring and the second clock wiring, the display device according to claim 1.

3. The clock noise compensation wiring, Includes a first clock noise compensation wiring and a second clock noise compensation wiring arranged outside the first clock wiring and the second clock wiring, the display device according to claim 1.

4. Each of the first clock noise compensation wiring and the second clock noise compensation wiring is connected to a source driving integrated circuit arranged between the source driving integrated circuits connected to the clock wiring among the plurality of source driving integrated circuits, the display device according to claim 3.

5. The clock noise compensation wiring has a bent shape, the display device according to claim 1.

6. At least one clock noise compensation switch is arranged between the clock noise compensation wiring and each of the plurality of source driving integrated circuits, the display device according to claim 3.

7. The clock noise compensation wiring, Further includes a third clock noise compensation wiring extending in the first direction and connecting the first clock noise compensation wiring and the second clock noise compensation wiring, the display device according to claim 3.

8. The width of the clock noise compensation wiring is wider than the width of the clock wiring, the display device according to claim 1.

9. The first clock noise compensation wiring is composed of a plurality of pieces, The second clock noise compensation wiring is composed of a plurality, and the display device according to claim 3.

10. Each of the plurality of first clock noise compensation wirings is connected to a different source drive integrated circuit, Each of the plurality of second clock noise compensation wirings is connected to a different source drive integrated circuit, and the display device according to claim 9.

11. All of the plurality of first clock noise compensation wirings are connected to one of the source drive integrated circuits, All of the plurality of second clock noise compensation wirings are connected to another one of the source drive integrated circuits, and the display device according to claim 9.

12. A multiplexer that is connected to the plurality of source drive integrated circuits and is controlled by a multiplexer control signal applied through a multiplexer control wiring to provide a data voltage to the plurality of pixels, and The display device according to claim 1, further including a multiplexer noise compensation wiring that is disposed in a non-display area of the display panel and to which a multiplexer pseudo signal having a phase inverted from the multiplexer control signal is applied from the plurality of source drive integrated circuits.

13. At least one multiplexer noise compensation switch is disposed between the multiplexer noise compensation wiring and each of the plurality of source drive integrated circuits, and the display device according to claim 12.

14. The multiplexer noise compensation wiring includes a plurality of multiplexer noise compensation wirings, Each of the plurality of multiplexer noise compensation wirings is connected to at least one of the plurality of source drive integrated circuits through the at least one multiplexer noise compensation switch, and the display device according to claim 13.

15. The length of the clock noise compensation wiring is the same as the length of the clock wiring, and the display device according to claim 1.

16. The radiation amount of the clock signal is equivalent to the radiation amount of the clock pseudo signal, and the display device according to claim 1.

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