Display device

Abstract

To reduce the power consumption of a display device and to reduce the power consumption of a driving circuit of a display device.SOLUTION: A pixel of the display device has a display element. The pixel has a function of holding a first voltage according to a first input pulse signal and a function of driving the display element by a third voltage obtained by adding a second voltage corresponding to a second input pulse signal to the first voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display device, and a driving method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. The semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] In recent years, display devices included in mobile phones such as smartphones, tablet-type information terminals, notebook PCs (personal computers), portable game machines, etc. have been improved in various aspects. For example, development of display devices such as increasing the resolution, improving the color reproducibility, reducing the size of the driving circuit, and reducing the power consumption has been carried out.

[0004] For example, as a switching element included in a pixel circuit of a display device, a technique of applying a transistor in which a metal oxide is included in a channel formation region can be mentioned. In particular, as the metal oxide, an In-Ga-Zn-based oxide can be used. Patent Document 1 discloses an invention of using a transistor including an In-Ga-Zn-based oxide in a channel formation region in a pixel circuit of a display device.

[0005] Also, for example, in order to display a multi-tone image on a display device having a light-emitting element, an invention of a source driver IC using a multi-tone linear digital-to-analog conversion circuit is described in Patent Document 2.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] In order to display high-quality images, a display device is required to have, for example, high resolution, multiple gradations, a wide color gamut, etc. For example, in a display device including a light-emitting element such as a liquid crystal element or an organic EL (Electro Luminescence) element, in order to realize an image with multiple gradations, it is necessary to suitably design a source driver circuit.

[0008] However, in order to handle image data with multiple gradations, it is necessary to increase the resolution of the digital-to-analog conversion circuit included in the source driver circuit. On the other hand, when designing a digital-to-analog conversion circuit with high resolution, the circuit area increases.

[0009] Also, in a circuit section that handles analog signals, such as the digital-to-analog conversion circuit included in the source driver circuit, a higher power supply voltage is required compared to a circuit section that generates digital signals. Therefore, it has been difficult to reduce the power consumption of the source driver circuit. In addition, a circuit for generating at least two types of power supply voltages is required for a device on which a display panel is mounted.

[0010] One aspect of the present invention is to reduce the power consumption of a display device as one of the problems. Or, to reduce the power consumption of a drive circuit of a display device as one of the problems. Or, to provide a display device including a source driver circuit that can be driven by a single power supply voltage as one of the problems. Or, to reduce the power consumption of a device including a display device as one of the problems. Or, to simplify the configuration of a display device, a drive circuit, or a device including a display device as one of the problems.

[0011] Another object is to provide a pixel circuit (also described as a semiconductor device in this specification and the like) capable of generating multi-tone image data. Another object is to provide a display device having the semiconductor device. Another object is to provide an electronic apparatus having the display device.

[0012] Another object is to provide a display device having a source driver circuit with a small circuit area. Another object is to provide a display device having a source driver circuit with low power consumption.

[0013] Note that the description of these objects does not preclude the existence of other objects. Note that one aspect of the present invention does not necessarily have to solve all of these objects. Other objects can be extracted from the description in the specification, drawings, claims, and the like.

Means for Solving the Problems

[0014] One aspect of the present invention is a display device including pixels, each pixel including a display element, the pixel having a function of holding a first voltage corresponding to a first pulse signal input thereto, and a function of driving the display element with a third voltage obtained by adding a second voltage corresponding to a second pulse signal input thereto to the first voltage.

[0015] In the above, the display element is preferably a light-emitting element. At this time, the light-emitting element preferably emits light with a luminance corresponding to the third voltage. Further, the light-emitting element preferably uses an organic EL element or a light-emitting diode. Further, the light-emitting diode preferably uses a micro LED or a mini LED.

[0016] In the above, the display element is preferably a liquid crystal element. At this time, the liquid crystal element preferably changes the alignment of the liquid crystal in response to the third voltage.

[0017] Also, in the above, it is preferable to have a first driving circuit that supplies a first pulse signal. At this time, in the first driving circuit, the first power supply voltage for generating the first pulse signal is preferably lower than the maximum value of the third voltage. Further, it is preferable that the first driving circuit generates the first pulse signal without boosting the first power supply voltage. Also, the first power supply voltage is preferably half of the maximum value of the third voltage or a voltage in the vicinity thereof.

[0018] Also, in the above, it is preferable to have a system circuit that controls the first driving circuit. At this time, it is preferable that the system circuit has a function of supplying the first power supply voltage to the first driving circuit.

[0019] Also, in the above, one of the driving voltages of the system circuit is 1.8V, 2.5V, 3.3V, or in the vicinity thereof, and it is preferable that the system circuit has a function of supplying the same voltage as the driving voltage to the first driving circuit as the first power supply voltage.

[0020] Also, in the above, the first power supply voltage supplied from the system circuit to the first driving circuit is preferably supplied without being boosted.

Advantages of the Invention

[0021] According to one aspect of the present invention, the power consumption of the display device can be reduced. Or, the power consumption of the driving circuit of the display device can be reduced. Or, a display device including a source driver circuit that can be driven by a single power supply voltage can be provided. Or, the power consumption of the device including the display device can be reduced. Or, the configuration of the display device, the driving circuit, or the device including the display device can be simplified.

[0022] Also, according to one aspect of the present invention, a semiconductor device capable of generating multi-tone image data can be provided. Or, a display device having a source driver circuit with a small circuit area can be provided. Or, a display device having a source driver circuit with low power consumption can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0024]

Figure 1

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Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0026] In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description thereof is omitted. Also, when referring to the same function, the hatching pattern may be the same, and there may be cases where no reference numerals are particularly assigned.

[0027] In each of the drawings described in this specification, the size, layer thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0028] In this specification and the like, ordinal numbers such as "first" and "second" are attached to avoid confusion of components and are not numerically limiting.

[0029] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0030] Also, in this specification and the like, a display panel on which a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached to the substrate, or a display panel on which an IC is mounted on the substrate by a COG (Chip On Glass) method or the like may be referred to as a display panel module, a display module, or simply a display panel.

[0031] (Embodiment 1) In this embodiment, a semiconductor device according to an aspect of the present invention and a display device having the semiconductor device will be described.

[0032] <Circuit Configuration of Display Device> FIG. 1 is a block diagram showing an example of a display device DD. The display device DD includes a display unit PA, a source driver circuit SD, and a gate driver circuit GD.

[0033] The display unit PA has a plurality of pixels PIX. In FIG. 1, only one of the plurality of pixels PIX included in the display unit PA is shown, and the other pixels PIX are omitted. The plurality of pixels PIX included in the display unit PA are preferably arranged in a matrix.

[0034] The pixel PIX is electrically connected to the source driver circuit SD via a wiring DL. The pixel PIX is electrically connected to the gate driver circuit GD via a wiring GL. Since the display unit PA has a plurality of pixels PIX, a plurality of pixels PIX may be electrically connected to the wiring DL and the wiring GL. Also, each of the wiring DL and the wiring GL may be provided in plurality according to the number of pixels PIX included in the display unit PA. Further, depending on the circuit configuration of the pixel PIX, a configuration may be adopted in which a plurality of wirings DL or a plurality of wirings GL are electrically connected to one pixel PIX.

[0035] The pixel PIX can be configured to have one or more sub-pixels. For example, the pixel PIX may have a configuration having one sub-pixel (any one color such as red (R), green (G), blue (B), white (W), etc.), a configuration having three sub-pixels (such as three colors of red (R), green (G), and blue (B)), or a configuration having four or more sub-pixels (for example, four colors of red (R), green (G), blue (B), white (W), or four colors of red (R), green (G), blue (B), yellow (Y), etc.). Note that the color elements applied to the sub-pixels are not limited to the above, and cyan (C) and magenta (M) etc. may be combined as necessary.

[0036] The pixel PIX includes at least one or more display elements. As the display element, various display elements such as a light-emitting element, a liquid crystal element, a microcapsule, an electrophoretic element, an electro-wetting element, an electro-fluidic element, an electrochromic element, and a MEMS element can be used.

[0037] As the light-emitting element, an organic EL element, an LED (Light Emitting Diode) element, an inorganic EL element, etc. can be used.

[0038] As for the LED element, there are macro LEDs (also called giant LEDs), mini LEDs, and micro LEDs from those with large sizes. Here, those with a side dimension of the LED chip exceeding 1 mm are called macro LEDs, those larger than 100 μm and less than or equal to 1 mm are called mini LEDs, and those less than or equal to 100 μm are called micro LEDs. As the LED element applied to the pixel PIX, it is particularly preferable to use a mini LED or a micro LED. By using a micro LED, a very high-definition display device can be realized.

[0039] The source driver circuit SD has a function of generating image data for input to the pixel PIX included in the display unit PA and a function of transmitting the image data to the pixel PIX.

[0040] The source driver circuit SD can include, for example, a shift register SR, a latch circuit LAT, a level shift circuit LVS, a digital-to-analog conversion circuit DAC, an amplifier circuit AMP, and a data bus wiring DB. In FIG. 1, the output terminal of the shift register SR is electrically connected to the clock input terminal of the latch circuit LAT, the input terminal of the latch circuit LAT is electrically connected to the data bus wiring DB, the output terminal of the latch circuit LAT is electrically connected to the input terminal of the level shift circuit LVS, the output terminal of the level shift circuit LVS is electrically connected to the input terminal of the digital-to-analog conversion circuit DAC, the output terminal of the digital-to-analog conversion circuit DAC is electrically connected to the input terminal of the amplifier circuit AMP, and the output terminal of the amplifier circuit AMP is electrically connected to the display unit PA.

[0041] Note that the latch circuit LAT, level shift circuit LVS, digital-to-analog conversion circuit DAC, and amplifier circuit AMP shown in FIG. 1 are provided for one wiring DL. That is, according to the number of wirings DL, it is necessary to provide a plurality of each of the latch circuit LAT, level shift circuit LVS, digital-to-analog conversion circuit DAC, and amplifier circuit AMP. In this case, the shift register SR may be configured to sequentially transmit a pulse signal to each of the clock input terminals of the plurality of latch circuits LAT.

[0042] The data bus wiring DB is a wiring for transmitting a digital signal including image data for input to the display unit PA. The image data has a gradation level, and the larger the gradation level, the more smoothly the change in color or brightness can be expressed as a natural-looking gradation, and a natural-looking image can be displayed on the display unit PA. However, the larger the gradation level, the larger the data amount of the image data, and it is necessary to use a digital-to-analog conversion circuit with high resolution.

[0043] A digital signal including image data is input to the input terminal of the latch circuit LAT from the data bus wiring DB. Then, the latch circuit LAT performs either the operation of holding the image data or outputting the held image data from the output terminal, depending on the signal transmitted from the shift register SR.

[0044] The level shift circuit LVS has a function of converting an input signal into an output signal with a larger or smaller amplitude voltage. In FIG. 1, the level shift circuit LVS has a role of converting the amplitude voltage of the digital signal including the image data sent from the latch circuit LAT into an amplitude voltage at which the digital-to-analog conversion circuit DAC operates appropriately.

[0045] The digital-to-analog conversion circuit DAC has a function of converting a digital signal including the input image data into an analog signal, and a function of outputting the analog signal from an output terminal. In particular, when displaying multi-tone image data on the display unit PA, the digital-to-analog conversion circuit DAC needs to be a high-resolution digital-to-analog conversion circuit.

[0046] The amplifier circuit AMP has a function of amplifying (for example, amplifying voltage or current) an analog signal input to an input terminal and outputting it to an output terminal. By providing the amplifier circuit AMP between the digital-to-analog conversion circuit DAC and the display unit PA, the image data can be stably sent to the display unit PA. As the amplifier circuit AMP, a voltage follower circuit having an operational amplifier or the like can be applied. When a circuit having a differential input circuit is used as the amplifier circuit, it is preferable that the offset voltage of the differential input circuit is a voltage as close to 0V as possible.

[0047] By performing the above-described operations, the source driver circuit SD can convert a digital signal including image data sent from the data bus wiring DB into an analog signal and transmit it to the display unit PA. The source driver circuit SD has a function of generating a first signal S1 and a second signal S2, which are analog signals, and supplying them to the pixel PIX via the wiring DL. Here, the first signal S1 and the second signal S2 are pulse signals having amplitudes corresponding to the image data, respectively.

[0048] The gate driver circuit GD has a function of selecting a pixel PIX that is the input destination of the image data among a plurality of pixels PIX included in the display unit PA.

[0049] As a method of inputting image data to the display unit PA, for example, the gate driver circuit GD transmits a selection signal to a plurality of pixels PIX electrically connected to a single wiring GL, turns on the write switching elements of the image data of the plurality of pixels PIX, and then transmits the image data to the plurality of pixels PIX from the source driver circuit SD via the wiring DL to perform the writing.

[0050] Note that one aspect of the present invention is not limited to the configuration of the display device DD shown in FIG. 1. One aspect of the present invention can be, for example, a configuration in which the components of the display device DD are appropriately changed according to circumstances such as design specifications and purposes.

[0051] By the way, when displaying a multi-tone image on the display unit PA, the resolution of the digital-to-analog conversion circuit DAC may be increased. In this case, however, since the digital-to-analog conversion circuit DAC becomes large, the circuit area of the source driver circuit SD may become large. In order to reduce the circuit area of the source driver circuit SD, if circuit elements such as transistors and capacitor elements included in the circuits of the source driver circuit SD are made small, the electrical characteristics of the circuit elements may be impaired due to the influence of parasitic resistance and the influence of variations in the structure caused during the fabrication of the circuit elements.

[0052] One aspect of the present invention has a configuration in which the potential of the holding unit of the image data of the pixel PIX is varied by capacitive coupling to a potential having a higher resolution than that of the digital-to-analog conversion circuit DAC in view of the above. As a result, it is not necessary to increase the resolution of the digital-to-analog conversion circuit, so a digital-to-analog conversion circuit with a low resolution can be used. Therefore, the circuit area of the source driver circuit SD including the digital-to-analog conversion circuit DAC can be reduced, and the power consumption of the source driver circuit SD can be reduced.

[0053] FIG. 1 shows an example in which the display device DD has a system circuit SYS. The system circuit SYS has a function of controlling the operation of the source driver circuit SD. For example, the system circuit SYS has a function of supplying various signals such as a data signal, a clock signal, and a start pulse signal, and a power supply voltage to the source driver circuit SD.

[0054] Here, an example is shown in which the system circuit SYS includes a power supply generation unit PU and a control unit CU.

[0055] The control unit CU has at least a logic circuit. For example, it can be configured to have a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit).

[0056] The power supply generation unit PU has a function of generating a power supply voltage VDD for supplying the control unit CU and the source driver circuit SD. For example, the power supply generation unit PU can convert the power supplied from a battery, a power plug, etc. to generate the power supply voltage VDD.

[0057] As will be described later, the pixel PIX included in the display device DD can generate a voltage obtained by adding the amplitudes of two signals (the first signal S1 and the second signal S2) and drive the display element using these signals. Therefore, when the pixel PIX is displayed at the maximum gradation value, the voltages of the first signal S1 and the second signal S2 supplied by the source driver circuit SD can be set to half of the voltage obtained by adding them or a voltage in the vicinity thereof.

[0058] Therefore, the source driver circuit SD does not require a high power supply voltage for generating an analog signal and can operate with a single power supply voltage VDD. In FIG. 1, the power supply voltage VDD supplied from the system circuit SYS to the source driver circuit SD can be shared with the power supply voltage VDD for driving the control unit CU. The power supply voltage VDD supplied from the system circuit SYS is supplied to the shift register SR, the latch circuit LAT, the level shift circuit LVS, the digital-to-analog conversion circuit DAC, and the amplifier circuit AMP in the source driver circuit SD. At this time, the level shift circuit LVS can also be omitted.

[0059] With such a configuration, there is no need for a boosting circuit such as a DCDC converter for boosting the power supply voltage between the system circuit SYS and the source driver circuit SD. That is, the power supply voltage VDD supplied from the system circuit SYS to the source driver circuit SD is supplied to the source driver circuit SD as it is without being boosted, and is used for generating the first signal S1 and the second signal S2.

[0060] Also, since there is no need to provide a boosting circuit for boosting the power supply voltage VDD in the source driver circuit SD, not only can the circuit configuration of the source driver circuit SD be simplified, but also the power consumption of the source driver circuit SD can be reduced. That is, the source driver circuit SD can generate the first signal S1 and the second signal S2 without boosting the power supply voltage VDD.

[0061] For example, when one of the driving voltages of each circuit including the control unit CU in the system circuit SYS is 1.8V, 2.5V, 3.3V, or a voltage in the vicinity thereof, it is possible to supply that voltage as the power supply voltage VDD to the source driver circuit SD. Thereby, since the power supply generation unit PU in the system circuit SYS does not need to generate a high power supply voltage for supplying to the source driver circuit SD, the circuit configuration can be simplified.

[0062] With such a configuration, the source driver circuit SD can be driven at a low voltage, so that the power consumption of the source driver circuit SD and the display device DD can be significantly reduced.

[0063] Note that in this specification and the like, when a voltage is expressed as a voltage in the vicinity of a certain voltage, it is assumed to be a voltage including a range of plus or minus 20% of the voltage.

[0064] <Circuit configuration of pixel> An example of the circuit configuration of the pixel PIX, which is a semiconductor device according to one aspect of the present invention, will be described.

[0065] The pixel PIX illustrated below has a function of holding a first voltage corresponding to a first pulse signal (first signal S1) input from a source driver circuit SD, and a function of driving a display element with a third voltage obtained by adding a second voltage corresponding to a second pulse signal (second signal S2) to the first voltage. That is, the pixel PIX can drive the display element with a voltage higher than the maximum voltages of the first pulse signal and the second pulse signal input from the source driver circuit SD.

[0066] For example, when a light-emitting element is used as the display element, an image can be displayed by causing the light-emitting element to emit light with a luminance corresponding to the third voltage. Further, when a liquid crystal element is used as the display element, the transmittance of light from a light source such as a backlight changes by changing the alignment of the liquid crystal according to the third voltage, and an image can be displayed.

[0067] Also, the power supply voltage VDD used by the source driver circuit SD shown in FIG. 1 to generate the first signal S1 and the second signal S2 can be set to a voltage lower than the maximum value of the third voltage that can be generated by the pixel PIX (for example, the value of the third voltage when displaying at the highest gradation). Preferably, the power supply voltage VDD can be set to half (1 / 2) of the maximum value of the third voltage, or a voltage in the vicinity thereof.

[0068] The pixel PIX shown in FIG. 2A is an example when a light-emitting element is applied as the display element.

[0069] The pixel PIX illustrated in FIG. 2A includes transistors Tr1 to Tr5, a capacitor element C1, a capacitor element C2, and a light-emitting element LD. Also, wirings DL, WDL, GL1 to GL3, VL, AL, and CAT are electrically connected to the pixel PIX.

[0070] Each of transistor Tr1, transistor Tr2, transistor Tr4, and transistor Tr5 functions as a switching element. Transistor Tr3 functions as a drive transistor that controls the current flowing through light-emitting element LD. Also, the configurations described in Embodiment 3 can be applied to transistors Tr1 to Tr5.

[0071] Each of wiring DL and wiring WDL is a wiring for transmitting image data to pixel PIX, and is a wiring corresponding to wiring DL of display device DD in FIG. 1. In addition, each of wirings GL1 to GL3 is a selection signal line for pixel PIX, and is a wiring corresponding to wiring GL of display device DD in FIG. 1.

[0072] Wiring VL is a wiring for applying a predetermined potential to a specific node in pixel PIX. Wiring AL is a wiring for supplying a current to flow through light-emitting element LD.

[0073] Wiring CAT is a wiring for applying a predetermined potential to the cathode terminal of light-emitting element LD. The predetermined potential can be, for example, a reference potential, a low-level potential, a potential lower than these, and the like.

[0074] The first terminal of transistor Tr1 is electrically connected to the first terminal of capacitor C1, the second terminal of transistor Tr1 is electrically connected to wiring DL, and the gate of transistor Tr1 is electrically connected to wiring GL1. The first terminal of transistor Tr2 is electrically connected to the gate of transistor Tr3, the second terminal of capacitor C1, and the first terminal of capacitor C2. The second terminal of transistor Tr2 is electrically connected to wiring WDL, and the gate of transistor Tr2 is electrically connected to wiring GL2.

[0075] In this embodiment, the electrical connection point between the first terminal of transistor Tr1 and the first terminal of capacitor element C1 is referred to as node ND1, and the electrical connection point between the first terminal of transistor Tr2, the gate of transistor Tr3, the second terminal of capacitor element C1, and the first terminal of capacitor element C2 is referred to as node ND2.

[0076] Here, the voltage (potential) written from wiring WDL to node ND2 via transistor Tr2 corresponds to the first voltage (potential). Also, the voltage written from wiring DL to node ND1 via transistor Tr1 corresponds to the second voltage. Further, when the second voltage is written to node ND1, the second voltage is added to the first voltage by capacitive coupling through capacitor element C1, and the voltage of node ND2 changes. The voltage of node ND2 generated as a result corresponds to the third voltage.

[0077] The first terminal of transistor Tr3 is electrically connected to wiring AL, and the second terminal of transistor Tr3 is electrically connected to the first terminal of transistor Tr4, the first terminal of transistor Tr5, and the second terminal of capacitor element C2. The second terminal of transistor Tr4 is electrically connected to wiring VL, and the gate of transistor Tr4 is electrically connected to wiring GL1. The second terminal of transistor Tr5 is electrically connected to the anode terminal of light-emitting element LD, and the gate of transistor Tr5 is electrically connected to wiring GL3. The cathode terminal of light-emitting element LD is electrically connected to wiring CAT.

[0078] In the pixel PIX of FIG. 2A, the transistors Tr1, Tr2, and Tr5 are preferably OS transistors. In particular, the OS transistor is preferably an oxide having at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. Further, the oxide is described in detail in Embodiment 4. By applying such an OS transistor to the transistors Tr1, Tr2, and Tr5, the off-current of the transistor can be made very low. When holding data at the first terminal (node ND1) of the capacitor element C1, by using the transistor Tr1 as an OS transistor, it is possible to prevent the data held at the node ND1 from being destroyed by the off-current. Similarly, when holding data at the gate of the transistor Tr3, the second terminal of the capacitor element C1, the first terminal of the capacitor element C2, and (node ND2), by using the transistor Tr2 as an OS transistor, it is possible to prevent the data held at the node ND2 from being destroyed by the off-current. Further, when temporarily stopping the light emission of the light emitting element LD, by using the transistor Tr5 as an OS transistor, it is possible to prevent the light emission of the light emitting element LD due to the off-current.

[0079] As the transistors Tr3 and Tr4, for example, a transistor having silicon in the channel formation region can be applied (hereinafter referred to as an Si transistor). As the silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used.

[0080] Further, as the transistors Tr3 and Tr4, an OS transistor can be applied. In particular, by making all of the transistors Tr1 to Tr5 OS transistors, each transistor can be formed simultaneously, so that the manufacturing process of the display unit PA may be shortened. That is, since the production time of the display unit PA can be reduced, the production number per unit time can be increased.

[0081] <<Operation Example>> Next, an operation example of the pixel PIX illustrated in FIG. 2A will be described. It is assumed that the wiring DL and the wiring WDL of the pixel PIX are electrically connected to the source driver circuit SD in FIG. 1 in order to transmit image data to the pixel PIX in FIG. 2A.

[0082] FIG. 4 is a timing chart showing the operation example of the pixel PIX illustrated in FIG. 2A. The timing chart shown in FIG. 4 shows the potential changes of the wiring DL, the wiring WDL, the wiring VL, the wirings GL1 to GL3, the node ND1, and the node ND2 at times T1 to T8 and times in the vicinity thereof. Note that high described in FIG. 4 indicates a high-level potential, and low indicates a low-level potential. Also, V GND described in FIG. 4 indicates a reference potential.

[0083] Note that the wiring VL is always at V GND is applied at times T1 to T8 and times in the vicinity thereof.

[0084] In this operation example, the transistors Tr1, Tr2, Tr4, and Tr5 operate in the linear region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistors Tr1, Tr2, Tr4, and Tr5 are appropriately biased to voltages within the range of operating in the linear region.

[0085] Also, in this operation example, the transistor Tr3 operates in the saturation region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistor Tr3 are appropriately biased to voltages within the range of operating in the saturation region. Note that even if the operation of the transistor Tr3 deviates from the ideal operation in the saturation region, if the accuracy of the output current can be obtained within the desired range, the gate voltage, source voltage, and drain voltage of the transistor Tr3 are regarded as being appropriately biased.

[0086] [Before time T1] Before time T1, a low-level potential is applied to wirings GL1 and GL2, and a high-level potential is applied to wiring GL3. When the potential of wiring GL1 is at a low level, a low-level potential is applied to the gates of transistors Tr1 and Tr4, respectively, so that transistors Tr1 and Tr4 are turned off. That is, there is no electrical connection between wiring DL and node ND1. Similarly, when the potential of wiring GL2 is at a low level, a low-level potential is applied to the gate of transistor Tr2, so that transistor Tr2 is turned off. That is, there is no electrical connection between wiring WDL and node ND2. Further, when the potential of wiring GL3 is at a high level, a high-level potential is applied to the gate of transistor Tr5, so that transistor Tr5 is turned on. That is, there is an electrical connection between the anode terminal of light-emitting element LD and the first terminal of transistor Tr5.

[0087] Incidentally, when the difference (gate-source voltage) between the potential of node ND2 and the potential of the source of transistor Tr3 is higher than the threshold voltage of transistor Tr3, transistor Tr3 is turned on, and the current flowing between the source and drain of transistor Tr3 is determined according to the gate-source voltage of transistor Tr3. At this time, when the second terminal of transistor Tr3 is the source, current flows from wiring AL, through transistors Tr3 and Tr5, to the anode terminal of light-emitting element LD. As a result, light-emitting element LD emits light. In the timing chart shown in FIG. 4, the potential of node ND2 is described as V0 as a potential at which transistor Tr3 is turned off (that is, the difference between V0 and the potential of the source of transistor Tr3 is lower than the threshold voltage of transistor Tr3, and light-emitting element LD also does not emit light).

[0088] Also, for simplicity of explanation of this operation example, the potential of node ND1 before time T1 is also set to V0.

[0089] Before time T1, it is assumed that no image data is sent from the source driver circuit SD to the pixel PIX, and V is applied to the wiring DL and the wiring WDL. GND is applied.

[0090] [Time T1] At time T1, a low-level potential is applied to the wiring GL3. Therefore, between time T1 and time T2, a low-level potential is applied to the gate of the transistor Tr5, so that the transistor Tr5 is turned off. As a result, regardless of whether the transistor Tr3 is in the on state or the off state, no current flows through the anode terminal of the light-emitting element LD, so the light-emitting element LD does not emit light.

[0091] [Time T2] At time T2, a high-level potential is applied to the wiring GL1. Therefore, between time T2 and time T3, a high-level potential is applied to the gates of the transistors Tr1 and Tr4, so that the transistors Tr1 and Tr4 are turned on.

[0092] When the transistor Tr1 is turned on, the wiring DL and the node ND1 are electrically connected. Therefore, the potential of the node ND1 becomes V GND . Also, when the transistor Tr4 is turned on, the wiring VL and the second terminal of the capacitor element C2 are electrically connected. Therefore, the potential of the second terminal of the capacitor element C2 becomes V GND .

[0093] Further, since the second terminal (node ND2) of the capacitor element C1 is in a floating state, when the potential of the node ND1 changes, the potential of the node ND2 also changes due to capacitive coupling. Note that the amount of change in the potential of the node ND2 is determined by the amount of change in the potential of the node ND1, the capacitance of the capacitor element C1, etc. In this operation example, since the potential of the node ND1 has decreased from V0 to V GND , the potential of the node ND2 decreases from V0.

[0094] [Time T3] At time T3, a high-level potential is applied to the wiring GL2. Therefore, between time T3 and time T4, a high-level potential is applied to the gate of the transistor Tr2, so that the transistor Tr2 is turned on.

[0095] When the transistor Tr2 is turned on, the wiring WDL and the node ND2 are electrically connected. Therefore, the potential of the node ND2 is V GND Note that since the transistor Tr1 is turned on, the potential of the node ND1 does not fluctuate due to the change in the potential of the node ND2. Similarly, since the transistor Tr4 is turned on, the potential of the second terminal of the capacitor element C2 also does not fluctuate due to the change in the potential of the node ND2.

[0096] [Time T4] At time T4, an analog signal as image data is transmitted from the source driver circuit SD to the wiring DL and the wiring WDL. Here, as the potential of the analog signal, V data is input to the wiring DL and the wiring WDL.

[0097] Since the transistor Tr1 is turned on, V data is applied from the wiring DL to the first terminal (node ND1) of the capacitor element C1. Also, since the transistor Tr2 is turned on, V data is applied from the wiring WDL to the gate of the transistor Tr3, the second terminal of the capacitor element C1, and the first terminal (node ND2) of the capacitor element C2. Note that the potential of the second terminal of the capacitor element C2 does not fluctuate due to the change in the potentials of the node ND1 and the node ND2 since the transistor Tr4 is turned on.

[0098] [Time T5] At time T5, a low-level potential is applied to the wiring GL2. Therefore, between time T5 and time T6, a low-level potential is applied to the gate of the transistor Tr2, so that the transistor Tr2 is turned off.

[0099] When the transistor Tr2 is turned off, the connection between the wiring WDL and the node ND2 is electrically disconnected. Therefore, the node ND2 is in a floating state.

[0100] [Time T6] At time T6, a signal obtained by adding a potential of height ΔV to the potential V input between time T4 and time T5 is transmitted from the source driver circuit SD to the wiring DL and the wiring WDL. That is, the potential of each of the wiring DL and the wiring WDL becomes V data + ΔV data . data + ΔV data

[0101] Since the transistor Tr1 is on, V data + ΔV data is applied from the wiring DL to the node ND1. That is, the potential of the node ND1 varies from V data to V data + ΔV data between time T4 and time T6.

[0102] Since the transistor Tr2 is off, V data + ΔV data is not applied from the wiring WDL to the node ND2. However, since the potential of the node ND1 varies from V data to V data + ΔV data , and the node ND2 is in a floating state, the potential of the node ND2 also varies due to the capacitive coupling of the capacitive element C1 when the potential of the node ND1 varies. In the timing chart of FIG. 4, the amount of variation in the potential of the node ND2 is described as ΔV g , but ΔV g can be estimated by the following equation (E1).

[0103] [Number]

[0104] Therefore, when the potential of node ND2 is V ND2 , the capacitance value of capacitor element C1 is C1, and the capacitance value of capacitor element C2 is C2, V ND2 is expressed by the following equation (E2).

[0105] [Number]

[0106] Note that at time T6, the potential of wiring WDL is V data +ΔV data . However, in the circuit configuration example shown in Fig. 2A, the potential V data +ΔV data of the wiring WDL is not input to any element. Therefore, in the circuit configuration example shown in Fig. 2A, at time T6, the potential of the wiring WDL does not have to be V data +ΔV data .

[0107] [Time T7] At time T7, a low-level potential is applied to wiring GL1. Therefore, between time T7 and time T8, a low-level potential is applied to the gate of transistor Tr1, so that transistor Tr1 is turned off. As a result, node ND1 becomes a floating state, and the potential of node ND1 is held by capacitor element C1.

[0108] Also, between time T7 and time T8, a low-level potential is applied to the gate of transistor Tr4, so that transistor Tr4 is turned off. At this time, the potential of the second terminal of capacitor element C2 is V GND , and the potential of the gate (node ND2) of transistor Tr3 is V ND2 . Therefore, V ND2 -VGND When it is higher than the threshold voltage, the transistor Tr3 turns on. Also, the current flowing between the source and drain of the transistor Tr3 is determined according to V ND2 -V GND .

[0109] [Time T8] At time T8, a high-level potential is applied to the wiring GL3. Therefore, after time T8, a high-level potential is applied to the gate of the transistor Tr5, so that the transistor Tr5 turns on. As a result, the current flowing from the wiring AL is input to the anode terminal of the light-emitting element LD via the transistor Tr3 and the transistor Tr5, so that the light-emitting element LD emits light. At this time, since a voltage is applied between the anode terminal and the cathode terminal of the light-emitting element LD and a predetermined potential is applied to the wiring CAT, the potential of the electrical connection point of the second terminal of the transistor Tr3, the first terminal of the transistor Tr4, the first terminal of the transistor Tr5, and the second terminal of the capacitor element C2 becomes high. And since each of the nodes ND1 and ND2 is in a floating state, the potential of each of the nodes ND1 and ND2 may also become high by capacitive coupling as the potential of the electrical connection point becomes high. In the timing chart of FIG. 4, the potentials of the nodes ND1 and ND2 after time T8 are shown higher than the potentials of the nodes ND1 and ND2 between time T7 and time T8.

[0110] Note that the luminance of the light-emitting element LD is determined by the current flowing through the light-emitting element LD. According to Kirchhoff's law, since the current flowing through the light-emitting element LD is approximately equal to the current flowing between the source and drain of the transistor Tr3, the luminance of the light-emitting element LD is determined by the voltage between the gate and source of the transistor Tr3.

[0111] As described above, by performing operations on the pixel PIX illustrated in FIG. 2A at times T1 to T8 of the timing chart in FIG. 4 and times in the vicinity thereof, a potential with a resolution higher than that of the digital-to-analog conversion circuit DAC can be applied to the holding portion (node ND2) of the image data of the pixel PIX.

[0112] <<Specific Example>> Here, an example of displaying image data with more gradations than the image data output from the digital-to-analog conversion circuit DAC on the display portion PA of the display device DD will be described by the above-described operation example.

[0113] In this example, a 6-bit digital-to-analog conversion circuit is provided as the digital-to-analog conversion circuit DAC of the source driver circuit SD, and the ratio of the capacitance values of the capacitance elements C1 and C2 included in the pixel PIX is set to C1:C2 = 1:15.

[0114] By using a 6-bit digital-to-analog conversion circuit DAC as the digital-to-analog conversion circuit DAC, the V written to the node ND1 and the node ND2 of the pixel PIX data can take values from "000000" to "111111" in binary notation. Here, assuming that the voltage value of "111111" is 6.3V, the V that can be output by the digital-to-analog conversion circuit DAC data can take voltage values in the range from 0V to 6.3V in 0.1V increments.

[0115] Therefore, in the above-described operation example, between time T4 and time T5, V in the range from 0V to 6.3V can be written to the node ND1 and the node ND2 of the pixel PIX. data

[0116] [When V data takes values from 0V to 4.8V] First, V in the range from 0V to 4.8V (from "000000" to "110000" in binary notation) is written to the node ND1 and the node ND2 of the pixel PIX. data ​The case where it is written will be described.

[0117] Since the ratio of the capacitance values of the capacitance elements C1 and C2 is C1:C2 = 1:15, Equation (E1) becomes the following Equation (E3).

[0118] [Number]

[0119] Here, ΔV data is assumed to take values from "000000" to "001111" in binary notation, for example. At this time, the possible voltage values of ΔV data are in the range from 0V to 1.5V in 0.1V increments. That is, from Equation (E3), ΔV g can take values from 0V to 0.09375V in 0.00625V increments.

[0120] Therefore, in the above operation example, between time T6 and time T7, the potential of the node ND2 of the pixel PIX can take values from 0V to 4.8 + 0.09375V in 0.00625V increments according to Equations (E2) and (E3).

[0121] [When V data takes values from 4.9V to 6.3V] Next, the case where V data in the range from 4.9V to 6.3V (from "110001" to "111111" in binary notation) is written to the node ND1 and the node ND2 of the pixel PIX will be described.

[0122] Since the ratio of the capacitance values of the capacitance element C1 and the capacitance element C2 is the same as "the case where V data takes values from 0V to 4.8V", Equation (E3) can also be used in this case.

[0123] Here, ΔV dataFor example, it is assumed to take voltage values in the range from -1.5V to 0V in steps of 0.1V. That is, ΔV data is a negative value, and V data +ΔV data is assumed to be able to take values from 3.4V to 6.3V (from "100010" to "111111" in binary notation).

[0124] At this time, from equation (E3), ΔV g can take values from -0.09375V to 0V in steps of 0.00625V.

[0125] Therefore, in the above operation example, between time T6 and time T7, the potential of the node ND2 of the pixel PIX can take values from 4.9 - 0.09375V to 6.3V in steps of 0.00625V according to equations (E2) and (E3).

[0126] Summarizing the above specific example, as a digital - to - analog conversion circuit DAC, a digital - to - analog conversion circuit (6 - bit) capable of outputting analog values from 0V to 6.3V in steps of 0.1V is provided, and by setting the ratio of the capacitance values of the capacitance elements C1 and C2 included in the pixel PIX to C1:C2 = 1:15, a potential from 0V to 6.3V can be given to the node ND2 in steps of 0.00625V.

[0127] That is, in the pixel PIX shown in Fig. 2A, by performing the above operation example, a finer voltage value that cannot be output by the 6 - bit digital - to - analog conversion circuit DAC can be given to the node ND2. In the above specific example, the digital - to - analog conversion circuit DAC outputs potentials in steps of 0.1V, but a potential in steps of 0.00625V can be written to the node ND2 of the pixel PIX. In other words, a potential (image data) with a resolution larger than that of the 6 - bit digital - to - analog conversion circuit DAC can be written to the pixel PIX.

[0128] In the above specific example, the ΔV given by the 6 - bit digital - to - analog conversion circuit DAC datacorresponds to the upper 6 bits of the image data and is the ΔV applied to the node ND2 by the capacitive coupling of the pixel PIX g corresponds to the lower 4 bits of the image data. That is, the lower 4 bits of the image data can complement the upper 6 bits of the image data provided by the digital - analog conversion circuit DAC by the pixel PIX in FIG. 2A.

[0129] Note that the configuration of the pixel PIX according to one aspect of the present invention and the configuration of the wiring electrically connected to the pixel PIX are not limited to the configuration illustrated in FIG. 2A. One aspect of the present invention can be, for example, a configuration in which the components of the pixel PIX and each wiring are appropriately changed according to situations such as design specifications and purposes.

[0130] As a specific example, at least one of the transistors Tr1 to Tr5 included in the pixel PIX of FIG. 2A may be a transistor having a back - gate. By applying a potential to the back - gate of the transistor, the threshold voltage of the transistor can be increased or decreased.

[0131] Also, in the same transistor, by electrically connecting the gate and the back - gate, the source - drain current flowing when the transistor is in the on - state can be made larger. FIG. 2B shows a configuration in which all of the transistors Tr1 to Tr5 included in the pixel PIX of FIG. 2A are transistors having a back - gate, and in the same transistor, the gate and the back - gate are electrically connected.

[0132] Also, as another specific example, the wiring DL and the wiring WDL may be combined into one wiring (see FIG. 3). Note that the operation method of the pixel PIX illustrated in FIG. 3 refers to the above - mentioned operation examples.

[0133] As another specific example, in the present embodiment, a pixel circuit including a light-emitting element such as an EL element is illustrated in FIGS. 2A, 2B, and 3 as an example. However, one aspect of the present invention is not limited thereto. For example, one aspect of the present invention may also be configured to provide a capacitive element to a pixel circuit including a liquid crystal element in the same manner as in FIGS. 2A, 2B, and 3, and increase or decrease the potential of one terminal of the liquid crystal element by capacitive coupling to give an analog value finer than the resolution of the digital-to-analog conversion circuit DAC.

[0134] FIG. 5A shows an example in the case where a liquid crystal element LC is used as the display element. In the following, mainly the parts different from the above will be described, and the above description can be incorporated for the overlapping parts.

[0135] The pixel PIX shown in FIG. 5A includes a transistor Tr1, a transistor Tr2, a transistor Tr6, a capacitive element C1, a capacitive element C3, and a liquid crystal element LC. Further, a wiring GL1, a wiring GL2, a wiring GL4, a wiring DL, a wiring WDL, a wiring VCC, and a wiring CAT are connected to the pixel PIX.

[0136] The gate of the transistor Tr6 is electrically connected to the wiring GL4, one of the source or drain is electrically connected to the node ND2, and the other is electrically connected to one electrode of the capacitive element C3 and one electrode of the liquid crystal element LC. The other electrode of the capacitive element C3 is electrically connected to the wiring VCC. The other electrode of the liquid crystal element LC is electrically connected to the wiring CAT.

[0137] The wiring VCC is a wiring that gives a predetermined potential to the other electrode of the capacitive element C3. As the potential given to the wiring VCC, for example, a fixed potential such as a common potential, a reference potential, or a ground potential can be given. The wiring VCC may be shared with the wiring CAT and configured to have the same potential applied.

[0138] Transistor Tr6 can have a function as a switch for controlling the operation of liquid crystal element LC. When the signal written from wiring WDL to node ND2 is greater than the threshold for operating liquid crystal element LC, liquid crystal element LC may operate before the image signal is written from wiring DL. Therefore, it is preferable to provide transistor Tr6 and turn on transistor Tr6 by the signal applied to wiring GL4 after the potential of node ND2 is determined, so as to operate liquid crystal element LC.

[0139] The pixel PIX shown in FIG. 5B has a configuration in which transistor Tr6 and wiring GL4 are omitted from the configuration shown in FIG. 5A.

[0140] The transistor Tr6 in FIG. 5A is a switch for preventing liquid crystal element LC from operating inadvertently. However, if it is possible to prevent visual recognition even when liquid crystal element LC operates, transistor Tr6 can be omitted. For example, an operation such as turning off the backlight during the period when a signal is supplied from wiring WDL to node ND2 may be used in combination.

[0141] Also, as shown in FIG. 5C, a configuration in which capacitor element C3 is omitted may be adopted. An OS transistor can be used for the transistor connected to node ND2. Since the leakage current of the OS transistor in the off state is extremely small, image data can be held for a relatively long time even if capacitor element C3 functioning as a holding capacitor is omitted.

[0142] Also, this configuration is effective even when the frame frequency is high and the holding period of image data is relatively short, such as in field sequential driving. By omitting capacitor element C3, the aperture ratio can be improved. Or, the transmittance of the pixel can be improved. Note that the configuration in which capacitor element C3 is omitted may be applied to other pixel circuit configurations shown in this specification.

[0143] Also, the pixel PIX shown in FIG. 6A has a configuration in which transistor Tr7 and wiring VL are added to the configuration of FIG. 5A.

[0144] In the configuration shown in FIG. 6A, a reset potential is supplied to the wiring VL, and by turning on the transistor Tr7, the reset operation of the liquid crystal element LC can be performed. With this configuration, the rewriting operation can be independently controlled by the node ND2 and the potential applied to the liquid crystal element LC, and the display operation period by the liquid crystal element LC can be lengthened.

[0145] Further, when performing low-tone display, an image signal may be supplied from the wiring VL, and the display operation by the liquid crystal element LC may be performed by controlling the conduction and non-conduction of the transistor Tr7. At this time, the transistor Tr6 may be kept non-conductive at all times.

[0146] The pixel PIX shown in FIG. 6B has a configuration in which each transistor is provided with a back gate. The back gate is electrically connected to the front gate and has the effect of increasing the on-current. Also, it may be configured such that a fixed potential different from the front gate can be supplied to the back gate. With this configuration, the threshold voltage of the transistor can be controlled. In FIG. 6B, a configuration in which all transistors are provided with back gates is illustrated, but it may have transistors without back gates. Also, the configuration in which the transistor has a back gate is effective for other pixel circuits in the present embodiment.

[0147] The above is the description of the configuration example in the case of using a liquid crystal element.

[0148] One aspect of the present invention disclosed in this specification and the like is a semiconductor device having first to third transistors and first and second capacitor elements. The first terminal of the first transistor is electrically connected to the first terminal of the first capacitor element. The first terminal of the second transistor is electrically connected to the gate of the third transistor, the second terminal of the first capacitor element, and the first terminal of the second capacitor element. The first terminal of the third transistor is electrically connected to the second terminal of the second capacitor element. The semiconductor device has the following first to fourth functions. The first function is to turn on the first transistor and write a first potential to the first terminal of the first capacitor element, and to turn on the second transistor and write the first potential to the gate of the third transistor, the second terminal of the first capacitor element, and the second terminal of the second capacitor element. The second function is to turn off the second transistor and hold the potential of the gate of the third transistor by the second terminal of the first capacitor element and the second terminal of the second capacitor element. The third function is to write the sum of the first potential and the third potential to the first terminal of the first capacitor element, and when the sum of the first potential and the third potential is written to the first terminal of the first capacitor element, the first potential held at the gate of the third transistor, the second terminal of the first capacitor element, and the first terminal of the second capacitor element varies to the sum of the first potential and the fourth potential. The fourth function is to allow a current corresponding to the sum of the first potential and the fourth potential to flow between the first terminal and the second terminal of the third transistor.

[0149] Also, in the above, at least one of the first to third transistors preferably has a metal oxide in the channel formation region.

[0150] Also, in the above, it is preferable to have a fourth transistor and a light-emitting element. At this time, the first terminal of the fourth transistor is preferably electrically connected to the first terminal of the third transistor and the second terminal of the second capacitor element, and the anode terminal of the light-emitting element is preferably electrically connected to the second terminal of the fourth transistor.

[0151] Also, in the above, the fourth transistor preferably has a metal oxide in the channel formation region.

[0152] Also, in the above, it is preferable that the first potential corresponds to the data of the upper bit and the fourth potential corresponds to the data of the lower bit.

[0153] Another aspect of the present invention is a display device including the semiconductor device having the above configuration and a digital-analog conversion circuit. At this time, an output terminal of the digital-analog conversion circuit is electrically connected to a first terminal of the first transistor and a first terminal of the second transistor, and the digital-analog conversion circuit preferably has a function of generating a first potential or a sum of the first potential and the third potential and outputting the first potential or the sum of the first potential and the third potential from the output terminal of the digital-analog conversion circuit.

[0154] Another aspect of the present invention is an electronic device including the display device having the above configuration and a housing.

[0155] Also, the operation method of the semiconductor device or the display device according to an aspect of the present invention is not limited to the above-described operation examples or specific examples. For example, the order of applying potentials to elements, circuits, wirings, etc. and the values of the potentials can be appropriately changed. Further, as described above, since the configuration of the semiconductor device or the display device according to an aspect of the invention can be appropriately changed, the operation method of the semiconductor device or the display device may also be changed according to the configuration.

[0156] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0157] (Embodiment 2) In this embodiment, a configuration example of the display device will be described.

[0158] In FIG. 7A, a sealing material 4005 is provided so as to surround a display portion 215 provided on a first substrate 4001, and the display portion 215 is sealed by the sealing material 4005 and a second substrate 4006.

[0159] The display unit 215 is provided with a pixel array having the pixels PIX shown in the first embodiment.

[0160] In FIG. 7A, the scan line driving circuit 221a, the signal line driving circuit 231a, the signal line driving circuit 232a, and the common line driving circuit 241a each have a plurality of integrated circuits 4042 provided on the printed circuit board 4041. The integrated circuit 4042 is formed of a single crystal semiconductor or a polycrystalline semiconductor. The signal line driving circuit 231a and the signal line driving circuit 232a have the functions of the source driver circuit SD shown in the first embodiment. The scan line driving circuit 221a has the functions of the gate driver circuit GD shown in the first embodiment. The common line driving circuit 241a has the function of supplying a prescribed potential to the wiring CAT shown in the first embodiment.

[0161] Various signals and potentials supplied to the scan line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal line driving circuit 232a are supplied via the FPC 4018.

[0162] The integrated circuits 4042 included in the scan line driving circuit 221a and the common line driving circuit 241a have the function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have the function of supplying an image signal to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0163] Note that the connection method of the integrated circuit 4042 is not particularly limited, and a wire bonding method, a COG method, a TCP method, a COF (Chip On Film) method, or the like can be used.

[0164] FIG. 7B shows an example in which the integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a are mounted by the COG method. By providing part or all of the driving circuit on the same substrate as the display unit 215, a system on panel can be realized.

[0165] In FIG. 7B, an example is shown in which the scanning line driving circuit 221a and the common line driving circuit 241a are formed on the same substrate as the display unit 215. By forming these driving circuits on the same substrate as the display unit 215 through the same process, the number of components can be reduced. Therefore, productivity can be enhanced.

[0166] Also, in FIG. 7B, a sealing material 4005 is provided so as to surround the display unit 215 provided on the first substrate 4001, the scanning line driving circuit 221a, and the common line driving circuit 241a. Also, a second substrate 4006 is provided on the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a. Therefore, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a are sealed together with the display elements by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0167] Also, in FIG. 7B, an example is shown in which the signal line driving circuit 231a and the signal line driving circuit 232a are separately formed and mounted on the first substrate 4001, but the configuration is not limited to this. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0168] Also, the display device may include a panel in a state where the display elements are sealed, and a module in a state where an IC including a controller is mounted on the panel.

[0169] Also, the display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors. As the transistors, OS transistors or Si transistors can be applied.

[0170] The transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit 215 may have the same structure or may have different structures. All of the transistors included in the peripheral driving circuit may have the same structure, or two or more types of structures may be combined and used. Similarly, all of the transistors included in the pixel circuit may have the same structure, or two or more types of structures may be combined and used.

[0171] Further, an input device 4200 described later can be provided on the second substrate 4006. The configuration in which the input device 4200 is provided in the display device shown in FIG. 7A or FIG. 7B can function as a touch panel.

[0172] There is no limitation to the detection element (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention. Various sensors capable of detecting the proximity or contact of a detection object such as a finger or a stylus can be applied as the detection element.

[0173] As the sensor method, for example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

[0174] In the present embodiment, a touch panel having a capacitance-type detection element will be described as an example.

[0175] As the capacitance method, there are a surface capacitance method, a projected capacitance method, etc. Further, as the projected capacitance method, there are a self-capacitance method, a mutual capacitance method, etc. Using the mutual capacitance method is preferable because simultaneous multi-point detection becomes possible.

[0176] The touch panel according to one aspect of the present invention can adopt various configurations, such as a configuration in which a separately manufactured display device and a detection element are bonded together, and a configuration in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element and the counter substrate.

[0177] Figures 8A and 8B show an example of a touch panel. Figure 8A is a perspective view of the touch panel 4210. Figure 8B is a perspective schematic view of the input device 4200. For clarity, only representative components are shown.

[0178] The touch panel 4210 has a configuration in which a separately manufactured display device and input device are bonded together.

[0179] The touch panel 4210 has an input device 4200 and a display device, and these are provided overlapping each other.

[0180] The input device 4200 has a substrate 4263, electrodes 4227, electrodes 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. Also, the electrode 4228 can be electrically connected to the wiring 4238. The FPC 4272b is electrically connected to each of the plurality of wirings 4237, the plurality of wirings 4238, and the plurality of wirings 4239. An IC 4273b can be provided on the FPC 4272b.

[0181] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to a capacitive touch sensor, an optical touch sensor using a photoelectric conversion element may be applied.

[0182] Figure 9 is a cross-sectional view corresponding to the portion indicated by the chain line N1 - N2 in Figure 7B. The display device shown in Figure 9 has an electrode 4015. The electrode 4015 is electrically connected via an anisotropic conductive layer 4019 to the terminal of the FPC 4018. Also, in Figure 9, the electrode 4015 is electrically connected to the wiring 4014 at the openings formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0183] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed from the same conductive layer as the source and drain electrodes of the transistors 4010 and 4011.

[0184] In addition, the display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors. In FIG. 9, the transistors 4010 included in the display unit 215 and the transistors 4011 included in the scanning line driving circuit 221a are illustrated. Note that, in FIG. 9, bottom gate transistors are illustrated as the transistors 4010 and 4011, but top gate transistors may also be used. Further, the transistor 4011 can be a transistor included in the gate driver circuit GD described in Embodiment 1.

[0185] In FIG. 9, an insulating layer 4112 is provided over the transistors 4010 and 4011. In addition, a partition wall 4510 is formed over the insulating layer 4112.

[0186] In addition, the transistors 4010 and 4011 are provided over the insulating layer 4102. The transistors 4010 and 4011 have an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can function as a back gate electrode.

[0187] In addition, the display device shown in FIG. 9 has a capacitive element 4020. The capacitive element 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source and drain electrodes. The respective electrodes overlap with each other with the insulating layer 4103 therebetween. Note that the capacitive element 4020 can be, for example, the capacitive element C1 or C2 of the pixel PIX described in Embodiment 1.

[0188] The capacitance of the capacitive element provided in the pixel portion of the display device is set so that it can hold electric charges for a predetermined period, taking into account the leakage current of the transistor arranged in the pixel portion. The capacitance of the capacitive element may be set in consideration of the off-current of the transistor and the like.

[0189] The transistor 4010 provided in the display unit 215 is electrically connected to the display element.

[0190] Also, the display device shown in FIG. 9 has an insulating layer 4111 and an insulating layer 4102. As the insulating layer 4111 and the insulating layer 4102, an insulating layer that hardly transmits impurity elements is used. By sandwiching the transistor with the insulating layer 4111 and the insulating layer 4102, it is possible to prevent the intrusion of impurities from the outside into the semiconductor layer.

[0191] As a display element included in the display device, a light-emitting element (EL element) that utilizes electroluminescence can be applied. The EL element has a layer containing a light-emitting compound (also referred to as an "EL layer") between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting substance contained in the EL layer emits light.

[0192] Also, the EL element is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0193] In the organic EL element, by applying a voltage, electrons are injected into the EL layer from one electrode and holes are injected into the EL layer from the other electrode. Then, when these carriers (electrons and holes) recombine, a light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0194] In addition to the light-emitting compound, the EL layer may also contain a substance with high hole injection properties, a substance with high hole transport properties, a hole blocking material, a substance with high electron transport properties, a substance with high electron injection properties, or a bipolar substance (a substance with high electron transport and hole transport properties).

[0195] The EL layer can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer method, printing method, inkjet method, coating method, etc.

[0196] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. Dispersed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used for explanation as the light-emitting element.

[0197] For the light-emitting element to extract light, at least one of the pair of electrodes may be transparent. There are light-emitting elements with a top emission structure in which a transistor and a light-emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, a bottom emission structure in which light is extracted from the surface on the substrate side, and a dual emission structure in which light is extracted from both surfaces, and light-emitting elements of any emission structure can be applied.

[0198] FIG. 9 is an example of a light-emitting display device (also referred to as an "EL display device") using a light-emitting element as a display element. The light-emitting element 4513, which is the display element, is electrically connected to a transistor 4010 provided in the display unit 215. That is, the transistor 4010 corresponds to the transistor Tr5 described in Embodiment 1, and the light-emitting element 4513 corresponds to the light-emitting element LD described in Embodiment 1. The configuration of the light-emitting element 4513 is a laminated structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, but is not limited to this configuration. The configuration of the light-emitting element 4513 can be appropriately changed according to the direction of light extracted from the light-emitting element 4513 and the like.

[0199] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature.

[0200] The light-emitting layer 4511 may be composed of a single layer or may be configured such that a plurality of layers are laminated.

[0201] The emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, or yellow, depending on the material constituting the light-emitting layer 4511.

[0202] As a method for realizing color display, there are a method of combining a light-emitting element 4513 having a white emission color with a coloring layer, and a method of providing light-emitting elements 4513 having different emission colors for each pixel. In the latter method, since it is necessary to separately produce the light-emitting layer 4511 for each pixel, the productivity is inferior to that of the former method. However, in the latter method, an emission color with higher color purity can be obtained than in the former method. In addition to the latter method, the color purity can be further increased by providing a microcavity structure to the light-emitting element 4513.

[0203] Note that the light-emitting layer 4511 may contain an inorganic compound such as quantum dots. For example, by using quantum dots in the light-emitting layer, it can also function as a light-emitting material.

[0204] A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not penetrate into the light-emitting element 4513. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), etc. can be formed. Further, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this way, it is preferable to package (encase) with a highly airtight and low outgassing protective film (laminated film, ultraviolet curable resin film, etc.) or cover material so as not to be exposed to the outside air.

[0205] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate), etc. can be used. Further, the filler 4514 may contain a desiccant.

[0206] As the sealing material 4005, a glass material such as glass frit, a curable resin that cures at room temperature such as a two-component mixed resin, a photocurable resin, a thermosetting resin, etc. can be used. Further, the sealing material 4005 may contain a desiccant.

[0207] Further, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface unevenness and reduce the reflection.

[0208] Also, by forming the light-emitting element into a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and a color filter, reflection can be reduced and the visibility of the displayed image can be enhanced.

[0209] In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, the light transmittance and reflectivity may be selected according to the direction of the light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0210] As the first electrode layer 4030 and the second electrode layer 4031, a conductive material having light transmittance such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used.

[0211] Also, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or an alloy thereof, or a metal nitride thereof.

[0212] Also, as the first electrode layer 4030 and the second electrode layer 4031, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, so-called π - electron conjugated system conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers composed of two or more of aniline, pyrrole, and thiophene or their derivatives, etc. can be mentioned.

[0213] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0214] FIG. 10 shows an example in the case where a light-emitting diode chip (hereinafter also referred to as an LED chip) is used as the display element.

[0215] The LED chip has a light-emitting diode. The configuration of the light-emitting diode is not particularly limited, and an MIS (Metal Insulator Semiconductor) junction may be used, or a homo-structure, hetero-structure, or double hetero-structure having a PN junction or a PIN junction can be used. Further, a superlattice structure, or a single quantum well structure or a multi-quantum well (MQW) structure in which thin films generating quantum effects are laminated may be used.

[0216] The LED chip 4600 includes a substrate 4601, an n-type semiconductor layer 4611, a light-emitting layer 4612, a p-type semiconductor layer 4613, electrodes 4615, 4621, 4622, an insulating layer 4603, etc.

[0217] As the material of the p-type semiconductor layer 4613, a material that is larger than the bandgap energy of the light-emitting layer 4612 and can confine carriers with respect to the light-emitting layer 4612 can be used. Further, the LED chip 4600 is provided with an electrode 4621 that functions as a cathode on the n-type semiconductor layer 4611, an electrode 4615 that functions as a contact electrode on the p-type semiconductor layer 4613, and an electrode 4622 that functions as an anode on the electrode 4615. Also, it is preferable that the upper surface of the n-type semiconductor layer 4611, and the upper surface and side surfaces of the electrode 4615 are covered with the insulating layer 4603. The insulating layer 4603 functions as a protective film for the LED chip 4600.

[0218] The LED chip 4600 has an area of the region for emitting light of 1 mm 2 Hereinafter, preferably 10000 μm 2Hereinafter, more preferably 3000 μm 2 Hereinafter, even more preferably 700 μm 2 It can be made to be the following.

[0219] As the LED chip 4600, a macro LED having a side dimension exceeding 1 mm may be used, but it is preferable to use an LED having a smaller size. In particular, a mini LED having a side dimension greater than 100 μm and less than or equal to 1 mm, and more preferably, a micro LED having a side dimension of 100 μm or less can be used. By using a micro LED, an extremely high-definition display device can be realized.

[0220] The n-type semiconductor layer 4611 may have a structure in which an n-type contact layer is laminated on the substrate 4601 side and an n-type cladding layer is laminated on the light-emitting layer 4612 side. Further, the p-type semiconductor layer 4613 may have a structure in which a p-type cladding layer is laminated on the light-emitting layer 4612 side and a p-type contact layer is laminated on the electrode 4615 side.

[0221] The light-emitting layer 4612 can use a multiple quantum well (MQW) structure in which a barrier layer and a well layer are laminated multiple times. It is preferable to use a material for the barrier layer having a larger bandgap energy than the well layer. By adopting such a configuration, energy can be confined in the well layer, the quantum efficiency can be improved, and the light-emitting efficiency of the LED chip 4600 can be improved.

[0222] The LED chip 4600 is a face-down type LED chip from which light is mainly emitted on the substrate 4601 side. At this time, as the electrode 4615, a material that reflects light can be used, for example, metals such as silver, aluminum, and rhodium can be used. When a face-up type LED chip is used, a light-transmissive material may be used for the electrode 4615, for example, oxides such as ITO (In2O3-SnO2), AZO (Al2O3-ZnO), IZO (In2O3-ZnO), GZO (GeO2-ZnO), and ICO (In2O3-CeO2) can be used.

[0223] As the substrate 4601, oxide single crystals such as sapphire single crystal (Al2O3), spinel single crystal (MgAl2O4), ZnO single crystal, LiAlO2 single crystal, LiGaO2 single crystal, MgO single crystal, Si single crystal, SiC single crystal, GaAs single crystal, AlN single crystal, GaN single crystal, and boride single crystals such as ZrB2 can be used. In the face-down type LED chip 4600, it is preferable to use a material that transmits light for the substrate 4601. For example, a sapphire single crystal or the like can be used.

[0224] Also, a buffer layer (not shown) may be provided between the substrate 4601 and the n-type semiconductor layer 4611. The buffer layer has a function of relaxing the difference in lattice constants between the substrate 4601 and the n-type semiconductor layer 4611.

[0225] The electrodes 4621 and 4622 of the LED chip 4600 are joined to the first electrode layer 4030 or the second electrode layer 4031 via the bumps 4605, respectively.

[0226] Also, it is preferable to provide a light-shielding resin layer 4607 covering the side surface of the LED chip 4600. Thereby, the light emitted laterally from the LED chip 4600 can be shielded, and a decrease in contrast due to waveguide light can be prevented.

[0227] Also, FIG. 10 shows an example in which a further substrate 4006 is provided on the substrate 4601. In this way, by providing the resin layer 4607 around the LED chip 4600 and further covering the upper surface with the substrate 4006, the bonding of the LED chip 4600 can be made stronger, and it is possible to suitably prevent the occurrence of poor bonding of the LED chip 4600.

[0228] FIG. 11 is an example of a liquid crystal display device using a liquid crystal element as a display element.

[0229] In FIG. 11, a liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033, which function as alignment films, are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 therebetween.

[0230] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers may be used.

[0231] Further, if necessary, optical members (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light, or the like may be used as a light source. Further, a micro LED or the like may be used as the backlight and the side light.

[0232] In the display device shown in FIG. 11, a light-shielding layer 4132, a colored layer 4131, and an insulating layer 4133 are provided between the substrate 4006 and the second electrode layer 4031.

[0233] Examples of materials that can be used as the light-shielding layer 4132 include carbon black, titanium black, metals, metal oxides, and composite oxides including a solid solution of a plurality of metal oxides. The light-shielding layer 4132 may be a film containing a resin material or a thin film of an inorganic material such as a metal. Further, a laminated film of a film containing the material of the colored layer 4131 may be used for the light-shielding layer 4132. For example, a laminated structure of a film containing a material used for a colored layer that transmits light of a certain color and a film containing a material used for a colored layer that transmits light of another color can be used. It is preferable to share the materials of the colored layer and the light-shielding layer because the device can be shared and the process can be simplified.

[0234] Examples of materials that can be used for the coloring layer 4131 include metal materials, resin materials, and resin materials containing pigments or dyes. The method of forming the light-shielding layer and the coloring layer may be the same as the method of forming each of the above-described layers. For example, it may be performed by an inkjet method or the like.

[0235] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0236] (Embodiment 3) In this embodiment, the configuration of a semiconductor device according to an aspect of the present invention or a transistor that can be used in a display device will be described.

[0237] A semiconductor device according to an aspect of the present invention or a display device can be manufactured using various types of transistors such as bottom-gate type transistors and top-gate type transistors. Therefore, the material of the semiconductor layer and the transistor structure to be used can be easily replaced according to the existing manufacturing line.

[0238] [Bottom-Gate Type Transistor] FIG. 12A1 is a cross-sectional view of a channel protection type transistor 810, which is a type of bottom-gate type transistor. The transistor 810 is formed on a substrate 771. The transistor 810 also has an electrode 746 on the substrate 771 via an insulating layer 772. The transistor 810 further has a semiconductor layer 742 on the electrode 746 via an insulating layer 726. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0239] The semiconductor layer 742 further includes an insulating layer 741 over a channel formation region of the semiconductor layer 742. An electrode 744a and an electrode 744b are provided over the insulating layer 726 in contact with part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode and a drain electrode. The electrode 744b can function as the other of the source electrode and the drain electrode. Part of the electrode 744a and part of the electrode 744b are formed over the insulating layer 741.

[0240] The insulating layer 741 can function as a channel protective layer. Providing the insulating layer 741 over the channel formation region can prevent the semiconductor layer 742 from being exposed when the electrodes 744a and 744b are formed. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrodes 744a and 744b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0241] The transistor 810 further includes an insulating layer 728 over the electrode 744 a, the electrode 744 b, and the insulating layer 741 , and an insulating layer 729 over the insulating layer 728 .

[0242] When an oxide semiconductor is used for the semiconductor layer 742, it is preferable to use a material capable of removing oxygen from a part of the semiconductor layer 742 and generating oxygen vacancies for at least the portions of the electrodes 744a and 744b in contact with the semiconductor layer 742. The carrier concentration increases in the region in the semiconductor layer 742 where oxygen vacancies are generated, and the region becomes n-type, forming an n-type region (n + Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, examples of a material that can remove oxygen from the semiconductor layer 742 and cause oxygen vacancies include tungsten, titanium, and the like.

[0243] By forming a source region and a drain region in the semiconductor layer 742, the contact resistance between the electrodes 744a and 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as the field-effect mobility and the threshold voltage, can be made good.

[0244] When using a semiconductor such as silicon for the semiconductor layer 742, it is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of the transistor.

[0245] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing the diffusion of impurities from the outside to the transistor. Note that the insulating layer 729 can be omitted if necessary.

[0246] The transistor 811 shown in FIG. 12A2 is different from the transistor 810 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. The electrode 723 can be formed by the same material and method as the electrode 746.

[0247] Generally, the back gate electrode is formed of a conductive layer and is arranged so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same way as the gate electrode. The potential of the back gate electrode may be the same as the potential of the gate electrode, or may be a ground potential (GND potential) or an arbitrary potential. Also, by changing the potential of the back gate electrode independently without linking it to the potential of the gate electrode, the threshold voltage of the transistor can be changed.

[0248] Both electrode 746 and electrode 723 can function as gate electrodes. Therefore, insulating layer 726, insulating layer 728, and insulating layer 729 can each function as a gate insulating layer. Note that electrode 723 may be provided between insulating layer 728 and insulating layer 729.

[0249] When one of electrode 746 or electrode 723 is referred to as the "gate electrode", the other is referred to as the "back gate electrode". For example, in transistor 811, when electrode 723 is referred to as the "gate electrode", electrode 746 is referred to as the "back gate electrode". Also, when electrode 723 is used as the "gate electrode", transistor 811 can be considered as a type of top gate transistor. Further, either electrode 746 or electrode 723 may be referred to as the "first gate electrode" and the other as the "second gate electrode".

[0250] By providing electrode 746 and electrode 723 with the semiconductor layer 742 therebetween, and further by setting electrode 746 and electrode 723 to the same potential, the region where carriers flow in semiconductor layer 742 becomes larger in the film thickness direction, so that the amount of carrier movement increases. As a result, the on-current of transistor 811 increases and the field effect mobility becomes higher.

[0251] Therefore, transistor 811 is a transistor having a large on-current with respect to the occupied area. That is, the occupied area of transistor 811 can be reduced with respect to the required on-current. According to one aspect of the present invention, the occupied area of the transistor can be reduced. Thus, according to one aspect of the present invention, a semiconductor device with a high integration degree can be realized.

[0252] Also, since the gate electrode and the back gate electrode are formed of a conductive layer, they have a function (particularly an electric field shielding function against static electricity, etc.) of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed. Note that the back gate electrode can be formed larger than the semiconductor layer, and by covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced.

[0253] Further, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, it is possible to prevent light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0254] According to one aspect of the present invention, a transistor with good reliability can be realized. In addition, a semiconductor device with good reliability can be realized.

[0255] FIG. 12B1 shows a cross-sectional view of a channel protection type transistor 820 which is one of the bottom gate type transistors. The transistor 820 has substantially the same structure as the transistor 810, but is different in that the insulating layer 741 covers the end portion of the semiconductor layer 742. Also, in the opening formed by selectively removing a part of the insulating layer 741 overlapping with the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a are electrically connected. Also, in another opening formed by selectively removing a part of the insulating layer 741 overlapping with the semiconductor layer 742, the semiconductor layer 742 and the electrode 744b are electrically connected. The region of the insulating layer 741 overlapping with the channel formation region can function as a channel protection layer.

[0256] The transistor 821 shown in FIG. 12B2 is different from the transistor 820 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729.

[0257] By providing the insulating layer 741, it is possible to prevent the exposure of the semiconductor layer 742 that occurs during the formation of the electrodes 744a and 744b. Therefore, it is possible to prevent thinning of the semiconductor layer 742 during the formation of the electrodes 744a and 744b.

[0258] In addition, for transistors 820 and 821, the distances between electrode 744a and electrode 746 and between electrode 744b and electrode 746 are longer than those of transistors 810 and 811. Therefore, the parasitic capacitance generated between electrode 744a and electrode 746 can be reduced. Also, the parasitic capacitance generated between electrode 744b and electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0259] The transistor 825 shown in FIG. 12C1 is a channel etching type transistor which is one of the bottom gate type transistors. The transistor 825 forms electrodes 744a and 744b without using the insulating layer 741. For this reason, a part of the semiconductor layer 742 exposed during the formation of electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be increased.

[0260] The transistor 826 shown in FIG. 12C2 is different from the transistor 820 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729.

[0261] 〔Top Gate Type Transistor〕 The transistor 842 illustrated in FIG. 13A1 is one of the top gate type transistors. The transistor 842 is different from transistors 810, 811, 820, 821, 825, and 826 in that electrodes 744a and 744b are formed after the insulating layer 729 is formed. Electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at the openings formed in the insulating layer 728 and the insulating layer 729.

[0262] Further, by removing a part of the insulating layer 726 that does not overlap with the electrode 746 and introducing the impurity 755 into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, an impurity region can be formed self-alignedly in the semiconductor layer 742 (see Fig. 13A3). The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 into which the impurity 755 is introduced through the insulating layer 726 is lower than that in the region into which the impurity 755 is introduced without passing through the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that does not overlap with the electrode 746.

[0263] The transistor 843 shown in Fig. 13A2 is different from the transistor 842 in that it has an electrode 723. The transistor 843 has an electrode 723 formed on the substrate 771. The electrode 723 overlaps with the semiconductor layer 742 through the insulating layer 772. The electrode 723 can function as a back gate electrode.

[0264] Also, as in the transistor 844 shown in Fig. 13B1 and the transistor 845 shown in Fig. 13B2, all of the insulating layer 726 in the region that does not overlap with the electrode 746 may be removed. Also, as in the transistor 846 shown in Fig. 13C1 and the transistor 847 shown in Fig. 13C2, the insulating layer 726 may be left.

[0265] For the transistors 842 to 847 as well, after forming the electrode 746, by using the electrode 746 as a mask and introducing the impurity 755 into the semiconductor layer 742, an impurity region can be formed self-alignedly in the semiconductor layer 742. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Also, according to one aspect of the present invention, a semiconductor device with high integration can be realized.

[0266] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0267] (Embodiment 4) In this embodiment, the configuration of the metal oxide that can be used for the OS transistor described in the above embodiment will be described.

[0268] <Configuration of Metal Oxide> In the specification and the like, CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be described. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration.

[0269] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be enhanced to the maximum extent.

[0270] Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0271] In addition, in CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0272] In addition, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to the insulating region and a component having a narrow band gap due to the conductive region. In such a configuration, when carriers flow, the carriers mainly flow in the component having the narrow band gap. Further, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0273] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0274] <Structure of Metal Oxide> Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0275] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. Note that the strain refers to a location where the orientation of the lattice arrangement changes between a region with an aligned lattice arrangement and another region with an aligned lattice arrangement in the region where the plurality of nanocrystals are connected.

[0276] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons. Note that in CAAC-OS, even in the vicinity of the strain, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is presumably because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0277] Also, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In,M) layer.

[0278] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, since distinct grain boundaries cannot be confirmed in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation or defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0279] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0280] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has loose or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0281] Oxide semiconductors take various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0282] <Transistor having an oxide semiconductor> Subsequently, the case where the above oxide semiconductor is used for a transistor will be described.

[0283] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0284] In addition, it is preferable to use an oxide semiconductor with a low carrier density for the transistor. When reducing the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced, and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the oxide semiconductor has a carrier density of 8 × 10 11 / cm 3 less than, preferably 1 × 10 11 / cm 3 less than, more preferably 1 × 10 10 / cm 3 less than, and 1 × 10 -9 / cm 3 or more is sufficient.

[0285] In addition, since the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0286] In addition, the charge trapped in the trap levels of the oxide semiconductor has a long time required to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

[0287] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

[0288] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0289] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0290] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0291] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor. For example, the nitrogen concentration in the oxide semiconductor is 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×1017 atoms / cm 3 Shall be as follows.

[0292] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 shall be less than.

[0293] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0294] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0295] (Embodiment 5) In this embodiment, a product example in which the semiconductor device or display device described in the above embodiment is applied to an electronic device will be described.

[0296] <Notebook Personal Computer> A semiconductor device or a display device according to an aspect of the present invention can be applied to a display provided in an information terminal device. FIG. 14A shows a notebook personal computer which is a kind of information terminal device, and includes a housing 5401, a display unit 5402, a keyboard 5403, a pointing device 5404, and the like.

[0297] <Smartwatch> A semiconductor device or a display device according to an aspect of the present invention can be applied to a wearable terminal. FIG. 14B shows a smartwatch which is a kind of wearable terminal, and includes a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, and the like. Also, a display device with a function as a position input device may be used for the display unit 5902. Further, the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. Further, the operation button 5903 can be provided with any one of a power switch for starting the smartwatch, a button for operating an application of the smartwatch, a volume adjustment button, or a switch for lighting or extinguishing the display unit 5902. In addition, in the smartwatch shown in FIG. 14B, the number of operation buttons 5903 is shown as two, but the number of operation buttons of the smartwatch is not limited to this. Also, the operator 5904 functions as a crown for adjusting the time of the smartwatch. Further, the operator 5904 may be used as an input interface for operating an application of the smartwatch in addition to adjusting the time. Note that, in the smartwatch shown in FIG. 14B, it has a configuration including the operator 5904, but it is not limited to this, and a configuration without the operator 5904 may also be used.

[0298] <Video camera> A semiconductor device or a display device according to an aspect of the present invention can be applied to a video camera. The video camera shown in FIG. 14C includes a first housing 5801, a second housing 5802, a display unit 5803, operation keys 5804, a lens 5805, a connection unit 5806, and the like. The operation keys 5804 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by the connection unit 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection unit 5806. The video on the display unit 5803 may be switched according to the angle between the first housing 5801 and the second housing 5802 at the connection unit 5806.

[0299] <Mobile phone> A semiconductor device or a display device according to an aspect of the present invention can be applied to a mobile phone. FIG. 14D is a mobile phone having the functions of an information terminal, and includes a housing 5501, a display unit 5502, a microphone 5503, a speaker 5504, and operation buttons 5505. Further, a display device having an additional function as a position input device may be used for the display unit 5502. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. Further, the operation buttons 5505 may be provided with any one of a power switch for starting the mobile phone, buttons for operating applications of the mobile phone, volume adjustment buttons, or a switch for turning on or off the display unit 5502.

[0300] In the mobile phone shown in FIG. 14D, the number of operation buttons 5505 is shown as two, but the number of operation buttons of the mobile phone is not limited to this. Although not shown, the mobile phone shown in FIG. 14D may be configured to have a light emitting device for use as a flashlight or illumination.

[0301] <Television device> The semiconductor device or display device according to one aspect of the present invention can be applied to a television device. The television device shown in FIG. 14E has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, and the like. The television device can incorporate a large display unit 9001, for example, 50 inches or more, or 100 inches or more.

[0302] <Mobile body> The semiconductor device or display device according to one aspect of the present invention can be applied to the periphery of the driver's seat of an automobile, which is a mobile body.

[0303] For example, FIG. 14F is a diagram showing the periphery of the windshield in the interior of an automobile. In FIG. 14F, in addition to display panels 5701, 5702, and 5703 attached to the dashboard, a display panel 5704 attached to the pillar is illustrated.

[0304] The display panels 5701 to 5703 can provide various information by displaying navigation information, a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the designability can be enhanced. The display panels 5701 to 5703 can also be used as lighting devices.

[0305] The display panel 5704 can complement the visual field (blind spot) blocked by the pillar by projecting the video from the imaging means provided on the vehicle body. That is, by displaying the image from the imaging means provided outside the automobile, the blind spot can be compensated and the safety can be enhanced. In addition, by projecting the video that complements the invisible part, the safety check can be performed more naturally without a sense of incongruity. The display panel 5704 can also be used as a lighting device.

[0306] <Electronic device for electronic bulletin> A semiconductor device or a display device according to an aspect of the present invention can be applied to a display for electronic announcements. FIG. 15A shows an example of an electronic signboard (digital signage) that can be attached to a wall. FIG. 15A shows a state where the electronic signboard 6200 is attached to the wall 6201.

[0307] <Foldable tablet-type information terminal> A semiconductor device or a display device according to an aspect of the present invention can be applied to a tablet-type information terminal. FIG. 15B shows a tablet-type information terminal having a foldable structure. The information terminal shown in FIG. 15B includes a housing 5321a, a housing 5321b, a display unit 5322, and operation buttons 5223. In particular, the display unit 5322 has a flexible base material, and a structure that can be folded by the base material can be realized.

[0308] In addition, the housing 5321a and the housing 5321b are coupled by a hinge portion 5321c, and the hinge portion 5321c enables the device to be folded in two. The display unit 5322 is provided on the housing 5321a, the housing 5321b, and the hinge portion 5321c.

[0309] Although not shown, the electronic devices shown in FIGS. 14A to 14C, 14E, 15A, and 15B may be configured to have a microphone and a speaker. With this configuration, for example, a voice input function can be added to the above-described electronic devices.

[0310] Although not shown, the electronic devices shown in FIGS. 14A, 14B, 14D, 15A, and 15B may be configured to have a camera.

[0311] Also, although not shown, the electronic devices shown in FIGS. 14A to 14F, FIG. 15A, and FIG. 15B may be configured to have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays, etc.) inside the housing. In particular, by providing a detection device having a sensor for detecting inclination, such as a gyro or an acceleration sensor, in the mobile phone shown in FIG. 14D, the orientation of the mobile phone (which direction the mobile phone is facing with respect to the vertical direction) can be determined, and the screen display of the display unit 5502 can be automatically switched according to the orientation of the mobile phone.

[0312] Also, although not shown, the electronic devices shown in FIGS. 14A to 14F, FIG. 15A, and FIG. 15B may be configured to have a device for acquiring biometric information such as fingerprint, vein, iris, or voiceprint. By applying this configuration, an electronic device having a biometric authentication function can be realized.

[0313] Also, as the display unit of the electronic devices shown in FIGS. 14A to 14E and FIG. 15A, a flexible base material may be used. Specifically, the display unit may be configured to have transistors, capacitive elements, display elements, etc. provided on a flexible base material. By applying this configuration, not only a housing having a flat surface like the electronic devices shown in FIGS. 14A to 14E and FIG. 15A, but also an electronic device with a housing having a curved surface like the dashboard and pillar shown in FIG. 14F can be realized.

[0314] Examples of flexible base materials applicable to the display units of FIGS. 14A to 14F, 15A, and 15B include materials having light transmittance for visible light, such as polyethylene terephthalate resin (PET), polyethylene naphthalate resin (PEN), polyethersulfone resin (PES), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate resin, polyamide resin, polycycloolefin resin, polystyrene resin, polyamideimide resin, polypropylene resin, polyester resin, polyvinyl halide resin, aramid resin, epoxy resin, urethane resin, etc. Also, these materials may be used by mixing or laminating them.

[0315] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Explanation of Reference Numerals

[0316] DD: Display device, PA: Display unit, GD: Gate driver circuit, SD: Source driver circuit, PIX: Pixel, SR: Shift register, LAT: Latch circuit, LVS: Level shift circuit, DAC: Digital-analog conversion circuit, AMP: Amplifier circuit, GL: Wiring, DL: Wiring, DB: Data bus wiring, Tr1 to 7: Transistors, C1, C2, C3: Capacitive elements, LD: Light-emitting element, GL1 to 4: Wiring, DL: Wiring, WDL: Wiring, VL: Wiring, AL: Wiring, CAT: Wiring, ND1: Node, ND2: Node

Claims

1. A plurality of pixels arranged in a matrix form, One of the pixels includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, and a display element, one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitance element; the other of the source and the drain of the first transistor is electrically connected to a first wiring; one of a source and a drain of the second transistor is electrically connected to the first wiring; the other of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitance element, to a gate of the third transistor, and to one electrode of the second capacitance element, respectively; one of a source and a drain of the third transistor is electrically connected to a second wiring; the other of the source and the drain of the third transistor is electrically connected to the other electrode of the second capacitance element, one of the source and the drain of the fourth transistor, and one of the source and the drain of the fifth transistor, the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the other of the source and the drain of the fifth transistor is electrically connected to the display element; a gate of the first transistor is electrically connected to a first gate line; a gate of the fourth transistor is electrically connected to the first gate line.

2. In claim 1, one of the pixels has a function of holding a first voltage written to the other of the source and drain of the second transistor from the first wiring through a channel formation region of the second transistor, and a function of holding a second voltage written to one of the source and drain of the first transistor from the first wiring through a channel formation region of the first transistor, a gate of the third transistor is supplied with a voltage corresponding to a third voltage obtained by adding the first voltage and the second voltage together.

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