Single-threaded detection of a valid synchronization header

Abstract

An integrated circuit having an interface circuit is described. In operation, the interface circuit may receive a signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels. The interface circuit may then calculate a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the interface circuit may determine a location of a synchronization field in the header relative to the identified first dominant bit, and calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

Description

Technical Field

[0001] The present disclosure relates to techniques for communicating using a serial communication protocol.

Background Art

[0002] In serial communication, a recipient electronic device (sometimes called a "slave") that supports autobaud may need to extract the baud rate from a synchronization header in a frame. The synchronization header is typically constrained by a communication protocol to ensure detection or identification of misinterpreted synchronization headers without losing a valid synchronization header. For example, the Local Interconnect Network (LIN) is a single-wire serial communication protocol used for communication between components in a vehicle. The LIN specification expects a slave to always detect a "break and sync" (or "break+sync") sequence or field in the synchronization header, which is transmitted by another electronic device (sometimes called a "master"). Moreover, a valid detection of the "break+sync" field may cause or enable detection of the baud rate the master wishes to communicate at. Further, a frame in LIN communication may be initiated by a master, and the frame begins with a break field followed by a synchronization byte field (which may include, for example, eight synchronization bits). This sequence is unique in the LIN communication protocol and may guarantee that a slave detects the start of a new frame. FIG. 1 presents an example of an existing break field and a synchronization (break+sync) field in a frame conforming to the LIN communication protocol.

[0003] However, for some reason, if the slave gets confused (e.g., as to whether the "break+sync" field is currently being detected), the slave may miss a valid "break+sync" field with a distinct starting point or time. This undesirable situation can also be caused by a short circuit to a transient ground. In particular, the short circuit to ground can cause a dominant (or low) bit on the LIN bus for tens of milliseconds. This can confuse the slave, for example, because an incorrect "break" field may be detected, and a subsequent real break can be confused with the start bit of the sync field.

[0004] To recover from such a scenario and be able to detect a valid "break+sync" field, the controller or control logic in the receiver circuit within the slave may start a thread on any dominant or extended low (e.g., "0") bit that is considered a possible break field. The controller may then continue to verify the sync field until the sync verification fails (in which case the thread is released or terminated). From a hardware perspective, even if the maximum number of threads is a bounded problem, the cost of implementing a multi-threading approach can be significantly higher than a single-threading approach. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0005] An embodiment of an integrated circuit will be described. This integrated circuit includes an interface circuit for use with an electronic device. During operation, the interface circuit receives a signal corresponding to the header of a frame that conforms to a serial communication protocol, and the received signal includes a temporal pattern of binary bits having instances of a dominant signal level and a recessive signal level. The interface circuit then calculates a set of conditions based at least in part on the received signal, and when valid, the set of conditions identifies a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions is valid, the interface circuit determines the location of a synchronization field in the header for the identified first dominant bit and calculates the baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0006] Note that the serial communication protocol may include a Local Interconnect Network (LIN) communication protocol.

[0007] Moreover, the dominant signal level may be less than the recessive signal level.

[0008] Furthermore, the set of conditions may include a first instance of a first condition, where when valid, the first instance of the first condition may include that the second dominant bit time of a second dominant bit in the binary bits having the dominant signal level is less than or equal to a first predetermined multiple of the first dominant bit time of the first dominant bit, and the first dominant bit may precede the second dominant bit. For example, the first predetermined multiple may include 1.25. Alternatively, the set of conditions may include a second condition, where when valid, the second condition may include that the sum of the second dominant bit time and the first recessive bit time of a first recessive bit in the binary bits having the recessive signal level is greater than or equal to a second predetermined multiple of the first dominant bit time. Note that the first recessive bit may be between the first dominant bit and the second dominant bit.

[0009] In some embodiments, the second predetermined multiple includes the ratio of 2 to 11. Alternatively or additionally, the set of conditions may include a second instance of the first condition, where, when valid, the second instance of the first condition has a dominant signal level and the third dominant bit time of the third dominant bit among the binary bits is less than or equal to a first predetermined multiple of the second dominant bit time of the second dominant bit, and the second dominant bit may precede the third dominant bit. Note that the set of conditions may include a third condition, where, when valid, the third condition may include that the third dominant bit time is greater than or equal to a third predetermined multiple of the second dominant bit time.

[0010] Moreover, the third predetermined multiple may include 0.75.

[0011] Alternatively or additionally, the set of conditions may include a fourth condition. When valid, the fourth condition may include that the sum of the second inferior bit time of the second inferior bit among the binary bits and the third dominant bit time is greater than or equal to a third predetermined multiple of the average bit time of the bit pair of the bits in the binary bits and less than or equal to a first predetermined multiple of the average bit time, and the third dominant bit may precede the second inferior bit, and the bit pair may include the first inferior bit and a dominant bit selected from the group including the first dominant bit, the second dominant bit, and the third dominant bit. In some embodiments, the first predetermined multiple includes 1.25 and the third predetermined multiple includes 0.75.

[0012] Another embodiment provides a vehicle including an integrated circuit.

[0013] Another embodiment provides a system including an integrated circuit.

[0014] Another embodiment provides a computer-readable storage medium having program instructions for use with an electronic device. When executed by the electronic device, the program instructions cause the electronic device to perform at least some of the above-described operations in one or more of the foregoing embodiments.

[0015] Another embodiment provides a method for selectively calculating the baud rate of a received signal. The method includes at least some of the operations performed by an integrated circuit.

[0016] This summary is provided to introduce some exemplary embodiments in order to provide a basic understanding of some aspects of the subject matter described herein. Accordingly, it is to be understood that the above-described features are examples and should not be construed as in any way narrowing the scope or spirit of the subject matter described herein. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description of the invention, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017]

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[0018] Note that the same reference numbers refer to corresponding parts throughout the drawings. Moreover, multiple instances of the same part are designated by a common prefix separated by a dash from the instance number.

[0019] An integrated circuit for use with an electronic device is described. The integrated circuit may include an interface circuit. During operation, the interface circuit may receive a signal corresponding to a header of a frame that conforms to a serial communication protocol, and the received signal includes a temporal pattern of binary bits having instances of a dominant signal level and a recessive signal level. The interface circuit may then calculate a set of conditions, at least partially based on the received signal, and when valid, the set of conditions identifies a first dominant bit in the binary bits having the dominant signal level. Additionally, when the set of conditions is valid, the interface circuit may determine a location of a synchronization field in the header relative to the identified first dominant bit and calculate a baud rate of the received signal, at least partially based on a subset of the binary bits in the synchronization field.

[0020] By correctly identifying the location of the synchronization field and determining the baud rate, these circuit techniques can improve serial communication, for example, using the LIN communication protocol. In particular, these circuit techniques can enable a recipient electronic device using a serial communication protocol to recover from an undesirable state on the bus and detect a valid synchronization header (such as an "interrupt + synchronization" sequence or field) in the frame. Thus, these circuit techniques can improve the reliability and performance of serial communication. Accordingly, these circuit techniques can make communication by an electronic device more robust and reliable, and thus facilitate the use of integrated circuits in a wide variety of systems, electronic devices, and applications, such as in a vehicle. For example, the integrated circuit may be used in vehicle assistance or autonomous (or self-driving) operation.

[0021] Here, an embodiment of circuit technology will be described. The circuit technology may enable an integrated circuit to selectively calculate the baud rate of a received signal. During operation, the integrated circuit may receive a signal corresponding to a header of a frame conforming to a serial communication protocol (such as the LIN communication protocol), and the received signal includes a time pattern of binary bits having instances of a dominant signal level and a recessive signal level. Next, the integrated circuit may calculate a set of conditions, at least partially based on the received signal, and when valid, the set of conditions identifies a first dominant bit in a binary bit having a dominant signal level. Moreover, when the set of conditions is valid, the integrated circuit may determine the location of a synchronization field in the header for the identified first dominant bit and calculate the baud rate of the received signal, at least partially based on a subset of binary bits in the synchronization field.

[0022] The disclosed circuit technology may guarantee the detection of a valid synchronization header, regardless of an undesirable state transition on the LIN bus.

[0023] As described above, a slave may need to detect a "break+sync" sequence or field to identify the start of a frame and then to determine or derive the baud rate of the current transmission. The LIN specification includes several conditions that can help a slave succeed in detecting a "break+sync" sequence or field. In particular, a synchronization field (sometimes called a "sync field") follows a break field. Moreover, the break field may have a width or duration of at least 11 times the LIN bit time (thus, there may be an upper limit on the length or duration of the break field, as in the LIN specification). (However, 11 is used as an example for illustration, and more generally, the width or duration may be M times the LIN bit time, where M is a non-zero integer). Further, although not included in the LIN specification, sync field bits may be compared to each other, at least partially based on the LIN-specified tolerance.

[0024] As expected in the LIN specification, the slave may detect a "break+sync" sequence or field in various situations. In fact, integrated circuits compliant with the LIN specification are expected to guarantee the detection of a "break+sync" sequence or field in a very wide variety of scenarios. For example, one abnormal scenario can occur when the ground of the LIN bus is short-circuited while the screwdriver is being used to replace a component. This short-circuit to ground may appear as a dominant bit on the LIN bus and can have a random width or duration. If the dominant bit is long (e.g., 10 ms) and is followed by an actual or real break field (which should have a duration longer than 550 μs for a 20 k baud rate), the slave may become confused and may treat the pulse of the short-circuit to ground as the break field and the actual break field as the start bit of the sync field. In this scenario, the slave may assume that the sync byte (0x55) is followed first by the least significant bit (LSB). Depending on the implementation, the start bit of the sync field may be ignored, and two sync bits (one dominant and one recessive) may be used for comparison to check the validity of the "break+sync" sequence or field. In particular, two consecutive or adjacent bits of the sync field may be used together for comparison to avoid the rise and fall time differences of the receiving circuit in the slave. For this comparison, the slave may use two bit times for the break field to ensure that the break field is at least 11 times the average sync bit time or duration. Note that some integrated circuits may use the start bit (or dominant bit) of the sync field and the first recessive bit (the least significant bit of the sync byte) to perform the comparison. In any scenario, it is recognized during the reception of the sync field or byte that the short-circuit to ground was not a break field. This is usually too late for the slave to recover from the actual break and start considering the break as the start of a "break+sync" sequence or field. Therefore, in these scenarios, the slave may lose the entire frame.Figure 2 shows a timing diagram illustrating an example where a valid "break+sync" sequence or field is not detected when there is an undesirable event.

[0025] To address these issues, the slave may use multithreading. In particular, each dominant bit may be treated as if it were an interrupt field, and subsequent bits may be evaluated as if they were part of the sync field. Moreover, the slave may continue to verify the sync field against the expected interrupt field until a valid "break+sync" field is received. When this occurs (and thus the verification fails), the thread may be released for a new detection. Since there are six dominant bits in the "break+sync" field, the slave may require at least six threads to ensure that none of the dominant bits in the interrupt field are lost.

[0026] Note that the multithreading approach can be implemented using multiple instances of the receiving circuit in the slave. Although it can be gradually improved, the multithreading approach may still require starting a new thread by assuming that each dominant bit is a potential interrupt field.

[0027] Alternatively, to address the above-mentioned issues, the slave may use an improved single-thread approach. With these approaches, the slave can achieve the desired results in a single thread using one or more aspects or characteristics of the LIN communication protocol and a predefined comparison. These approaches can reduce cost and complexity compared to the multithreading approach.

[0028] In the improved single-thread approach, it may be important to optimize the receiving circuit without compromising the ability to detect the occurrence of the "break+sync" sequence or field. Moreover, in the single-thread approach, one or more of the following aspects or characteristics of the LIN communication protocol may be used. · The interrupt field may always precede the sync field. · When comparing, the dominant bit shall not be used alone to represent the LIN bit time. (In particular, since the rise and fall times of the receiving circuit can vary significantly, the dominant or recessive bits may be shorter or longer than expected. However, individual dominant bits may be used for comparison between them because the rise and fall time differences within the receiving circuit affect each dominant bit in the same way). · The width or duration of the interrupt field may be at least 11 times the average LIN bit time received in the sync field. · The duration or width of a new pair of bits (dominant and recessive bits) in the sync field may remain within a range of a predefined amount or twice the average bit time. (More generally, 2 may be replaced by N, where N is a non-zero even integer. For example, the predefined range may be ±25% or ±12.5% depending on system requirements. More generally, the predefined range may be between 1 + P and 1 - P, where P is a decimal between 0 and 0.4). · The dominant bit comparison may be sub-divided to evaluate the potential interrupt field when "break + sync" detection fails during the same comparison period. And / or · The memory unit may be used to hold previous or historical information in order to detect a valid "break + sync" field, and by doing so, autobaud detection can be optimized to use, for example, two memory units or registers. (Note that the information in the two memory units can be tracked by the same state machine that tracks the progress of "break + sync" field detection).

[0029] The LIN communication protocol is used as an example for illustration in this discussion, but it should be noted that the disclosed circuit technology may be used with serial communication protocols other than the LIN communication protocol. In particular, the present circuit technology may be used with other serial communication protocols where detection of a synchronization pattern is desired to avoid frame loss.

[0030] As described above, a LIN - compliant slave may support autobaud detection or determination. With this ability, the slave can derive or determine the transmission baud rate (or bit rate) from the detected "break + sync" field in the frame's synchronization header. Moreover, the LIN specification restricts the sync bit so as to have a relationship with the break field to help the slave detect a valid "break + sync" field. The current LIN specification does not limit the maximum duration of the break field. This freedom constrains the controller or control logic in or associated with the receiving circuit in the slave to assume the dominant bits as the break field and then proceed with their verification when subsequent sync bits are received. However, when there is a short - circuit, the resulting signal glitch may be assumed as the break field and the controller may proceed to verify the sync field. Thus, a glitch associated with a short - circuit may be large enough to confuse the controller into thinking that the actual or real break is the sync bit. Therefore, in this process, the controller may miss the actual or real break and thus may miss a frame.

[0031] In some embodiments, the "break + sync" field detection is implemented using a state machine that tracks incoming LIN bits and continuously searches for a valid "break + sync" field using predefined conditions, where the conditions are COND1: TLy+THy≧2 / 11 TLx, COND2: 3 / 4 mean(T)≦Ty≦5 / 4 mean(T), COND3: TLy ≥ 3 / 4 TLx, and COND4: TLy ≤ 5 / 4 TLx, where x is the previous dominant or recessive bit, y is the current dominant or recessive bit, TLx is the previous dominant bit time, TLy is the current dominant bit time, THy is the current recessive bit, Ty is the sum of TLy and THy or the sum of the most recent dominant bit time and recessive bit time, and mean(T) is the average 2-bit time (one dominant bit and one recessive bit) of the previous bit pair in the sync field.

[0032] COND1 can ensure that the width or duration of the break field is at least 11 times one-half of the sum of the start bit of the sync byte and the first least significant byte, which is noted to represent the LIN bit time. Moreover, COND2 can ensure that the sync field bits are within a bounded or predefined range of each other. Further, COND3 can compare the current dominant bit with the previous dominant bit, which ideally should have the same width, and the inequality can be true when both dominant bits are from the sync field. However, when this comparison is false (or not true), the previous dominant bit x may have been in the break field, and the current dominant bit y may be the start bit of the sync field. Additionally, COND4 can compare the current dominant bit with the previous dominant bit, which ideally should have the same width, and the inequality can be true when both dominant bits are from the sync field. However, when this comparison is false (or not true), the current dominant bit y may be in the break field.

[0033] FIG. 3 presents a diagram showing an example of a state machine with state transitions using the above-described predefined conditions. RE is a rising edge, IDLE is the default state, BREAK is a possible received interruption, SYN is during the process of obtaining the sync field, and it should be noted that RECEIVED indicates that a valid break+sync has been received. Moreover, note that the SYN state is a state machine representing to what extent of the sync field is verified. FIG. 4 presents a diagram showing an example of the SYN state in the state machine of FIG. 3.

[0034] As shown in FIG. 3, if any of the predefined conditions are evaluated as sync_fail, the state machine may move to the BRK state, where the previously held interrupt field value is replaced with the most recently received dominant bit.

[0035] In some embodiments, the receiving circuit may include a counter that counts the dominant and recessive bit widths by the number of system clocks. Moreover, there may be two registers, namely REG1 and REG2, which may be used to hold or store various values during the processing of the received signal to facilitate the evaluation of predefined conditions (such as inequality checks) and to assist in determining the baud rate from the sync field when a valid "break+sync" field is received. In particular, REG1 may hold or store the potential interrupt field count in IDL and SYN0, and sometimes may hold or store an average of 2 bit times (one dominant bit and one recessive bit). Further, REG2 may hold or store the most recently received dominant bit.

[0036] In the foregoing discussion, numerical examples are given, but in other embodiments, different numerical values may be used. Therefore, the numerical values given are not intended to be limiting.

[0037] Here, a timing diagram is presented along with examples showing various scenarios where zero or more of the default conditions fail. In Scenario 1, none of the default conditions fail (the ideal scenario). This scenario is shown in FIG. 5, which presents a timing diagram showing an example of a received signal during LIN communication. In FIGS. 5 - 9, an instance of operation 510 involves examining COND1, an instance of operation 512 involves examining COND2, an instance of operation 514 involves examining COND3, and an instance of operation 516 involves examining COND4. In FIG. 5, operation 510 - 1 detects an interruption that proves the interruption field is at least 11 bit times. In operation 512 - 1, the bit size is compared and aggregated with the bit period. Operation 516 - 1 is a rough check that this dominant bit is less than the previous one and that the sequence is worth considering as the break + sync bits of the sync field. Note that operations 514 - 1 and 516 - 2 are dominant bit comparisons to confirm they are of the same size.

[0038] Moreover, in Scenario 2, COND1 fails. This scenario is shown in FIG. 6, which presents a timing diagram showing an example of a received signal during LIN communication. Note that the failure of COND1 in operation 510 - 1 is essentially the sync_fail condition that sets the state machine to the BRK state, in which the previous interruption is replaced by the most recently received dominant bit.

[0039] Furthermore, in Scenario 3, COND2 fails. This scenario is shown in FIG. 7, which presents a timing diagram showing an example of a received signal during LIN communication. Note that the failure of COND2 in operation 512 - 1 is essentially the sync_fail condition that sets the state machine to the BRK state, in which the previous interruption is replaced by the most recently received dominant bit. Also note that in operation 516 - 3, the sync_fail condition sets the state machine to the BRK state, in which the previous interruption is replaced by the most recently received dominant bit.

[0040] Furthermore, in Scenario 4, COND3 fails. This scenario is shown in FIG. 8, which presents a timing diagram showing an example of a received signal during LIN communication. In operation 514-1, the failure of COND3 sets the state machine to state SYN0, where the previous dominant bit becomes interrupted and the current dominant bit acts as the start bit of the sync field.

[0041] In Scenario 5, COND4 fails. This scenario is shown in FIG. 9, which presents a timing diagram showing an example of a received signal during LIN communication. In operation 516-3, the failure of COND4 is the sync_fail condition that sets the state machine to the BRK state, in which the previous break is replaced by the most recently received dominant bit.

[0042] As described above, an integrated circuit may implement at least partially this circuit technology. In particular, FIG. 10 presents a block diagram showing an example of an integrated circuit 1000. This integrated circuit may include an interface circuit 1010 that includes a receiving circuit 1012. In some embodiments, the receiving circuit 1012 may include an analog front end (such as a preamplifier), an analog-to-digital converter (ADC), one or more detection channels implementing one or more detection techniques, a clock, and control logic that configures and manages the detection circuit. Note that there may be dedicated detection channels among one or more detection channels for measurements implemented by a given integrated circuit. Alternatively or additionally, one or more detection channels may be shared when analyzing measurements implemented by various integrated circuits.

[0043] Note that FIG. 10 does not show all the connections between components. Moreover, the integrated circuit 1000 may include fewer or additional components, two or more components may be combined, a single component may be divided into two or more components, and / or the positions of one or more components may be changed.

[0044] Here, embodiments of the method will be described. FIG. 11 presents a flowchart showing an example of a method 1100 for selectively calculating the baud rate of a received signal. This method may be implemented by an integrated circuit such as an interface circuit.

[0045] During operation, the interface circuit may receive a signal corresponding to the header of a frame conforming to a serial communication protocol (operation 1110), and the received signal includes a time pattern of binary bits having instances of a dominant signal level and a recessive signal level. Next, the interface circuit may calculate a set of conditions based at least in part on the received signal (operation 1112), and when valid, the set of conditions identifies a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions is valid (operation 1114), the interface circuit may determine the location of the synchronization field in the header for the identified first dominant bit (operation 1116) and calculate the baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field (operation 1118). If not valid (operation 1114), the interface circuit may perform a return to operation 1110.

[0046] In some embodiments of method 1100, there may be additional or fewer operations. Moreover, the order of operations may be changed and / or two or more operations may be combined into a single operation.

[0047] The disclosed integrated circuits and circuit techniques may be (or may be included in) any electronic device or system. For example, the electronic device may include a cellular phone or smartphone, tablet computer, laptop computer, notebook computer, personal or desktop computer, netbook computer, media player device, electronic book device, MiFi (registered trademark) device, smartwatch, wearable computing device, portable computing device, consumer electronic device, camera or image sensor, access point, router, switch, communication device, test device, vehicle, drone, ship, airplane, car, truck, bus, motorcycle, manufacturing equipment, agricultural implement, construction equipment, or another type of electronic device.

[0048] Certain components are used to describe an embodiment of the integrated circuit, but in alternative embodiments, different components and / or subsystems may be present in the integrated circuit. Thus, embodiments of the integrated circuit may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more positions of one or more components may be changed, and / or there may be different types of components.

[0049] Moreover, the circuits and components in embodiments of the integrated circuit may be implemented using any combination of analog and / or digital circuit configurations, including bipolar, PMOS and / or NMOS gates or transistors. Further, the signals in these embodiments may include digital signals having approximate discrete values and / or analog signals having continuous values. Further, the components and circuits may be single-ended or differential, and the power supply mechanism may be single-pole or bipolar. Note that the electrical couplings or connections in the foregoing embodiments may be direct or indirect. In the foregoing embodiments, a single line corresponding to a certain route may represent one or more single lines or routes.

[0050] As described above, an integrated circuit may implement some or all of the functionality of the present circuit technology. This integrated circuit may include hardware and / or software mechanisms used to implement the functionality associated with the present circuit technology.

[0051] In some embodiments, the output of a process for designing an integrated circuit, or a portion of an integrated circuit, that includes one or more of the circuits described herein may be, for example, a computer-readable medium such as a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with other information describing a data structure or a circuit configuration that may be physically instantiated as an integrated circuit or a portion of an integrated circuit. Various formats may be used for such encoding, but these data structures are generally written in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA), or Open Artwork System Interchange Standard (OASIS). One of ordinary skill in the art of integrated circuit design can develop such data structures from the schematic diagrams and corresponding descriptions of the types detailed above and can encode the data structures in a computer-readable medium. One of ordinary skill in the art of integrated circuit fabrication can use such encoded data to manufacture an integrated circuit that includes one or more of the circuits described herein.

[0052] Some of the operations in the above-described embodiments are implemented in hardware or software, but generally, the operations in the above-described embodiments can be implemented in a wide variety of configurations and architectures. Therefore, some or all of the operations in the above-described embodiments may be implemented in hardware, in software, or in both. For example, at least some of the operations in this circuit technology may be implemented using program instructions executed by a processor or in firmware in an integrated circuit.

[0053] Moreover, in the above discussion, numerical examples are given, but in other embodiments, different numerical values may be used. Therefore, the given numerical values are not intended to be limiting.

[0054] In the above description, "some embodiments" are referred to. Note that "some embodiments" describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0055] The above description is intended to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of specific application examples and their requirements. Moreover, the above description of the embodiments of the present disclosure is presented only for purposes of illustration and description. The above description is not intended to be exhaustive or to limit the present disclosure to the form disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments and application examples without departing from the spirit and scope of the present disclosure. Furthermore, the discussion of the above-described embodiments is not intended to limit the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Description of Reference Numerals

[0056] 1000 Integrated Circuit 1010 Interface Circuit 1012 Receiving circuit

Claims

1. An integrated circuit comprising an interface circuit, wherein the interface circuit is configured to: receive a signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a temporal pattern of binary bits having instances of a dominant signal level and a recessive signal level; identify a subset of the received signal; be configured to perform; identifying a subset of the received signal comprises: calculating a set of conditions based at least in part on the received signal, the set of conditions including a comparison, the comparison being a comparison between a predetermined time reference and a dominant bit time of a dominant bit having the dominant signal level, or a comparison between a predetermined time reference and a sum of the dominant bit time of the dominant bit having the dominant signal level and a recessive bit time of a recessive bit having the recessive signal level, and when effective based at least in part on the comparison, the set of conditions calculates to identify a first dominant bit among the binary bits having the dominant signal level; when the set of conditions is effective based at least in part on the comparison; determine a location of a synchronization field in the header with respect to the identified first dominant bit; calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field; including; the set of conditions includes a first instance of a first condition; when effective based at least in part on the comparison, the first instance of the first condition includes that a second dominant bit time of a second dominant bit among the binary bits having the dominant signal level is less than or equal to a first predetermined multiple of a first dominant bit time of the first dominant bit; the first dominant bit precedes the second dominant bit, the integrated circuit.

2. The integrated circuit according to claim 1, wherein the serial communication protocol includes a Local Interconnect Network (LIN) communication protocol.

3. The integrated circuit according to claim 1, wherein the dominant signal level is less than the recessive signal level.

4. The integrated circuit according to claim 1, wherein the first predetermined multiple includes 1.

25.

5. The set of conditions includes a second condition, When effective, the second condition includes that the sum of the second dominant bit time and the first dominant bit time of the first inferior bit among the binary bits having the inferior signal level is not less than a second predetermined multiple of the first dominant bit time. The integrated circuit according to claim 1, wherein the first inferior bit is between the first dominant bit and the second dominant bit. **Claim 6** The integrated circuit according to claim 5, wherein the second predetermined multiple includes a ratio of 2 to 11. **Claim 7** The set of conditions includes a second instance of the first condition. When effective, the second instance of the first condition includes that the third dominant bit time of the third dominant bit among the binary bits having the dominant signal level is not more than a first predetermined multiple of the second dominant bit time of the second dominant bit. The integrated circuit according to claim 5, wherein the second dominant bit precedes the third dominant bit. **Claim 8** The set of conditions includes a third condition. The integrated circuit according to claim 7, wherein when effective, the third condition includes that the third dominant bit time is not less than a third predetermined multiple of the second dominant bit time. **Claim 9** The integrated circuit according to claim 8, wherein the third predetermined multiple includes 0.

75. **Claim 10** The integrated circuit according to claim 9, wherein the first predetermined multiple includes 1.25 and the third predetermined multiple includes 0.

75. **Claim 11** The set of conditions includes a fourth condition. When effective, the fourth condition includes that the sum of the second dominant bit time of the second inferior bit among the binary bits and the third dominant bit time is not less than a third predetermined multiple of the average bit time of a pair of bits among the binary bits, and the sum is not more than a first predetermined multiple of the average bit time. The third dominant bit precedes the second inferior bit. The integrated circuit according to claim 8, wherein the pair of bits includes the first inferior bit and a dominant bit selected from a group including the first dominant bit, the second dominant bit, and the third dominant bit. **Claim 12** A computer-readable storage medium for use with an electronic device, the computer-readable storage medium storing program instructions which, when executed by the electronic device, cause the electronic device to perform one or more operations, the operations comprising: Receiving a signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a temporal pattern of binary bits having instances of a dominant signal level and a recessive signal level; Identifying a subset of the received signal; Including; Identifying a subset of the received signal comprises: Calculating a set of conditions based at least in part on the received signal, the set of conditions including a comparison, the comparison being a comparison between a predetermined time reference and a dominant bit time of a dominant bit having the dominant signal level, or a comparison between a predetermined time reference and a sum of the dominant bit time of the dominant bit having the dominant signal level and a recessive bit time of a recessive bit having the recessive signal level, and when the comparison is valid based at least in part on the comparison, the set of conditions identifying, calculating a first dominant bit in the binary bits having the dominant signal level; When the set of conditions is valid based at least in part on the comparison; Determining a location of a synchronization field in the header with respect to the identified first dominant bit; Calculating a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field; Including; The set of conditions includes a first instance of a first condition; When valid based at least in part on the comparison, the first instance of the first condition includes that a second dominant bit time of a second dominant bit in the binary bits having the dominant signal level is less than or equal to a first predetermined multiple of a first dominant bit time of the first dominant bit; The first dominant bit precedes the second dominant bit, computer-readable storage medium. **Claim 13** The computer-readable storage medium according to claim 12, wherein the serial communication protocol includes a Local Interconnect Network (LIN) communication protocol. **Claim 14** The computer-readable storage medium according to claim 12, wherein the dominant signal level is less than the recessive signal level. **Claim 15** A method for selectively calculating the baud rate of a received signal, comprising: by an electronic device, receiving, by the electronic device, the signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a temporal pattern of binary bits having instances of a dominant signal level and a recessive signal level; identifying a subset of the received signal; comprising: The step of identifying a subset of the received signal comprises: calculating, based at least in part on the received signal, a set of conditions, the set of conditions including a comparison, the comparison being a comparison between a predefined time reference and a dominant bit time of a dominant bit having the dominant signal level, or a comparison between a predefined time reference and a sum of the dominant bit time of the dominant bit having the dominant signal level and a recessive bit time of a recessive bit having the recessive signal level, and when valid based at least in part on the comparison, the set of conditions identifying a first dominant bit in the binary bits having the dominant signal level; when the set of conditions is valid based at least in part on the comparison; determining, for the identified first dominant bit, a location of a synchronization field in the header; calculating, based at least in part on a subset of the binary bits in the synchronization field, the baud rate of the received signal; comprising: The set of conditions includes a first instance of a first condition, when valid based at least in part on the comparison, the first instance of the first condition including that a second dominant bit time of a second dominant bit in the binary bits having the dominant signal level is less than or equal to a first predefined multiple of a first dominant bit time of the first dominant bit; wherein the first dominant bit precedes the second dominant bit. **Claim 16** The method according to claim 15, wherein the serial communication protocol includes a Local Interconnect Network (LIN) communication protocol. **Claim 17** The method according to claim 15, wherein the dominant signal level is less than the recessive signal level. **Claim 18** The method according to claim 15, wherein the serial communication protocol includes a local interconnection network (LIN) communication protocol.

19. The method according to claim 15, wherein the dominant signal level is less than the inferior signal level.

20. The set of conditions includes a second instance of the first condition, when valid, the second instance of the first condition includes that the third dominant bit time of the third dominant bit among the binary bits having the dominant signal level is less than or equal to a first predetermined multiple of the second dominant bit time of the second dominant bit, The method according to claim 15, wherein the second dominant bit precedes the third dominant bit.

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