Radio wave generator with automatic level control

Abstract

A radio frequency (RF) generator incorporates an automatic level control (ALC) circuit to control the output level of an RF signal. The ALC circuit implements synchronous ADC sampling, pulse sample indexing, and gate accumulation, enabling high speed ALC loop control, especially for pulse modulated RF signals. In another embodiment, the ALC circuit implements multi-level control for multi-level RF signals. In this manner, the RF generator uses the ALC circuit to generate an RF signal with a constant power level for RF signals with any pulse shape or output level. In another embodiment, a clock generation circuit in an impedance matching network synchronizes a slave clock to the clock signal of the RF signal only if the load impedance is resistive or if the clock signal of the RF signal has a given phase condition.

Description

Technical Field

[0001] The present invention relates to a radio frequency (RF) generator, and more particularly, to an automatic level control circuit in an RF generator.

Background Art

[0002] An RF generator or RF power supply is industrial equipment used to provide RF energy to a load device. RF generators are commonly used in the semiconductor industry, such as in plasma semiconductor devices for generating plasma to manufacture silicon wafers. A typical plasma tool may include an RF generator, an impedance matching system, and a plasma chamber. In semiconductor applications, an RF generator can generate a continuous wave (CW) signal, a pulse-modulated signal, a ramp signal, or a multi-level RF signal. A pulse-modulated RF generator applies an RF signal by pulsing the RF signal to the load.

[0003] An RF generator generates an RF signal having a desired amplitude and output frequency. An RF generator typically performs some form of amplitude level control. Specifically, the output level of an RF generator can vary due to temperature variations of the components of the generator, power supply drift or variations, or other reasons. An RF generator executes an amplitude level control loop to maintain the RF output power at a desired level based on a feedback signal. For example, the RF output is sampled and compared to a reference level to set the desired output power level. The difference between the sampled RF output and the reference level constitutes an error signal. The operation of the feedback loop is to control the output level of the RF signal in response to the error signal to achieve a stable output level.

Brief Description of the Drawings

[0004] Various embodiments of the present invention are disclosed in the following detailed description and the accompanying drawings.

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DETAILED DESCRIPTION OF THE INVENTION

[0018] According to an embodiment of the present invention, a radio frequency (RF) generator incorporates an automatic level control (ALC) circuit for controlling the output level of an RF signal, where the ALC circuit performs synchronized ADC sampling, pulse sample indexing, and gate accumulation to enable fast ALC loop control, particularly for pulse - modulated RF signals. In other embodiments, the ALC circuit performs multi - level control for multi - level RF signals. In this way, the RF generator uses the ALC circuit to generate an RF signal having a constant power level for an RF signal having any pulse shape or output level.

[0019] The ALC circuit of the present disclosure can be applied to an RF generator that generates a continuous wave (CW) RF signal, or a pulse-modulated RF signal, or a ramp RF signal, or other RF signal waveforms. However, the ALC circuit of the present disclosure can be advantageously applied to a pulse-modulated RF signal, particularly a pulse-modulated RF signal having a short pulse width. In some embodiments, the ALC circuit of the present disclosure does not require oversampling and can instead be implemented using sampling of the RF signal at a frequency lower than the RF frequency.

[0020] In other embodiments of the present disclosure, a clock generation circuit for synchronizing a slave clock signal with a master clock signal of an RF signal is described. In one embodiment, the clock generation circuit in the impedance matching system synchronizes the slave clock with the clock signal of the RF signal only when the load impedance is resistive. In this way, the slave clock can be synchronized with the RF signal without a phase shift due to a non-resistive load impedance. In other embodiments, the slave clock is synchronized with the master clock of the RF signal, and the impedance matching system generates a sampling signal based on the synchronized slave clock.

[0021] FIG. 1 is a schematic diagram of an RF system in which an RF generator is employed in some embodiments. Referring to FIG. 1, RF system 1 is configured to supply an RF signal to load 6. For example, load 6 may be a semiconductor device such as a plasma semiconductor device. The RF signal can be applied to generate plasma in a plasma tool such as for etching semiconductor components. RF system 1 includes an RF generator 2 that generates an RF signal 3 having a predetermined RF frequency. In some embodiments, RF signal 3 can be a continuous wave such as a sine wave, a ramp signal, or a pulse waveform. In other embodiments, the RF signal can be a burst signal or a pulse - modulated RF signal, i.e., the RF signal is provided as a burst of RF signals having different pulse rates and / or different duty cycles. RF signal 3 is provided to an impedance - matching system 4 that matches the impedance of the RF signal to the desired impedance of load 6. Impedance - matching system 4 modifies the RF signal, such as the phase, amplitude, and other parameters of the RF signal, to convert the RF signal into a matched - impedance RF signal 5 provided to load 6.

[0022] RF generator 2 performs level control by measuring or sampling the RF signal at its output terminal. The sampled RF signal typically includes the forward RF signal from a power amplifier within the generator, is fed back to RF generator 2, and forms a control loop for adjusting the level or amplitude of the RF signal.

[0023] Embodiments of the present disclosure describe an RF generator incorporating an automatic - level - control (ALC) circuit for providing accurate level control of the output RF signal.

[0024] Figure 2 is a schematic diagram of an RF generator incorporating an automatic level control (ALC) circuit according to an embodiment of the present disclosure. Referring to FIG. 2, an RF generator 10 (also referred to as an "RF power supply") includes an RF circuit 20 and an automatic level control (ALC) circuit 50. The RF circuit 20 generates an RF signal from an RF signal source and provides, typically via an impedance matching network, an RF signal for driving a load to an output terminal 35. The ALC circuit 50 controls the RF circuit to generate an RF output signal having a controlled amplitude. The RF generator 10 may include other circuits and components (not shown) for assisting the functions of the RF generator. Other circuits and components of the RF generator 10 are omitted in FIG. 2 for simplicity of explanation.

[0025] In the RF circuit 20, a signal generator 22 generates an RF source signal at a predetermined RF frequency as a function of an RF clock CLK1. In one embodiment, the oscillator 22 generates an RF source signal that is a fixed-level sine wave at a desired RF frequency. The RF source signal may be amplified by a driver 24. The RF source signal is then modulated by a signal modulator 26. The signal modulator 26 may be connected to gate the RF source signal to generate a pulse-modulated RF signal. The signal modulator 26 may also be connected to adjust the signal level, signal phase, signal amplitude, or a combination of these parameters of the RF source signal. In one embodiment, the signal modulator 26 modulates the RF signal based on the input level of an analog control signal provided by a DAC 80 and adjusts the amplitude of the RF signal at the output of the signal modulator 26. The modulated RF signal may be further amplified by a driver 28 and a power amplifier 30. For example, the power amplifier 30 amplifies the power of the RF signal output from the signal modulator 26 at a predetermined amplification rate. The power amplifier 30 amplifies the power of the RF signal to achieve a desired signal amplitude for the output RF signal. The RF signal thus generated is provided to the output terminal 35 and can be transmitted via an impedance matching system to a load on a transmission line such as an RF cable.

[0026] In particular, the RF signal is provided to the output terminal 35 of the RF circuit 20 via a pair of directional couplers 32, 34. The directional couplers 32, 34 attenuate and extract the respective forward power and reflected power at the output terminal 35, where the sampled signals are used to monitor the output level of the RF generator 10. In other words, each directional coupler measures a very small part of the output power (forward RF signal or reflected RF signal) and redirects the measured value to the ALC circuit 50.

[0027] In the ALC circuit 50, the measured value of the forward RF signal output by the directional coupler 32 is provided to an analog-to-digital converter (ADC) 52 and converted into digital data samples. Similarly, the sample of the reflected RF signal output by the directional coupler 34 is provided to an analog-to-digital converter (ADC) 54 and converted into digital data samples. The ADCs 52, 54 digitize the analog samples from the respective directional couplers at a sampling frequency based on the sampling clock CLK2 indicated by the clock source 56. In some embodiments, the directional coupler 32 is connected to the ADC 52 via a signal amplifier and an attenuator. Similarly, the directional coupler 34 is connected to the ADC 54 via a signal amplifier and an attenuator.

[0028] Next, the digital samples of the forward and reflected RF signals are processed by signal processing path 85. Signal processing path 85 generates an error signal (node 75) or a vector error signal indicating the difference between the measured signal level value of the RF signal and the reference signal level (level Ref). This difference may be a scalar value or a vector value (multiple possible). The error signal (node 75) is provided to modulation control device 78. Modulation control device 78 also obtains a pulse modulation signal from pulse and level control circuit 82. Modulation control device 78 obtains other waveform data from pulse and level control circuit 82 for a lamp signal or a multi-level pulse modulation signal, etc. The pulse modulation signal from pulse and level control circuit 82 indicates the modulation to be applied to the RF signal, such as for generating a pulse-modulated or burst RF signal. Modulation control device 78 synthesizes the error signal and the pulse modulation signal to generate a control signal, which is converted into an analog form by digital-to-analog converter 80 and then provided to signal modulator 26 to control the modulation of the RF source signal and also to modify the level or amplitude or phase of the RF source signal to generate an RF output signal having a desired pulse modulation and a desired signal amplitude. Because it is configured in this way, a feedback loop is formed within RF generator 10, and ALC circuit 50 can continuously monitor and control the output power or output level of the RF signal. In some embodiments, signal modulator 26 can be a multiplier that combines the RF source signal and the control signal provided by ALC circuit 50.

[0029] In this specification, the RF signal generated in this way can be a sine wave signal, or a continuous wave (CW) RF signal such as a pulse train or a ramp signal, or another amplitude-modulated RF signal such as a signal generated from an arbitrary waveform generator (AWG). Alternatively, the RF signal can be a pulse-modulated RF signal. For example, the ramp RF signal includes an output level that continuously changes based on a reference level input to the modulation control device 78. In other embodiments, the level control signal from the pulse and level control circuit 82 may vary the amplitude of the RF output as a function of time. In this specification, a pulse-modulated RF signal, also referred to as a pulse RF signal, means an RF signal of a predetermined RF frequency having an on period during which the RF signal is provided to the output terminal and an off period during which the RF signal is not provided. That is, the RF signal of the predetermined RF frequency is provided only during the on period. The on period and the off period may be repeated, and the pulse RF signal may have the same or different pulse widths for each pulse of the RF signal.

[0030] In an embodiment of the present disclosure, a prominent feature of the ALC circuit 50 is the use of a synchronous ADC sampling clock. Specifically, the ADC sampling clock CLK2 is synchronized with the RF clock CLK1. In one example, both the ADC sampling clock CLK2 and the RF clock CLK1 can be synchronized or locked to a master clock (CLK0), and the ADC sampling frequency and the RF frequency can be derived from the master clock. By using a synchronous ADC sampling clock, fewer sampling points are required to accurately sample the forward / reflected RF signals. In an embodiment of the present disclosure, an ADC sampling frequency lower than the RF frequency can be used. By using a synchronous sampling clock, the ADCs 52, 54 sample the RF signals measured at the same position within each pulse period. Therefore, fewer points are required for the ADCs 52, 54 to capture the peaks of the RF signal pulses where level information is important. Since fewer samples are required to obtain the measured signal level value, the ALC circuit 50 can achieve a faster settling time. In fact, the ALC circuit 50 can determine the control signal without using many digital samples. In one example, only one digital sample within one RF signal period is needed.

[0031] In some embodiments, the sampling frequencies of ADCs 52, 54 are selected such that the intermediate frequency (IF) is aligned with one of the sampling points. In one example, the RF frequency is 11 MHz and a sampling frequency of 8.8 MHz is used. As a result, the mixed intermediate frequency (IF) from the ADC appears at 2.2 MHz. Using a 4-point FFT, one of the IF signals appears in the first FFT result at 2.2 MHz. Thus, the number of sampling points required to obtain the desired result is very small. In another example, the RF frequency is 110 MHz and a sampling frequency of 80 MHz is used. As a result, the mixed intermediate frequency (IF) from the ADC appears at 30 MHz. Using an 8-point FFT, one of the IF signals appears in the third FFT result at 30 MHz. Thus, the RF-related data always appears in one of the FFT results, stabilizing and accurately performing ADC sampling. Configured in this way, the ALC circuit can use a lower-cost ADC and be implemented with fewer memory requirements.

[0032] In other embodiments, when the RF frequency is low, the sampling frequency can be made greater than the RF frequency. For example, when the RF signal frequency is as low as 1 MHz, the ADC sampling frequency can be 1.6 MHz. In this case, the IF frequency appears at 400 KHz. By applying a 4-point FFT with a 1.6 MHz ADC sampling frequency, one of the FFT results is at 400 KHz. The IF signal appears at the frequency and satisfies the following equation: IFFreq = |N x RF signal ± M x ADC sampling|. This configuration can be applied when the sampling frequency is an integer multiple (i.e., 1, 2, 3, 4...) of the IF frequency. In other embodiments, this configuration is such that the RF frequency is 2 NIt can also be applied when it is (or a power of 2). For example, when the RF frequency is 1 MHz and the ADC sampling frequency is 4 MHz, the RF signal (amplitude, phase, etc.) can be sampled using a 4-point FFT in the same manner as described above. Therefore, one ADC with a wider RF input frequency can be used to cover a wide range of RF frequencies. That is, the ADC circuit can be applied to a wide input RF frequency range.

[0033] By using a synchronous ADC sampling clock, each digital sample of the RF signal can be indexed or labeled. Further, the index can be used to indicate the position of the digital sample obtained on the RF signal pulse. In an embodiment of the present disclosure, the ALC circuit 50 processes the digitized samples of the forward / reflected RF signal based on a sample index that identifies the digital samples generated by the ADCs 52, 54. In one example, the ADC sampling is processed using a 4-point FFT (Fast Fourier Transform), and the four digital samples for each conversion obtained within the period of the RF signal are labeled by the sample indices "0, 1, 2, 3". The sample index also indicates the phase position of the digital sample obtained within the period of the RF signal. For example, sample index 0 indicates a digital sample obtained at a 0° phase angle, sample index 1 indicates a digital sample obtained at a 90° phase angle, sample index 2 indicates a digital sample obtained at a 180° phase angle, and sample index 3 indicates a digital sample obtained at a 270° phase angle. Thus, when the digital samples obtained by the ADCs 52 and 54 are indexed, the signal processing of the digital samples can be simplified and rationalized. In an embodiment of the present disclosure, the ALC circuit 50 includes an index generator 84 for generating a sample index value for each digital sample provided by the ADCs 52, 54. The index generator 84 obtains RF level-related data from the pulse and level control circuit 82 and provides the sample index value to the signal processing path 85.

[0034] Another prominent feature of the ALC circuit of the present disclosure is that the ADC digitization step uses a small number of FFT points, such as 4, 16, or 32. By enabling the use of a small number of FFT points and using a synchronous sampling clock, the ALC circuit can support shorter pulse widths in the pulsed RF signal. Since the digital samples can be processed based on the sample index, the shorter pulse width of the pulsed RF signal can still be accurately sampled. When a large FFT, such as 4096, 32768, or 65536, is used, the more data points there are, the longer the processing time required by the system. This reduces the processing capacity of the data output. The system will also require a faster ADC so that the system does not miss short pulses. For example, when a small number of FFT points are used, it only takes a short time to perform the conversion to capture the digital samples for one set of indices. In one embodiment, a 4-point FFT is used and the sampling time is 1 ms. For one conversion, it only takes 4 ms to capture the digital samples for the entire set of indices (0, 1, 2, 3). Then, the captured digital samples can be used to calculate the accurate phase value and amplitude value. However, when the ALC circuit uses a large FFT, such as a 65536-point FFT, the ALC circuit has to wait 65.536 ms to perform one conversion to capture the entire data set. Alternatively, the system needs to use a faster ADC and requires a faster processor and a larger buffer memory. When a large FFT is used, the ALC circuit cannot calculate the accurate phase and amplitude values from the low-speed sampling ADC with only the use of a part of the captured digital samples and has to wait for the entire data set to be captured.

[0035] Next, the signal processing path 85 of the ALC circuit 50 will be described in more detail. After the forward and reflected RF signals measured by the directional couplers 32 and 34 are digitized by the ADCs 52 and 54, the digitized samples are provided to the respective gate accumulation blocks 58a and 58b. The gate accumulation blocks 58a and 58b determine which digital samples should be used in the signal processing operation. In particular, the gate accumulation blocks 58a and 58b determine which digital samples should be passed for signal processing and which digital samples should be blocked. In other words, the gate accumulation blocks 58a and 58b apply a gate to the input digital samples based on the sample index to select the specific digital samples to be passed to the signal processing operation.

[0036] The selected digital samples are provided to respective digital filters 60a, 60b that are to be processed. The digital filters 60a, 60b generate processed values indicative of the signal levels and impedances of the measured forward and reflected RF signals. In some embodiments, the digital filters 60a, 60b are implemented as discrete Fourier transform filters. In the present embodiment, the digital filters 60a, 60b generate S-parameter related vector values "raw a1" (62a) and "raw b1" (62b), where each vector value indicates the magnitude and phase measured by the digital samples for the forward or reflected RF signal. More specifically, the S-parameter related values "raw a1" and "raw b1" mean scattering parameters (or S-parameters), which are the coefficients of a scattering matrix representing the possible input-output paths of the RF signal. The S-parameters are complex numbers having a real part and an imaginary part representing the magnitude and phase parts. The magnitude provides a level measurement value and the phase provides an impedance measurement value. That is, each S-parameter value has a magnitude value related to the signal level of the RF signal and a phase value related to the impedance seen by the RF signal. Thus, the value "raw a1" represents an S-parameter value calculated from the forward RF signal transmitted on the signal line, and the value "raw b1" represents an S-parameter value calculated from the reflected RF signal. In this specification, the digital filters 60a, 60b generate "raw" S-parameters, which refers to the values "raw a1" and "raw b1", because these are uncalibrated values.

[0037] The processed values (raw a1 and raw b1) are provided to processor 72 to calculate the impedance and level values of the sampled RF signal. Processor 72 can be implemented as a logic circuit or as firmware executed in the processor. Processor 72 generates a measurement signal level value for the RF signal. Alternatively, in other embodiments, processor 72 can provide vector error data or an error data matrix. The measurement signal level value is provided to processor 74 to compare the measurement signal level value to a reference signal level (level Ref). Processor 74 generates an error signal (node 75) indicating the difference between the measurement signal level value and the reference signal level. Processor 74 can be implemented as a logic circuit or as firmware executed in the processor. Configured in this way, signal processing path 85 acquires digital samples of the forward and reflected RF signals and generates an error signal indicating the difference between the measurement signal level value and the reference signal level. The error signal (node 75) is provided to modulation control device 78 to control the level of the RF signal generated by RF circuit 20, completing the ALC loop.

[0038] In some embodiments, gate accumulation block 58 selects digital samples only when an RF signal is provided (during the on period). During the RF signal off period when no RF signal is provided, signal processing path 85 may simply output the previously calculated measurement signal level value. By gating digital samples only during the on period, the ALC loop can be implemented with reduced complexity and improved stability.

[0039] In the embodiment shown in FIG. 2, signal processing path 85 shows separate gate accumulation blocks 58a, 58b for digital samples of the forward RF signal and the reflected RF signal, respectively. In this specification, in order to process digital samples for both the forward and reflected RF signals, the signal processing path may be illustrated as including a single set of gate accumulation blocks and digital filters. The gate accumulation blocks and digital filters are merely representative elements and it should be understood that they are used herein to illustrate circuitry for processing digital samples from one or more signal sources. FIGS. 2 and subsequent figures are merely exemplary and are not intended to be limiting.

[0040] In some embodiments, the RF generator generates a multi-level RF signal. That is, the RF signal can have two or more signal levels. In the case of a pulse-modulated RF signal, each pulse or each burst of the RF signal may have the same or different signal levels. In embodiments of the present disclosure, the ALC circuit can be configured to provide level control of the multi-level RF signal. FIG. 3 is a schematic diagram of an RF generator incorporating an automatic level control (ALC) circuit for a multi-level RF signal in an embodiment of the present disclosure. Similar elements in FIGS. 2 and 3 are given similar reference numerals for simplicity of explanation. Referring to FIG. 3, the RF generator 100 includes an RF circuit 20 that generates an RF signal that can be a multi-level RF signal on an output terminal 35. The RF generator 100 further includes an automatic level control (ALC) circuit 150 for providing level control of one or more levels of the RF signal. In the ALC circuit 150, a plurality of signal processing paths 185-1 to 185-N are provided to process signal levels 1 to N of the RF signal. Each signal processing path 185 includes elements for processing digital samples of the forward and reflected RF signals at one signal level. For example, each signal processing path 185 can include a gate integration block, a digital filter, and one or more processors for calculating a signal level value measured from the digital samples and calculating an error signal indicating the difference between the measured signal level value and a reference signal level of each signal level. For example, the first signal processing path 185-1 is arranged to process digital samples of the forward and reflected RF signals for the first signal level. The first signal processing path 185-1 generates an error signal-1 indicating the difference between the measured signal level value for the first signal level and the reference signal level 1 associated with the first signal level. The ALC circuit 150 includes two or more signal processing paths for generating an error signal for each signal level of the RF signal.

[0041] To support multi-level RF signals, the index generator 184 provides a first index as a sample index for digital samples and a second index as a level index for identifying signal levels. The sample index and the level index are provided to the gate accumulation block in the signal processing path to select the digital samples to be processed.

[0042] Error signals generated by all signal processing paths 185-1 to 185-N are provided to a data selector 76 that operates to select one of the error signals of the signal level currently controlled by the ALC circuit 150. The selected error signal is then provided to a modulation control device 78, generates a control signal converted to an analog form by a DAC 80, modulates the signal level of the RF source signal, and generates a multi-level RF signal having a controlled amplification section.

[0043] A prominent feature of the ALC circuit of the present disclosure is the use of a synchronous ADC sampling clock. FIG. 4 shows a clock synchronization scheme implemented in the ALC circuit of an RF generator in some embodiments. Referring to FIG. 4, a master clock 90 provides a clock signal CLK0 having a given clock frequency. A frequency control device 92 is used to generate a clock signal CLK1 for an oscillator 22 in the RF circuit 20 to generate an RF source signal having a predetermined RF frequency. A frequency control device 94 is used to generate a clock signal CLK2 for use as a sampling clock for the ADCs 52, 54. In this way, the sampling clock CLK2 is synchronized with the RF clock CLK1 used to generate the RF signal. By using a synchronized ADC sampling clock, the ADC circuit 50 can implement a sample index for more efficient sampling and processing. Further, in embodiments of the present disclosure, the sampling frequency is a frequency lower than the RF frequency.

[0044] As used herein, a synchronized ADC sampling clock means a sampling clock that is synchronized with the RF clock used to generate the RF source signal, and the two clocks may have different clock frequencies. In other words, while the ADC sampling clock is locked to the RF clock, both clocks operate at their respective frequencies. In one embodiment, the frequency control devices 92, 94 can be implemented as phase-locked loops that generate the sampling clock and the RF clock from the master clock CLK0.

[0045] In some embodiments, the master clock CLK0 can also be shared with an external system 96, such as the impedance matching network 4 of FIG. 1, to enable the external system to synchronize with the same master clock.

[0046] FIG. 5 shows a pulse-modulated RF signal and its digital sampling in an embodiment of the present disclosure. Referring to FIG. 5, the RF signal (curve 112) is a pulse-modulated RF signal that includes an on period during which the RF signal is provided at a predetermined RF frequency and an off period during which the RF signal is not provided. The ADC digitizes the pulse-modulated RF signal and generates digital samples in response to a sampling clock indicated by curve 114. Since the sampling clock is synchronized with the RF clock, each digital sample can be indexed, and the position of each digital sample relative to the RF pulse can be determined.

[0047] In this embodiment, ADC sampling uses a 4-point FFT, and four samples are used to measure the analog signal in each sampling period, and each sample provides the same amount of phase shift. Thus, sample indices 0, 1, 2, and 3 represent the four samples acquired within one conversion. In some embodiments, index generator 84 (FIG. 2) generates sample indices 0, 1, 2, or 3 for each sampling pulse. Index generator 84 also acquires a pulse modulation signal that provides the envelope of the pulse-modulated RF signal. Thus, index generator 84 can associate each sampling pulse with the on or off period of the pulse-modulated RF signal. Configured in this way, the gate accumulation block can select digital samples related to the RF samples only during the on period.

[0048] In the embodiment shown in FIG. 5, in this embodiment, the gate accumulation block is configured to select digital samples using the set of indices 0-1-2-3 during the on period of the RF signal. Thus, as shown by curve 116, the gate accumulation block selects digital samples related to indices 0-1-2-3, 0-1-2-3, etc. during the on period of the RF signal.

[0049] In other embodiments, the gate accumulation block can be configured to select digital samples using other index orders or other sets of indexes. FIG. 6 shows a pulse - modulated RF signal and its digital sampling in an embodiment of the present disclosure. Referring to FIG. 6, the gate accumulation block uses a set of indexes 2 - 3 - 0 - 1 within the on - period (curve 122) of the RF signal of the first and second RF signal pulses, as shown by curve 126, and uses a set of indexes 3 - 0 - 1 - 2 (curve 124) of the third RF signal pulse to select digital samples. When using the index order 2 - 3 - 0 - 1, there are two index shifts (from 0), and the signal processing path adds phase offset values corresponding to the two index shifts. When using the index order 3 - 0 - 1 - 2, there are three index shifts (from 0), and the signal processing path adds phase offset values corresponding to the three index shifts.

[0050] More specifically, the ALC circuit of the present disclosure can determine the set of digital samples to use according to the width of the pulse - modulated RF signal. When the width of the RF signal on - period is long, the ALC circuit can select pulse signals in any order, such as 0 - 1 - 2 - 3 or 2 - 3 - 0 - 1, and can capture sufficient digital samples. However, when the width of the RF signal on - period is short, the ALC circuit has the flexibility to select an appropriate order of sample indexes to use to maximize the digital samples captured.

[0051] The use of a sample index to select digital samples for processing is particularly advantageous in a pulse - modulated RF signal. This is because pulse - modulated RF signals often contain overshoots and undershoots during the transitions between on - periods and off - periods. The gate accumulation block in the ALC circuit of the present disclosure can be configured to not select initial digital samples just when the RF signal is turned on, but instead wait to select digital samples when the RF signal is more stable. Further, the gate accumulation block can be configured to not select digital samples at the end of the on - period when the RF signal is about to be turned off.

[0052] FIG. 7 is a schematic diagram of an RF generator incorporating an automatic level control (ALC) circuit in an embodiment of the present disclosure. Similar elements in FIGS. 2 and 7 are given similar reference numerals for simplicity of explanation. Referring to FIG. 7, the RF generator 200 includes an RF circuit 20 and an automatic level control (ALC) circuit 250. The ALC circuit 250 includes a signal processing path 285 configured to obtain digital samples from measurements of forward and reflected RF signals and to generate an error signal (node 75) for a modulation control device 78 within the ALC loop. In this embodiment, the signal processing path 285 includes a gate accumulation block 258 for selecting digital samples from each of the sampled forward and reflected RF signals. The signal processing path 285 further includes a signal processor 263 for processing the digital samples. In this example, the signal processor 263 includes a digital filter and a processor or logic circuit for calculating a measured signal level value from the digital samples. The measured signal level value is used to generate an error signal for the modulation control device 78 for power level control.

[0053] Furthermore, the signal processing path 285 in the ALC circuit 250 of the present embodiment further includes an analog attenuation circuit 286 that generates an analog signal level value during the off period of the pulse-modulated RF signal. In particular, during the on period of the pulse-modulated RF signal when the ADCs 52, 54 sample the RF signal, the signal processor 263 generates a measured signal level value that passes through the analog attenuation circuit 286 and is provided to the error processor 74. However, during the off period of the pulse-modulated RF signal, the ADCs 52, 54 do not have an RF signal to sample, and the signal processor 263 may not need to generate an output with a meaningful value. In this case, the error processor 74 is placed in an undesirable state and may result in an out-of-range error signal. When the RF signal returns to on again, the error processor may have a large error to correct, resulting in a longer settling time and unstable output power for the RF signal.

[0054] In an embodiment of the present disclosure, the analog attenuation block 286 estimates or simulates the RF signal (or the transfer function of the analog / RF signal path within the ALC loop) during the off period of the pulse-modulated RF signal. In particular, the analog attenuation block 286 generates an estimated signal level value during the off period of the pulse-modulated RF signal and provides the estimated signal level value to the error processor 74 so that the error processor 74 can generate an error signal that is not far out of range and is closer to the expected value. In this way, when the pulse-modulated RF signal enters the next on period, the ALC loop can quickly settle to the error signal required to control the signal level or power of the RF signal.

[0055] In one embodiment, the analog attenuation block 286 uses a pre-measured transfer function of the control signal to the power amplifier to generate the estimated signal level value. That is, the estimated signal level value describes the relationship between the control signal generated by the modulation control device and the change of the power amplifier. The analog attenuation block 286 obtains the previous error signal feedback and determines the estimated or simulated signal level value to be used when the pulsed RF signal is turned off based on the transfer function.

[0056] In this way, the ALC loop operates as if there were a sampled RF signal. The error signal can be set to approach the expected value so that when the RF signal is turned on, the error signal and the ALC loop do not receive large signal swings. In some embodiments, the analog attenuation block 286 can be implemented as logic circuitry or as firmware within a processor. In this way, even when the pulse-modulated RF signal is in the off period without an RF signal, the signal processing path provides an estimated or simulated signal level value to provide an appropriate error signal to the ALC loop and generate a control signal for the RF circuit. The control loop can operate efficiently without large signal swings when the RF signal is turned back on during the on period.

[0057] FIG. 8 is a schematic diagram of an RF generator incorporating an automatic level control (ALC) circuit for a multi-level RF signal in an embodiment of the present disclosure. Similar elements in FIGS. 2, 3, and 8 are given similar reference numerals for simplicity of explanation. In particular, FIG. 8 shows an embodiment of an ALC circuit for a multi-level RF signal having two signal levels. Referring to FIG. 8, when the RF signal has two signal levels (level #0 and level #1), the ALC circuit 350 includes two signal processing paths (level #0 path 385-0 and level #1 path 385-1). Each signal processing path 385-0, 385-1 acquires digital samples of the forward and reflected RF signals from the ADCs 52, 54. Each signal processing path 385-0, 385-1 selects digital samples related to their respective signal levels for processing. For example, the index generator 384 acquires a pulse modulation signal from the pulse and level control circuit 82 and provides a sample index and a level index to the gate accumulation blocks 358-0 and 358-1. The level index indicates whether the digital samples belong to signal level 0 or signal level 1 so that each signal processing path can process accordingly.

[0058] Each signal processing path 385-0, 385-1 includes a gate accumulation block 358, a signal processor 363, an analog attenuation block 386, and an error processor 374. The signal processing path 385-0 generates an error signal ER0 indicating the difference between the measured or estimated signal level value and the reference signal level for signal level #0. The signal processing path 385-1 generates an error signal ER1 indicating the difference between the measured or estimated signal level value and the reference signal level for signal level #1. The data selector 76 selects one of the error signals ER0 and ER1 for the modulation control device 78. The data selector 76 selects an appropriate error signal by obtaining a level index from the index generator 384. The modulation control device 78 generates a control signal for controlling the signal modulator 26 in the RF circuit to adjust the RF source signal to a desired controlled signal level.

[0059] In some applications, the ALC circuit may be configured to apply level control only to one signal level. For example, the ALC circuit may be configured to control only signal level #1. In this case, the data selector 76 can be configured to select only the error signal ER1, and the ALC circuit controls the signal level only during the on period of the RF signal having signal level #1. For example, when the pulse-modulated RF signal has a long pulse width, the ALC circuit 250 may be configured to control both signal levels. However, when the pulse-modulated RF signal has a short pulse width, the ALC circuit 250 may be configured to control only one of the signal levels to ensure a faster response.

[0060] FIG. 9 shows a multi-level pulse-modulated RF signal and its digital sampling in an embodiment of the present disclosure. Referring to FIG. 9, the multi-level RF signal (curve 132) is a pulse-modulated RF signal that includes an on period during which the RF signal is provided at a predetermined RF frequency and an off period during which the RF signal is not provided. The RF signal also includes a first signal level (level #0) and a second signal level (level #1). For example, the first and third pulses are at level #0, and the second pulse is at level #1.

[0061] The ADC digitizes the pulse-modulated RF signal and generates digital samples in response to a sampling clock indicated by curve 134. In this embodiment, the ADC sampling uses a 4-point FFT, and the four samples are used to measure the analog signal in each sampling period, and each sample provides the same amount of phase shift. Thus, sample indices 0, 1, 2, and 3 indicate the four samples acquired for one conversion. In some embodiments, an index generator 384 (FIG. 8) generates sample indices 0, 1, 2, or 3 for each sampling pulse. The index generator 384 further generates a level index (curve 136) indicating the signal level of the RF signal. In this embodiment, only 1 bit is required for the level index to indicate the two signal levels.

[0062] The index generator 384 acquires a pulse-modulated signal that provides the envelope of the pulse-modulated RF signal and the signal level of each pulse. Thus, the index generator 384 can associate each sampling pulse not only with the on or off period of the pulse-modulated RF signal but also with the signal level of the RF signal. Configured in this way, the gate accumulation block can select digital samples associated with the RF samples during the on period and also for a specific signal level - level #0 or level #1.

[0063] In the embodiment shown in FIG. 9, the gate accumulation block is configured to select digital samples using an index order that maximizes the number of digital samples captured during each on-period. In this example, as shown by curve 138, the gate accumulation block uses the index order 2-3-0-1 during the on-periods of the RF signals of the first and second RF signal pulses, and the index order 3-0-1-2 (curve 134) of the third RF signal pulse to select digital samples. FIG. 9 further shows the target signal level of the RF signal (curve 140) that the ALC circuit should adjust.

[0064] In the above-described embodiment, the RF circuit of the RF generator generates an RF source signal using an oscillator, and uses a signal modulator to modulate the RF source signal in response to a control signal to generate a desired RF signal. In this case, a DAC is used to convert the digital control signal generated by the modulation control device into an analog control signal to drive the signal modulator. In an alternative embodiment of the present disclosure, the RF circuit can be implemented using a digital signal generator, and the ALC circuit can control the RF circuit using a digital control signal.

[0065] FIG. 10 is a schematic diagram of an RF generator incorporating an automatic level control (ALC) circuit in an alternative embodiment of the present disclosure. Referring to FIG. 10, the RF generator 400 includes an RF circuit 420 and an automatic level control (ALC) circuit 50. In this embodiment, the automatic level control circuit 50 is implemented in the same manner as the ALC circuit 50 in FIG. 2. The same components as those in FIGS. 2 and 10 are denoted by the same reference numerals, and their descriptions are omitted. The RF circuit 420 includes a direct digital synthesizer 422 that generates a desired RF signal in response to a control signal from a modulation control device 78 of the ALC circuit 50. In particular, the direct digital synthesizer 422 is a direct digital synthesizer having a modulation capability and can create or generate an output signal having an arbitrary desired frequency, amplitude, or phase from an internal reference frequency. In an embodiment of the present disclosure, the direct digital synthesizer 422 is configured to generate an RF signal having a desired signal amplitude and phase in response to a control signal from the modulation control device 78. Since the direct digital synthesizer 422 responds to a digital signal input, the ALC circuit 50 can provide a control signal from the modulation control device 78, and digital-to-analog conversion of the control signal is not required. The direct digital synthesizer 422 includes an internal DAC for generating an RF signal in response to a digital control signal from the modulation control device 78.

[0066] In still other embodiments, the RF circuit can be implemented using a phase-locked loop (PLL) signal source having a modulation capability. The PLL signal source operates in the same manner as the direct digital synthesizer and can provide an RF signal having a desired frequency, amplitude, or phase in response to a digital control signal. In other embodiments, the RF circuit can also be implemented using an FPGA or a processor having digital-to-analog conversion capabilities.

[0067] In an RF system, an RF generator and an impedance matching system are two independent systems and are usually not synchronized. To build an RF system using an RF generator, the impedance matching system needs to recover the clock used by the RF generator. In embodiments of the present disclosure, circuits and methods in an impedance matching system for recovering a clock signal from an RF generator are described.

[0068] FIG. 11 shows a clock generation circuit in an impedance matching system connected to an RF generator in an embodiment of the present disclosure. Referring to FIG. 11, an impedance matching system 504 is connected to an RF generator 502 within an RF system, obtains an RF signal 35, and provides a matched impedance RF signal 564 to a load 590. The impedance matching system 504 includes an input impedance sensor 542, an impedance matching network 560, and an output impedance sensor 562 that provides the matched impedance RF signal 564.

[0069] Since the impedance matching system 504 and the RF generator 502 are independent systems, the impedance matching system 504 needs to replicate a clock signal from the RF signal (node 35) of the RF generator 502. For example, the impedance matching system 504 may desire to synchronize to the master clock 90 (CLK0) of the RF generator. Alternatively, the impedance matching system 504 may synchronize to another clock signal within the clock chain of the RF generator 502, such as the clock source 22.

[0070] In practice, when the phase of the RF signal is determined only by the RF generator 502, the impedance matching system 504 can lock its reference clock (also called the slave clock) to the RF signal. However, the phase of the RF signal generated by the RF generator 502 varies according to both the settings of the matching system and the load of the matching system. According to an embodiment of the present disclosure, the input impedance sensor 542 of the impedance matching system 504 determines the impedance at the input node. When the input impedance sensor 542 reports a fixed phase or a predetermined phase condition, the impedance matching system 504 attempts to lock the slave clock 550. In this case, the slave clock 550 locks to the RF signal of the RF generator 502 whenever the impedance matching system 504 is in the same phase state.

[0071] In other embodiments of the present disclosure, the clock generation circuit is provided within the impedance matching system 504, enabling the impedance matching system to recover an RF clock (master clock) from the RF signal received on the transmission line. The clock generation circuit obtains the RF signal from the RF generator 502 and obtains load impedance information from the output impedance sensor 562. In particular, the clock generation circuit uses the RF signal only when the output impedance sensor 562 indicates that the load impedance is resistive. By synchronizing the clock of the impedance matching system only when the load is resistive, no phase shift occurs in the impedance matching system, and the slave clock signal generated in this way has high stability.

[0072] In one embodiment, the output impedance sensor 562 extracts and measures the impedance-matched RF signal 564 to obtain load impedance information. The clock generation circuit includes a processor 544 that obtains not only the input RF signal 35 from the RF generator 502 but also the load impedance information. The clock generator 550 generates a slave clock signal that drives the frequency generator 548 to generate a clock signal CLK3' (node 557). The frequency generator 548 can be implemented as a phase-locked loop. Finally, the clock generation circuit includes a phase frequency detector 546 that obtains the clock signal CLK3' and the input RF signal and measures the phase difference between the two signals. The phase frequency detector 546 aligns the phase of the clock signal CLK3' with the input RF signal to generate a clock signal CLK3 provided to the processor 544.

[0073] During operation, the processor 544 continues to count the number of pulses within a certain time. When the processor 544 compares and recognizes the difference between the clock signal of the RF signal and the clock signal CLK3, the processor 544 adjusts the frequency and / or phase of the slave clock 550 within the impedance matching system. For example, the processor 544 may manipulate the DAC output in the processor 544.

[0074] In embodiments of the present disclosure, the clock generation circuit examines the load impedance of load 590 measured by output impedance sensor 562 and detects when the input impedance of the load is resistive. When the input impedance of the load is resistive, the clock generation circuit then measures the phase difference between the locally generated clock CLK3 and the RF signal and generates a frequency and phase adjustment signal for slave clock 550. In this way, slave clock 550 of impedance matching network 504 can be synchronized to the same phase as the RF clock. When the load impedance of the load is not resistive, i.e., when the load impedance is capacitive or inductive, the clock generation circuit does not synchronize the clock signal because the non-resistive load impedance causes phase variations. In this way, a phase-synchronized local clock signal for the impedance matching system is generated from the RF signal.

[0075] In some embodiments, processor 544 determines when the load impedance is only a resistive load and initiates frequency and phase synchronization by triggering a phase synchronization signal connected to frequency generator 548. Frequency generator 548 can be a phase-locked loop and obtains a clock signal from slave clock 550. Frequency generator 548 is connected to phase frequency detector 546 and generates local clock CLK3. Phase frequency detector 546 measures the phase difference between internal clock CLK3' and the RF clock from the RF clock signal. Frequency and phase adjustment values are provided to slave clock 550 by processor 544 to adjust the clock frequency and phase to match the RF clock signal within the RF signal.

[0076] FIG. 12 shows a clock generation circuit in an impedance matching system connected to an RF generator in an alternative embodiment of the present disclosure. Referring to FIG. 12, an impedance matching system 604 is connected to an RF generator 602 within an RF system, obtains an RF signal 35, and provides impedance-matched RF signals 664a, 664b to a load 680. The impedance matching system 604 includes an input impedance sensor 642, an impedance matching network 660, and an output impedance sensor 662 that provides the impedance-matched RF signal 664. In the present embodiment, the impedance matching system 604 includes two output impedance sensors 1 and 2, namely 662a, 662b, to provide two output RF signals 664a, 664b respectively.

[0077] In the RF system of FIG. 12, the master clock or reference clock of the RF generator 602 is shared with the impedance matching system 6 04 Furthermore, the sample index generated by the RF generator 602 is also shared with the impedance matching system 6 04 By using the same clock and the same sample index, the impedance matching system 604 can process the sensor data within the matching system with higher efficiency. For example, the master clock 90 of the RF generator 602 may be shared with the impedance matching system 604 by connecting the master clock 90 to a phase-locked loop 646 or the like. The sample index generated by the index generation processor 610 is provided to the matching system processor 670.

[0078] More specifically, in response to the master clock 90 being shared by the RF generator 602, the phase-locked loop 646 drives the oscillator 650. The oscillator 650 provides an output clock signal to the clock generator 644, which, in this embodiment, generates sampling signals for the input impedance sensor 642 and the two output impedance sensors 662a, 662b. Using the same clock signal and the same sample index, the input impedance sensor 642 and the output impedance sensors 664a, 664b can operate at the same timing as the RF generator 602. In practice, there is a certain clock delay, but the delay can be compensated for.

[0079] Generally, the clock synchronization method of FIG. 12 is implemented by sharing a clock signal and index data between two independent systems, having a sample index for each sample, and performing signal processing based on the shared clock and the shared sample index data.

[0080] In an alternative embodiment, the clock synchronization between the RF generator 602 and the impedance matching system 604 can be performed in reverse. That is, the reference clock within the impedance matching system can be used as the master clock, and the RF generator can be synchronized with the reference clock of the impedance matching system. Further, the processor of the impedance matching system can generate a sample index and share it with the RF generator.

[0081] In the impedance matching system 604 of FIG. 12, the same clock (slave clock 650) is used for both the input impedance sensor and the output impedance sensor. Therefore, the input frequency and the output frequency of the impedance matching system are the same. In some cases, the impedance matching system may be implemented using different clock frequencies for the input impedance sensor and the output impedance sensor.

[0082] FIG. 13 shows a clock generation circuit in an impedance matching system connected to an RF generator in an alternative embodiment of the present disclosure. Similar elements in FIGS. 12 and 13 are given similar reference numerals and are not further described. Referring to FIG. 13, the impedance matching system 604 includes a first clock generator 1 (644) for generating a sampling signal 1 and a second clock generator 2 (645) for generating a sample signal 2. Both clock generators 644 and 645 generate sampling signals based on the slave clock 650. In some embodiments, clock generators 644 and 645 generate sampling signals having different frequencies. The impedance matching system 604 may apply different clock frequencies to different sensors within the system. For example, in the present embodiment, the sampling signal 1 is applied to the input impedance sensor 642, and the sampling signal 2 is applied to one or both of the output impedance sensors 662a, 662b.

[0083] In one example, it may be desirable to look at the harmonic frequencies of the RF signal in the output impedance sensor so that the matching parameters of the impedance matching network 660 can be adjusted. In this case, it is desirable for the output impedance sensor to look at results from a different frequency than the input impedance sensor.

[0084] In the embodiments shown in FIGS. 12 and 13, the clock signal and the index data are shared across two signal lines. In some embodiments, both the phase-modulated signal and the index data are shared on the same data line.

[0085] In this detailed description, various embodiments or examples of the present invention may be implemented in many ways, including a process, an apparatus, a system, a composition embodied on a non-transitory computer-readable storage medium, a computer program product, and / or a processor such as a hardware processor or a processor device configured to execute instructions stored on and / or provided by a memory connected to the processor, and / or a series of program instructions on a non-transitory computer-readable medium (e.g., a computer-readable storage medium or a computer network through which program instructions are sent via an optical communication link, an electronic communication link, or a wireless communication link). Generally, the order of steps of the disclosed process may be changed within the scope of the present invention. Unless otherwise specified, components such as a processor or a memory described as being configured to perform a task are implemented as general components temporarily configured to perform the task at a given time, or as specific components manufactured to perform the task. As used herein, the term "processor" means one or more devices, circuits, and / or processing cores configured to process data such as computer program instructions.

[0086] A detailed description of one or more embodiments of the present invention is provided above along with the accompanying drawings that illustrate the principles of the present invention. The present invention is described in relation to such embodiments, but the present invention is not limited to any particular embodiment. Many modifications and variations are possible within the scope of the present invention. The scope of the present invention is limited only by the claims, and the present invention encompasses numerous alternatives, modifications, and equivalents. For the purpose of providing a complete understanding of the present invention, many specific details are set forth in the specification. These details are provided for illustrative purposes and the present invention may be practiced in accordance with the claims without some or all of these specific details. To clarify, technical content known in the technical field related to the present invention is not described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims. The following items are the contents described in the claims at the time of international application. (Item 1) A radio wave generator, A radio frequency (RF) circuit comprising: an RF source that provides an RF signal having a first frequency derived from a first clock; and a signal modulator that generates a pulsed radio frequency (RF) signal having an on period during which the RF signal is provided to an output terminal and an off period during which the RF signal is not provided. An automatic level control circuit configured to sample the pulsed RF signal at the output terminal and generate a control signal for modulating the RF signal in the radio wave circuit. Comprising The automatic level control circuit A first analog-to-digital converter and a second analog-to-digital converter configured to sample a respective forward RF signal and a reflected RF signal at the output terminal at a sampling frequency, the sampling frequency being derived from a sampling clock synchronized with the first clock and lower than the first frequency of the RF signal, the first analog-to-digital converter and the second analog-to-digital converter generating respective digital samples of the forward RF signal and the reflected RF signal. A gate accumulation circuit configured to receive respective digital samples of the forward RF signal and the reflected RF signal and select digital samples based on a sample index that identifies the digital samples. A digital signal processor configured to process the selected digital samples to generate a measured signal level value. An error processor configured to compare the measured signal level value with a reference signal level and generate an error signal indicating the difference. A modulation control device configured to generate the control signal in response to the error signal and a pulse modulation signal, the pulse modulation signal indicating the on period and the off period of the pulsed RF signal, the control signal being connected to the modulator of the radio wave circuit to modulate the RF signal to generate the pulsed RF signal and control the signal level of the pulsed RF signal during the on period. A radio wave generator comprising. (Item 2) The sample index is related to the sampling frequency and identifies the digital sample as a first number of data points sampled within a predetermined conversion, the radio wave generator according to item 1. (Item 3) The gate accumulation circuit selects the digital samples of the forward RF signal and the reflected RF signal during the on period of the pulse RF signal based on the sample index, the radio wave generator according to item 2. (Item 4) The sample index identifies the digital sample as four data points sampled within a predetermined conversion, the radio wave generator according to item 2. (Item 5) The radio wave generator according to item 1 further comprises a digital-to-analog converter configured to convert the control signal into an analog signal and connect the analog signal for controlling the signal modulator of the radio wave circuit. (Item 6) The digital signal processor is a digital filter configured to process the selected digital samples and generate a first parameter value related to the forward RF signal and a second parameter value related to the reflected RF signal, wherein each of the first parameter value and the second parameter value indicates a level value and a phase value of the forward RF signal or the reflected RF signal respectively measured by the selected digital sample, the digital filter; The radio wave generator according to item 1 further comprises an impedance and level processor configured to process the first parameter value and the second parameter value to generate the measured signal level value. (Item 7) A simulation attenuation processor configured to generate an estimated signal level value and provide the estimated signal level value to the error processor during an off period when the digital sample of the RF signal is not selected by the gate accumulation circuit, wherein the estimated signal level value is provided to the error processor as the measured signal level, further comprising the simulation attenuation processor, The simulation attenuation processor generates the estimated signal level value based on the error signal and the parameters of the radio wave circuit, the radio wave generator according to item 1. (Item 8) The pulse RF signal includes a multi-level pulse RF signal having a first signal level during a first on-period and a second signal level during a second on-period, The radio wave generator according to item 1, wherein the first signal level is different from the second level. (Item 9) The sample index includes a first sample index for identifying the digital sample as the first number of data points and a second sample index for identifying the signal level of the pulse RF signal, The radio wave generator according to item 8, wherein the second sample index has a first logical value indicating the first signal level and a second logical value indicating the second signal level. (Item 10) The automatic level control circuit further A first signal processing path for processing a digital sample having the first signal level identified by the second sample index, A second signal processing path for processing a digital sample having the second signal level identified by the second sample index, wherein each of the first signal processing path and the second signal processing path includes the gate accumulation circuit, the digital signal processor, and the error processor, the first signal processing path generates a first error signal indicating a difference between the first signal level and a first reference signal level, and the second signal processing path generates a second error signal indicating a difference between the second signal level and a second reference signal level, the second signal processing path A data selector configured to select one of the first error signal and the second error signal and provide a selected error signal to the modulation control device, and in order to control the signal level of the pulse RF signal during the on-period of the pulse RF signal having a signal level related to the selected error signal, the modulation control device generates the control signal in response to the selected error signal, the data selector The radio wave generator according to item 9, comprising (Item 11) Each of the first signal processing path and the second signal processing path further A radio wave generator according to item 10, comprising a simulation attenuation processor configured to generate an estimated signal level value and provide the estimated signal level value to the error processor in each signal processing path during the off period when the digital samples of the RF signal are not selected by the gate accumulation circuit, wherein the estimated signal level value is provided to the error processor as the measured signal level, and the simulation attenuation processor generates the estimated signal level value based on each error signal and the parameters of the radio wave circuit. (Item 12) The radio wave generator according to item 1, further comprising an index generator configured to generate the sample index in response to the pulse modulation signal and the sampling frequency. (Item 13) The radio wave generator according to item 1, further comprising a first directional coupler and a second directional coupler connected to the output terminal to sample the respective forward RF signals and the reflected RF signals and provide the sampled signals to the first analog-to-digital converter and the second analog-to-digital converter. (Item 14) A method for controlling the signal level of a radio frequency (RF) signal, comprising: generating the RF signal of a first frequency derived from a first clock; generating a pulsed RF signal having an on period during which the RF signal is provided and an off period during which the RF signal is not provided; sampling the forward RF signal and the reflected RF signal at a sampling frequency to generate digital samples of the forward RF signal and the reflected RF signal related to the pulsed RF signal, wherein the sampling frequency is derived from a sampling clock synchronized with the first clock and lower than the first frequency of the RF signal; selecting the digital samples of the forward RF signal and the reflected RF signal based on a sample index for identifying the digital samples; processing the selected digital samples to generate a measured signal level value; determining an error signal indicating a difference between the measured signal level value and a reference signal level; Generating a control signal in response to the error signal and the pulse modulation signal, wherein the pulse modulation signal indicates the on period and the off period of the pulse RF signal, the generating; Modulating the RF signal to generate the pulse RF signal, and applying the control signal to control the signal level of the pulse RF signal during the on period. A method comprising: (Item 15) The method according to item 14, further comprising identifying the digital sample as a first number of data points sampled within a predetermined conversion, wherein the sample index is related to the sampling frequency. (Item 16) Selecting digital samples of the forward RF signal and the reflected RF signal based on a sample index for identifying the digital samples; The method according to item 14, comprising selecting digital samples of the forward RF signal and the reflected RF signal during the on period of the pulse RF signal based on the sample index. (Item 17) Generating an estimated signal level value and providing the estimated signal level value as the measured signal level value for determining the error signal, wherein the estimated signal level value is based on the error signal and a parameter related to generating the RF signal. The method according to item 14, further comprising the providing. (Item 18) The pulse RF signal comprises a multi-level pulse RF signal having a first signal level during a first on period and a second signal level during a second on period, wherein the first signal level is different from the second level, the sample index comprises a first sample index for identifying the digital sample as the first number of data points and a second sample index for identifying the signal level of the pulse RF signal, The method according to item 14, wherein the second sample index has a first logical value indicating the first signal level and a second logical value indicating the second signal level. (Item 19) Processing digital samples having the first signal level identified by the second sample index; Generating a first error signal indicating a difference between the first signal level and a first reference signal level; processing digital samples having the second signal level identified by the second sample index; generating a second error signal indicative of a difference between the second signal level and a second reference signal level; selecting, as the error signal, one of the first error signal and the second error signal for generating the control signal; generating the control signal in response to the selected error signal to control the signal level of the pulsed RF signal during an on period of the pulsed RF signal having a signal level associated with the signal level of the selected error signal. The method according to item 18 further comprises: (Item 20) The method according to item 14 further comprising generating the sample index in response to the pulse modulation signal and the sampling frequency. (Item 21) A clock generation circuit for generating a local clock synchronized with a radio frequency (RF) signal of a first frequency derived from a first clock, the clock generation circuit comprising: an impedance measurement circuit configured to measure a load impedance value associated with a load to which the RF signal is applied; a processor that acquires the RF signal and the local clock and receives a signal indicating the load impedance value, the processor generating a phase synchronization signal in response to the load impedance value and further generating a frequency and phase adjustment signal; an oscillator that generates a slave clock in response to the frequency and phase adjustment signal; a frequency generator that acquires the slave clock and generates a second clock in response to the slave clock and the phase synchronization signal; a phase frequency detector that measures a phase difference between the RF signal and the second clock and generates the local clock in response to the phase difference; comprising The processor is configured to determine a time period when the load impedance value indicates a resistive load, and generate the phase synchronization signal to synchronize the local clock with the first clock of the RF signal. A clock generation circuit. (Item 22) The clock generation circuit according to item 21, wherein the processor is configured to disable synchronization of the local clock during a time period when the signal indicating the load impedance indicates a capacitive or inductive load. (Item 23) The clock generation circuit according to item 21, wherein the frequency generator includes a phase-locked loop.

Claims

1. A radio wave generator, A radio frequency (RF) circuit, comprising a first clock, an RF source that provides an RF signal of a first frequency derived from the first clock, and a signal modulator that generates a pulsed radio frequency (RF) signal having an on period during which the RF signal is provided to an output terminal and an off period during which the RF signal is not provided; An automatic level control circuit configured to sample the pulsed RF signal at the output terminal and generate a control signal for modulating the RF signal in the radio wave circuit; Comprising, The automatic level control circuit, A sampling clock synchronized with the first clock, A first analog-to-digital converter and a second analog-to-digital converter configured to sample a respective forward RF signal and a reflected RF signal at the output terminal at a sampling frequency, the sampling frequency being derived from the sampling clock and lower than the first frequency of the RF signal, the first analog-to-digital converter and the second analog-to-digital converter; A gate accumulation circuit configured to receive respective digital samples of the forward RF signal and the reflected RF signal and select a digital sample based on a sample index that identifies the digital sample; A digital signal processor configured to process the selected digital sample to generate a measured signal level value; An error processor configured to compare the measured signal level value with a reference signal level and generate an error signal indicating the difference; A modulation control device configured to generate the control signal in response to the error signal and a pulse modulation signal, the pulse modulation signal indicating the on period and the off period of the pulsed RF signal, modulating the RF signal to generate the pulsed RF signal, and connecting the control signal to the signal modulator of the radio wave circuit to control the signal level of the pulsed RF signal during the on period; A radio wave generator comprising.

2. The radio wave generator according to claim 1, wherein the sample index is related to the sampling frequency and identifies the digital sample as a first number of data points sampled within a predetermined conversion.

3. The radio wave generator according to claim 2, wherein the gate accumulation circuit selects the digital samples of the forward RF signal and the reflected RF signal during the on period of the pulse RF signal based on the sample index.

4. The radio wave generator according to claim 2, wherein the sample index identifies the digital sample as four data points sampled within a predetermined conversion.

5. The radio wave generator according to claim 1, further comprising a digital-to-analog converter configured to convert the control signal into an analog signal and connect the analog signal for controlling the signal modulator of the radio wave circuit.

6. The digital signal processor is a digital filter configured to process the selected digital samples and generate a first parameter value related to the forward RF signal and a second parameter value related to the reflected RF signal, wherein each of the first parameter value and the second parameter value indicates a level value and a phase value of the forward RF signal or the reflected RF signal measured by the selected digital sample, the digital filter; an impedance and level processor configured to process the first parameter value and the second parameter value to generate the measured signal level value, the radio wave generator according to claim 1.

7. An analog attenuation processor configured to generate an estimated signal level value during an off period when the digital sample of the RF signal is not selected by the gate accumulation circuit and provide the estimated signal level value to the error processor, wherein the estimated signal level value is provided to the error processor as the measured signal level value, further comprising the analog attenuation processor, The radio wave generator according to claim 1, wherein the analog attenuation processor generates the estimated signal level value based on the error signal and parameters of the radio wave circuit.

8. The pulse RF signal includes a multi-level pulse RF signal having a first signal level during a first on-period and a second signal level during a second on-period. The radio wave generator according to claim 1, wherein the first signal level is different from the second signal level.

9. The sample index includes a first sample index for identifying the digital sample as a first number of data points and a second sample index for identifying the signal level of the pulse RF signal. The radio wave generator according to claim 8, wherein the second sample index has a first logical value indicating the first signal level and a second logical value indicating the second signal level.

10. The automatic level control circuit further includes a first signal processing path for processing a digital sample having the first signal level identified by the second sample index, a second signal processing path for processing a digital sample having the second signal level identified by the second sample index, wherein each of the first signal processing path and the second signal processing path includes the gate accumulation circuit, the digital signal processor, and the error processor. The first signal processing path generates a first error signal indicating a difference between the first signal level and a first reference signal level, and the second signal processing path generates a second error signal indicating a difference between the second signal level and a second reference signal level. The second signal processing path a data selector configured to select one of the first error signal and the second error signal and provide a selected error signal to the modulation control device. During the on-period of the pulse RF signal having a signal level related to the selected error signal, the modulation control device generates the control signal in response to the selected error signal. The data selector The radio wave generator according to claim 9, comprising

11. Each of the first signal processing path and the second signal processing path further includes An analog attenuation processor configured to generate an estimated signal level value during the off period when the digital samples of the RF signal are not selected by the gate accumulation circuit and to provide the estimated signal level value to the error processor within each signal processing path, wherein the estimated signal level value is provided to the error processor as the measured signal level value, and the analog attenuation processor generates the estimated signal level value based on each error signal and parameters of the radio wave circuit. The radio wave generator according to claim 10, comprising the analog attenuation processor.

12. The radio wave generator according to claim 1, further comprising an index generator configured to generate the sample index in response to the pulse modulation signal and the sampling frequency.

13. The radio wave generator according to claim 1, further comprising a first directional coupler and a second directional coupler connected to the output terminal to sample the respective forward RF signal and the reflected RF signal and provide the sampled signals to the first analog-to-digital converter and the second analog-to-digital converter.

14. A method for controlling the signal level of a radio frequency (RF) signal, comprising: generating the RF signal at a first frequency derived from a first clock; generating a pulsed RF signal having an on period during which the RF signal is provided and an off period during which the RF signal is not provided; generating a sampling clock synchronized with the first clock and having a sampling frequency lower than the first frequency of the RF signal; sampling the forward RF signal and the reflected RF signal related to the pulsed RF signal at the sampling frequency to generate digital samples of the forward RF signal and the reflected RF signal; selecting digital samples of the forward RF signal and the reflected RF signal based on a sample index identifying the digital samples; processing the selected digital samples to generate a measured signal level value; determining an error signal indicating a difference between the measured signal level value and a reference signal level; Generating a control signal in response to the error signal and the pulse modulation signal, wherein the pulse modulation signal indicates the on period and the off period of the pulse RF signal, and said generating; Modulating the RF signal to generate the pulse RF signal, and applying the control signal to control the signal level of the pulse RF signal during the on period. A method comprising:

15. The method of claim 14, further comprising identifying the digital sample as a first number of data points sampled within a predetermined conversion, wherein the sample index is related to the sampling frequency.

16. Selecting digital samples of the forward RF signal and the reflected RF signal based on a sample index that identifies the digital samples, The method of claim 14, comprising selecting digital samples of the forward RF signal and the reflected RF signal during the on period of the pulse RF signal based on the sample index.

17. Generating an estimated signal level value during the off period when the digital sample of the RF signal is not selected by the gate accumulation circuit, and providing the estimated signal level value as the measured signal level value for determining the error signal, wherein the estimated signal level value is based on the error signal and a parameter related to generating the RF signal. The method of claim 14, further comprising said providing.

18. The pulse RF signal comprises a multi-level pulse RF signal having a first signal level during a first on period and a second signal level during a second on period, The first signal level is different from the second signal level, The sample index comprises a first sample index that identifies the digital sample as a first number of data points and a second sample index that identifies the signal level of the pulse RF signal, The method of claim 14, wherein the second sample index has a first logical value indicating the first signal level and a second logical value indicating the second signal level.

19. Processing the digital sample having the first signal level identified by the second sample index; generating a first error signal indicative of a difference between the first signal level and a first reference signal level; processing a digital sample having the second signal level identified by the second sample index; generating a second error signal indicative of a difference between the second signal level and a second reference signal level; selecting, as the error signal, one of the first error signal and the second error signal for generating the control signal; generating the control signal in response to the selected error signal to control the signal level of the pulsed RF signal during an on period of the pulsed RF signal having a signal level associated with the selected error signal. The method according to claim 18, further comprising: **Claim 20** The method according to claim 14, further comprising generating the sample index in response to the pulse modulation signal and the sampling frequency.

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