MRAM structure with a T-shaped bottom electrode to overcome the galvanic effect

Abstract

A memory structure is provided that avoids high resistance due to galvanic effects. This high resistance is reduced and / or eliminated by providing a uniform (i.e., single-piece) T-shaped bottom electrode structure. The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a flat top surface that interfaces with the MTJ pillar.

Description

Technical Field

[0001] This application relates to a memory structure and a method of forming the memory structure. More particularly, this application relates to a magnetoresistive random access memory (MRAM) structure including a T-shaped bottom electrode structure that avoids high resistance due to the galvanic effect.

Background Art

[0002] MRAM is a viable memory option for stand-alone and embedded applications such as, for example, the Internet of Things (IoT), automotive, or artificial intelligence (AI). MRAM is a non-volatile random access memory technology in which data is stored by magnetic memory elements. The magnetic memory elements are typically formed from two ferromagnetic plates separated by a thin dielectric layer, i.e., a tunnel barrier layer, and these two ferromagnetic plates can each hold a magnetization. One of these two plates is a permanent magnet set to a particular polarity, and the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. This permanent magnet can be referred to as a magnetic pinned layer or a magnetic reference layer, and the magnet whose magnetization is changed to match the magnetization of the external magnetic field can be referred to as a magnetic free layer. The magnetic pinned layer, the tunnel barrier layer, and the magnetic free layer together provide a multilayered magnetic tunnel junction (MTJ) pillar.

[0003] The MTJ pillar is formed on the bottom electrode. The size of the bottom electrode is highly related to the array yield loss due to partial metal short - circuit, especially when the MTJ size is reduced to increase the switching efficiency. Usually, a small - sized bottom electrode is desirable.

[0004] Furthermore, conventional bottom electrodes in an MRAM structure are made of metals such as TiN or Cu, which are prone to the so - called galvanic effect during the chemical - mechanical planarization process used to form the bottom electrode. The galvanic effect is observed when the bottom electrode is formed on a conductive structure connected to a complementary metal - oxide - semiconductor (CMOS) device, and it should be noted that no galvanic effect is observed for a bottom electrode formed on a conductive structure separated from the CMOS device. The galvanic effect can lead to undesirable oxidation or corrosion or both of the bottom electrode, which can result in high resistance and high array yield loss. Therefore, there is a need to provide a memory structure (i.e., an MRAM structure) in which the galvanic effect is reduced or eliminated.

[0005] Therefore, in the art, it is required to solve the above - mentioned problems.

Summary of the Invention

[0006] According to a first aspect, the present invention provides a memory structure, which includes a T - shaped bottom - electrode structure of uniform construction placed on the surface of a conductive structure (hereinafter referred to as a complementary metal - oxide - semiconductor (CMOS) device - connected conductive structure) connected to a complementary metal - oxide - semiconductor (CMOS) device and embedded in a first interconnect dielectric material layer, a multi - layer magnetic tunnel junction (MTJ) pillar placed on the T - shaped bottom - electrode structure, and a top - electrode structure placed on the MTJ pillar.

[0007] According to another aspect, the present invention provides a structure, which includes a first memory cell having a first T-shaped bottom electrode structure with a uniform structure disposed on the surface of a complementary metal oxide semiconductor (CMOS) device connection conductive structure embedded in a first interconnect dielectric material layer, a first multilayer magnetic tunnel junction (MTJ) pillar disposed on the first T-shaped bottom electrode structure, and a first top electrode structure disposed on the first MTJ pillar, and a second memory cell disposed adjacent to the first memory cell. The second memory cell includes a second T-shaped bottom electrode structure with a uniform structure disposed on the surface of an isolated conductive structure embedded in the first interconnect dielectric material layer, a second MTJ pillar disposed on the second T-shaped bottom electrode structure, and a second top electrode structure disposed on the second MTJ pillar.

[0008] According to another aspect, the present invention provides a method of forming a memory structure, the method including forming a second interconnect dielectric material layer on an interconnect level including at least one CMOS device connection conductive structure embedded in a first interconnect dielectric material layer; forming at least one opening in the second interconnect dielectric material layer to physically expose the surface of the at least one CMOS device connection conductive structure; forming a bottom electrode layer containing metal (hereinafter referred to as the bottom electrode metal-containing layer) on the second interconnect dielectric material layer and within the at least one opening; performing first and second planarizations of the bottom electrode metal-containing layer to provide a twice-planarized bottom electrode metal-containing layer; forming a multilayer magnetic tunnel junction (MTJ) material stack on the twice-planarized bottom electrode metal-containing layer; forming a top electrode layer containing metal (hereinafter referred to as the top electrode metal-containing layer) on the MTJ material stack; and patterning the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer to provide a top electrode structure, an MTJ pillar, and a T-shaped bottom electrode structure, respectively.

[0009] A memory structure is provided that avoids the high resistance resulting from the galvanic effect. This high resistance is reduced or eliminated or both by providing a T-shaped bottom electrode structure of a uniform structure (i.e., a single piece). This T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a flat topmost surface that forms an interface with the MTJ pillar.

[0010] In one aspect of the present application, a memory structure is provided. In one embodiment, the memory structure includes a T-shaped bottom electrode structure of a uniform structure placed on the surface of a complementary metal oxide semiconductor (CMOS) device connection conductive structure embedded in a first interconnect dielectric material layer. A multilayer magnetic tunnel junction (MTJ) pillar is placed on this T-shaped bottom electrode structure, and a top electrode structure is placed on this MTJ pillar.

[0011] The MTJ pillar that can be used in the present application can be a bottom-pinned MTJ material structure or a top-pinned MTJ material structure. The T-shaped bottom electrode structure of the present application includes a base portion and a shelf portion, and the width of the shelf portion is larger than the width of the base portion. In some embodiments, the base portion of the T-shaped bottom electrode structure can be surrounded laterally by a second interconnect dielectric material layer, and this second interconnect dielectric material layer is placed on top of the first interconnect dielectric material layer. In some embodiments, a diffusion barrier liner can be placed directly under the shelf portion of the T-shaped bottom electrode structure, and this diffusion barrier liner covers the side walls and the bottom wall of the base portion of the T-shaped bottom electrode structure.

[0012] In some embodiments, an encapsulation liner and a third interconnect dielectric material layer can be placed adjacent to the shelf portion of the T-shaped bottom electrode structure, the MTJ pillar, and the side of the top electrode structure. In other embodiments, a bit line contact can be placed on the third interconnect dielectric material layer, and this bit line contact contacts the surface of the top electrode structure.

[0013] In another aspect of the present application, a structure is provided. In one embodiment, the structure includes a first memory cell including a first T-shaped bottom electrode structure of uniform structure placed on the surface of a complementary metal oxide semiconductor (CMOS) device connection conductive structure embedded in a first interconnect dielectric material layer, a first multilayer magnetic tunnel junction (MTJ) pillar placed on the first T-shaped bottom electrode structure, and a first top electrode structure placed on the first MTJ pillar. The structure further includes a second memory cell placed adjacent to the first memory cell. The second memory cell includes a second T-shaped bottom electrode structure of uniform structure placed on the surface of an isolated conductive structure embedded in the first interconnect dielectric material layer, a second MTJ pillar placed on the second T-shaped bottom electrode structure, and a second top electrode structure placed on the second MTJ pillar.

[0014] The first MTJ pillar and the second MTJ pillar can be a bottom-fixed MTJ material structure or a top-fixed MTJ material structure. In some embodiments, the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure include a base portion and a shelf portion, and the width of the shelf portion is greater than the width of the base portion. In some embodiments, the base portions of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure can be surrounded laterally by a second interconnect dielectric material layer, and this second interconnect dielectric material layer is placed on top of the first interconnect dielectric material layer. In other embodiments, a diffusion barrier liner can be placed directly under the shelf portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure, and this diffusion barrier liner covers the side walls and the bottom wall of the base portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure.

[0015] In some embodiments, a encapsulation liner and a third interconnect dielectric material layer can be placed next to the shelf portion of each of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure, each of the first MTJ pillar and the second MTJ pillar, and each of the first top electrode structure and the second top electrode structure. In other embodiments, a bit line contact can be placed on the third interconnect dielectric material layer, and this bit line contact contacts the surfaces of the first top electrode structure and the second top electrode structure.

[0016] In another aspect of the present application, a method of forming a memory structure is provided. In one embodiment, the method includes forming a second interconnection dielectric material layer over an interconnection level that includes at least one CMOS device connection conductive structure embedded in a first interconnection dielectric material layer. Next, at least one opening is formed in the second interconnection dielectric material layer to physically expose the surface of the at least one CMOS device connection conductive structure. Next, a bottom electrode metal-containing layer is formed over the second interconnection dielectric material layer and within the at least one opening. Next, first and second planarization steps are performed over the bottom electrode metal-containing layer to provide a twice-planarized bottom electrode metal-containing layer. A multilayer magnetic tunnel junction (MTJ) material stack is formed over the twice-planarized bottom electrode metal-containing layer, and then a top electrode metal-containing layer is formed over the MTJ material stack. Next, the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer are patterned to provide a top electrode structure, an MTJ pillar, and a T-shaped bottom electrode structure, respectively.

[0017] In some embodiments, the MTJ material stack includes a bottom-fixed MTJ material stack or a top-fixed MTJ material stack. In some embodiments, the T-shaped bottom electrode structure has a unitary structure and includes a base portion and a shelf portion, and the width of the shelf portion is greater than the width of the base portion. In some embodiments, after the patterning step, a capping liner, a third interconnection dielectric material layer, and a bit line contact can be formed. In some embodiments, by patterning Second removing also the upper portion of the interconnection dielectric material layer of Second a concave surface can be provided in the dielectric material layer of

[0018] In some embodiments, before forming the bottom electrode metal-containing layer, a diffusion barrier material layer is formed on the second interconnection dielectric material layer and covers the inside of at least one opening. In some embodiments, patterning further provides a diffusion barrier liner disposed under the T-shaped bottom electrode structure. In some embodiments, after the patterning step, a capping liner, a third interconnection dielectric material layer, and bit line contacts are formed.

[0019] Next, the present invention will be described by way of example only with respect to the preferred embodiments shown in the following figures.

Brief Description of the Drawings

[0020]

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DETAILED DESCRIPTION OF THE INVENTION

[0021] Next, the present application will be described in more detail by referring to the following discussions and drawings accompanying the present application. It should be noted that the drawings of the present application are provided for illustrative purposes only and are not drawn at a certain magnification. It should also be noted that the same elements and corresponding elements are referred to by the same reference numerals.

[0022] In the following description, to facilitate understanding of various embodiments of the present application, numerous specific details such as specific structures, components, materials, dimensions, processing steps, and technologies are shown. However, those skilled in the art will understand that the various embodiments of the present application can be implemented even without these specific details. Also, to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0023] When one element such as a layer, region, or substrate is described as being "on" or "above" another element, it is understood that this one element may be directly on this other element or there may be intervening elements. In contrast, when one element is described as being "directly on" or "directly above" another element, there are no intervening elements. When one element is described as being "under" or "below" another element, it is understood that this one element may be directly under or below this other element or there may be intervening elements. In contrast, when one element is described as being "directly under" or "directly below" another element, there are no intervening elements.

[0024] Note that the drawings of the present application show a memory device region in which a memory device such as an MRAM device is formed. There may also be a non-memory device region placed adjacent to the memory device region shown in the drawings of the present application.

[0025] First, referring to FIG. 1, an exemplary structure that can be used in one embodiment of the present application is shown. The exemplary structure of FIG. 1 includes a second interconnect dielectric material layer 18 placed on interconnect level L n where n is an integer starting from 1. Interconnect level L n includes at least one CMOS device connection conductive structure 16L, 16R embedded in the first interconnect dielectric material layer 14. Interconnect level Ln may further include at least one isolated conductive structure 16 embedded in the first interconnect dielectric material layer 14.

[0026] As further shown in FIG. 1, at interconnect level L n there is a metal level L n-1 placed. In some embodiments, and when n = 1, the metal level L n-1 is a middle-of-the-line (MOL) level. In other embodiments, and when n = 2, 3, 4, etc., the metal level L n-1 is a lower interconnect level disposed below the interconnect level L n . In any embodiment, the metal level L n-1 includes a dielectric material layer 10 in which at least one metal level conductive structure 12 is embedded, and the metal level conductive structure 12 is directly or indirectly connected to the underlying CMOS device (which is also not shown) present at the front-end-of-the-line (FEOL) level (not shown).

[0027] When n = 1, the metal level L n-1The dielectric material layer 10 can be made of, for example, a MOL dielectric material such as silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or a combination thereof. The term "low-k" used throughout this application means a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants shown in this specification are measured in a vacuum). Further, in such an embodiment (i.e., when n is 1), at least one metal level conductive structure 12 is a contact structure including a contact metal or a contact metal alloy such as tungsten (W), cobalt (Co), platinum (Pt), nickel (Ni), or an alloy thereof.

[0028] When n is greater than 1, the metal level L n-1 The dielectric material layer 10 can be made of, for example, an interconnect dielectric material such as silicon dioxide, silsesquioxane, a C-doped oxide containing Si, C, O, and H atoms (i.e., an organosilicate), a thermosetting polyarylene ether, or a multilayer thereof. In this application, the term "polyarylene" is used to mean an aryl moiety or an inertly substituted aryl moiety bonded together by a bond, a fused ring, or an inert linking group, and the inert linking group is, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl, etc. Further, in such an embodiment (i.e., when n is greater than 1), at least one metal level conductive structure 12 is made of a conductive metal or a conductive metal alloy. Examples of conductive materials that can be used in this application include copper (Cu), aluminum (Al), or tungsten (W), while an example of a conductive metal alloy is a Cu-Al alloy.

[0029] Interconnection level L n The first interconnect dielectric material layer 14 of n can consist of one of the interconnect dielectric materials described above with respect to the dielectric material layer 10. The at least one CMOS device connection conductive structure 16L, 16R embedded in the first interconnect dielectric material layer 14, and, if present, the at least one isolated conductive structure 16 can consist of one of the conductive metals or metal alloys described above with respect to the at least one metal level conductive structure 12.

[0030] In some embodiments, a diffusion barrier liner (not shown) is formed along the sidewalls and bottom walls of the at least one metal level conductive structure 12, and / or the at least one CMOS device connection conductive structures 16L, 16R and / or the at least one isolated conductive structure 16. In some embodiments, as shown in FIG. 1, there is no diffusion barrier liner. This diffusion barrier liner consists of a diffusion barrier material (i.e., a material that serves as a barrier to prevent the diffusion of conductive materials such as copper through it). Examples of diffusion barrier materials that can be used to provide this diffusion barrier liner include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, this diffusion barrier material can include a material stack of the diffusion barrier material. In one example, this diffusion barrier material can consist of a Ta / TaN stack.

[0031] Metal level L n-1 and the interconnection level L n can be formed using conventional processes well known to those skilled in the art. To avoid obscuring the method of the present application, the techniques used to form the metal level L n-1 and the interconnection level L n are not described herein. In one embodiment, the metal level L n-1 and the interconnection level L nThe damascene process can be used when forming both of them. The damascene process can include forming an opening in a dielectric material, filling the opening with a material containing contact metal or a conductive material containing metal, and, if necessary, performing a planarization process such as, for example, chemical mechanical polishing (CMP) or grinding or both.

[0032] In some embodiments, the top surface of at least one metal level conductive structure 12 is coplanar with the top surface of the dielectric material layer 10, and the top surfaces of at least one CMOS device connection conductive structure 16L, 16R, and, if present, at least one isolated conductive structure 16 are coplanar with the top surface of the first interconnect dielectric material layer 14.

[0033] Interconnection level L n After forming the interconnection level L n a second interconnect dielectric material layer 18 is formed on the physically exposed top surface of the interconnection level L. The second interconnect dielectric material layer 18 can consist of one of the interconnect dielectric materials described above with respect to the dielectric material layer 10. In some embodiments, the second interconnect dielectric material layer 18 consists of an interconnect material having the same composition as the interconnect dielectric material providing the first interconnect dielectric material layer 14. In other embodiments, the second interconnect dielectric material layer 18 consists of an interconnect material having a different composition from the interconnect dielectric material providing the first interconnect dielectric material layer 14. The second interconnect dielectric material layer 18 is a continuous layer that can be formed using conventional deposition processes such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), chemical solution deposition, evaporation, or atomic layer deposition (ALD). In one embodiment, the second interconnect dielectric material layer 18 can have a thickness (i.e., vertical height) from 50 nm to 200 nm. The thickness of the interconnect dielectric material layer 18 determines the height of the base portion of the subsequently formed T-shaped bottom electrode structure.

[0034] Next, referring to FIG. 2, an exemplary structure of FIG. 1 is shown after forming at least one opening 20 in the second interconnection dielectric material layer 18, and this at least one opening 20 physically exposes the surfaces of at least one CMOS device connection conductive structure 16L, 16R. In some embodiments where isolated conductive structures 16 are present, another opening 20 can be formed in the first interconnection dielectric material layer 14 to physically expose the surface of at least one isolated conductive structure 16.

[0035] Each opening 20 can be formed in the second interconnection dielectric material layer 18 by lithography and etching. Lithography includes forming a photoresist material on or on a material stack to be patterned, exposing this photoresist material in a predetermined irradiation pattern, and developing the exposed photoresist to provide a patterned photoresist. Etching can include an anisotropic etching process such as reactive ion etching (RIE). Each opening 20 can have a width from 5 nm to 100 nm. The width of each opening 20 determines the width of the base portion of the subsequently formed T-shaped bottom electrode structure.

[0036] Next, referring to FIG. 3, an exemplary structure of FIG. 2 is shown after forming a bottom electrode metal-containing layer 22 on the second interconnection dielectric material layer 18 and within at least one opening 20. In the illustrated embodiment, the bottom electrode metal-containing layer 22 within each opening 20 completely fills each opening 20 so as to form an interface between the bottom electrode metal-containing layer 22 and the physically exposed surfaces of at least one CMOS device connection conductive structure 16L, 16R, and, if present, at least one isolated conductive structure 16. The upper surface of the bottom electrode metal-containing layer 22 is not planarized.

[0037] The bottom electrode metal-containing layer 22 can be made of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, or WN. The thickness (i.e., the vertical height) of the bottom electrode metal-containing layer 22 is much thicker (usually ≥ 1.5 times) than the thickness of the second interconnection dielectric material layer 18. In one embodiment, the bottom electrode metal-containing layer 22 has a thickness of from 200 nm to 300 nm. The bottom electrode metal-containing layer 22 can be formed by a conformal deposition process such as sputtering, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0038] Referring next to FIG. 4, an exemplary structure of FIG. 3 after performing the first planarization of the bottom electrode metal-containing layer 22 is shown. This first planarization, which can include chemical mechanical polishing (CMP), grinding, or both, removes the upper portion of the bottom electrode metal-containing layer 22 while maintaining the lower portion of the bottom electrode metal-containing layer 22. The maintained lower portion of this bottom electrode metal-containing layer 22 can be referred to as the once-planarized bottom electrode metal-containing layer 22P1.

[0039] The once-planarized bottom electrode metal-containing layer 22P1 has an overall flat top surface that is entirely located above the topmost surface of the second interconnection dielectric material layer 18. The thickness of the once-planarized bottom electrode metal-containing layer 22P1 is thinner than the thickness of the bottom electrode metal-containing layer 22.

[0040] Referring next to FIG. 5, an exemplary structure of FIG. 4 after performing the second planarization of the bottom electrode metal-containing layer 22 is shown. This second planarization, which can include CMP, grinding, or both, removes the upper portion of the once-planarized bottom electrode metal-containing layer 22P1 while maintaining the lower portion of the once-planarized bottom electrode metal-containing layer 22P1. The maintained lower portion of this once-planarized bottom electrode metal-containing layer 22P1 can be referred to as the twice-planarized bottom electrode metal-containing layer 22P2.

[0041] The twice-planarized bottom electrode metal-containing layer 22P2 has an overall flat top surface that is entirely located above the topmost surface of the second interconnection dielectric material layer 18. The thickness of the twice-planarized bottom electrode metal-containing layer 22P2 is thinner than the thickness of the once-planarized bottom electrode metal-containing layer 22P1. In the present application, the twice-planarized bottom electrode metal-containing layer 22P2 has an upper portion that extends over the topmost surface of the second interconnection dielectric material layer 18. The upper portion of the twice-planarized bottom electrode metal-containing layer 22P2 that extends over the topmost surface of the second interconnection dielectric material layer 18 has a thickness T of from 5 nm to 40 nm. The thickness T of the upper portion of the twice-planarized bottom electrode metal-containing layer 22P2 that extends over the topmost surface of the second interconnection dielectric material layer 18 determines the thickness of the shelf portion of the subsequently formed T-shaped bottom electrode structure.

[0042] Next, referring to FIG. 6, an exemplary structure of FIG. 5 is shown after forming a multilayer magnetic tunnel junction (MTJ) material stack 24 on the twice-planarized bottom electrode metal-containing layer 22P2 and forming a top electrode metal-containing layer 32 on the MTJ material stack 24.

[0043] The MTJ material stack 24 includes at least a magnetic fixed layer, a tunnel barrier layer, and a magnetic free layer. In some embodiments, the MTJ material stack 24 is a bottom-fixed MTJ material stack that includes a magnetic fixed layer 26, a tunnel barrier layer 28, and a magnetic free layer 30 from bottom to top as shown in FIG. 6. The bottom-fixed MTJ material stack can further have an optional metal seed layer (not shown). In the bottom-fixed MTJ material stack, this optional metal seed layer is formed under the magnetic fixed layer 26. The bottom-fixed MTJ material stack can further include a non-magnetic spacer layer (not shown) placed on the magnetic free layer 30, a second magnetic free layer (not shown) placed on the non-magnetic spacer layer, or an MTJ cap layer (not shown) placed on the magnetic free layer 30 or the second magnetic free layer, or a combination thereof.

[0044] In other embodiments (not shown), the MTJ material stack 24 is a top-fixed MTJ material stack including a magnetic free layer, a tunnel barrier layer, and a magnetic fixed layer from bottom to top, and in this embodiment, the order of elements 26 and 30 is reversed from the order shown in FIG. 6. In such an embodiment, the top-fixed MTJ material stack can further include an optional metal seed layer placed under the magnetic free layer, a non-magnetic spacer layer placed on the magnetic free layer, a second magnetic free layer placed on the non-magnetic spacer layer, or an MTJ cap layer placed on the magnetic fixed layer, or a combination thereof.

[0045] These various material layers of the MTJ material stack 24 can be formed by utilizing one or more deposition processes such as sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0046] The optional metal seed layer can consist of platinum (Pt), palladium (Pd), nickel (Ni), rhodium (Rh), iridium (Ir), rhenium (Re), or alloys and multilayers of these metals. In one example, the optional metal seed layer consists of platinum (Pt).

[0047] The magnetic fixed layer 26 has a fixed magnetization. The magnetic fixed layer 26 can consist of a metal or metal alloy (or stacks thereof) including one or several metals showing high spin polarization. In an alternative embodiment, exemplary metals for forming the magnetic fixed layer 26 include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys can include the metals exemplified above.

[0048] In another embodiment, the magnetic fixed layer 26 can be a multilayer arrangement having (1) a high spin polarization region formed of a metal or a metal alloy or both using the above-described metals, and (2) a region constructed from one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials having strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and the materials can be arranged as multilayers. This strong PMA region can also include an alloy exhibiting strong PMA, and exemplary alloys include cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum or iron-palladium, or combinations thereof. The alloys can be arranged as multilayers. In one embodiment, combinations of these materials and regions can also be used as the magnetic fixed layer 26.

[0049] The tunnel barrier layer 28 is made of an insulator material and is formed to a thickness that provides an appropriate tunneling resistance. Exemplary materials for the tunnel barrier layer 28 include magnesium oxide, aluminum oxide, and titanium oxide, or materials having a higher electrical tunnel conductance such as semiconductors or low bandgap insulators.

[0050] The magnetic free layer 30 can be made of a magnetic material (or a stack of magnetic materials) having a magnetization that can change its orientation with respect to the orientation of the magnetization of the magnetic fixed layer 26. Exemplary magnetic materials for the magnetic free layer 30 include alloys or multilayers or both of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys.

[0051] When present, the non-magnetic metal spacer layer enables the transmission of magnetic information therethrough and further enables the two magnetic free layers to be magnetically coupled together such that the first magnetic free layer and the second magnetic free layer are always parallel in the equilibrium state. The non-magnetic metal spacer layer is made of a non-magnetic metal or a metal alloy that enables spin torque switching between the first magnetic free layer and the second magnetic free layer.

[0052] When present, the second magnetic free layer can include one of the magnetic materials described above with respect to the magnetic free layer 30. In one embodiment, the second magnetic free layer is made of the same magnetic material as the magnetic free layer 30. In another embodiment, the second magnetic free layer is made of a magnetic material having a composition different from that of the magnetic free layer 30.

[0053] When present, the MTJ capping layer can be made of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al or other high melting point metals or conductive metal nitrides. The MTJ capping layer can have a thickness from 2 nm to 25 nm. Other thicknesses are possible and other thicknesses can be used as the thickness of the MTJ capping layer in the present application.

[0054] The top electrode metal-containing layer 32 can be made of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN or a combination thereof. In one embodiment of the present application, the top electrode metal-containing layer 32 is made of Ti / TiN. The conductive material providing the top electrode metal-containing layer 32 can be a conductive material having the same composition as the conductive material providing the bottom electrode metal-containing layer 22 or a conductive material having a composition different from that of the conductive material providing the bottom electrode metal-containing layer 22.

[0055] In the present application, the top electrode metal-containing layer 32 can have a thickness of 100 nm to 500 nm, but other thicknesses are also possible, and other thicknesses can be used as the thickness of the top electrode metal-containing layer 32. The top electrode metal-containing layer 32 can be formed by a deposition process such as sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0056] Referring next to FIG. 7, an exemplary structure of FIG. 6 is shown after patterning the top electrode metal-containing layer 32, the MTJ material stack 24, and the twice-planarized bottom electrode metal-containing layer 22P2 to provide a top electrode structure 32S, an MTJ pillar 24P, and a T-shaped bottom electrode structure 22S, respectively.

[0057] The patterning of the top electrode metal-containing layer 32, the MTJ material stack 24, and the twice planarized bottom electrode metal-containing layer 22P2 can include first forming a patterned mask (not shown) on the physically exposed surface of the top electrode metal-containing layer 32. In some embodiments, the patterned mask can consist of a photolithography resist stack. In one embodiment, the photolithography resist stack that provides the patterned mask can include a bottom organic layer, an intermediate inorganic layer, and a top resist layer. The bottom organic layer of the photolithography resist stack can include an organic planarization layer (OPL). The bottom organic layer of the photolithography resist stack can include a spin-on organic layer such as, for example, near frictionless carbon (NFC), diamond-like carbon, thermosetting polyarylene ether, or polyimide. The intermediate inorganic layer of the photolithography resist stack can include an oxide layer such as, for example, a low temperature (e.g., 250 °C or less) CVD oxide, an oxide derived from TEOS (tetraethyl orthosilicate), silicon oxide, silane oxide, or a Si-containing anti-reflection coating material (SiARC). The top resist layer of the photolithography resist stack can consist of a resist material that provides high resolution lithography patterning. This photolithography resist stack can be formed by a series of deposition processes including a first spin-on coating of the bottom organic layer, a second spin-on coating of the intermediate inorganic layer, and a third spin-on coating of the top resist layer.After forming a photolithography resist stack, the top resist layer is patterned by photolithography (i.e., exposing the top resist layer with an irradiation pattern and then developing the exposed top resist layer), and then the pattern provided in the top resist layer is transferred to the underlying layer of the photolithography resist stack to provide a patterned mask. This transfer can include one or more etching processes.

[0058] In some embodiments, patterning can include first patterning the top electrode metal-containing layer 32 using a first etching process such as reactive ion etching that utilizes the patterned mask as an etching mask. The remaining portion of the top electrode metal-containing layer 32, i.e., the portion that is not patterned, provides the top electrode structure 32S. The shape of the top electrode structure 32S can be cylindrical, but other asymmetric shapes are possible, and in the present application, other asymmetric shapes can be used as the shape of the top electrode structure 32S. The critical dimension (CD) of the top electrode structure 32S can vary and is not important in the present application.

[0059] After patterning the top electrode metal-containing layer 32, the patterned mask formed using a conventional process well-known to those skilled in the art is removed from above the top electrode structure 32S. Next, patterning of the MTJ material stack 24 and the twice-planarized bottom electrode metal-containing layer 22P2 is performed using ion beam etching (IBE). In this IBE, the top electrode structure 32S is used as the patterned mask. The remaining portion of the MTJ material stack 24, i.e., the portion that was not patterned, provides the MTJ pillar 24P. In one example, as shown in FIG. 7, the MTJ pillar 24P, from bottom to top, includes a magnetically pinned material layer portion 26P (i.e., the remaining portion of the magnetically pinned material layer 26 that was not etched), a tunnel barrier layer portion 28P (i.e., the remaining portion of the tunnel barrier layer 28 that was not etched), and a magnetically free layer portion 30P (i.e., the remaining portion of the magnetically free layer 30 that was not etched). In another example (not shown), the MTJ pillar 24P, from bottom to top, includes a magnetically free layer portion 30P, a tunnel barrier layer portion 28P, and a magnetically pinned material layer portion 26P. The MTJ pillar 24P can include the remaining portions of other layers present in the MTJ material stack 24. The shape of the MTJ pillar 24P can be cylindrical, but other asymmetric shapes are possible, and in this application, other asymmetric shapes can be used as the shape of the MTJ pillar 24P. The MTJ pillar 24P and the top electrode structure 32S have the same shape. The critical dimension (CD) of the MTJ pillar 24P can be various and is not important in this application. The CD of the MTJ pillar 24P is usually the same as the CD of the top electrode structure 32S.

[0060] The IBE etching then continues to pattern the underlying twice-planarized bottom electrode metal-containing layer 22P2 to provide a T-shaped bottom electrode structure 22S. As shown in FIG. 7, during this IBE, the physically exposed upper portion of the second interconnection dielectric material 18 can also be removed. After this IBE, the remaining second interconnection dielectric material can have a concave surface S1, as shown in FIG. 7.

[0061] The T-shaped bottom electrode structures 22S each include a remaining portion of the planarized bottom electrode metal-containing layer 22P2. The T-shaped bottom electrode structures 22S each include a base portion (i.e., the vertically extending portion) (the portion labeled "base" in FIG. 7) and a shelf portion (i.e., the horizontal portion) (the portion labeled "shelf" in FIG. 7). The T-shaped bottom electrode structures 22S have a uniform structure without a material interface between the shelf portion and the base portion (i.e., they are a single piece). The shelf portion has an outermost edge that extends outward beyond the outermost edge of the base portion. In some embodiments (as shown in FIG. 7), the outermost edge of the shelf portion of the T-shaped bottom electrode structure 22S tapers outward from the uppermost surface of the shelf portion toward the lowermost surface of the shelf portion. The width of the base portion of each T-shaped bottom electrode structure 22S is smaller than the width of the shelf portion. The base portion and the shelf portion of each T-shaped bottom electrode structure 22S have an integral structure made of the same bottom electrode material (i.e., they are a single piece). The shelf portion of each T-shaped bottom electrode structure 22S provides a flat surface on which the MTJ pillar 24P forms an interface with the shelf portion. Thus, variations in the height uniformity of the MTJ pillars are avoided.

[0062] The T-shaped bottom electrode structures 22S, the MTJ pillars 24P, and the top electrode structures 32S together provide the memory structure according to the present application. The presence of the T-shaped bottom electrode structures 22S in the memory structure shorts the CMOS device connection conductive structures 16L, 16R, and the isolated conductive structure 16. Thus, the high resistance due to the galvanic effect described above is reduced or eliminated or both. Further, due to the presence of the T-shaped bottom electrode structures 22S, no array yield loss is observed.

[0063] Next, referring to FIG. 8, an exemplary structure of FIG. 7 after forming the encapsulation liner 34, the third interconnect dielectric material layer 36, and the bit line contact 38 is shown. The encapsulation liner 34 laterally surrounds the shelf portions of the top electrode structure 32S, the MTJ pillar 24P, and the T-shaped bottom electrode structure 22S. The third interconnect dielectric material layer 36 is disposed on the encapsulation liner 34 and fills the gap located between adjacent memory structures. The bit line contacts 38 are disposed on each memory structure and the third interconnect dielectric material layer 36. In the illustrated embodiment, the bit line contacts 38 have a surface that contacts the surface of each top electrode structure 32S.

[0064] The encapsulation liner 34 can be present on the concave surface S1 of the second interconnect dielectric material layer 18. The encapsulation liner 34 is made of a dielectric material having a composition different from that of the second interconnect dielectric material layer 18. The dielectric material providing the encapsulation liner 34 can provide passivation to the shelf portions of the top electrode structure 32S, the MTJ pillar 24P, and the T-shaped bottom electrode structure 22S. In one embodiment, the encapsulation liner 34 is made of silicon nitride. In another embodiment, the encapsulation liner 34 can be made of a dielectric material containing silicon, carbon, and hydrogen atoms. In some embodiments, the dielectric material providing the encapsulation liner 34 can contain at least one of nitrogen and oxygen atoms in addition to carbon and hydrogen atoms. In other embodiments, the dielectric material providing the encapsulation liner 34 can contain boron atoms in addition to silicon, nitrogen, carbon, and hydrogen atoms. In one example, the encapsulation liner 34 can be made of an nBLOK dielectric material containing silicon, carbon, hydrogen, nitrogen, and oxygen atoms. As an alternative, the encapsulation liner 34 can be made of a SiBCN dielectric material containing silicon, boron, carbon, hydrogen, and nitrogen atoms.

[0065] The encapsulation liner 34 can be formed by first depositing a continuous layer of dielectric material that provides the encapsulation liner 34. During the subsequent planarization process used to form the third interconnect dielectric material layer 36, the dielectric material that provides the encapsulation liner 34 is removed from the topmost surface of each top electrode structure 32S. The encapsulation liner 34 can have a thickness from 10 nm to 200 nm. Other thicknesses are possible and other thicknesses can be used as the thickness of the encapsulation liner 34. The topmost surface of the encapsulation liner 34 is typically coplanar with the topmost surface of the top electrode structure 32S.

[0066] The third interconnect dielectric material layer 36 can include one of the interconnect dielectric materials described above. The interconnect dielectric material that provides the third interconnect dielectric material layer 36 can be the same interconnect dielectric material as the interconnect dielectric material that provides the first interconnect dielectric material layer 14 or the second interconnect dielectric material layer 18 or both, or can be an interconnect dielectric material having a composition different from the interconnect dielectric material that provides the first interconnect dielectric material layer 14 or the second interconnect dielectric material layer 18 or both. The third interconnect dielectric material layer 36 can be formed using conventional deposition processes including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or spin-on coating. Following the deposition of the interconnect dielectric material that provides the third interconnect dielectric material layer 36, a planarization process such as chemical mechanical polishing (CMP) can be performed. As described above, this planarization step further removes the dielectric material that provides the encapsulation liner 34 from the topmost surface of the top electrode structure 32S.

[0067] The bit line contact 38 can include one of the conductive metals or metal alloys described above. The bit line contact 36 can be formed by depositing a layer of conductive metal or metal alloy and subsequently patterning the layer of conductive metal or metal alloy. As defined above, patterning can be performed by lithography and etching.

[0068] Next, referring to FIG. 9, an exemplary structure of FIG. 2 is shown after forming a diffusion barrier material layer 19 on the second interconnect dielectric material layer 18 and covering the inside of at least one opening 20. The diffusion barrier material layer 19 is a continuous layer made of a diffusion barrier material (i.e., a material that serves as a barrier to prevent a conductive material such as copper from diffusing therethrough). Examples of diffusion barrier materials that can be used when providing the diffusion barrier material layer 19 include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the diffusion barrier material layer 19 can include a material stack of a diffusion barrier material. In one example, the diffusion barrier material layer 19 can be composed of a Ta / TaN stack.

[0069] The diffusion barrier material layer 19 can be formed using a deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The diffusion barrier material layer 19 can have a thickness of from 1 nm to 20 nm. Other thicknesses for the diffusion barrier material layer 19 are contemplated, and other thicknesses for the diffusion barrier material layer 19 can be used as long as the thickness of the diffusion barrier material layer 19 does not completely fill at least one opening 20.

[0070] Next, referring to FIG. 10, a bottom electrode metal-containing layer (not shown; described above in FIG. 3) is formed on the diffusion barrier material layer 19, a first planarization of the bottom electrode metal-containing layer (described above in FIG. 4) is performed, and a second planarization of the bottom electrode metal-containing layer (described above in FIG. 5) is performed to provide an exemplary structure of FIG. 9 after providing a two-time planarized bottom electrode metal-containing layer 22P2. The first and second planarizations can include sequential CMP or grinding steps or both. The two-time planarized bottom electrode metal-containing layer 22P2 has an overall flat top surface disposed on the topmost surface of the second interconnect dielectric material layer 18. The two-time planarized bottom electrode metal-containing layer 22P2 has the thickness T described above in FIG. 5.

[0071] Referring next to FIG. 11, an exemplary structure of FIG. 10 is shown after forming a multi-layer magnetic tunnel junction (MTJ) material stack on the twice planarized bottom electrode metal-containing layer 22P2, forming a top electrode metal-containing layer on the MTJ material stack, and patterning the top electrode metal-containing layer, the MTJ material stack, the twice planarized bottom electrode metal-containing layer, and the diffusion barrier material layer to provide a top electrode structure 32A, an MTJ pillar 24P, a T-shaped bottom electrode structure 22S, and a diffusion barrier liner 19L, respectively.

[0072] The exemplary structure shown in FIG. 11 can be formed using the basic processing steps and materials described above for forming the exemplary structures shown in FIGS. 6 and 7. In this embodiment, as shown in FIG. 11, the diffusion barrier liner 19L is placed under the shelf portion of the T-shaped bottom electrode structure 22S and covers the entire inside of at least one opening 20. Thus, the diffusion barrier liner 19L is placed between the T-shaped bottom electrode structure 22S and the second interconnect dielectric material layer 18, and between the lowermost surface of the T-shaped bottom electrode structure 22S and one of the conductive structures 16L, 16R, 16 embedded in the first interconnect dielectric material layer 14.

[0073] Referring next to FIG. 12, an exemplary structure of FIG. 11 is shown after forming a encapsulation liner 34, a third interconnect dielectric material layer 36, and a bit line contact 38. The encapsulation liner 34, the third interconnect dielectric material layer 36, and the bit line contact 38 used in this embodiment of the present application are exactly the same as the encapsulation liner 34, the third interconnect dielectric material layer 36, and the bit line contact 38 used to provide the exemplary structure shown in FIG. 8.

[0074] Next, referring to FIG. 13, a prior art memory structure is shown. The difference between this prior art memory structure and the memory structure of the present application is that a diffusion barrier liner 53L is placed between the bottom electrode pillar 52S and the flat landing pad structure 54P. Both the bottom electrode pillar 52S and the flat landing pad structure 54P are made of a metal or metal alloy that is susceptible to oxidation or corrosion or both. Therefore, this prior art structure may exhibit high resistance and low array yield. Note that the prior art structure does not have a homogeneous T-shaped bottom electrode structure 22S of a uniform structure (i.e., a single piece).

[0075] Although the present application has been shown and described with particular reference to preferred embodiments of the present application, those skilled in the art will understand that the above and other changes in form and detail can be made without departing from the scope of the present application. Therefore, the present application is not limited to the exact forms and details described and illustrated, and the present application is intended to be included within the scope of the appended claims.

Claims

1. A memory structure, comprising: a T-shaped bottom electrode structure with a uniform structure placed on the surface of a complementary metal oxide semiconductor (CMOS) device connection conductive structure embedded in a first interconnect dielectric material layer, the T-shaped bottom electrode structure including a base portion and a shelf portion, the width of the shelf portion being greater than the width of the base portion, the T-shaped bottom electrode structure; a second interconnect dielectric material layer placed on the first interconnect dielectric material layer, surrounding only the base portion of the T-shaped bottom electrode structure from the side, and provided with a concave surface; a multilayer magnetic tunnel junction (MTJ) pillar placed on the T-shaped bottom electrode structure; a top electrode structure placed on the MTJ pillar; an encapsulation liner and a third interconnect dielectric material layer placed adjacent to the side of the shelf portion of the T-shaped bottom electrode structure, the MTJ pillar, and the top electrode structure, and on the concave surface provided in the second interconnect dielectric material layer The memory structure is provided.

2. The memory structure according to claim 1, wherein the MTJ pillar includes a bottom-fixed MTJ material structure.

3. The memory structure according to claim 1, wherein the MTJ pillar includes a top-fixed MTJ material structure.

4. A diffusion barrier liner placed directly under the shelf portion of the T-shaped bottom electrode structure, covering the side wall and the bottom wall of the base portion of the T-shaped bottom electrode structure, and further comprising the diffusion barrier liner, the memory structure according to claim 1.

5. A bit line contact placed on the third interconnect dielectric material layer, contacting the surface of the top electrode structure, and further comprising the bit line contact, the memory structure according to claim 1.

6. A structure, comprising: a first T-shaped bottom electrode structure with a uniform structure placed on the surface of a complementary metal oxide semiconductor (CMOS) device connection conductive structure embedded in a first interconnect dielectric material layer; a first multilayer magnetic tunnel junction (MTJ) pillar placed on the first T-shaped bottom electrode structure; and a first top electrode structure placed on the first MTJ pillar, a first memory cell; A second memory cell placed adjacent to the first memory cell horizontally, a second T-shaped bottom electrode structure with a uniform structure placed on the surface of an isolated conductive structure embedded in the first interconnect dielectric material layer, a second MTJ pillar placed on the second T-shaped bottom electrode structure, and a second top electrode structure placed on the second MTJ pillar, the second memory cell comprising: Comprising: The first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure include a base portion and a shelf portion, and the width of the shelf portion is made larger than the width of the base portion. The structure further comprises: A second interconnect dielectric material layer placed on the first interconnect dielectric material layer, surrounding only the base portions of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure horizontally, and provided with a concave surface. An encapsulation liner and a third interconnect dielectric material layer placed adjacent to the shelf portions of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure respectively, the first MTJ pillar and the second MTJ pillar respectively, and the first top electrode structure and the second top electrode structure respectively, and on the concave surface provided in the second interconnect dielectric material. A structure comprising:

7. The structure according to claim 6, wherein the first MTJ pillar and the second MTJ pillar include a bottom-fixed MTJ material structure.

8. The structure according to claim 6, wherein the first MTJ pillar and the second MTJ pillar include a top-fixed MTJ material structure.

9. A diffusion barrier liner placed directly under the shelf portions of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure respectively, and further comprising the diffusion barrier liner covering the side walls and the bottom walls of the base portions of the first T-shaped bottom electrode structure and the second T-shaped bottom electrode structure respectively, the structure according to claim 6.

10. A bit line contact placed on the third interconnect dielectric material layer, and further comprising the bit line contact contacting the surfaces of the first top electrode structure and the second top electrode structure, the structure according to claim 6.

11. A method of forming a memory structure, Forming a second interconnect dielectric material layer on an interconnect level including at least one CMOS device connection conductive structure embedded in a first interconnect dielectric material layer; Forming at least one opening in the second interconnect dielectric material layer to physically expose the surface of the at least one CMOS device connection conductive structure; Forming a bottom electrode metal-containing layer on the second interconnect dielectric material layer and within the at least one opening; Performing first and second planarizations of the bottom electrode metal-containing layer to provide a twice-planarized bottom electrode metal-containing layer; Forming a multilayer magnetic tunnel junction (MTJ) material stack on the twice-planarized bottom electrode metal-containing layer and forming a top electrode metal-containing layer on the MTJ material stack, and Patterning the top electrode metal-containing layer, the MTJ material stack, and the twice-planarized bottom electrode metal-containing layer to provide a top electrode structure, an MTJ pillar, and a T-shaped bottom electrode structure, respectively; Including; By removing an upper portion of the second interconnect dielectric material layer by the patterning, a concave surface is provided in the second interconnect dielectric material layer; Further including forming a capping liner, a third interconnect dielectric material layer, and a bit line contact on the concave surface provided in the second interconnect dielectric material layer after the patterning; Method.

12. The method according to claim 11, wherein the MTJ material stack includes a bottom-fixed MTJ material stack.

13. The method according to claim 11, wherein the MTJ material stack includes a top-fixed MTJ material stack.

14. The method according to any one of claims 11 to 13, wherein the T-shaped bottom electrode structure includes a base portion and a shelf portion, and the width of the shelf portion is greater than the width of the base portion.

15. The method according to any one of claims 11 to 14, further including forming a diffusion barrier material layer on the second interconnect dielectric material layer and covering the inside of the at least one opening before forming the bottom electrode metal-containing layer.

16. The method according to claim 15, wherein the patterning further provides a diffusion barrier liner disposed under the T-shaped bottom electrode structure.

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