Semiconductor device, imaging device, and display device

Abstract

The present invention increases the reading accuracy of an imaging device. Clear imaging is realized even in a situation in which the luminance is high. A read circuit of the imaging device includes an amplification unit and a conversion unit. The amplification unit amplifies a difference between potentials of a first signal and a second signal that are input in order, and outputs same to the conversion unit. The conversion unit converts the output potential of the amplification unit into a digital value. The amplification unit is reset on the basis of a first reference potential and the first signal, and amplifies the difference between potentials on the basis of a second reference potential, which is different from the first reference potential, and the second signal.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to an imaging device. One aspect of the present invention relates to a display device having an imaging function. One aspect of the present invention relates to a readout circuit.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] An imaging device in which pixels including photoelectric conversion elements are arranged in a matrix is known. In many cases, an analog signal acquired by a pixel is converted into digital data by an analog-to-digital conversion circuit (A-D conversion circuit) and output. Also, a technique for expanding the dynamic range by amplifying the amplitude of a signal output from a pixel and performing A-D conversion processing is known. For example, Patent Document 1 discloses an imaging device including an amplification circuit that amplifies a pixel signal with a set gain and an AD conversion unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One aspect of the present invention aims to improve the reading accuracy of an imaging device. One aspect of the present invention aims to achieve clear imaging even when the imaging luminance is high. One aspect of the present invention aims to provide a semiconductor device or an imaging device including a readout circuit that can be realized at low cost.

[0006] One aspect of the present invention aims to provide a display device having an imaging function. One aspect of the present invention aims to provide an imaging device or a display device that can clearly image fingerprints and the like. One aspect of the present invention aims to provide a semiconductor device, an imaging device, or a display device with a reduced number of terminals or wirings. One aspect of the present invention aims to reduce the number of components in electronic devices and the like. One aspect of the present invention aims to provide a semiconductor device, an imaging device, a display device, or an electronic device having a novel configuration.

[0007] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, and the like.

Means for Solving the Problems

[0008] One aspect of the present invention is a semiconductor device including an amplification unit and a conversion unit. The amplification unit includes a comparison circuit, and a first signal and a second signal are input in order. The comparison circuit is supplied with a first reference potential during a period when the first signal is input. Also, the comparison circuit is supplied with a second reference potential during a period when the second signal is input. The amplification unit outputs, to the conversion unit, an output potential obtained by amplifying a potential difference between the first signal and the second signal during a period when the second signal is input. The conversion unit converts the output potential into a digital value.

[0009] Another aspect of the present invention is a semiconductor device including an amplification unit, a conversion unit, and an input terminal. The amplification unit includes a comparison circuit, a first capacitor, a second capacitor, and a first switch. The comparison circuit includes an inverting input terminal, a non-inverting input terminal, and an output terminal. A first signal and a second signal are sequentially supplied to the input terminal. One of a pair of electrodes of the first capacitor is electrically connected to the input terminal, and the other is electrically connected to the inverting input terminal. The second capacitor and the first switch are electrically connected in parallel to the inverting input terminal and the output terminal, respectively. When the first signal is supplied, the first switch is turned on, and a first reference potential is supplied to the non-inverting input terminal. When the second signal is supplied, the first switch is turned off, and a second reference potential different from the first reference potential is supplied to the non-inverting input terminal. The conversion unit converts the potential output from the output terminal into a digital value.

[0010] Another aspect of the present invention is a semiconductor device including an amplification unit, a conversion unit, and an input terminal. The amplification unit includes a comparison circuit, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a first wiring, and a second wiring. The comparison circuit includes an inverting input terminal, a non-inverting input terminal, and an output terminal. A first signal and a second signal are sequentially supplied to the input terminal. One of a pair of electrodes of the first capacitor is electrically connected to the input terminal, and the other is electrically connected to the inverting input terminal. The second capacitor and the first switch are electrically connected in parallel to the inverting input terminal and the output terminal, respectively. The first wiring to which a first reference potential is supplied and the non-inverting input terminal are electrically connected via the second switch. The second wiring to which a second reference potential different from the first reference potential is supplied and the non-inverting input terminal are electrically connected via the third switch. The conversion unit converts the potential output from the output terminal into a digital value.

[0011] One aspect of the present invention is an imaging device including the semiconductor device according to any of the above, a pixel, and a third wiring. The pixel includes a photoelectric conversion element and a pixel circuit. The pixel circuit outputs a first signal including a received light potential and a second signal including a reset potential to the third wiring. The third wiring is electrically connected to an input terminal.

[0012] Another aspect of the present invention is an imaging device including the semiconductor device according to any of the above, a plurality of pixels, a plurality of third wirings, and a first selection circuit. The pixel includes a photoelectric conversion element and a pixel circuit. The pixel circuit outputs a first signal including a received light potential and a second signal including a reset potential to the third wiring. The plurality of third wirings are electrically connected to the first selection circuit. The first selection circuit selects one of the plurality of third wirings and electrically connects the selected third wiring to the input terminal.

[0013] In any of the above imaging devices, it is preferable to have a correlated double sampling circuit between the third wiring and the input terminal.

[0014] In any of the above imaging devices, it is preferable to have a first substrate and a second substrate. At this time, it is preferable that the semiconductor device is provided on the first substrate and the pixel is provided on the second substrate.

[0015] Another aspect of the present invention is a semiconductor device having an amplification unit, a first conversion unit, a second conversion unit, an input terminal, and a first output terminal. The amplification unit includes a comparison circuit, a first capacitor, a second capacitor, and a first switch. The comparison circuit has an inverting input terminal, a non-inverting input terminal, and a second output terminal. A first signal and a second signal are sequentially applied to the input terminal. One of the pair of electrodes of the first capacitor is electrically connected to the input terminal, and the other is electrically connected to the inverting input terminal. The second capacitor and the first switch are electrically connected in parallel to the inverting input terminal and the second output terminal, respectively. When the first signal is applied, the amplification unit applies a first reference potential to the non-inverting input terminal, and when the second signal is applied, the amplification unit applies a second reference potential different from the first reference potential to the non-inverting input terminal. The first conversion unit converts the potential output from the second output terminal into a digital value. The second conversion unit receives a digital signal, converts the digital signal into an analog third signal, and outputs the analog third signal to the first output terminal. The amplification unit, the first conversion unit, and the second conversion unit are provided on a first substrate.

[0016] Also, in the above, it is preferable to have a fourth switch. At this time, the first output terminal and the non-inverting input terminal are electrically connected via the fourth switch. Also, the second conversion unit outputs a third signal including a data potential, a first reference potential, and a second reference potential based on the digital signal. Also, it is preferable that the fourth switch is in a conductive state during a period when the first reference potential is output to the first output terminal and during a period when the second reference potential is output, and the fourth switch is in a non-conductive state during a period when the data potential is output to the first output terminal.

[0017] Also, in any of the above, it is preferable to have a second switch, a third switch, a first wiring, and a second wiring. At this time, the first wiring to which the first reference potential is applied and the non-inverting input terminal are electrically connected via the second switch. The second wiring to which the second reference potential is applied and the non-inverting input terminal are electrically connected via the third switch.

[0018] Also, one aspect of the present invention is a display device including any of the semiconductor devices described above, a first pixel, a second pixel, a third wiring, and a fourth wiring. The first pixel includes a photoelectric conversion element and a first pixel circuit. The first pixel circuit outputs a first signal including a received light potential and a second signal including a reset potential to the third wiring. The third wiring is electrically connected to an input terminal. The second pixel includes a display element and a second pixel circuit. The fourth wiring is electrically connected to a first output terminal and the second pixel circuit. The second pixel circuit controls the gradation of the display element based on a third signal.

[0019] Also, in the above, it is preferable to include a second selection circuit, a third selection circuit, and a fifth wiring. At this time, the third wiring and the fourth wiring are electrically connected to the second selection circuit. The input terminal and the first output terminal are electrically connected to the third selection circuit. The second selection circuit and the third selection circuit are electrically connected via the fifth wiring. The second selection circuit selects either the third wiring or the fourth wiring and electrically connects it to the fifth wiring. The third selection circuit selects either the input terminal or the first output terminal and electrically connects it to the fifth wiring.

[0020] Also, in any of the above, the display element is preferably a light-emitting element. Further, the photoelectric conversion element and the light-emitting element are preferably located on the same plane. Also, the photoelectric conversion element preferably has an electron injection layer, an electron transport layer, a light-emitting layer, an active layer, a hole injection layer, and a hole transport layer between a pixel electrode and a first electrode. Further, the light-emitting element preferably has one or more of the first electrode, the electron injection layer, the electron transport layer, the hole injection layer, and the hole transport layer.

[0021] Also, in any of the above, it is preferable to have a second substrate different from the first substrate. At this time, the semiconductor device is preferably provided on the first substrate, and the first pixel and the second pixel are preferably provided on the second substrate. Further, the first substrate is preferably a single crystal substrate, and the second substrate preferably includes glass or an organic resin.

Advantages of the Invention

[0022] According to one aspect of the present invention, the reading accuracy of the imaging device can be improved. According to one aspect of the present invention, clear imaging can be realized even when the imaging luminance is high. According to one aspect of the present invention, a semiconductor device or an imaging device including a reading circuit that can be realized at low cost can be provided.

[0023] According to one aspect of the present invention, a display device having an imaging function can be provided. According to one aspect of the present invention, an imaging device or a display device capable of clearly imaging fingerprints or the like can be provided. According to one aspect of the present invention, a semiconductor device, an imaging device, or a display device with a reduced number of terminals or wirings can be provided. According to one aspect of the present invention, the number of components such as in an electronic device can be reduced. According to one aspect of the present invention, a semiconductor device, an imaging device, a display device, or an electronic device having a novel configuration can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0025] FIG. 1A is a configuration example of an imaging device. FIG. 1B is a configuration example of a circuit section. FIGS. 2A and 2B are diagrams for explaining the operation of an amplification section. FIG. 3 is a configuration example of a circuit section. FIGS. 4A and 4B are diagrams for explaining the operation of an amplification section. FIG. 5A is a configuration example of an imaging device. FIG. 5B is a timing chart. FIG. 6 is a configuration example of an imaging device. FIG. 7A is a configuration example of a display device. FIGS. 7B and 7C are configuration examples of pixels. FIGS. 8A and 8B are configuration examples of a circuit section. FIGS. 9A and 9B are configuration examples of a circuit section. Figures 10A to 10C are configuration examples of a circuit section. Figures 11A and 11B are configuration examples of a display device. Figures 12A, 12B, 12D, 12F to 12H are configuration examples of a display device. Figures 12C and 12E are examples of images. Figures 13A to 13D are configuration examples of a display device. Figures 14A to 14C are configuration examples of a display device. Figures 15A and 15B are configuration examples of a display device. Figures 16A to 16C are configuration examples of a display device. Figure 17 is a configuration example of a display device. Figure 18 is a configuration example of a display device. Figures 19A and 19B are configuration examples of a display device. Figures 20A and 20B are configuration examples of a display device. Figure 21 is a configuration example of a display device. Figures 22A and 22B are configuration examples of an electronic device. Figures 23A to 23D are configuration examples of an electronic device. Figures 24A to 24F are configuration examples of an electronic device.

Mode for Carrying Out the Invention

[0026] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it will be easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0027] In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description thereof is omitted. Also, when referring to the same function, the hatch patterns are the same, and there may be cases where no reference numerals are particularly assigned.

[0028] In each of the figures described in this specification, the size of each component, the thickness of a layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0029] Note that ordinal numbers such as "first" and "second" in this specification and the like are attached to avoid confusion of components and are not numerically limiting.

[0030] In addition, in this specification and the like, "electrically connected" includes cases where it is connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors, resistance elements, coils, capacitance elements, and other elements having various functions.

[0031] Note that in this specification and the like, a node refers to an element (such as wiring) that enables electrical connection of elements constituting a circuit. Therefore, "the node to which A is connected" refers to the wiring that is electrically connected to A and can be regarded as having the same potential as A. Note that even if one or more elements (such as switches, transistors, capacitance elements, inductors, resistance elements, diodes, etc.) that enable electrical connection are arranged in the middle of the wiring, if it can be regarded as having the same potential as A, that wiring is the same node.

[0032] In this specification and the like, a display panel, which is an aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is an aspect of an output device.

[0033] In addition, in this specification and the like, a display panel substrate to which a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached, or a substrate on which an IC is mounted by a COG (Chip On Glass) method or the like may be referred to as a display panel module, a display module, or simply a display panel.

[0034] (Embodiment 1) In this embodiment, a configuration example of a semiconductor device, an imaging device, and a display device according to an aspect of the present invention will be described.

[0035] [Configuration Example 1 of Imaging Device] FIG. 1A shows a block diagram of an imaging device 10. The imaging device 10 includes an imaging unit 11, a circuit unit 12, a drive circuit unit 13, and the like.

[0036] The imaging unit 11 has a plurality of pixels 15 arranged in a matrix. Each pixel 15 has a light-receiving element that functions as a photoelectric conversion element and a pixel circuit. FIG. 1A shows an example in which the pixels 15 are arranged in m rows and n columns.

[0037] The pixel 15 is electrically connected to a wiring TX, a wiring SE, a wiring RS, and a wiring WX. The wiring TX, the wiring SE, and the wiring RS are electrically connected to the drive circuit unit 13. The wiring WX is electrically connected to the circuit unit 12.

[0038] The pixel 15 is driven to output a first signal and a second signal to the wiring WX in this order. The first signal is a signal including a received light potential (potential V S ) corresponding to the amount of light received by the light-receiving element of the pixel 15 during the exposure period. The second signal is a signal including a reset potential (potential V R ) output in a state where the pixel 15 is reset to a predetermined potential. The first signal can also be referred to as a received light signal, and the second signal can also be referred to as a reset signal.

[0039] The drive circuit unit 13 has a function of generating signals for driving the pixel 15 and outputting them to the pixel 15 via the wiring SE, the wiring TX, and the wiring RS. The circuit unit 12 has a function of receiving signals output from the pixel 15 via the wiring WX and outputting them to the outside as digital image data. The circuit unit 12 functions as a readout circuit.

[0040] The circuit unit 12 includes a plurality of amplification units PA and a plurality of conversion units ADC. The wiring WX is electrically connected to the amplification unit PA. The amplification unit PA is electrically connected to the conversion unit ADC. FIG. 1A shows an example in which the circuit unit 12 includes n amplification units PA and n conversion units ADC. Note that other circuits may be provided between the wiring WX and the amplification unit PA. For example, various circuits such as a circuit that forms a transistor and a source follower included in the pixel 15, an amplifier circuit, a buffer circuit, a multiplexer circuit, or a correlated double sampling (CDS) circuit may be provided.

[0041] The amplification unit PA has a function of amplifying the difference between the first signal and the second signal output from the pixel 15 via the wiring WX and outputting the amplified signal to the conversion unit ADC as an analog signal. The amplification unit PA can also be called a preamplifier. The conversion unit ADC has a function of converting the analog signal input from the amplification unit PA into a digital signal.

[0042] Here, as shown in FIG. 1A, the imaging unit 11 is provided on the substrate 21. The circuit unit 12 is provided on the substrate 22. The drive circuit unit 13 is provided on the substrate 23. As the substrate 21, the substrate 22, and the substrate 23, a single crystal substrate such as silicon or a compound semiconductor, or an SOI (Silicon on Insulator) substrate can be used. Further, as the substrate 21 on which the imaging unit 11 is provided, an insulating substrate such as glass, quartz, ceramic, sapphire, or resin may be used. Further, as the substrate 21, a rigid substrate or a flexible substrate may be used. Note that the imaging unit 11 and the drive circuit unit 13 may be provided on the same substrate, and the circuit unit 12 may be provided on another substrate. Further, the imaging unit 11, the circuit unit 12, and the drive circuit unit 13 may be provided on the same substrate.

[0043] [Configuration Example 1 of Readout Circuit] FIG. 1B shows a configuration example of the circuit unit 12, which is a semiconductor device according to an aspect of the present invention. In FIG. 1B, as the circuit unit 12, an amplification unit PA[j] and a conversion unit ADC[j] corresponding to the j-th (j is an integer from 1 to n) wiring WX[j] are shown. Further, an input terminal IN included in the circuit unit 12 is shown in FIG. 1B. The wiring WX[j] is electrically connected to the input terminal IN.

[0044] The amplification unit PA[j] includes a comparison circuit AMP, a capacitor C1, a capacitor C2, a switch SW1, and the like. The comparison circuit AMP has an inverting input terminal, a non-inverting input terminal, and an output terminal. As the comparison circuit AMP, for example, a differential amplifier (also referred to as a differential amplification circuit) such as a comparator or an operational amplifier can be used.

[0045] One electrode of the capacitor C1 is electrically connected to the input terminal IN, and the other electrode is electrically connected to one terminal of the switch SW1, one electrode of the capacitor C2, and the inverting input terminal of the comparison circuit AMP. The other terminal of the switch SW1 is electrically connected to the other electrode of the capacitor C2 and the output terminal of the comparison circuit AMP. The output terminal of the comparison circuit AMP is electrically connected to the input terminal of the conversion unit ADC[j]. The non-inverting input terminal of the comparison circuit AMP is the reference potential V REFis electrically connected to the provided wiring.

[0046] In FIG. 1B, it can also be said that the switch SW1 and the capacitor C2 are connected in parallel to the inverting input terminal and the output terminal of the comparison circuit AMP, respectively.

[0047] 〔Example of driving method 1〕 The readout circuit according to one aspect of the present invention includes an amplification unit and a conversion unit. The amplification unit amplifies the potential difference between the first signal and the second signal input in order and outputs it to the conversion unit. The conversion unit converts the output potential of the amplification unit into a digital value. The amplification unit can be reset based on the first reference potential and the first signal, and amplify the potential difference based on the second reference potential different from the first reference potential and the second signal.

[0048] An example of the driving method of the circuit unit 12 shown in FIG. 1B will be described with reference to FIGS. 2A and 2B. Note that in FIGS. 2A and 2B, the conversion unit ADC[j] is omitted.

[0049] The operation of the amplification unit PA[j] is roughly divided into two operations: initialization and amplification. FIG. 2A corresponds to the operation related to initialization (also referred to as the initialization operation), and FIG. 2B corresponds to the operation related to amplification (also referred to as the amplification operation). In the following, the period related to the initialization operation is called the initialization period, and the period related to the amplification operation is called the amplification period.

[0050] First, the initialization operation of the amplification unit PA[j] will be described with reference to FIG. 2A. In the initialization operation, the switch SW1 is turned on. Also, during the initialization period, from the wiring WX[j], the potential V which is the potential of the first signal S is provided.

[0051] In the initialization operation, since the switch SW1 is in the conductive state, the output terminal and the inverting input terminal of the comparison circuit AMP are electrically short-circuited. Therefore, the output potential of the comparison circuit AMP becomes the same potential as the reference potential V REF At this time, the voltage V applied across the pair of electrodes of the capacitor C1 C1is the difference between the reference potential V REF and the potential V S . Also, since there is no potential difference between the pair of electrodes of the capacitor C2, the voltage V C2 applied to the capacitor C2 is 0V. As a result, the output potential V OUT of the amplifier section PA[j] during the initialization period is REF identical to the reference potential V

[0052] That is, during the initialization period, the voltage V C1 , the voltage V C2 , and the output potential V OUT are as follows.

[0053]

Equation

[0054] Subsequently, the amplification operation of the amplifier section PA[j] will be described with reference to FIG. 2B. In the amplification operation, first, the switch SW1 is set to the non-conductive state. Then, the potential of the wiring WX[j] changes from the potential V S of the first signal to the potential V R which is the potential of the second signal. Along with this, since the potential of the inverting input terminal of the comparator circuit AMP changes, the output potential of the comparator circuit AMP changes until the potential difference between the inverting input terminal and the non-inverting input terminal of the comparator circuit AMP becomes 0V. When the amplifier section PA[j] reaches the equilibrium state, the potential of the output terminal of the comparator circuit AMP is determined by the potential difference between the potential V S and the potential V R , the amplification factor G, and the reference potential V REF . Here, the amplification factor G of the amplifier section PA[j] is determined by the capacitance ratio of the capacitor C1 and the capacitor C2.

[0055] That is, during the amplification period, the output potential V OUT and the amplification factor G are as follows. In the following, the capacitance value of the capacitor C1 is denoted as C1, and the capacitance value of the capacitor C2 is denoted as C2.

[0056]

Equation

[0057] As described above, the amplification unit PA[j] can amplify the difference between the two input signals and output it to the conversion unit ADC[j]. As a result, the amplification unit PA[j] can output an output potential V that is free from the influence of variations in the pixel circuit of pixel 15 or a circuit provided between the pixel circuit and the amplification unit PA[j]. OUT can be output.

[0058] Here, in the comparison circuit AMP of the amplification unit PA[j], an offset voltage may occur between the inverting input terminal and the non-inverting input terminal. Due to the offset voltage, the inverting input terminal and the non-inverting input terminal in the balanced state may not be at the same potential. However, by taking the difference between the two types of output potentials V OUT output from the amplification unit PA[j], the influence of the offset voltage can be eliminated.

[0059] [Configuration Example 2 of the Readout Circuit] The amplification unit PA exemplified in FIG. 1B etc. above can amplify and output the difference between two input signals. However, when the potential difference between the two input signals is too large, a phenomenon may occur where the output potential saturates. Such a phenomenon where the output potential of the amplification circuit saturates can also be referred to as clipping. Clipping may occur, for example, because the comparison circuit of the amplification unit PA cannot output a voltage (potential) exceeding the power supply voltage.

[0060] Therefore, one aspect of the present invention exemplified below has a configuration with a function of switching the reference potential input to the comparison circuit during the initialization period and the amplification period. At this time, the reference potential during the amplification period is set to a lower potential than the reference potential during the initialization period. Thereby, even when the potential difference between the two input signals is large, clipping can be suitably suppressed.

[0061] Fig. 3 shows a configuration example of the circuit section 12, which will be exemplified below. The circuit section 12 shown in Fig. 3 is mainly different from the configuration shown in Fig. 1B in that the configuration of the wiring connected to the non-inverting input terminal of the comparison circuit AMP is different.

[0062] The amplification section PA[j] has a switch SW2 and a switch SW3.

[0063] One terminal of the switch SW2 is electrically connected to the wiring to which the reference potential V REFS is applied, and the other terminal is electrically connected to the non-inverting input terminal of the comparison circuit AMP. One terminal of the switch SW3 is electrically connected to the wiring to which the reference potential V REFR is applied, and the other terminal is electrically connected to the non-inverting input terminal of the comparison circuit AMP. In other words, the non-inverting input terminal of the comparison circuit AMP is electrically connected to the wiring to which the reference potential V REFS is applied via the switch SW2, and further electrically connected to the wiring to which the reference potential V REFR is applied via the switch SW3.

[0064] The reference potential V REFS and the reference potential V REFR are different potentials. The reference potential V REFS is preferably set to a potential higher than the reference potential V REFR . Depending on the driving method, the reference potential V REFR may be set to a potential higher than the reference potential V REFS . Here, as shown in Fig. 3, the potential difference between the reference potential V REFS and the reference potential V REFR is denoted as ΔV REF .

[0065] 〔Example of driving method 2〕 Hereinafter, the operation of the amplification section PA[j] exemplified in Fig. 3 will be described with reference to Figs. 4A and 4B. For parts that overlap with the above, detailed descriptions may be omitted or simplified.

[0066] First, the operation of the amplifier section PA[j] during the initialization period will be described with reference to FIG. 4A. During the initialization period, switches SW1 and SW2 are turned on, and switch SW3 is turned off. The non-inverting input terminal of the comparator circuit AMP is provided with the reference potential V REFS through switch SW2. Also, the potential V S which is the potential of the first signal is applied from the wiring WX[j].

[0067] Similar to the above, the output potential V OUT during the initialization period is consistent with the reference potential V REFS . That is, during the initialization period, the voltage V C1 , the voltage V C2 , and the output potential V OUT are as follows.

[0068]

Equation

[0069] Subsequently, the amplification operation will be described with reference to FIG. 4B. During the amplification period, switch SW1 is turned off. Also, switch SW2 is turned off and switch SW3 is turned on. As a result, the non-inverting input terminal of the comparator circuit AMP is provided with the reference potential V REFR through switch SW3. Also, the potential of the wiring WX[j] changes from the potential V S of the first signal to the potential V R of the second signal.

[0070] During the amplification period, the output potential V OUT when the amplifier section PA[j] reaches the equilibrium state is as follows.

[0071]

Equation

[0072] In this way, the amplifier section PA[j] has a potential difference ΔV REF which is the difference between the two reference potentials.and the potential difference ΔV between the two input signals S can be amplified and output. Thereby, the occurrence of clipping can be suitably suppressed.

[0073] For example, in the amplifier section PA[j] of FIG. 1B, when the potential V S is 6.0 V, the potential V R is 4.0 V, the amplification factor G is 10 times, the reference potential V REF is 4.5 V, and the power supply voltage of the comparison circuit AMP is 9.0 V. At this time, the output potential V OUT becomes 24.5 V, exceeding the upper limit of the power supply voltage, so clipping occurs.

[0074] On the other hand, in the amplifier section PA[j] of FIG. 3, when the potential V S is 6.0 V, the potential V R is 4.1 V, the amplification factor G is 10 times, the reference potential V REFS is 6.5 V, the reference potential V REFR is 4.5 V, and the power supply voltage of the comparison circuit AMP is 9.0 V. At this time, the potential difference ΔV S is 1.9 V, and the potential difference ΔV REF is 2.0 V. Therefore, the output potential V OUT becomes 5.5 V, which is within the range of the power supply voltage, so the occurrence of clipping can be suppressed.

[0075] However, even when the configuration shown in FIG. 3 is used, if the potential difference ΔV REFS between the reference potential V REFR and the reference potential V REF and the potential difference ΔV S between the two signals are too large, there is a risk of clipping occurring. Therefore, it is preferable to determine the value of the potential difference ΔV REF in advance according to the signal width that the pixel circuit can output. Alternatively, the value of the potential difference ΔV REF may be changed according to the drive mode of the imaging device, the illuminance of the environment in which the imaging device is used, etc.

[0076] Also, depending on the drive mode of the imaging device, the illuminance of the environment in which the imaging device is used, etc., the potential difference ΔV between the two signalsS may be small enough. In this case, the read operation may be performed using either the reference potential V REFS or the reference potential V REFR . Specifically, during both the initialization period and the amplification period, the read operation may be performed with either switch SW2 or switch SW3 in the conductive state and the other in the non-conductive state. At this time, the driving method of switching the reference potential according to the driving mode of the imaging device or the environment in which the imaging device is used, and the driving method of fixing the reference potential can be switched. As a result, without changing the circuit configuration illustrated in FIG. 3, two types of read operations can be performed, enabling more accurate imaging.

[0077] [Configuration Example 2 of Imaging Device] Hereinafter, a more specific configuration example of the imaging device will be described.

[0078] FIG. 5A shows a circuit diagram of the imaging device. In FIG. 5A, as elements provided on the substrate 21, a circuit diagram of the pixel 15[i,j] at the i-th row and j-th column, and the current source I C [j] and the CDS circuit CDS[j] are shown. Here, only one pixel 15[i,j] connected to the wiring WX[j] is shown, but actually, m pixels 15 are connected to one wiring WX[j].

[0079] Also, in FIG. 5A, as elements provided on the substrate 22, the amplification unit PA[j] and the conversion unit ADC[j] are shown. The configurations of the amplification unit PA[j] and the conversion unit ADC[j] can be applied to the above description.

[0080] The pixel 15[i,j] includes transistors M1, M2, M3, M4, a capacitor C, a light receiving element PD, etc. Also, the wiring TX[i], the wiring SE[i], the wiring RS[i], and the wiring WX[j] are connected to the pixel 15[i,j].

[0081] Transistor M1 has its gate electrically connected to wiring TX[i], one of its source and drain electrically connected to the anode of light-receiving element PD, the other of its source and drain electrically connected to one of the source and drain of transistor M2, the first electrode of capacitor C, and the gate of transistor M3, respectively. Transistor M2 has its gate electrically connected to wiring RS[i], and the other of its source and drain electrically connected to the wiring to which potential V1 is applied, respectively. One of the source and drain of transistor M3 is electrically connected to the wiring to which potential V3 is applied, and the other is electrically connected to one of the source and drain of transistor M4, respectively. Transistor M4 has its gate electrically connected to wiring SE[i], and the other of its source and drain electrically connected to wiring WX[j], respectively. Capacitor C has its second electrode electrically connected to the wiring to which potential V2 is applied. Light-receiving element PD has its cathode electrically connected to wiring CL to which the cathode potential is applied.

[0082] Transistors M1, M2, and M4 function as switches. Transistor M3 functions as an amplification element (amplifier).

[0083] It is preferable to apply transistors (hereinafter referred to as Si transistors) using silicon (including single-crystalline silicon, polycrystalline silicon, and low-temperature polycrystalline silicon (LTPS)) for the semiconductor in which the channel is formed to all of transistors M1 to M4. Alternatively, it is preferable to apply transistors (hereinafter referred to as OS transistors) using an oxide semiconductor for the semiconductor in which the channel is formed to all of transistors M1 to M4.

[0084] Also, both Si transistors and OS transistors may be used. For example, it is preferable to apply OS transistors to transistors M1 and M2, and apply Si transistors to transistor M3. At this time, either an OS transistor or an Si transistor may be applied to transistor M4.

[0085] By applying an OS transistor to transistor M1 and transistor M2, it is possible to prevent the potential held at the gate of transistor M3 from leaking through transistor M1 or transistor M2 based on the charge generated in the light receiving element PD.

[0086] As the OS transistor, a transistor using an oxide semiconductor for the semiconductor layer in which a channel is formed can be used. The semiconductor layer preferably has, for example, indium, M (where M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin. In particular, it is preferable to use an oxide (also referred to as IGZO) containing indium, gallium, and zinc as the semiconductor layer of the OS transistor. Alternatively, it is preferable to use an oxide containing indium, tin, and zinc. Alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc.

[0087] A transistor using an oxide semiconductor having a wider bandgap and a lower carrier density than silicon can achieve an extremely small off-current. Therefore, due to its small off-current, it is possible to hold the charge accumulated in the capacitor connected in series with the transistor for a long period of time. Therefore, in particular, for transistors M1 and M2 connected in series to capacitor C, it is preferable to use transistors to which an oxide semiconductor is applied. By applying transistors having an oxide semiconductor as transistors M1 and M2, it is possible to prevent the charge held in capacitor C from leaking through transistor M1 or transistor M2. In addition, since the charge held in capacitor C can be held for a long time, the period from exposure to reading can be extended.

[0088] For example, when imaging is performed using the global shutter method, the period (charge holding period) from when the charge transfer operation is completed by a pixel until the readout operation starts differs among pixels. For example, when imaging an image in which the gradation values are equal for all pixels, ideally, output signals having the same potential height are obtained for all pixels. However, when the length of the charge holding period differs for each row, if the charge accumulated in the nodes of the pixels in each row leaks over time, the potential of the output signal of the pixel will differ for each row, and image data with a changed gradation number for each row will be obtained. Therefore, by applying OS transistors as transistors M1 and M2, the potential change of the node can be made extremely small. That is, even when imaging is performed using the global shutter method, the change in gradation of the image data due to the difference in the charge holding period can be suppressed to a small level, and the quality of the captured image can be improved.

[0089] On the other hand, it is preferable to apply an Si transistor to transistor M3. An Si transistor can achieve a higher field-effect mobility than an OS transistor and is excellent in driving ability and current ability. Therefore, transistor M3 can operate at a higher speed compared to transistors M1 and M2. By using an Si transistor for transistor M3, an output corresponding to a minute potential based on the amount of light received by the light-receiving element PD can be quickly performed for transistor M4.

[0090] That is, in pixel 15[i,j], transistors M1 and M2 have a small leakage current, and transistor M3 has a high driving ability, so that the charge received by the light-receiving element PD and transferred through transistor M1 can be held without leaking and can be read out at high speed.

[0091] Since transistor M4 functions as a switch that allows the output from transistor M3 to flow through wiring WX[j], small off-current and high-speed operation, etc., like those of transistors M1 to M3, are not necessarily required. Therefore, an Si transistor or an OS transistor may be applied to transistor M4.

[0092] In addition, in FIG. 5A, although the transistors are shown as n-channel type transistors, p-channel type transistors can also be used.

[0093] Each transistor included in pixel 15[i,j], the transistors included in CDS circuit CDS[j], current source I C [j], etc. are preferably fabricated on substrate 21 through the same process.

[0094] Current source I C [j] is connected in series to the wiring WX[j] connected to pixel 15[i,j]. Current source I C [j] and the transistor M3 included in pixel 15[i,j] constitute a source follower circuit.

[0095] Current source I C [j] is not particularly limited in its configuration, and for example, a transistor with a constant potential applied to its gate or a current mirror circuit can be used.

[0096] Also, CDS circuit CDS[j] is connected to wiring WX[j]. CDS circuit CDS[j] is a circuit capable of performing correlated double sampling.

[0097] The output terminal of CDS circuit CDS[j] is connected to the input terminal of amplifier section PA[j]. The signal sampled by CDS circuit CDS[j] is output to amplifier section PA[j].

[0098] In circuit section 12, as an output signal from conversion section ADC[j], signal S OUT[j] is output. Signal S OUT [j] is a digital signal converted from an analog signal by the conversion unit ADC[j]. Signal S OUT [j] is output to an arithmetic circuit or the like provided outside the imaging device and is processed.

[0099] 〔Example of pixel driving method〕 Here, the driving method of pixel 15[i, j] will be described. FIG. 5B is a timing chart regarding the driving method of pixel 15[i, j]. In FIG. 5B, the potential transitions of wiring TX[i], wiring SE[i], wiring RS[i], and wiring WX[j] are shown respectively.

[0100] The driving of pixel 15[i, j] is roughly divided into an imaging period T1 and a readout period T2. During the imaging period T1, imaging is performed on all pixels of the imaging unit 11, and then by sequentially reading out each row during the subsequent readout period T2, global shutter driving can be realized. On the other hand, by providing an imaging period T1 and a readout period T2 for each row, rolling shutter driving can be realized.

[0101] The imaging period T1 is divided into a period T11, a period T12, and a period T13. The period T11 corresponds to the reset period of the pixel, the period T12 corresponds to the exposure period, and the period T13 corresponds to the transfer period.

[0102] During the period T11, the wiring TX[i] and the wiring RS[i] become high-level potentials. Thereby, the transistors M1 and M2 become conductive states, and the potential of the anode of the light-receiving element PD is reset to the potential V1.

[0103] Subsequently, during the period T12, the wiring TX[i] and the wiring RS[i] become low-level potentials. Thereby, the transistor M1 becomes a non-conductive state. During the period T12, photoelectric conversion occurs due to the light incident on the light-receiving element PD, and charges are accumulated at the anode of the light-receiving element PD.

[0104] Subsequently, in period T13, the wiring TX[i] becomes a high-level potential. As a result, the transistor M1 becomes conductive, and the charge accumulated in the light-receiving element PD is transferred to the capacitor C.

[0105] Thereafter, a low-level potential is applied to the wiring TX[i], and the transistor M1 becomes non-conductive, thereby holding the charge in the capacitor C.

[0106] The read period T2 is divided into a period T21 and a period T22. In the period T21, a signal including the received light potential is output, and in the period T22, a signal including the reset potential is output.

[0107] In global shutter driving, after the imaging period T1, a read operation is performed for each row. In FIG. 5B, the read period T2[i] of the i-th row is shown.

[0108] In the period T21, a high-level potential is applied to the wiring SE[i]. As a result, the transistor M4 becomes conductive. At this time, a source follower circuit is formed by the transistor M3 and the current source I C [j], and a data signal D is output to the CDS circuit CDS[j] via the wiring WX[j]. S At this time, the potential of the data signal D S output to the wiring WX[j] is determined according to the gate potential of the transistor M3. The data signal D S corresponds to the first signal (received light signal).

[0109] Subsequently, in the period T22, high-level potentials are applied to the wiring SE[i] and the wiring RS[i]. As a result, the transistors M2 and M4 become conductive. As a result, a potential V1 is applied to the gate of the transistor M3. That is, the pixel 15[i,j] is in a reset state. In the period T22, the data signal D R in this state is output to the wiring WX[j]. The data signal D R corresponds to the second signal (reset signal).

[0110] By driving in this manner, in the read period T2, the first signal and the second signal can be sequentially output from the pixel 15[i,j] to the wiring WX[j].

[0111] The above is the description of the driving method of the pixel circuit.

[0112] [Configuration Example 3 of Imaging Device] FIG. 6 shows a configuration example of an imaging device whose configuration is partially different from that of FIG. 5A above. The imaging device shown in FIG. 6 has a multiplexer circuit MUX between a plurality of CDS circuits and an amplifier section PA.

[0113] Here, a configuration is shown in which the outputs from the j-th pixel 15[i,j] to the k-th pixel 15[i,k] among the n pixels 15 in the i-th column are output to the amplifier section PA via one multiplexer circuit MUX.

[0114] Also, as shown in FIG. 6, a CDS circuit CDS may be provided between each pixel 15 and the multiplexer circuit MUX.

[0115] With such a configuration, the number of connection terminals between the substrate 21 and the substrate 22 can be reduced. In particular, when the substrate 22 is made into a chip and the IC chip having the substrate 22 is mounted by bonding it to the substrate 21 or another circuit board using bumps or the like, reducing the number of terminals of the substrate 22 greatly contributes to reducing the chip size, which is preferable.

[0116] [Configuration Example of Display Device] Hereinafter, a display device having both a function of displaying an image and a function of imaging an image will be described.

[0117] A display device according to an aspect of the present invention includes a display unit having a light receiving element (also referred to as a light receiving device) and a light emitting element (also referred to as a light emitting device). In the display unit, the light emitting elements are arranged in a matrix, and an image can be displayed on the display unit using the light emitting elements. Further, in the display unit, the light receiving elements are arranged in a matrix, and the display unit has a function as a light receiving unit. Since an image can be captured by a plurality of light receiving elements provided in the display unit, the display device can function as an image sensor, a touch panel, or the like. That is, an image can be captured by the display unit, and proximity or contact of an object (such as a finger or a pen) can be detected. Furthermore, since the light emitting elements provided in the display unit can be used as a light source during light reception, there is no need to provide a light source separately from the display device, and a highly functional display device can be realized without increasing the number of parts of the electronic device.

[0118] According to an aspect of the present invention, when the light emitted from the light emitting element of the display unit is reflected by an object, the light receiving element can detect the reflected light, so that imaging and touch (including non-contact) detection can be performed even in a dark environment.

[0119] In addition, the display device according to an aspect of the present invention can capture a fingerprint or a palmprint when a finger, a palm, or the like touches the display unit. Therefore, an electronic device including the display device according to an aspect of the present invention can perform personal authentication using the captured fingerprint. As a result, there is no need to separately provide an imaging device for fingerprint authentication or palmprint authentication, and the number of parts of the electronic device can be reduced. Further, since the light receiving elements are arranged in a matrix in the display unit, imaging of a fingerprint, a palmprint, or the like can be performed at any location within the display unit, and an electronic device with excellent convenience can be realized.

[0120] Here, the display unit may be configured such that a first pixel circuit including a light receiving element and one or more transistors and a second pixel circuit including a light emitting element and one or more transistors are each arranged in a matrix.

[0121] Hereinafter, a more specific configuration example will be described with reference to the drawings.

[0122] Figure 7A shows a block diagram of the display device 50. The display device 50 includes a display unit 51, a circuit unit 52, a drive circuit unit 53, and the like.

[0123] In Figure 7A, an example is shown in which the display unit 51 and the drive circuit unit 53 are provided on the substrate 21, and the circuit unit 52 is provided on the substrate 22. The substrate 22 is preferably chip-sized and in the form of an IC chip. At this time, the IC chip having the substrate 22 is preferably bonded to the substrate 21 or an FPC (Flexible Printed Circuit) connected to the substrate 21 by an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or bumps. Note that the display unit 51 and the drive circuit unit 53 may be provided on separate substrates. Alternatively, the display unit 51, the circuit unit 52, and the drive circuit unit 53 may be provided on one substrate.

[0124] The display unit 51 has a plurality of pixels 70 arranged in a matrix. The pixel 70 includes a sub-pixel 61R, a sub-pixel 61G, a sub-pixel 61B, and an imaging pixel 62. The sub-pixel 61R, the sub-pixel 61G, and the sub-pixel 61B each have a light-emitting element that functions as a display element. The imaging pixel 62 has a light-receiving element that functions as a photoelectric conversion element.

[0125] The pixel 70 is electrically connected to wirings such as a wiring GL, a wiring SLR, a wiring SLG, a wiring SLB, a wiring TX, a wiring SE, a wiring RS, and a wiring WX. The wirings SLR, SLG, SLB, and WX are electrically connected to the circuit unit 52. The wirings GL, TX, SE, and RS are electrically connected to the drive circuit unit 53. The circuit unit 52 has a function as a source line drive circuit (also referred to as a source driver) and a function as a readout circuit. The drive circuit unit 53 has a function as a gate line drive circuit (also referred to as a gate driver) and a function as a drive circuit for the imaging pixel 62.

[0126] Pixel 70 has sub-pixels 61R, sub-pixels 61G, and sub-pixels 61B. For example, sub-pixel 61R is a sub-pixel that exhibits red, sub-pixel 61G is a sub-pixel that exhibits green, and sub-pixel 61B is a sub-pixel that exhibits blue. Thereby, display device 50 can perform full-color display. Here, an example in which pixel 70 has three-color sub-pixels is shown, but it may have four or more color sub-pixels.

[0127] Sub-pixels 61R, sub-pixels 61G, and sub-pixels 61B each have a light-emitting element and a pixel circuit. The pixel circuit has a function of controlling the gradation of the light-emitting element based on a signal (potential) supplied from circuit unit 52 and input via wiring SLR, wiring SLG, or wiring SLB.

[0128] Sub-pixel 61R has a light-emitting element that exhibits red light. Sub-pixel 61G has a light-emitting element that exhibits green light. Sub-pixel 61B has a light-emitting element that exhibits blue light. Note that pixel 70 may have a sub-pixel having a light-emitting element that exhibits other light. For example, in addition to the above three sub-pixels, pixel 70 may have a sub-pixel having a light-emitting element that exhibits white light, or a sub-pixel having a light-emitting element that exhibits yellow light.

[0129] Wiring GL is electrically connected to sub-pixels 61R, sub-pixels 61G, and sub-pixels 61B arranged in the row direction (the extending direction of wiring GL). Wiring SLR is electrically connected to a plurality of sub-pixels 61R (not shown) arranged in the column direction (the extending direction of wiring SLR etc.). Similarly, wiring SLG and wiring SLB are electrically connected to a plurality of sub-pixels 61G or sub-pixels 61B (not shown) arranged in the column direction, respectively.

[0130] The imaging pixel 62 included in pixel 70 has wiring TX, wiring SE, wiring RS, and wiring WX electrically connected thereto.

[0131] The drive circuit unit 53 has a function of generating a signal for driving the imaging pixel 62 and outputting the signal to the imaging pixel 62 via the wiring SE, the wiring TX, and the wiring RS. The circuit unit 52 has a function of receiving a signal output from the imaging pixel 62 via the wiring WX and outputting the signal to the outside as image data. The circuit unit 52 functions as a readout circuit.

[0132] 〔Configuration Example 1 of Pixel Circuit〕 FIG. 7B shows an example of a circuit diagram of the pixel 61 that can be applied to the sub-pixel 61R, the sub-pixel 61G, and the sub-pixel 61B. The pixel 61 includes a transistor M5, a transistor M6, a transistor M7, a capacitor C11, and a light-emitting element EL. Further, a wiring GL and a wiring SL are electrically connected to the pixel 61. The wiring SL corresponds to any one of the wirings SLR, SLG, and SLB shown in FIG. 7A.

[0133] The gate of the transistor M5 is electrically connected to the wiring GL, one of the source and the drain is electrically connected to the wiring SL, and the other is electrically connected to one electrode of the capacitor C11 and the gate of the transistor M6. One of the source and the drain of the transistor M6 is electrically connected to the wiring AL, and the other of the source and the drain is electrically connected to one electrode of the light-emitting element EL, the other electrode of the capacitor C11, and one of the source and the drain of the transistor M7. The gate of the transistor M7 is electrically connected to the wiring GL, and the other of the source and the drain is electrically connected to the wiring RL. The other electrode of the light-emitting element EL is electrically connected to the wiring CL.

[0134] The transistor M5 and the transistor M7 function as switches. The transistor M6 functions as a transistor for controlling the current flowing through the light-emitting element EL.

[0135] Here, it is preferable to apply Si transistors to all of transistors M5 to M7. In particular, as the Si transistor, it is preferable to use a transistor (LTPS transistor) in which LTPS is applied to the semiconductor in which the channel is formed. Alternatively, it is preferable to apply OS transistors to all of transistors M5 to M7. Alternatively, it is preferable to apply OS transistors to transistors M5 and M7, and apply an LTPS transistor to transistor M6.

[0136] The OS transistor can realize an extremely small off-current. Therefore, it is particularly preferable to use transistors in which an oxide semiconductor is applied to transistors M5 and M7 connected in series to capacitor C11, respectively. Thereby, it is possible to prevent the charge held in capacitor C1 from leaking through transistor M5 or transistor M7. In addition, since the charge held in capacitor C11 can be held for a long time, it is possible to display a still image for a long time without rewriting the data of pixel 61.

[0137] A data potential is applied to wiring SL. A selection signal is applied to wiring GL. The selection signal includes a potential that turns on the transistor and a potential that turns off the transistor.

[0138] A reset potential is applied to wiring RL. An anode potential is applied to wiring AL. A cathode potential is applied to wiring CL. In pixel 61, the anode potential is set to a potential higher than the cathode potential. Further, the reset potential applied to wiring RL can be set to a potential such that the potential difference between the reset potential and the cathode potential is smaller than the threshold voltage of light-emitting element EL. The reset potential can be a potential higher than the cathode potential, the same potential as the cathode potential, or a potential lower than the cathode potential.

[0139] FIG. 7C shows an example of the circuit diagram of the imaging pixel 62. The imaging pixel 62 has the same configuration as the pixel 15[i,j] illustrated in FIG. 5A. Since the configuration shown in FIG. 7C is the same as that in FIG. 5A except that the capacitor C is replaced with the capacitor C12, the above description can be incorporated by reference for the detailed description.

[0140] Note that, as the transistors included in the pixel 61 and the imaging pixel 62, a transistor having a pair of gates overlapping via a semiconductor layer can also be applied.

[0141] In a transistor having a pair of gates, by configuring the pair of gates to be electrically connected to each other and supplied with the same potential, there are advantages such as an increase in the on-current of the transistor and an improvement in saturation characteristics. Further, a potential for controlling the threshold voltage of the transistor may be applied to one of the pair of gates. Further, by applying a fixed potential to one of the pair of gates, the stability of the electrical characteristics of the transistor can be improved. For example, one of the gates of the transistor may be configured to be electrically connected to a wiring supplied with a fixed potential, or may be configured to be electrically connected to its own source or drain.

[0142] [Example of Configuration of Circuit Section] Subsequently, an example of a configuration that can be used for the circuit section 52 will be described.

[0143] [Configuration Example 1] FIG. 8A shows the circuit diagram of the circuit section 52. FIG. 8A shows some components corresponding to the j-th wiring WX[j] and the wiring SL[j]. The wiring SL[j] corresponds to any one of the j-th wirings SLR[j], SLG[j], and SLB[j] (not shown). Further, FIG. 8A shows an input terminal IN to which the wiring WX[j] is connected and an output terminal OUT to which the wiring SL[j] is connected.

[0144] The circuit section 52 includes an amplification section PA[j], a conversion section ADC[j], an amplification section VA[j], and a conversion section DAC[j].

[0145] The amplification unit PA[j] and the conversion unit ADC[j] have the same configuration as that in FIG. 1B above. The amplification unit PA[j] includes a comparison circuit AMP1, a capacitor C1, a capacitor C2, and a switch SW1. The conversion unit ADC[j] converts the analog potential input from the amplification unit PA[j] into a digital potential, and outputs it as a digital signal S OUT [j] to the outside.

[0146] The conversion unit DAC[j] has a function of receiving the digital signal S[j], converting it into an analog potential V DATA , and outputting it to the amplification unit VA[j]. The conversion unit DAC[j] functions as a digital-to-analog conversion circuit. The signal S[j] can also be called a video signal.

[0147] The amplification unit VA[j] outputs the input potential V DATA to the wiring SL[j]. The amplification unit VA[j] functions as a video amplifier.

[0148] FIG. 8A shows an example in which the amplification unit VA[j] includes a comparison circuit AMP2. The output terminal and the inverting input terminal of the comparison circuit AMP2 are electrically connected, and the potential V DATA output from the conversion unit DAC[j] is input to the non-inverting input terminal. The output terminal of the comparison circuit AMP2 is electrically connected to the output terminal OUT to which the wiring SL[j] is connected. Thereby, the potential V DATA can be stably output to the wiring SL[j].

[0149] By providing the amplification unit PA[j], the conversion unit ADC[j], the amplification unit VA[j], and the conversion unit DAC[j] on the substrate 22 and chipifying the substrate 22 into the form of an IC, the source line drive circuit and the readout circuit in the display device 50 can be realized by one IC. Thereby, the number of components of the display device 50 and the electronic device to which the display device 50 is applied can be reduced. Thereby, the manufacturing cost of the display device 50 and the electronic device to which the display device 50 is applied can be reduced.

[0150] 〔Configuration Example 2〕 In FIG. 8B, FIG. 3 shows a configuration example of the circuit unit 52 when the configuration exemplified in FIG. 3 is applied as the amplification unit PA[j].

[0151] In the amplification unit PA[j], a wiring to which a reference potential V is applied via a switch SW2 and a wiring to which a reference potential V is applied via a switch SW3 are connected to the non-inverting input terminal of the comparison circuit AMP1, respectively. REFS A wiring to which is applied and a wiring to which is applied via a switch SW3 are each connected. REFR are each connected.

[0152] Regarding the example of the driving method of the amplification unit PA[j], the above description can be incorporated by reference. With such a configuration, the occurrence of clipping in the read operation can be preferably suppressed.

[0153] 〔Configuration Example 3〕 FIG. 9A shows a configuration example of the circuit unit 52 in which a part of the configuration is different from the above.

[0154] In FIG. 9A, the output terminal of the comparison circuit AMP2 included in the amplification unit VA[j] is electrically connected to the non-inverting input terminal of the comparison circuit AMP1 included in the amplification unit PA[j]. Therefore, the output potential of the amplification unit VA[j] is given as a reference potential to the non-inverting input terminal of the comparison circuit AMP1.

[0155] In addition, the signal S[j] input to the conversion unit DAC[j] includes, in addition to video data, data of two types of reference potentials used for the operation of the amplification unit PA[j]. Therefore, the analog potential output from the conversion unit DAC[j] is the potential V, the reference potential V, and the reference potential V, and the three types of potentials are output in different periods. DATA reference potential V REFS and reference potential V REFR are output in different periods.

[0156] During the writing period to each pixel of the display unit 51, based on the video data included in the signal S[j], the potential V is applied to the wiring SL[j] via the output terminal OUT. DATAare sequentially output. During the imaging period using the imaging pixels 62 of the display unit 51, based on the data of the reference potential included in the signal S[j], the reference potential V REFS and the reference potential V REFR are output in sequence.

[0157] With such a configuration, for example, in the configuration illustrated in FIG. 8B, the switch SW2, the switch SW3, the wiring to which the reference potential V REFS is applied, and the wiring to which the reference potential V REFR is applied, etc. can be omitted. Also, the circuit and wiring for controlling the switch SW2 and the switch SW3 can be omitted. Thereby, the configuration of the circuit unit 52 can be simplified. Further, since a power supply circuit (potential generation circuit) for generating the reference potential V REFS and the reference potential V REFR becomes unnecessary, not only can the configuration be simplified, but it can also contribute to reducing power consumption.

[0158] Here, the case where the conversion unit DAC[j] outputs two types of reference potentials (reference potential V REFS , reference potential V REFR ) and the amplification unit PA[j] uses a driving method of switching between the two reference potentials has been described, but a configuration in which the reference potential is not switched may be used. That is, the signal S[j] can be changed so that one type of reference potential (reference potential V REF ) is output from the conversion unit DAC[j]. In this way, the configuration shown in FIG. 9A can easily switch the driving method of the readout circuit depending on the signal given as the signal S[j]. Also, by changing the data of the reference potential included in the signal S[j], the optimization of the value of the reference potential can be easily performed without changing the circuit configuration.

[0159] 〔Configuration Example 4〕 FIG. 9B shows an example of the circuit unit 52 having a configuration different from the above.

[0160] To the non-inverting input terminal of the comparison circuit AMP1 included in the amplifier section PA[j], a wiring through which the reference potential V REFS is supplied, a wiring through which the reference potential V REFR is supplied, and the output terminal of the amplifier section VA[j] through the switch SW4 are respectively connected.

[0161] The configuration shown in FIG. 9B can drive the amplifier section PA[j] by the method exemplified in FIGS. 3, 4A, and 4B by setting the switch SW4 to the non-conductive state. By setting the switch SW4 to the non-conductive state, the output terminal OUT and the amplifier section PA[j] are electrically disconnected. As a result, it becomes possible to perform the data writing operation to the pixel 70 of the display section 51 and the data reading operation from the imaging pixel 62 in parallel. Thereby, it becomes possible to execute high-speed imaging.

[0162] Also, by setting the switch SW4 to the conductive state, the amplifier section PA[j] can be driven based on the reference potential included in the signal S[j] and analog-converted by the conversion section DAC[j]. With such a configuration, the amplifier section PA[j] can be driven using a reference potential other than the preset reference potential V REFS and the reference potential V REFR .

[0163] As described above, in the circuit section 52 shown in FIG. 9B, the driving method of the amplifier section PA[j] can be switched by controlling the switch SW4. For example, it becomes easy to select and switch the optimal driving method according to the imaging mode or the illuminance of external light.

[0164] 〔Modification Example〕 The circuit section 52 shown in FIG. 10A is an example in which the switch SW4 shown in FIG. 9B is added to the configuration shown in FIG. 9A.

[0165] During the writing period to each pixel of the display section 51, the circuit section 52 shown in FIG. 10A sets the switch SW4 to the non-conductive state, so that the potential V DATASince it can be prevented from being input to the comparison circuit AMP1, the load of the amplification unit VA[j] can be reduced. Also, during the imaging period, by setting the switch SW4 to the conducting state, the reference potential V REFS or the reference potential V REFR can be output to the comparison circuit AMP1. Alternatively, only the reference potential V REF may be output to the comparison circuit AMP1.

[0166] The circuit section 52 shown in FIG. 10B is an example in which a switch SW5 is further added to the configuration shown in FIG. 10A. One terminal of the switch SW5 is electrically connected to the output terminal OUT, and the other terminal is electrically connected to one terminal of the switch SW4 and the output terminal of the comparison circuit AMP2.

[0167] The switch SW5 can be set to the conducting state during the writing period to each pixel of the display unit 51 and to the non-conducting state during the imaging period. Thereby, during the imaging period, the amplification unit VA[j] and the wiring SL[j] can be electrically disconnected, so that the load of the amplification unit VA[j] can be reduced.

[0168] Note that in FIG. 10B, a configuration without the switch SW4 may be adopted. That is, a configuration in which only the switch SW5 is added to the circuit section 52 shown in FIG. 9A may be adopted.

[0169] Also, the circuit section 52 shown in FIG. 10C is an example in which a switch SW5 is further added to the configuration illustrated in FIG. 9B.

[0170] The above is the description of the configuration example of the circuit section.

[0171] [Configuration Example of Connection Section] Hereinafter, a configuration example of the connection section between the substrate 21 and the substrate 22 will be described.

[0172] As described above, when the substrate 22 is diced and the IC chip including the substrate 22 is bonded to the substrate 21 or the like, reducing the number of terminals between them is important for meeting requirements such as cost reduction and miniaturization of electronic devices. Hereinafter, the configuration of the connection portion capable of reducing the number of terminals will be described.

[0173] 〔Configuration Example 1〕 FIG. 11A shows a part of the substrate 21 and the substrate 22 and the configuration of the connection portion therebetween. The substrate 21 has terminals 31, and the substrate 22 has terminals 32. Further, the terminals 31 and 32 are connected by a wiring 33.

[0174] The wiring 33 is not limited to wiring and can take various forms to achieve electrical connection between the terminals 31 and 32. For example, one or more of bumps, plugs, connectors, FPCs, ACFs, ACPs, etc. can be used for the wiring 33.

[0175] The substrate 21 is provided with a wiring WX[j], a wiring SL[j], and a selection circuit SEL1[j]. Here, the wiring SL[j] corresponds to any one of a wiring SLR[j], a wiring SLG[j], and a wiring SLB[j] (not shown).

[0176] The selection circuit SEL1[j] is electrically connected to the wiring WX[j], the wiring SL[j], and the terminal 31. The selection circuit SEL1[j] is a circuit that selects either the wiring WX[j] or the wiring SL[j] and electrically connects it to the terminal 31. Thereby, for example, the wiring WX[j] or the wiring SL[j] is electrically connected to the wiring 33 via the terminal 31.

[0177] The substrate 22 is provided with a selection circuit SEL2[j], an amplification unit PA[j], a conversion unit ADC[j], an amplification unit VA[j], and a conversion unit DAC[j]. The configurations of the amplification unit PA[j], the conversion unit ADC[j], the amplification unit VA[j], and the conversion unit DAC[j] can be applied by referring to the above description. In FIG. 11A, the amplification unit PA[j] and the amplification unit VA[j] are simply indicated using circuit symbols.

[0178] The selection circuit SEL2[j] has its input terminal of the amplification unit PA[j], the output terminal of the amplification unit VA[j], and the terminal 32 electrically connected. The selection circuit SEL2[j] is a circuit that selects either the wiring to which the input terminal of the amplification unit PA[j] is connected or the wiring to which the output terminal of the amplification unit VA[j] is connected and electrically connects it to the terminal 32. As a result, for example, the wiring to which the input terminal of the amplification unit PA[j] is connected or the wiring to which the output terminal of the amplification unit VA[j] is connected is conducted to the wiring 33 via the terminal 32.

[0179] During the writing period to each pixel of the display unit 51, the selection circuit SEL1[j] selects the wiring SL[j], and the selection circuit SEL2[j] selects the wiring to which the output terminal of the amplification unit VA[j] is connected. As a result, the potential V DATA generated by the conversion unit DAC[j] is output to the wiring SL[j] via the selection circuit SEL2[j], the terminal 32, the wiring 33, the terminal 31, and the selection circuit SEL1[j].

[0180] On the other hand, during the imaging period using the imaging pixel 62 of the display unit 51, the selection circuit SEL1[j] selects the wiring WX[j], and the selection circuit SEL2[j] selects the wiring to which the input terminal of the amplification unit PA[j] is connected. As a result, the potential V S , which is the potential of the first signal input from the wiring WX[j], and the potential V R , which is the potential of the second signal, are input to the amplification unit PA[j] via the selection circuit SEL1[j], the terminal 31, the wiring 33, the terminal 32, and the selection circuit SEL2[j].

[0181] With such a configuration, the number of terminals for connecting the substrate 21 and the substrate 22 can be reduced.

[0182] 〔Configuration Example 2〕 In the example shown in FIG. 11B, the wiring WX[j], the wiring SLR[j], the wiring SLG[j], and the wiring SLB[j] are connected to the selection circuit SEL1[j] provided on the substrate 21.

[0183] The selection circuit SEL1[j] has a function of selecting any one of the wiring WX[j], the wiring SLR[j], the wiring SLG[j], and the wiring SLB[j] and electrically connecting it to the terminal 31. For example, the wiring WX[j], the wiring SLR[j], the wiring SLG[j], or the wiring SLB[j] is electrically connected to the wiring 33 via the terminal 31.

[0184] On the other hand, on the substrate 22, the signals SR[j], SG[j], and SB[j] are input to the conversion unit DAC[j] at different times. The signal SR[j] is a signal including the data potential output to the wiring SLR[j]. Similarly, the signal SG[j] is a signal including the data potential output to the wiring SLG[j], and the signal SB[j] is a signal including the data potential output to the wiring SLB[j].

[0185] During the writing period to each pixel of the display unit 51, the selection circuit SEL1[j] sequentially selects the wiring SLR[j], the wiring SLG[j], and the wiring SLB[j], and the selection circuit SEL2[j] selects the wiring to which the output terminal of the amplification unit VA[j] is connected. As a result, data potentials are sequentially output to the wiring SLR[j], the wiring SLG[j], and the wiring SLB[j].

[0186] On the other hand, during the imaging period using the imaging pixel 62 of the display unit 51, the selection circuit SEL1[j] selects the wiring WX[j], and the selection circuit SEL2[j] selects the wiring to which the input terminal of the amplification unit PA[j] is connected. As a result, the potential V S and the potential V R are input to the amplification unit PA[j].

[0187] Here, an example in which three source lines (the wiring SLR[j], the wiring SLG[j], and the wiring SLB[j]) are connected to the selection circuit SEL1[j] is shown, but the present invention is not limited to this, and two or four or more may be used. In particular, it is preferable to connect source lines that are multiples of three.

[0188] With such a configuration, the number of terminals for connecting the substrate 21 and the substrate 22 can be further reduced.

[0189] Here, the configurations of the selection circuits SEL1[j] and SEL2[j] are not particularly limited and can take various configurations. For example, a circuit having a plurality of analog switches and capable of controlling conduction and non-conduction of wiring by the analog switches can be preferably used.

[0190] The above is the description of the configuration example of the terminal portion.

[0191] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be appropriately combined with at least a part of other configuration examples, or drawings, etc.

[0192] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0193] (Embodiment 2) In this embodiment, a configuration example of a display device according to an aspect of the present invention will be described.

[0194] The display device exemplified below includes a light-emitting element and a light-receiving element. The display device has a function of displaying an image, a function of performing position detection using reflected light from a detected object, and a function of imaging a fingerprint or the like using reflected light from the detected object. It can also be said that the display device exemplified below has a function as a touch panel and a function as a fingerprint sensor.

[0195] A display device according to an aspect of the present invention includes a light-emitting element (light-emitting device) that emits a first light and a light-receiving element (light-receiving device) that receives the first light. That is, the light-receiving element is an element whose light-receiving wavelength range includes the emission wavelength of the light-emitting element. The light-receiving element is preferably a photoelectric conversion element. As the first light, visible light or infrared light can be used. When infrared light is used as the first light, in addition to the light-emitting element that emits the first light, a configuration having a light-emitting element that emits visible light can be adopted.

[0196] In addition, the display device has a pair of substrates (also referred to as the first substrate and the second substrate). The light-emitting element and the light-receiving element are disposed between the first substrate and the second substrate. The first substrate is located on the display surface side, and the second substrate is located on the side opposite to the display surface side.

[0197] The visible light emitted from the light-emitting element is emitted to the outside through the first substrate. By having a plurality of such light-emitting elements arranged in a matrix, the display device can display an image.

[0198] In addition, the first light emitted from the light-emitting element reaches the surface of the first substrate. Here, when an object touches the surface of the first substrate, the first light is scattered at the interface between the first substrate and the object, and a part of the scattered light is incident on the light-receiving element. When the light-receiving element receives the first light, it can convert it into an electrical signal corresponding to the intensity and output it. By having a plurality of light-receiving elements arranged in a matrix, the display device can detect the position information, shape, etc. of the object touching the first substrate. That is, the display device can function as an image sensor panel, a touch sensor panel, etc.

[0199] Even when the object does not touch the surface of the first substrate, the first light transmitted through the first substrate is reflected or scattered on the object surface, and the reflected light or scattered light is incident on the light-receiving element through the first substrate. Therefore, the display device can also be used as a non-contact type touch sensor panel (also referred to as a near-touch panel).

[0200] When visible light is used as the first light, the first light used for image display can be used as the light source of the touch sensor. At this time, since the light-emitting element has both the function as a display element and the function as a light source, the configuration of the display device can be simplified. On the other hand, when infrared light is used as the first light, since it is not visible to the user, imaging or sensing by the light-receiving element can be performed without degrading the visibility of the displayed image.

[0201] When using infrared light as the first light, it preferably contains infrared light, preferably near-infrared light. In particular, near-infrared light having one or more peaks in the wavelength range of 700 nm or more and 2500 nm or less can be preferably used. In particular, by using light having one or more peaks in the wavelength range of 750 nm or more and 1000 nm or less, the range of material selection for the active layer of the light-receiving element is widened, which is preferable.

[0202] When a fingertip touches the surface of the display device, the shape of the fingerprint can be imaged. A fingerprint has concave and convex portions, and the first light is likely to be scattered at the convex portions of the fingerprint that touch the surface of the first substrate. Therefore, the intensity of the scattered light incident on the light-receiving element that overlaps with the convex portion of the fingerprint is large, and the intensity of the scattered light incident on the light-receiving element that overlaps with the concave portion is small. Thereby, the fingerprint can be imaged. A device having the display device according to one aspect of the present invention can perform fingerprint authentication, which is one type of biometric authentication, using the imaged fingerprint image.

[0203] In addition, the display device can also image blood vessels such as fingers or hands, particularly veins. For example, light having a wavelength of 760 nm and in its vicinity is not absorbed by reduced hemoglobin in the vein. Therefore, the position of the vein can be detected by receiving the reflected light from the palm of the hand, finger, etc. with a light-receiving element and imaging it. A device having the display device according to one aspect of the present invention can perform vein authentication, which is one type of biometric authentication, using the imaged vein image.

[0204] In addition, a device having the display device according to one aspect of the present invention can also perform touch sensing, fingerprint authentication, and vein authentication simultaneously. Thereby, high-security biometric authentication can be executed at low cost without increasing the number of components.

[0205] The light-receiving element is preferably an element capable of receiving both visible light and infrared light. At this time, as the light-emitting element, it is preferable to have a configuration including both a light-emitting element that emits infrared light and a light-emitting element that emits visible light. Thereby, by receiving, with the light-receiving element, the reflected light reflected by the user's finger using visible light, the shape of the fingerprint can be imaged. Furthermore, the shape of the vein can be imaged using infrared light. Thereby, it becomes possible to execute both fingerprint authentication and vein authentication with one display device. Also, the imaging of the fingerprint and the imaging of the vein may be executed at different timings or simultaneously. By simultaneously performing the imaging of the fingerprint and the imaging of the vein, it becomes possible to acquire image data including both the information on the shape of the fingerprint and the information on the shape of the vein, and more accurate biometric authentication can be realized.

[0206] Also, the display device according to one aspect of the present invention may have a function of detecting the health state of the user. For example, by utilizing the fact that the reflectance and transmittance with respect to visible light and infrared light change according to the change in the oxygen saturation in the blood, and acquiring the time modulation of the oxygen saturation, it becomes possible to measure the heart rate. Also, the glucose concentration in the dermis, the neutral fat concentration in the blood, etc. can also be measured by infrared light or visible light. A device having the display device according to one aspect of the present invention can be used as a healthcare device capable of acquiring information that serves as an indicator of the health state of the user.

[0207] Also, for the first substrate, a sealing substrate for sealing the light-emitting element, a protective film, or the like can be used. Also, there may be a resin layer for adhering these between the first substrate and the second substrate.

[0208] Here, it is preferable to use an EL element such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) as the light-emitting element. Examples of the light-emitting substance included in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and inorganic compounds (such as quantum dot materials). Further, an LED such as a micro LED (Light Emitting Diode) can also be used as the light-emitting element.

[0209] As the light-receiving element, for example, a pn-type or pin-type photodiode can be used. The light-receiving element functions as a photoelectric conversion element that detects light incident on the light-receiving element and generates electric charges. The amount of electric charges generated by the photoelectric conversion element is determined according to the amount of incident light. In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving element. The organic photodiode can be easily thinned, lightened, and enlarged in area, and has a high degree of freedom in shape and design, so it can be applied to various display devices.

[0210] The light-emitting element can have, for example, a stacked structure including a light-emitting layer between a pair of electrodes. Further, the light-receiving element can have a stacked structure including an active layer between a pair of electrodes. A semiconductor material can be used for the active layer of the light-receiving element. For example, an inorganic semiconductor material such as silicon can be used.

[0211] In addition, it is preferable to use an organic compound for the active layer of the light-receiving element. At this time, it is preferable to provide one of the electrodes (also referred to as a pixel electrode) of the light-emitting element and the light-receiving element on the same plane. Further, it is more preferable that the other electrode of the light-emitting element and the light-receiving element is an electrode (also referred to as a common electrode) formed by a continuous single conductive layer. Furthermore, it is more preferable that the light-emitting element and the light-receiving element have a common layer. Thereby, the manufacturing process when manufacturing the light-emitting element and the light-receiving element can be simplified, the manufacturing cost can be reduced, and the manufacturing yield can be improved.

[0212] Hereinafter, more specific examples will be described with reference to the drawings.

[0213] [Configuration Example 1 of Display Panel] [Configuration Example 1-1] FIG. 12A shows a schematic diagram of a display panel 80. The display panel 80 includes a substrate 81, a substrate 82, a light-receiving element 83, a light-emitting element 87R, a light-emitting element 87G, a light-emitting element 87B, a functional layer 85, and the like.

[0214] The light-emitting elements 87R, 87G, 87B, and the light-receiving element 83 are provided between the substrate 81 and the substrate 82.

[0215] The light-emitting elements 87R, 87G, 87B emit red (R), green (G), or blue (B) light, respectively.

[0216] The display panel 80 has a plurality of pixels arranged in a matrix. One pixel has one or more sub-pixels. One sub-pixel has one light-emitting element. For example, the pixel may have a configuration having three sub-pixels (such as three colors of R, G, B, or three colors of yellow (Y), cyan (C), and magenta (M)), or a configuration having four sub-pixels (such as four colors of R, G, B, white (W), or four colors of R, G, B, Y). Further, the pixel has a light-receiving element 83. The light-receiving element 83 may be provided in all pixels or in some pixels. Also, one pixel may have a plurality of light-receiving elements 83.

[0217] FIG. 12A shows a state in which finger 90 touches the surface of substrate 82. A part of the light emitted from light-emitting element 87G is reflected or scattered at the contact portion between substrate 82 and finger 90. Then, a part of the reflected light or scattered light is incident on light-receiving element 83, whereby it can be detected that finger 90 has touched substrate 82. That is, display panel 80 can function as a touch panel.

[0218] Functional layer 85 has a circuit for driving light-emitting elements 87R, 87G, and 87B, and a circuit for driving light-receiving element 83. Switch, transistor, capacitor, wiring, etc. are provided in functional layer 85. When light-emitting elements 87R, 87G, 87B, and light-receiving element 83 are driven in a passive matrix system, a configuration without providing a switch, transistor, etc. may be adopted.

[0219] Display panel 80 may have a function of detecting the fingerprint of finger 90. FIG. 12B schematically shows an enlarged view of the contact portion in a state where finger 90 touches substrate 82. FIG. 12B also shows light-emitting elements 87 and light-receiving elements 83 arranged alternately.

[0220] Fingerprint is formed on finger 90 by concave and convex portions. Therefore, as shown in FIG. 12B, the convex portion of the fingerprint touches substrate 82, and scattered light (indicated by a broken-line arrow) is generated at these contact surfaces.

[0221] As shown in FIG. 12B, the intensity distribution of the scattered light scattered at the contact surface between finger 90 and substrate 82 is such that the intensity in the direction substantially perpendicular to the contact surface is the highest, and the intensity distribution becomes lower as the angle in the oblique direction becomes larger than this. Therefore, the intensity of the light received by light-receiving element 83 located directly below the contact surface (overlapping the contact surface) becomes the highest. Also, among the scattered light, light with a scattering angle of a predetermined angle or more is totally reflected on the other surface of substrate 82 (the surface opposite to the contact surface) and does not transmit to the light-receiving element 83 side. Therefore, a clear fingerprint shape can be imaged.

[0222] By setting the array pitch of the light-receiving elements 83 to be smaller than the distance between two convex portions of a fingerprint, preferably the distance between an adjacent concave portion and convex portion, a clear fingerprint image can be obtained. Since the distance between the concave and convex portions of a human fingerprint is generally 200 μm, for example, the array pitch of the light-receiving elements 83 is 400 μm or less, preferably 200 μm or less, more preferably 150 μm or less, still more preferably 100 μm or less, and even more preferably 50 μm or less, and is 1 μm or more, preferably 10 μm or more, more preferably 20 μm or more.

[0223] An example of the fingerprint image captured by the display panel 80 is shown in FIG. 12C. In FIG. 12C, within the imaging range 93, the outline of the finger 90 is indicated by a dashed line, and the outline of the contact portion 91 is indicated by a dotted-dashed line. Within the contact portion 91, a fingerprint 92 with high contrast can be captured due to the difference in the amount of light incident on the light-receiving elements 83.

[0224] The display panel 80 can also function as a touch panel or a tablet. FIG. 12D shows a state where the tip of the stylus 95 is in contact with the substrate 82 and is being slid in the direction of the dashed arrow.

[0225] As shown in FIG. 12D, by the scattered light scattered at the contact surface between the tip of the stylus 95 and the substrate 82 being incident on the light-receiving elements 83 located at the portion overlapping the contact surface, the position of the tip of the stylus 95 can be detected with high precision.

[0226] FIG. 12E shows an example of the locus 96 of the stylus 95 detected by the display panel 80. Since the display panel 80 can detect the position of a detected object such as the stylus 95 with high positional accuracy, it is also possible to perform high-definition drawing in a drawing application or the like. Also, unlike the case of using a capacitive touch sensor or an electromagnetic induction type touch pen, since the position of a highly insulating detected object can be detected, the material of the tip of the stylus 95 is not limited, and various writing utensils (for example, pens, glass pens, feather pens, etc.) can also be used.

[0227] Here, FIGS. 12F to 12H show an example of a pixel applicable to the display panel 80.

[0228] The pixels shown in FIGS. 12F and 12G each have a red (R) light-emitting element 87R, a green (G) light-emitting element 87G, a blue (B) light-emitting element 87B, and a light-receiving element 83. Each pixel has a pixel circuit for driving the light-emitting element 87R, the light-emitting element 87G, the light-emitting element 87B, and the light-receiving element 83, respectively.

[0229] FIG. 12F is an example in which three light-emitting elements and one light-receiving element are arranged in a 2×2 matrix. FIG. 12G is an example in which three light-emitting elements are arranged in a row, and one horizontally long light-receiving element 83 is arranged below them.

[0230] The pixel shown in FIG. 12H is an example having a white (W) light-emitting element 87W. Here, four light-emitting elements are arranged in a row, and the light-receiving element 83 is arranged below them.

[0231] Note that the configuration of the pixel is not limited to the above, and various arrangement methods can be adopted.

[0232] 〔Configuration Example 1-2〕 Hereinafter, an example of a configuration including a light-emitting element that exhibits visible light, a light-emitting element that exhibits infrared light, and a light-receiving element will be described.

[0233] The display panel 80A shown in FIG. 13A has a light-emitting element 87IR in addition to the configuration illustrated in FIG. 12A. The light-emitting element 87IR is a light-emitting element that emits infrared light IR. At this time, it is preferable to use, as the light-receiving element 83, an element that can receive at least the infrared light IR emitted by the light-emitting element 87IR. More preferably, as the light-receiving element 83, an element that can receive both visible light and infrared light is used.

[0234] As shown in FIG. 13A, when the finger 90 touches the substrate 82, the infrared light IR emitted from the light-emitting element 87IR is reflected or scattered by the finger 90, and a part of the reflected light or scattered light is incident on the light-receiving element 83, thereby enabling the acquisition of the position information of the finger 90.

[0235] FIGS. 13B to 13D show an example of a pixel applicable to the display panel 80A.

[0236] FIG. 13B is an example in which three light-emitting elements are arranged in a row, and below that, the light-emitting element 87IR and the light-receiving element 83 are arranged side by side horizontally. Further, FIG. 13C is an example in which four light-emitting elements including the light-emitting element 87IR are arranged in a row, and below that, the light-receiving element 83 is arranged.

[0237] Also, FIG. 13D is an example in which three light-emitting elements are arranged in four directions centered on the light-emitting element 87IR, and the light-receiving element 83 is arranged.

[0238] In the pixels shown in FIGS. 13B to 13D, the positions of the light-emitting elements and between the light-emitting elements and the light-receiving element can be exchanged with each other.

[0239] [Configuration Example 2 of Display Panel] [Configuration Example 2-1] FIG. 14A shows a schematic cross-sectional view of the display panel 100A.

[0240] The display panel 100A includes a light-receiving element 110 and a light-emitting element 190. The light-receiving element 110 includes a pixel electrode 111, a common layer 112, an active layer 113, a common layer 114, and a common electrode 115. The light-emitting element 190 includes a pixel electrode 191, a common layer 112, a light-emitting layer 193, a common layer 114, and a common electrode 115.

[0241] The pixel electrode 111, the pixel electrode 191, the common layer 112, the active layer 113, the light-emitting layer 193, the common layer 114, and the common electrode 115 may each have a single-layer structure or a laminated structure.

[0242] The pixel electrode 111 and the pixel electrode 191 are located on the insulating layer 214. The pixel electrode 111 and the pixel electrode 191 can be formed of the same material and in the same process.

[0243] The common layer 112 is located on the pixel electrode 111 and on the pixel electrode 191. The common layer 112 is a layer commonly used for the light-receiving element 110 and the light-emitting element 190.

[0244] The active layer 113 overlaps with the pixel electrode 111 via the common layer 112. The light-emitting layer 193 overlaps with the pixel electrode 191 via the common layer 112. The active layer 113 has a first organic compound, and the light-emitting layer 193 has a second organic compound different from the first organic compound.

[0245] The common layer 114 is located on the common layer 112, on the active layer 113, and on the light-emitting layer 193. The common layer 114 is a layer commonly used for the light-receiving element 110 and the light-emitting element 190.

[0246] The common electrode 115 has a portion that overlaps with the pixel electrode 111 via the common layer 112, the active layer 113, and the common layer 114. Also, the common electrode 115 has a portion that overlaps with the pixel electrode 191 via the common layer 112, the light-emitting layer 193, and the common layer 114. The common electrode 115 is a layer commonly used for the light-receiving element 110 and the light-emitting element 190.

[0247] In the display panel of this embodiment, an organic compound is used for the active layer 113 of the light-receiving element 110. The light-receiving element 110 can have the same configuration as the light-emitting element 190 (EL element) for the layers other than the active layer 113. Therefore, only the step of forming the active layer 113 needs to be added to the manufacturing process of the light-emitting element 190, and the light-receiving element 110 can be formed in parallel with the formation of the light-emitting element 190. Also, the light-emitting element 190 and the light-receiving element 110 can be formed on the same substrate. Therefore, the light-receiving element 110 can be incorporated into the display panel without significantly increasing the manufacturing process.

[0248] In the display panel 100A, an example is shown in which the light receiving element 110 and the light emitting element 190 have a common configuration except that the active layer 113 of the light receiving element 110 and the light emitting layer 193 of the light emitting element 190 are made separately. However, the configurations of the light receiving element 110 and the light emitting element 190 are not limited to this. The light receiving element 110 and the light emitting element 190 may have layers that are separately made from each other in addition to the active layer 113 and the light emitting layer 193 (see the display panels 100D, 100E, and 100F described later). The light receiving element 110 and the light emitting element 190 preferably have one or more layers (common layers) that are commonly used. Thereby, the light receiving element 110 can be incorporated into the display panel without significantly increasing the manufacturing process.

[0249] The display panel 100A has a light receiving element 110, a light emitting element 190, a transistor 131, a transistor 132, etc. between a pair of substrates (substrate 151 and substrate 152).

[0250] In the light receiving element 110, the common layer 112, the active layer 113, and the common layer 114 located between the pixel electrode 111 and the common electrode 115, respectively, can also be referred to as organic layers (layers containing organic compounds). The pixel electrode 111 preferably has a function of reflecting visible light. The end portion of the pixel electrode 111 is covered by the partition wall 216. The common electrode 115 has a function of transmitting visible light.

[0251] The light receiving element 110 has a function of detecting light. Specifically, the light receiving element 110 is a photoelectric conversion element that receives the light 122 incident from the outside through the substrate 152 and converts it into an electrical signal.

[0252] A light shielding layer BM is provided on the surface of the substrate 152 on the side of the substrate 151. The light shielding layer BM has openings at positions overlapping the light receiving element 110 and positions overlapping the light emitting element 190. By providing the light shielding layer BM, the range in which the light receiving element 110 detects light can be controlled.

[0253] As the light-shielding layer BM, a material that blocks the light emitted from the light-emitting element can be used. The light-shielding layer BM preferably absorbs visible light. As the light-shielding layer BM, for example, a black matrix can be formed using a metal material, or a resin material containing a pigment (such as carbon black) or a dye. The light-shielding layer BM may have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0254] Here, a part of the light emitted from the light-emitting element 190 may be reflected within the display panel 100A and incident on the light-receiving element 110. The light-shielding layer BM can suppress the influence of such stray light. For example, when the light-shielding layer BM is not provided, the light 123a emitted from the light-emitting element 190 may be reflected by the substrate 152, and the reflected light 123b may be incident on the light-receiving element 110. By providing the light-shielding layer BM, the incidence of the reflected light 123b on the light-receiving element 110 can be suppressed. Thereby, noise can be reduced and the sensitivity of the sensor using the light-receiving element 110 can be enhanced.

[0255] In the light-emitting element 190, the common layer 112, the light-emitting layer 193, and the common layer 114, which are respectively located between the pixel electrode 191 and the common electrode 115, can also be referred to as an EL layer. The pixel electrode 191 preferably has a function of reflecting visible light. The end portion of the pixel electrode 191 is covered by the partition wall 216. The pixel electrode 111 and the pixel electrode 191 are electrically insulated from each other by the partition wall 216. The common electrode 115 has a function of transmitting visible light.

[0256] The light-emitting element 190 has a function of emitting visible light. Specifically, the light-emitting element 190 is an electroluminescent element that injects light 121 toward the substrate 152 side by applying a voltage between the pixel electrode 191 and the common electrode 115.

[0257] The light-emitting layer 193 is preferably formed so as not to overlap with the light-receiving region of the light-receiving element 110. Thereby, absorption of the light 122 by the light-emitting layer 193 can be suppressed, and the amount of light irradiated to the light-receiving element 110 can be increased.

[0258] The pixel electrode 111 is electrically connected to the source or drain of the transistor 131 through an opening provided in the insulating layer 214. The end of the pixel electrode 111 is covered by the partition wall 216.

[0259] The pixel electrode 191 is electrically connected to the source or drain of the transistor 132 through an opening provided in the insulating layer 214. The end of the pixel electrode 191 is covered by the partition wall 216. The transistor 132 has a function of controlling the driving of the light-emitting element 190.

[0260] The transistor 131 and the transistor 132 are in contact with each other on the same layer (the substrate 151 in FIG. 14A).

[0261] At least a part of the circuit electrically connected to the light-receiving element 110 is preferably formed of the same material and in the same process as the circuit electrically connected to the light-emitting element 190. Thereby, compared with the case where the two circuits are formed separately, the thickness of the display panel can be reduced and the manufacturing process can be simplified.

[0262] The light-receiving element 110 and the light-emitting element 190 are preferably each covered with a protective layer 195. In FIG. 14A, the protective layer 195 is provided in contact with the common electrode 115. By providing the protective layer 195, it is possible to suppress impurities such as water from entering the light-receiving element 110 and the light-emitting element 190, and to improve the reliability of the light-receiving element 110 and the light-emitting element 190. Further, the protective layer 195 and the substrate 152 are bonded together by the adhesive layer 142.

[0263] Note that, as shown in FIG. 15A, the light-receiving element 110 and the light-emitting element 190 may not have a protective layer thereon. In FIG. 15A, the common electrode 115 and the substrate 152 are bonded together by the adhesive layer 142.

[0264] Alternatively, as shown in FIG. 15B, a configuration without the light shielding layer BM may be adopted. This can increase the light-receiving area of the light-receiving element 110, thereby enhancing the sensitivity of the sensor.

[0265] 〔Configuration Example 2-2〕 FIG. 14B shows a schematic cross-sectional view of the display panel 100B. In the following description of the display panel, the description of the same configuration as the previously described display panel may be omitted.

[0266] The display panel 100B shown in FIG. 14B has a lens 149 in addition to the configuration of the display panel 100A.

[0267] The lens 149 is provided at a position overlapping the light-receiving element 110. In the display panel 100B, the lens 149 is provided in contact with the substrate 152. The lens 149 included in the display panel 100B is a convex lens having a convex surface on the substrate 151 side. Note that a convex lens having a convex surface on the substrate 152 side may be disposed in a region overlapping the light-receiving element 110.

[0268] When both the light shielding layer BM and the lens 149 are formed on the same surface of the substrate 152, the formation order is not limited. FIG. 14B shows an example in which the lens 149 is formed first, but the light shielding layer BM may be formed first. In FIG. 14B, the end portion of the lens 149 is covered by the light shielding layer BM.

[0269] The display panel 100B is configured such that light 122 enters the light-receiving element 110 through the lens 149. With the lens 149, the amount of light 122 incident on the light-receiving element 110 can be increased compared to the case where the lens 149 is not provided. Thereby, the sensitivity of the light-receiving element 110 can be enhanced.

[0270] As a method for forming the lens used in the display panel of the present embodiment, a lens such as a microlens may be directly formed on the substrate or on the light-receiving element, or a lens array such as a separately manufactured microlens array may be bonded to the substrate.

[0271] 〔Configuration Example 2-3〕 FIG. 14C shows a schematic cross-sectional view of the display panel 100C. The display panel 100C is different from the display panel 100A in that it does not have the substrates 151 and 152 and the partition wall 216, but has the substrates 153, 154, the adhesive layer 155, the insulating layer 212, and the partition wall 217.

[0272] The substrate 153 and the insulating layer 212 are bonded together by the adhesive layer 155. The substrate 154 and the protective layer 195 are bonded together by the adhesive layer 142.

[0273] The display panel 100C is configured by transferring the insulating layer 212, the transistors 131 and 132, the light receiving element 110, the light emitting element 190, etc. formed on the production substrate onto the substrate 153. The substrates 153 and 154 preferably each have flexibility. Thereby, the flexibility of the display panel 100C can be enhanced. For example, it is preferable to use resin for the substrates 153 and 154, respectively.

[0274] As the substrates 153 and 154, polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. can be used. Glass with a thickness that provides flexibility may be used for one or both of the substrates 153 and 154.

[0275] For the substrate included in the display panel of the present embodiment, a film with high optical isotropy may be used. Examples of the film with high optical isotropy include a triacetyl cellulose (TAC, also referred to as cellulose triacetate) film, a cycloolefin polymer (COP) film, a cycloolefin copolymer (COC) film, and an acrylic resin film.

[0276] It is preferable that the partition wall 217 absorbs the light emitted by the light-emitting element. As the partition wall 217, for example, a resin material containing a pigment or a dye can be used to form a black matrix. Further, by using a brown resist material, the partition wall 217 can be constituted by a colored insulating layer.

[0277] The light 123c emitted by the light-emitting element 190 may be reflected by the substrate 154 and the partition wall 217, and the reflected light 123d may enter the light-receiving element 110. Further, the light 123c may pass through the partition wall 217 and be reflected by a transistor or wiring or the like, and the reflected light may enter the light-receiving element 110. By absorbing the light 123c by the partition wall 217, it is possible to suppress the reflected light 123d from entering the light-receiving element 110. Thereby, noise can be reduced and the sensitivity of the sensor using the light-receiving element 110 can be enhanced.

[0278] It is preferable that the partition wall 217 absorbs at least the wavelength of the light detected by the light-receiving element 110. For example, when the light-receiving element 110 detects the red light emitted by the light-emitting element 190, it is preferable that the partition wall 217 absorbs at least the red light. For example, if the partition wall 217 has a blue color filter, it can absorb the red light 123c and suppress the reflected light 123d from entering the light-receiving element 110.

[0279] 〔Configuration Example 2-4〕 In the above, an example in which the light-emitting element and the light-receiving element have two common layers has been shown, but the present invention is not limited thereto. Hereinafter, examples in which the configuration of the common layer is different will be described.

[0280] FIG. 16A shows a schematic cross-sectional view of a display panel 100D. The display panel 100D is different from the display panel 100A in that it does not have a common layer 114 and has a buffer layer 184 and a buffer layer 194. The buffer layer 184 and the buffer layer 194 may each have a single-layer structure or a laminated structure.

[0281] In the display panel 100D, the light-receiving element 110 has a pixel electrode 111, a common layer 112, an active layer 113, a buffer layer 184, and a common electrode 115. Also, in the display panel 100D, the light-emitting element 190 has a pixel electrode 191, a common layer 112, a light-emitting layer 193, a buffer layer 194, and a common electrode 115.

[0282] In the display panel 100D, an example is shown in which the buffer layer 184 between the common electrode 115 and the active layer 113 and the buffer layer 194 between the common electrode 115 and the light-emitting layer 193 are separately formed. As the buffer layer 184 and the buffer layer 194, for example, one or both of an electron injection layer and an electron transport layer can be formed.

[0283] FIG. 16B shows a schematic cross-sectional view of a display panel 100E. The display panel 100E is different from the display panel 100A in that it does not have a common layer 112 and has a buffer layer 182 and a buffer layer 192. The buffer layer 182 and the buffer layer 192 may each have a single-layer structure or a laminated structure.

[0284] In the display panel 100E, the light-receiving element 110 has a pixel electrode 111, a buffer layer 182, an active layer 113, a common layer 114, and a common electrode 115. Also, in the display panel 100E, the light-emitting element 190 has a pixel electrode 191, a buffer layer 192, a light-emitting layer 193, a common layer 114, and a common electrode 115.

[0285] In the display panel 100E, an example is shown in which a buffer layer 182 between the pixel electrode 111 and the active layer 113 and a buffer layer 192 between the pixel electrode 191 and the light-emitting layer 193 are separately formed. As the buffer layer 182 and the buffer layer 192, for example, one or both of a hole injection layer and a hole transport layer can be formed.

[0286] FIG. 16C shows a schematic cross-sectional view of the display panel 100F. The display panel 100F is different from the display panel 100A in that it does not have the common layers 112 and 114 and has a buffer layer 182, a buffer layer 184, a buffer layer 192, and a buffer layer 194.

[0287] In the display panel 100F, the light-receiving element 110 has a pixel electrode 111, a buffer layer 182, an active layer 113, a buffer layer 184, and a common electrode 115. Also, in the display panel 100F, the light-emitting element 190 has a pixel electrode 191, a buffer layer 192, a light-emitting layer 193, a buffer layer 194, and a common electrode 115.

[0288] In the fabrication of the light-receiving element 110 and the light-emitting element 190, not only the active layer 113 and the light-emitting layer 193 can be separately formed, but also other layers can be separately formed.

[0289] In the display panel 100F, an example is shown in which the light-receiving element 110 and the light-emitting element 190 do not have a common layer between a pair of electrodes (the pixel electrode 111 or the pixel electrode 191 and the common electrode 115). The light-receiving element 110 and the light-emitting element 190 included in the display panel 100F are formed by forming the pixel electrode 111 and the pixel electrode 191 of the same material and in the same process on the insulating layer 214, and forming a buffer layer 182, an active layer 113, and a buffer layer 184 on the pixel electrode 111, and forming a buffer layer 192, a light-emitting layer 193, and a buffer layer 194 on the pixel electrode 191, respectively, and then forming the common electrode 115 so as to cover the buffer layer 184 and the buffer layer 194 and the like.

[0290] Note that the manufacturing order of the stacked structure of the buffer layer 182, the active layer 113, and the buffer layer 184 and the stacked structure of the buffer layer 192, the light-emitting layer 193, and the buffer layer 194 is not particularly limited. For example, after forming the buffer layer 182, the active layer 113, and the buffer layer 184, the buffer layer 192, the light-emitting layer 193, and the buffer layer 194 may be formed. Conversely, before forming the buffer layer 182, the active layer 113, and the buffer layer 184, the buffer layer 192, the light-emitting layer 193, and the buffer layer 194 may be formed. Also, they may be alternately formed in the order of the buffer layer 182, the buffer layer 192, the active layer 113, the light-emitting layer 193, and so on.

[0291] [Configuration Example 3 of Display Panel] Hereinafter, a more specific configuration example of the display panel will be described.

[0292] [Configuration Example 3-1] FIG. 17 shows a perspective view of the display panel 200A.

[0293] The display panel 200A has a configuration in which the substrate 151 and the substrate 152 are bonded together. In FIG. 17, the substrate 152 is shown by a broken line.

[0294] The display panel 200A includes a display unit 162, a circuit 164, a wiring 165, etc. FIG. 17 shows an example in which an IC (integrated circuit) 173 and an FPC 172 are mounted on the display panel 200A. Therefore, the configuration shown in FIG. 17 can also be referred to as a display module having the display panel 200A, an IC, and an FPC.

[0295] As the circuit 164, a scanning line driving circuit can be used.

[0296] The wiring 165 has a function of supplying signals and power to the display unit 162 and the circuit 164. The signals and power are input from the outside via the FPC 172 or input from the IC 173 to the wiring 165.

[0297] FIG. 17 shows an example in which an IC 173 is provided on a substrate 151 by a COG (Chip On Glass) method, a COF (Chip On Film) method, or the like. As the IC 173, for example, an IC having a scanning line driving circuit, a signal line driving circuit, and the like can be applied. Note that the display panel 200A and the display module may be configured not to include an IC. Further, the IC may be mounted on an FPC by a COF method or the like.

[0298] FIG. 18 shows an example of a cross-section when a part of the region including the FPC 172, a part of the region including the circuit 164, a part of the region including the display unit 162, and a part of the region including the end portion of the display panel 200A shown in FIG. 17 are each cut.

[0299] The display panel 200A shown in FIG. 18 includes a transistor 201, a transistor 205, a transistor 206, a light-emitting element 190, a light-receiving element 110, etc. between a substrate 151 and a substrate 152.

[0300] The substrate 152 and the insulating layer 214 are adhered via an adhesive layer 142. For sealing the light-emitting element 190 and the light-receiving element 110, a solid sealing structure, a hollow sealing structure, or the like can be applied. In FIG. 18, a space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 is filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure is applied. The adhesive layer 142 may be provided so as to overlap with the light-emitting element 190. Further, the space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 may be filled with a resin different from the adhesive layer 142.

[0301] The light-emitting element 190 has a stacked structure in which a pixel electrode 191, a common layer 112, a light-emitting layer 193, a common layer 114, and a common electrode 115 are stacked in this order from the insulating layer 214 side. The pixel electrode 191 is connected to the conductive layer 222b included in the transistor 206 through an opening provided in the insulating layer 214. The transistor 206 has a function of controlling the driving of the light-emitting element 190. The end portion of the pixel electrode 191 is covered by the partition wall 216. The pixel electrode 191 contains a material that reflects visible light, and the common electrode 115 contains a material that transmits visible light.

[0302] The light-receiving element 110 has a stacked structure in which a pixel electrode 111, a common layer 112, an active layer 113, a common layer 114, and a common electrode 115 are stacked in this order from the insulating layer 214 side. The pixel electrode 111 is electrically connected to the conductive layer 222b included in the transistor 205 through an opening provided in the insulating layer 214. The end portion of the pixel electrode 111 is covered by the partition wall 216. The pixel electrode 111 contains a material that reflects visible light, and the common electrode 115 contains a material that transmits visible light.

[0303] The light emitted from the light-emitting element 190 is emitted toward the substrate 152 side. Further, light is incident on the light-receiving element 110 through the substrate 152 and the space 143. It is preferable to use a material having high transmittance with respect to visible light for the substrate 152.

[0304] The pixel electrode 111 and the pixel electrode 191 can be manufactured from the same material and in the same process. The common layer 112, the common layer 114, and the common electrode 115 are used for both the light-receiving element 110 and the light-emitting element 190. The light-receiving element 110 and the light-emitting element 190 can have the same configuration except that the configurations of the active layer 113 and the light-emitting layer 193 are different. Thereby, the light-receiving element 110 can be incorporated into the display panel 200A without significantly increasing the manufacturing process.

[0305] On the surface of the substrate 152 on the side of the substrate 151, a light-shielding layer BM is provided. The light-shielding layer BM has openings at positions overlapping the light-receiving element 110 and positions overlapping the light-emitting element 190. By providing the light-shielding layer BM, the range in which the light-receiving element 110 detects light can be controlled. Also, by having the light-shielding layer BM, direct incidence of light from the light-emitting element 190 to the light-receiving element 110 can be suppressed. Therefore, a sensor with less noise and high sensitivity can be realized.

[0306] The transistor 201, the transistor 205, and the transistor 206 are all formed on the substrate 151. These transistors can be fabricated by the same material and the same process.

[0307] On the substrate 151, an insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided in this order. A part of the insulating layer 211 functions as a gate insulating layer of each transistor. A part of the insulating layer 213 functions as a gate insulating layer of each transistor. The insulating layer 215 is provided to cover the transistor. The insulating layer 214 is provided to cover the transistor and has a function as a planarization layer. Note that the number of gate insulating layers and the number of insulating layers covering the transistor are not limited, and each may be a single layer or two or more layers.

[0308] It is preferable to use a material in which impurities such as water or hydrogen hardly diffuse in at least one of the insulating layers covering the transistor. Thereby, the insulating layer can function as a barrier layer. With such a configuration, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0309] As the insulating layers 211, 213, and 215, it is preferable to use inorganic insulating films respectively. As the inorganic insulating film, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum nitride film can be used. Further, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, etc. may be used. Also, two or more of the above-described insulating films may be laminated and used.

[0310] Here, the organic insulating film often has lower barrier properties than the inorganic insulating film. Therefore, it is preferable that the organic insulating film has an opening near the end of the display panel 200A. Thereby, it is possible to suppress the diffusion of impurities from the end of the display panel 200A through the organic insulating film. Or, the organic insulating film may be formed such that the end of the organic insulating film is located inside the end of the display panel 200A so that the organic insulating film is not exposed at the end of the display panel 200A.

[0311] The insulating layer 214 that functions as a planarization layer is preferably an organic insulating film. Examples of the material that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene-based resin, phenol resin, and precursors of these resins.

[0312] In the region 228 shown in FIG. 18, an opening is formed in the insulating layer 214. Thereby, even when an organic insulating film is used for the insulating layer 214, it is possible to suppress the diffusion of impurities from the outside to the display portion 162 through the insulating layer 214. Therefore, the reliability of the display panel 200A can be improved.

[0313] Transistors 201, 205, and 206 include a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as a source and a drain, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate. Here, the same hatching pattern is applied to a plurality of layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0314] The structure of the transistor included in the display panel of the present embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverse staggered transistor, or the like can be used. Also, either a top gate type or a bottom gate type transistor structure may be used. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0315] Transistors 201, 205, and 206 are configured such that a semiconductor layer in which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying the same signal thereto. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0316] The crystallinity of the semiconductor material used for the transistor is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystal region in part) may be used. It is preferable to use a single crystal semiconductor or a semiconductor having crystallinity because deterioration of transistor characteristics can be suppressed.

[0317] The semiconductor layer of the transistor preferably contains a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystalline silicon).

[0318] The semiconductor layer preferably contains, for example, indium, one or more elements M (where M is selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0319] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also denoted as IGZO) as the semiconductor layer.

[0320] When the semiconductor layer is an In-M-Zn oxide, the sputtering target used for forming the In-M-Zn oxide preferably has an atomic ratio of In to M of 1 or more. Examples of the atomic ratio of the metal elements in such a sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc.

[0321] As a sputtering target, it is preferable to use a target containing a polycrystalline oxide because it facilitates the formation of a semiconductor layer having crystallinity. The atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer to be formed may be in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio].

[0322] When the atomic ratio is described as In:Ga:Zn = 4:2:3 or in its vicinity, when In is 4, it includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Also, when the atomic ratio is described as In:Ga:Zn = 5:1:6 or in its vicinity, when In is 5, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Also, when the atomic ratio is described as In:Ga:Zn = 1:1:1 or in its vicinity, when In is 1, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0323] The transistors included in circuit 164 and the transistors included in display unit 162 may have the same structure or different structures. The structures of the plurality of transistors included in circuit 164 may all be the same or there may be two or more types. Similarly, the structures of the plurality of transistors included in display unit 162 may all be the same or there may be two or more types.

[0324] A connection portion 204 is provided in a region of substrate 151 where substrate 152 does not overlap. In connection portion 204, wiring 165 is electrically connected to FPC 172 via conductive layer 166 and connection layer 242. On the upper surface of connection portion 204, conductive layer 166 obtained by processing the same conductive film as pixel electrode 191 is exposed. Thereby, connection portion 204 and FPC 172 can be electrically connected via connection layer 242.

[0325] Various optical members can be arranged outside the substrate 152. Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an antireflection layer, and a condenser film. Further, outside the substrate 152, an antistatic film for suppressing dust adhesion, a water-repellent film for making it difficult for dirt to adhere, a hard coat film for suppressing the occurrence of scratches during use, a shock absorption layer, etc. may be arranged.

[0326] For the substrate 151 and the substrate 152, glass, quartz, ceramic, sapphire, resin, etc. can be used respectively. When using a flexible material for the substrate 151 and the substrate 152, the flexibility of the display panel can be enhanced.

[0327] As the adhesive layer, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable type, a reaction curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Examples of these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, etc. In particular, a material with low moisture permeability such as epoxy resin is preferable. Also, a two-component mixed resin may be used. Also, an adhesive sheet or the like may be used.

[0328] As the connection layer 242, an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), etc. can be used.

[0329] The light-emitting element 190 has a top emission type, a bottom emission type, a dual emission type, etc. For the electrode on the side where light is extracted, a conductive film that transmits visible light is used. Also, for the electrode on the side where light is not extracted, it is preferable to use a conductive film that reflects visible light.

[0330] The light-emitting element 190 has at least a light-emitting layer 193. The light-emitting element 190 may further have, as layers other than the light-emitting layer 193, a layer containing a substance with high hole injection property, a substance with high hole transport property, a hole-blocking material, a substance with high electron transport property, a substance with high electron injection property, an electron-blocking material, or a bipolar substance (a substance with high electron transport property and high hole transport property), etc. For example, the common layer 112 preferably has one or both of a hole injection layer and a hole transport layer. For example, the common layer 114 preferably has one or both of an electron transport layer and an electron injection layer.

[0331] Either a low molecular weight compound or a high molecular weight compound can be used for the common layer 112, the light-emitting layer 193, and the common layer 114, and they may contain an inorganic compound. The layers constituting the common layer 112, the light-emitting layer 193, and the common layer 114 can be formed by methods such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, etc.

[0332] The light-emitting layer 193 may have an inorganic compound such as a quantum dot as a light-emitting material.

[0333] The active layer 113 of the light-receiving element 110 contains a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example of using an organic semiconductor as the semiconductor included in the active layer is shown. By using an organic semiconductor, the light-emitting layer 193 of the light-emitting element 190 and the active layer 113 of the light-receiving element 110 can be formed by the same method (for example, a vacuum vapor deposition method), and it is preferable because the manufacturing apparatus can be shared.

[0334] Examples of the material of the n-type semiconductor included in the active layer 113 include fullerenes (for example, C 60 , C 70Examples include electron-accepting organic semiconductor materials such as fullerenes and fullerene derivatives. Fullerenes have a soccer ball-like shape, which is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Due to the deep LUMO level, fullerenes have extremely high electron-accepting (acceptor) properties. Usually, when π-electron conjugation (resonance) spreads in a plane like benzene, the electron-donating (donor) property increases. However, since fullerenes have a spherical shape, despite the large spread of π electrons, they have high electron-accepting properties. High electron-accepting properties are beneficial for light-receiving devices because they cause efficient charge separation at high speed. C 60 , C 70 Both have broad absorption bands in the visible light region. In particular, C 70 is preferable because it has a larger π-electron conjugation system than C 60 and also has a broad absorption band in the long wavelength region.

[0335] In addition, examples of the material of the n-type semiconductor included in the active layer 113 include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, quinone derivatives, and the like.

[0336] Examples of the material of the p-type semiconductor included in the active layer 113 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0337] In addition, examples of the p-type semiconductor material include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, and the like. Further, examples of the p-type semiconductor material include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylene vinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, and the like.

[0338] For example, the active layer 113 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor. Alternatively, the active layer 113 may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0339] Materials that can be used for conductive layers such as various wirings and electrodes constituting the display panel, in addition to the gate, source, and drain of the transistor, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys mainly composed of these metals. A film containing these materials can be used as a single layer or in a laminated structure.

[0340] In addition, as the conductive material having translucency, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene can be used. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing the metal materials can be used. Alternatively, nitrides of the metal materials (for example, titanium nitride) may be used. In addition, when using a metal material, an alloy material (or a nitride thereof), it is preferable to make it thin enough to have translucency. Further, a laminated film of the above materials can be used as the conductive layer. For example, using a laminated film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting the display panel, or conductive layers of the display element (conductive layers functioning as pixel electrodes and common electrodes).

[0341] Examples of the insulating material that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0342] 〔Configuration Example 3-2〕 FIG. 19A shows a cross-sectional view of the display panel 200B. The display panel 200B is mainly different from the display panel 200A in that it has a lens 149 and a protective layer 195.

[0343] By providing the protective layer 195 that covers the light receiving element 110 and the light emitting element 190, it is possible to suppress the diffusion of impurities such as water into the light receiving element 110 and the light emitting element 190, and improve the reliability of the light receiving element 110 and the light emitting element 190.

[0344] In the region 228 near the end of the display panel 200B, it is preferable that the insulating layer 215 and the protective layer 195 are in contact with each other through the opening of the insulating layer 214. In particular, it is preferable that the inorganic insulating film of the insulating layer 215 and the inorganic insulating film of the protective layer 195 are in contact with each other. Thereby, it is possible to suppress the diffusion of impurities from the outside to the display unit 162 through the organic insulating film. Therefore, the reliability of the display panel 200B can be enhanced.

[0345] FIG. 19B shows an example in which the protective layer 195 has a three-layer structure. In FIG. 19B, the protective layer 195 includes an inorganic insulating layer 195a on the common electrode 115, an organic insulating layer 195b on the inorganic insulating layer 195a, and an inorganic insulating layer 195c on the organic insulating layer 195b.

[0346] The end of the inorganic insulating layer 195a and the end of the inorganic insulating layer 195c extend outside the end of the organic insulating layer 195b and are in contact with each other. The inorganic insulating layer 195a is in contact with the insulating layer 215 (inorganic insulating layer) through the opening of the insulating layer 214 (organic insulating layer). Thereby, since the insulating layer 215 and the protective layer 195 can surround the light receiving element 110 and the light emitting element 190, the reliability of the light receiving element 110 and the light emitting element 190 can be enhanced.

[0347] As described above, the protective layer 195 may have a laminated structure of an organic insulating film and an inorganic insulating film. At this time, it is preferable that the end of the inorganic insulating film extends outside the end of the organic insulating film.

[0348] A lens 149 is provided on the surface of the substrate 152 on the side of the substrate 151. The lens 149 has a convex surface on the side of the substrate 151. The light receiving region of the light receiving element 110 preferably overlaps with the lens 149 and does not overlap with the light emitting layer 193. Thereby, the sensitivity and accuracy of the sensor using the light receiving element 110 can be enhanced.

[0349] The refractive index of the lens 149 with respect to the wavelength of the light received by the light receiving element 110 is preferably 1.3 or more and 2.5 or less. The lens 149 can be formed using at least one of an inorganic material and an organic material. For example, a material containing a resin can be used for the lens 149. Also, a material containing at least one of an oxide and a sulfide can be used for the lens 149.

[0350] Specifically, a resin containing chlorine, bromine, or iodine, a resin containing heavy metal atoms, a resin containing an aromatic ring, a resin containing sulfur, etc. can be used for the lens 149. Alternatively, a material containing a resin and nanoparticles of a material having a higher refractive index than the resin can be used for the lens 149. Titanium oxide or zirconium dioxide, etc. can be used for the nanoparticles.

[0351] Also, cerium oxide, hafnium oxide, lanthanum oxide, magnesium oxide, niobium oxide, tantalum oxide, titanium oxide, yttrium oxide, zinc oxide, an oxide containing indium and tin, or an oxide containing indium, gallium, and zinc, etc. can be used for the lens 149. Alternatively, zinc sulfide, etc. can be used for the lens 149.

[0352] Also, in the display panel 200B, the protective layer 195 and the substrate 152 are bonded together by the adhesive layer 142. The adhesive layer 142 is provided so as to overlap with the light receiving element 110 and the light emitting element 190 respectively, and a solid sealing structure is applied to the display panel 200B.

[0353] 〔Configuration Example 3-3〕 FIG. 20A shows a cross-sectional view of the display panel 200C. The display panel 200C is mainly different from the display panel 200B in that the structure of the transistor is different and it does not have the light shielding layer BM and the lens 149.

[0354] The display panel 200C has transistors 208, 209, and 210 on the substrate 151.

[0355] Transistors 208, 209, and 210 each have a semiconductor layer having a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, a channel formation region 231i, and a pair of low-resistance regions 231n, a conductive layer 222a connected to one of the pair of low-resistance regions 231n, a conductive layer 222b connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 that functions as a gate insulating layer, a conductive layer 223 that functions as a gate, and an insulating layer 215 that covers the conductive layer 223. The insulating layer 211 is located between the conductive layer 221 and the channel formation region 231i. The insulating layer 225 is located between the conductive layer 223 and the channel formation region 231i.

[0356] The conductive layers 222a and 222b are each connected to the low-resistance region 231n through openings provided in the insulating layer 225 and the insulating layer 215. Of the conductive layers 222a and 222b, one functions as a source and the other functions as a drain.

[0357] The pixel electrode 191 of the light-emitting element 190 is electrically connected to one of the pair of low-resistance regions 231n of the transistor 208 through the conductive layer 222b.

[0358] The pixel electrode 111 of the light-receiving element 110 is electrically connected to the other of the pair of low-resistance regions 231n of the transistor 209 through the conductive layer 222b.

[0359] FIG. 20A shows an example in which the insulating layer 225 covers the upper surface and the side surface of the semiconductor layer. On the other hand, FIG. 20B shows an example of the transistor 202 in which the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 and does not overlap with the low-resistance region 231n. For example, the structure shown in FIG. 20B can be fabricated by processing the insulating layer 225 using the conductive layer 223 as a mask. In FIG. 20B, an insulating layer 215 is provided to cover the insulating layer 225 and the conductive layer 223, and the conductive layers 222a and 222b are each connected to the low-resistance region 231n through the opening of the insulating layer 215. Further, an insulating layer 218 that covers the transistor may be provided.

[0360] [Configuration Example 3-4] Fig. 21 shows a cross-sectional view of display panel 200D. Display panel 200D mainly differs from display panel 200C in that the configuration of the substrate is different.

[0361] Display panel 200D does not have substrates 151 and 152, but has substrate 153, substrate 154, adhesive layer 155, and insulating layer 212.

[0362] Substrate 153 and insulating layer 212 are bonded together by adhesive layer 155. Substrate 154 and protective layer 195 are bonded together by adhesive layer 142.

[0363] Display panel 200D is configured by transferring the insulating layer 212, transistor 208, transistor 209, light receiving element 110, light emitting element 190, etc. formed on the production substrate onto substrate 153. Substrate 153 and substrate 154 preferably each have flexibility. Thereby, the flexibility of display panel 200D can be enhanced.

[0364] For insulating layer 212, an inorganic insulating film that can be used for insulating layer 211, insulating layer 213, and insulating layer 215 can be used. Alternatively, insulating layer 212 may be a laminated film of an organic insulating film and an inorganic insulating film. At this time, it is preferable that the film on the transistor 209 side is an inorganic insulating film.

[0365] The above is the description of the configuration example of the display panel.

[0366] [Regarding Metal Oxides] Hereinafter, metal oxides applicable to the semiconductor layer will be described.

[0367] In addition, in this specification and the like, a metal oxide containing nitrogen may also be generically referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride. For example, a metal oxide containing nitrogen such as zinc oxynitride (ZnON) may be used for the semiconductor layer.

[0368] In addition, in this specification and the like, CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be described. CAAC represents an example of a crystal structure, and CAC represents an example of the configuration of a function or a material.

[0369] For example, CAC (Cloud-Aligned Composite)-OS (Oxide Semiconductor) can be used for the semiconductor layer.

[0370] CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used for the semiconductor layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be enhanced to the maximum extent.

[0371] In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed with a blurred periphery and connected in a cloud shape.

[0372] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0373] Also, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to the insulating region and a component having a narrow band gap due to the conductive region. In such a configuration, when carriers flow, carriers mainly flow in the component having the narrow band gap. Also, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0374] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0375] Oxide semiconductors (metal oxides) can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0376] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. The strain refers to a location where the orientation of the lattice array changes between a region with an aligned lattice array and another region with an aligned lattice array in the region where the plurality of nanocrystals are connected.

[0377] Nanocrystals are based on hexagons, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be lattice arrays such as pentagons and heptagons. In CAAC-OS, it is difficult to confirm a distinct grain boundary (also called a grain boundary) even in the vicinity of the strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice array. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0378] In addition, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In,M) layer.

[0379] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm distinct grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of metal oxides may decrease due to impurity incorporation, defect generation, etc., CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen vacancies (also referred to as V O : also called oxygen vacancy).). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0380] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0381] Note that indium-gallium-zinc oxide (hereinafter, IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may take a stable structure by using the above-described nanocrystals. In particular, since IGZO tends to be difficult to grow crystals in the air, a crystal smaller than a large crystal (here, a crystal of several mm or a crystal of several cm) (for example, the above-described nanocrystal) may be structurally more stable.

[0382] a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0383] Oxide semiconductors (metal oxides) have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0384] The metal oxide film functioning as a semiconductor layer can be formed using either one or both of an inert gas and an oxygen gas. Note that there is no particular limitation on the flow rate ratio (oxygen partial pressure) of oxygen during the formation of the metal oxide film. However, when obtaining a transistor with high field-effect mobility, the flow rate ratio (oxygen partial pressure) of oxygen during the formation of the metal oxide film is preferably 0% or more and 30% or less, more preferably 5% or more and 30% or less, and even more preferably 7% or more and 15% or less.

[0385] The metal oxide preferably has an energy gap of 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3 eV or more. By using a metal oxide with a wide energy gap in this way, the off-current of the transistor can be reduced.

[0386] The substrate temperature during the formation of the metal oxide film is preferably 350°C or lower, more preferably room temperature or higher and 200°C or lower, and even more preferably room temperature or higher and 130°C or lower. When the substrate temperature during the formation of the metal oxide film is room temperature, productivity can be increased, which is preferable.

[0387] The metal oxide film can be formed by a sputtering method. In addition, for example, a PLD method, a PECVD method, a thermal CVD method, an ALD method, a vacuum evaporation method, or the like may be used.

[0388] The above is the description of the metal oxide.

[0389] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0390] (Embodiment 3) In the present embodiment, an electronic device to which a display device according to an aspect of the present invention is applied will be described with reference to FIGS. 22 to 24.

[0391] The electronic device of the present embodiment includes a display device according to an aspect of the present invention. Since the display device has a function of detecting light, biometric authentication can be performed on the display unit, and touch or near-touch can be detected. The electronic device according to an aspect of the present invention is an electronic device that is difficult to be misused and has an extremely high security level. In addition, the functionality and convenience of the electronic device can be enhanced.

[0392] Examples of the electronic device include an electronic device having a relatively large screen such as a television device, a desktop or notebook personal computer, a monitor for a computer, a digital signage, a large game machine such as a pachinko machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio playback device, and the like.

[0393] The electronic device of the present embodiment may include a sensor (including a function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0394] The electronic device of the present embodiment can have various functions. For example, it can have a function of displaying various information (such as still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, and the like.

[0395] The electronic device 6500 shown in FIG. 22A is a portable information terminal that can be used as a smartphone.

[0396] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display unit 6502 has a touch panel function.

[0397] The display device according to an aspect of the present invention can be applied to the display unit 6502.

[0398] FIG. 22B is a schematic cross-sectional view including the end portion on the microphone 6506 side of the housing 6501.

[0399] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, and the like are arranged in a space surrounded by the housing 6501 and the protective member 6510.

[0400] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0401] In a region outside the display unit 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded-back portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0402] The flexible display according to an aspect of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Further, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. Further, by folding back a part of the display panel 6511 and arranging the connection portion with the FPC 6515 on the back side of the pixel portion, a narrow-bezel electronic device can be realized.

[0403] Fig. 23A shows an example of a television apparatus. In the television apparatus 7100, a display unit 7000 is incorporated in a housing 7101. Here, a configuration is shown in which the housing 7101 is supported by a stand 7103.

[0404] The display device according to one aspect of the present invention can be applied to the display unit 7000.

[0405] The operation of the television apparatus 7100 shown in Fig. 23A can be performed by an operation switch provided in the housing 7101 or a separate remote control unit 7111. Alternatively, the display unit 7000 may be provided with a touch sensor, and the television apparatus 7100 may be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit for displaying information output from the remote control unit 7111. Channel and volume operations can be performed by operation keys or a touch panel provided in the remote control unit 7111, and the video displayed on the display unit 7000 can be operated.

[0406] Note that the television apparatus 7100 has a configuration including a receiver and a modem. General television broadcasts can be received by the receiver. Also, by connecting to a communication network by wire or wirelessly via the modem, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication is also possible.

[0407] Fig. 23B shows an example of a notebook personal computer. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is incorporated in the housing 7211.

[0408] The display device according to one aspect of the present invention can be applied to the display unit 7000.

[0409] Figs. 23C and 23D show an example of digital signage.

[0410] The digital signage 7300 shown in Fig. 23C includes a housing 7301, a display unit 7000, a speaker 7303, etc. Further, it can have an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0411] Fig. 23D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0412] In Figs. 23C and 23(D), the display device according to an aspect of the present invention can be applied to the display unit 7000.

[0413] The larger the display unit 7000 is, the more information can be provided at once. Also, the larger the display unit 7000 is, the more likely it is to catch people's eyes, for example, the advertising effect can be enhanced.

[0414] By applying a touch panel to the display unit 7000, not only can an image or video be displayed on the display unit 7000, but also the user can operate it intuitively, which is preferable. Also, when used for applications such as providing route information or traffic information, the usability can be improved by intuitive operation.

[0415] Also, as shown in Figs. 23C and 23D, the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication and cooperation with an information terminal 7311 or an information terminal 7411 such as a smartphone held by the user. For example, the information of the advertisement displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched.

[0416] In addition, a game can also be executed on the digital signage 7300 or the digital signage 7400, using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). As a result, an unspecified number of users can participate in and enjoy the game simultaneously.

[0417] The electronic device shown in FIGS. 24A to 24F includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (including a function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 9008, and the like.

[0418] The electronic device shown in FIGS. 24A to 24F has various functions. For example, it can have a function of displaying various information (such as still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have a plurality of display units. In addition, a camera or the like may be provided in the electronic device, and it may have a function of taking a still image or a moving image and storing it in a recording medium (external or built-in to the camera), a function of displaying the taken image on the display unit, and the like.

[0419] Details of the electronic device shown in FIGS. 24A to 24F will be described below.

[0420] FIG. 24A is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as, for example, a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Further, the portable information terminal 9101 can display character or image information on its plurality of surfaces. FIG. 24A shows an example in which three icons 9050 are displayed. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming calls such as e-mail, SNS, and telephone, titles such as e-mail or SNS, sender names, dates and times, battery remaining amounts, antenna reception strengths, and the like. Or, an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0421] FIG. 24B is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces, respectively. For example, the user can check the information 9053 displayed at a position where it can be observed from above the portable information terminal 9102 in a state where the portable information terminal 9102 is stored in the breast pocket of the clothes. The user can check the display without taking the portable information terminal 9102 out of the pocket and can determine, for example, whether to receive a call.

[0422] FIG. 24C is a perspective view showing a wristwatch-type portable information terminal 9200. Also, the display surface of the display unit 9001 is provided to be curved, and display can be performed along the curved display surface. Further, the portable information terminal 9200 can also make a hands-free call by communicating with, for example, a wirelessly communicable headset. Also, the portable information terminal 9200 can perform data transmission and charging mutually with other information terminals by the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.

[0423] Figures 24D, 24E, and 24F are perspective views showing the foldable portable information terminal 9201. Further, FIG. 24D shows the state in which the portable information terminal 9201 is unfolded, FIG. 24F shows the state in which it is folded, and FIG. 24E is a perspective view of the state in the middle of changing from one of FIGS. 24D and 24F to the other. The portable information terminal 9201 is excellent in portability in the folded state and excellent in display listability due to a seamless wide display area in the unfolded state. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0424] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Description of Reference Numerals

[0425] ADC: Conversion unit: PA: Amplification unit: AMP: Comparison circuit: DAC: Conversion unit: VA: Amplification unit: MUX: Multiplexer circuit: TX, SE, RS, WX, SL, GL: Wiring: PD: Light receiving element: EL: Light emitting element: IN: Input terminal: OUT: Output terminal: V REF 、V REFR 、V REFS : Reference potential: AMP1, AMP2: Comparison circuit: C, C1, C2, C11, C12: Capacitance: M1 to M7: Transistor: SW1 to SW4: Switch: SEL1, SEL2: Selection circuit: 10: Imaging device: 11: Imaging unit: 12: Circuit unit: 13: Drive circuit unit: 15: Pixel: 21 to 23: Substrate: 30: Pixel: 31, 32: Terminal: 33: Wiring: 50: Display device: 51: Display unit: 52: Circuit unit: 53: Drive circuit unit: 61: Pixel: 61B, 61G, 61R: Sub-pixel: 62: Imaging pixel: 70: Pixel

Claims

1. having an amplification unit, a conversion unit, and an input terminal, wherein the amplification unit includes a comparison circuit, a first capacitor, a second capacitor, and a first switch, wherein the comparison circuit has an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein a first signal and a second signal are sequentially applied to the input terminal, wherein one of a pair of electrodes of the first capacitor is electrically connected to the input terminal, and the other is electrically connected to the inverting input terminal, wherein the second capacitor and the first switch are each electrically connected in parallel to the inverting input terminal and the output terminal, wherein when the first signal is applied, the first switch conducts, and a first reference potential is applied to the non-inverting input terminal; when the second signal is applied, the first switch is turned off, and a second reference potential having a potential different from the first reference potential is applied to the non-inverting input terminal, wherein the amplification unit outputs, to the output terminal, an output potential obtained by amplifying a difference between a potential difference between the first reference potential and the second reference potential and a potential difference between the first signal and the second signal during a period when the second signal is input, wherein the conversion unit is a semiconductor device that converts the output potential into a digital value.

2. having an amplification unit, a conversion unit, and an input terminal, wherein the amplification unit includes a comparison circuit, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a first wiring, and a second wiring, wherein the comparison circuit has an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein a first signal and a second signal are sequentially applied to the input terminal, wherein one of a pair of electrodes of the first capacitor is electrically connected to the input terminal, and the other is electrically connected to the inverting input terminal, wherein the second capacitor and the first switch are each electrically connected in parallel to the inverting input terminal and the output terminal, wherein the first wiring to which the first reference potential is applied and the non-inverting input terminal are electrically connected via the second switch, wherein the second wiring to which a second reference potential having a potential different from the first reference potential is applied and the non-inverting input terminal are electrically connected via the third switch, When the first signal is applied, the first switch conducts and a first reference potential is applied to the non-inverting input terminal. When the second signal is applied, the first switch is turned off and a second reference potential having a potential different from the first reference potential is applied to the non-inverting input terminal. During the period when the second signal is input, the amplification unit outputs an output potential obtained by amplifying the difference between the potential difference between the first reference potential and the second reference potential and the potential difference between the first signal and the second signal to the output terminal. The conversion unit is a semiconductor device that converts the output potential into a digital value. **Claim 3** The semiconductor device according to claim 1 or claim 2, a pixel, and a third wiring. The pixel includes a photoelectric conversion element and a pixel circuit. The pixel circuit outputs the first signal including the received light potential and the second signal including the reset potential to the third wiring. The third wiring is electrically connected to the input terminal, and it is an imaging device. **Claim 4** The semiconductor device according to claim 1 or claim 2, a plurality of pixels, a plurality of third wirings, and a first selection circuit. The pixel includes a photoelectric conversion element and a pixel circuit. The pixel circuit outputs the first signal including the received light potential and the second signal including the reset potential to the third wiring. The plurality of third wirings are electrically connected to the first selection circuit. The first selection circuit selects one of the plurality of third wirings and electrically connects the selected third wiring to the input terminal, and it is an imaging device. **Claim 5** In claim 3 or claim 4, An imaging device having a correlated double sampling circuit between the third wiring and the input terminal. **Claim 6** In any one of claims 3 to 5, It has a first substrate and a second substrate. The semiconductor device is provided on the first substrate. The pixel is provided on the second substrate, and it is an imaging device. **Claim 7** It has an amplification unit, a first conversion unit, a second conversion unit, an input terminal, and a first output terminal. The amplification unit includes a comparison circuit, a first capacitor, a second capacitor, and a first switch. The comparison circuit has an inverting input terminal, a non-inverting input terminal, and a second output terminal. The first signal and the second signal are sequentially applied to the input terminal. The first capacitance is such that one of the pair of electrodes is electrically connected to the input terminal and the other is electrically connected to the inverting input terminal. The second capacitance and the first switch are each electrically connected in parallel to the inverting input terminal and the second output terminal. When the first signal is applied, the non-inverting input terminal of the amplifier section is supplied with a first reference potential, and when the second signal is applied, the non-inverting input terminal is supplied with a second reference potential having a potential different from the first reference potential. During the period when the second signal is input, the amplifier section outputs to the second output terminal an output potential obtained by amplifying the difference between the potential difference between the first reference potential and the second reference potential and the potential difference between the first signal and the second signal. The first conversion section converts the output potential into a digital value. The second conversion section is supplied with a digital signal, converts the digital signal into an analog third signal, and outputs the analog third signal to the first output terminal. The amplifier section, the first conversion section, and the second conversion section are provided on a first substrate, and are semiconductor devices.

8. In claim 7, having a fourth switch; the first output terminal and the non-inverting input terminal are electrically connected via the fourth switch; the second conversion section outputs the third signal including a data potential, the first reference potential, and the second reference potential based on the digital signal; during the period when the first reference potential is output to the first output terminal and during the period when the second reference potential is output, the fourth switch is in a conductive state; during the period when the data potential is output to the first output terminal, the fourth switch is in a non-conductive state, and is a semiconductor device.

9. In claim 7, having a second switch, a third switch, a fourth switch, a first wiring, and a second wiring; the first output terminal and the non-inverting input terminal are electrically connected via the fourth switch; the first wiring to which the first reference potential is applied and the non-inverting input terminal are electrically connected via the second switch; the second wiring to which the second reference potential is applied and the non-inverting input terminal are electrically connected via the third switch; the second conversion section outputs the third signal including a data potential, the first reference potential, and the second reference potential based on the digital signal. During a period in which the first reference potential is output to the first output terminal and a period in which the second reference potential is output, the fourth switch is in a conductive state, A semiconductor device in which the fourth switch is in a non-conductive state during a period in which the data potential is output to the first output terminal.

10. A semiconductor device according to claim 8 or claim 9, a first pixel, a second pixel, a third wiring, and a fourth wiring, The first pixel includes a photoelectric conversion element and a first pixel circuit. The first pixel circuit outputs the first signal including the received light potential and the second signal including the reset potential to the third wiring. The third wiring is electrically connected to the input terminal. The second pixel includes a display element and a second pixel circuit. The fourth wiring is electrically connected to the first output terminal and the second pixel circuit. The second pixel circuit controls the gradation of the display element based on the data potential.

11. In claim 10, It has a second selection circuit, a third selection circuit, and a fifth wiring. The third wiring and the fourth wiring are electrically connected to the second selection circuit. The input terminal and the first output terminal are electrically connected to the third selection circuit. The second selection circuit and the third selection circuit are electrically connected via the fifth wiring. The second selection circuit selects either the third wiring or the fourth wiring and electrically connects it to the fifth wiring. The third selection circuit selects either the input terminal or the first output terminal and electrically connects it to the fifth wiring.

12. In claim 10 or claim 11, The display element is a light-emitting element.

13. In any one of claims 10 to 12, It has a second substrate different from the first substrate, The semiconductor device is provided on the first substrate, The first pixel and the second pixel are provided on the second substrate, The first substrate is a single crystal substrate, The second substrate includes glass or an organic resin.

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