Wafer Inspection and Verification

Abstract

The method includes acquiring a first reference image of a first wafer. The method includes acquiring a first image of the first wafer in a manufacturing state. The first wafer has a first verification structure. The method includes acquiring a first physical measurement when the first wafer is in a manufacturing state. The first physical measurement corresponds to the first verification structure. The method includes determining that the first image matches the first reference image. The method includes acquiring electrical parameter measurements corresponding to the verification structure of a received wafer in a post-manufacturing state. The method includes calculating a physical parameter value based on the electrical parameter measurements. The method includes generating a verification response by comparing the physical parameter value to the first physical measurement.

Description

Technical Field

[0001] The present disclosure relates to wafer manufacturing, and more particularly to wafer inspection and verification.

Background Art

[0002] Wafer manufacturing may include forming layers of various materials on a wafer (e.g., a silicon wafer) to fabricate multiple electronic circuits on the wafer. The wafer may be separated into a set of dies, each of which may be integrated into various electronic devices.

Summary of the Invention

[0003] According to an embodiment of the present disclosure, a method may include obtaining a first reference image of a first wafer. The method may include obtaining a first image of the first wafer in a fabrication state. In the fabrication state, the first wafer may have fewer than a threshold number of fabrication layers. The first wafer may have a first verification structure. The method may include obtaining a first physical measurement when the first wafer is in the fabrication state. The first physical measurement may correspond to the first verification structure. The method may include determining that the first image matches the first reference image by comparing the first image with the first reference image at a first time. The method may include obtaining an electrical parameter measurement at a second time after the first time. The electrical parameter measurement may correspond to a verification structure of a received wafer in a post-fabrication state. In the post-fabrication state, the received wafer may have a second number of fabrication layers equal to the threshold number. The method may include calculating a physical parameter value based on the electrical parameter measurement. The method may include generating a verification response by comparing the physical parameter value with the first physical measurement.

[0004] A system and a computer program product corresponding to the above method are also included herein.

[0005] According to an embodiment of the present disclosure, a method may include obtaining a first physical measurement value. The first physical measurement value may correspond to a first verification structure of a first wafer in a manufacturing state. In the manufacturing state, the first wafer may have some manufacturing layers less than a threshold number. The method may include obtaining an electrical parameter measurement value. The electrical parameter measurement value may correspond to a verification structure of a received wafer in a post-manufacture state. In the post-manufacture state, the received wafer may have a second number of manufacturing layers equal to the threshold number. The method may include calculating a physical parameter value based on the electrical parameter measurement value. The method may include generating a verification response by comparing the physical parameter value with the first physical measurement value.

[0006] Embodiments of the present disclosure may be shown as a device having a wafer. The wafer may have a first verification structure within a first region of the wafer. The first verification structure may include a first target component. The first verification structure may have a first measurable electrical parameter. The first measurable electrical parameter may correspond to a first physical characteristic of the first target component.

[0007] The above summary is not for the purpose of describing each illustrated embodiment or every implementation of the present disclosure.

[0008] The drawings included in this application are incorporated herein and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to clarify the principles of the present disclosure. The drawings are merely examples of some embodiments and do not limit the present disclosure.

Brief Description of the Drawings

[0009]

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DETAILED DESCRIPTION OF THE INVENTION

[0010] While there are various modifications and alternative forms of the present invention, the details of the present invention are shown by way of example in the drawings and will be described in detail. However, it should be understood that there is no intention to limit the present invention to the specific embodiments described. On the contrary, it is intended to embrace all modifications, equivalents, and alternative forms that fall within the spirit and scope of the present invention.

[0011] Aspects of the present disclosure relate to wafer manufacturing, and more particularly, aspects relate to wafer inspection and verification. The present disclosure is not necessarily limited to such fields of application, but various aspects of the present disclosure can be understood through the discussion of various examples using this context.

[0012] Wafer manufacturing can include forming layers of various materials on a wafer (e.g., a silicon wafer) to fabricate multiple electronic circuits on the wafer. Such layers can be formed according to a design plan that includes detailed specifications (e.g., size, shape, location, or material composition, or a combination thereof) for each layer of the wafer. In some examples, a designing entity can submit such a design plan to a manufacturing entity for manufacturing. Such a submission can introduce one or more security risks. As an example, a malicious actor within the manufacturing entity can potentially modify the design plan to omit functionality, or add functionality to one or more of the electronic circuits. As a result of the modification, damage, failure, or destruction, or a combination thereof, of the electronic circuit, or a device that subsequently includes the electronic circuit, or both, can occur. Thus, it can be essential for the designing entity to have effective means to confirm that each wafer is manufactured according to the detailed specifications.

[0013] Obtaining such confirmation can raise issues. For example, circuit designs can include a large number of layers and features, and thus it can be difficult to detect malicious design modifications during wafer inspection. Further, in some cases, malicious actors may attempt to bypass the inspection procedure by replacing genuine wafers that passed inspection with modified or non-genuine wafers.

[0014] To address these and other issues, embodiments of the present disclosure include a wafer verification system. In some embodiments, the wafer verification system can perform layer-specific inspections of the wafer during manufacturing. In some embodiments, after such layer-specific inspections, the wafer verification system can verify that the completed wafer is the wafer that received the layer-specific inspections during manufacturing. More specifically, in some embodiments, to perform layer-specific inspections, the wafer verification system can obtain a set of images of the wafer in its as-manufactured state. The images can include the manufacturing layers formed on the wafer after one or more pattern transfer processes. In such embodiments, the wafer verification system can confirm that one or more layers of the wafer are formed in accordance with predetermined specifications by comparing the set of images to a set of reference images. In some embodiments, the wafer verification system can obtain physical measurements corresponding to the verification structures of the wafer when the wafer is in its as-manufactured state. In such embodiments, the wafer verification system can verify that the received, completed wafer is the same wafer on which the physical measurements were obtained. In some embodiments, the wafer verification system can perform such verification by comparing the physical measurements to calculated physical parameter values corresponding to the verification structures. In some embodiments, the wafer verification system can perform such verification by comparing a plurality of such physical measurements to a plurality of calculated physical parameter values corresponding to respective verification structures of the wafer.

[0015] Accordingly, embodiments of the present disclosure can perform a complete and accurate inspection and / or verification of a wafer. By comparing images of multiple manufacturing layers of a wafer, embodiments of the present disclosure can identify deviations from a given wafer specification at the layer-specific level. Accordingly, embodiments of the present disclosure can achieve an improved ability to detect design modifications to a wafer. Embodiments of the present disclosure that can verify / authenticate a wafer based on measurements of one or more verification structures can provide several advantages. For example, the verification structure of a first wafer can provide unique physical measurements for the first wafer. Accordingly, embodiments of the present disclosure can verify the first wafer based on the unique physical measurements and / or distinguish the first wafer from a different second wafer. Further, embodiments of the present disclosure can include multiple verification structures at multiple wafer locations, and each verification structure can provide such unique physical measurements. Accordingly, the verification structure, the location of the verification structure, or the unique physical measurements that the verification structure can provide, or a combination thereof, can act substantially as a fingerprint for the wafer. Embodiments of the present disclosure can identify and / or distinguish a wafer based on such a fingerprint. Accordingly, embodiments of the present disclosure can assist in detecting when a modified or non-genuine wafer is presented as a genuine wafer.

[0016] Referring to the figures, FIG. 1 shows a computing environment 100 that includes one or more of each of a wafer verification system 105, a patterning device 125, a measurement device 135, an image capture device 140, a computing device 145, or a network 150, or a combination thereof. In some embodiments, at least one of the wafer verification system 105, the patterning device 125, the measurement device 135, the image capture device 140, or the computing device 145, or a combination thereof, can exchange data with at least each other through at least one network 150. One or more of each of the wafer verification system 105, the patterning device 125, the measurement device 135, the image capture device 140, the computing device 145, or the network 150, or a combination thereof, can include a computer system such as the computer system 401 discussed in connection with FIG. 4.

[0017] In some embodiments, the wafer verification system 105 can be included within software installed on at least one computer system of at least one of the patterning device 125, the measurement device 135, the image capture device 140, or the computing device 145, or a combination thereof. For example, in some embodiments, the wafer verification system 105 can be included as a plug-in software component of the software installed on the patterning device 125. The wafer verification system 105 can include program instructions implemented by a processor such as the processor of the computing device 145 to perform one or more operations discussed in connection with FIG. 2.

[0018] In some embodiments, the wafer verification system 105 may include one or more modules such as a data manager 110, an image analyzer 115, or a device manager 120, or a combination thereof. In some embodiments, the data manager 110, the image analyzer 115, or the device manager 120, or a combination thereof may be integrated into a single module. In some embodiments, the data manager 110 may obtain, interpret, analyze, store, and / or initiate storage of data such as reference data about the wafer 130. In some embodiments, the image analyzer 115 may obtain and analyze an image of the wafer 130. In some embodiments, the image analyzer 115 may include a set of neural networks or image analysis software or both to identify a match between the image of the wafer 130 and a reference image of the wafer 130. In some embodiments, the device manager 120 may send commands to one or more patterning devices 125, measurement devices 135, image capture devices 140, or computing devices 145, or a combination thereof. For example, in some embodiments, the device manager 120 may send a command to the measurement device 135 to obtain an electrical parameter measurement of the received wafer. In some embodiments, one or more of the data manager 110, the image analyzer 115, or the device manager 120, or a combination thereof may include program instructions implemented by a processor such as a processor of the computing device 145 to perform one or more operations discussed in connection with FIG. 2. For example, in some embodiments, the data manager 110 may include program instructions to perform operations 205 and 240 - 255 of FIG. 2. In some embodiments, the image analyzer 115 may include program instructions to perform operations 210 and 220 - 230 of FIG. 2. In some embodiments, the device manager 120 may include program instructions to perform operations 215 and 235 of FIG. 2.

[0019] In some embodiments, one or more patterning devices 125 may include a machine or apparatus or a set of both configured to perform processes such as photolithography, etching, deposition, etc. to form a manufacturing layer on the wafer 130. The wafer 130 may refer to a substrate on which a set of electronic circuits may be formed. In some embodiments, the wafer 130 may be composed of a semiconductor material such as silicon.

[0020] In some embodiments, one or more measurement devices 135 may include a machine or apparatus or a set of both configured to obtain physical measurements or electrical parameter measurements or both of the wafer 130. For example, in some embodiments, one or more measurement devices 135 may include a precision ellipsometer configured to measure the thickness of the material formed on the wafer 130. In some embodiments, one or more measurement devices 135 may be configured to measure the registration accuracy between shapes printed at different manufacturing levels or the same manufacturing level on the wafer 130. In some embodiments, one or more measurement devices 135 may include a scanning electron microscope configured to measure dimensions related to the wafer 130. In some embodiments, one or more measurement devices may include a precision multimeter configured to obtain electrical parameter measurements of the wafer 130.

[0021] In some embodiments, one or more image capture devices 140 may include a camera, a scanning electron microscope, and the like. The one or more image capture devices may be configured to capture a set of images of the wafer 130. In some embodiments, the set of images may include images of one or more regions or manufacturing layers or both of the wafer 130. In some embodiments, the patterning device 125, the measurement device 135, or the image capture device 140, or a combination thereof, may be integrated into a single device.

[0022] In some embodiments, one or more computing devices 145 may include a computer or a server. For example, in some embodiments, one or more computing devices 145 may include a physical computer, such as a computer in a manufacturing facility, that operates the patterning device 125. The one or more computing devices 145 may be configured to store and / or process data such as one or more thresholds, measurements, or images, or a combination thereof, of the wafer 130. In some embodiments, the network 180 may be a wide area network (WAN), a local area network (LAN), the Internet, or an intranet. In some embodiments, the network 180 may be substantially similar to, or the same as, the cloud computing environment 50 discussed in connection with FIG. 5.

[0023] FIG. 2 shows a flowchart of an exemplary method 200 for performing wafer inspection and verification according to an embodiment of the present disclosure. The method 200 may be performed by a wafer verification system, such as the wafer verification system 105 discussed in connection with FIG. 1.

[0024] In operation 205, the wafer verification system may obtain reference data for one or more wafers. The reference data may include information regarding the manufacture of one or more wafers. For example, in some embodiments, the reference data may include design specifications for manufacturing one or more wafers. Such specifications may include information such as the size, shape, pattern, position, orientation, or material, or a combination thereof, of features such as trenches, leads, conductors, insulators, pillars, or layers, or combinations thereof, for forming electronic circuits on one or more wafers. In some embodiments, the reference data may include a set of reference images (e.g., digital photographs, scanning electron microscope images, etc.). In some embodiments, the set of reference images may include images from an electronic model of the wafer (e.g., a set of computer-aided design drawings of the wafer). The set of reference images may indicate the appropriate manufacturing characteristics of the wafer, i.e., the characteristics of a wafer manufactured in accordance with the design specifications of the wafer. For example, the reference images may indicate the appropriate size, shape, pattern, position, orientation, or material, or a combination thereof, of features such as trenches, leads, conductors, insulators, pillars, or layers, or combinations thereof, for the wafer. As discussed in more detail below, the wafer verification system may utilize such reference images to identify deviations from the design specifications that occur during wafer manufacturing.

[0025] In some embodiments, the set of reference images may include images of the wafer after one or more pattern transfer processes. For example, in some embodiments, the design specification may include a plurality of pattern transfer processes (e.g., etching, deposition, or doping processes, or combinations thereof) to form a threshold number of manufacturing layers on the wafer. In this example, the pattern transfer process may form a total of 50 manufacturing layers on the wafer. In this example, the set of reference images may include one or more images of 50 manufacturing layers formed from each pattern transfer process. As an example, the set of reference images may include an image of a first wafer layer formed after etching the wafer and an image of a second wafer layer formed after subsequent deposition of material onto the wafer. In some embodiments, the set of reference images may include one or more images for each manufacturing layer of the wafer. In some embodiments, the set of reference images may include one or more images of a predetermined manufacturing layer of the wafer (e.g., images of the first, third, and seventh manufacturing layers of a wafer having a total of 10 manufacturing layers). In some embodiments, the set of reference images may include an image of the entire surface of the wafer, or an image of a predetermined region of the wafer, or both. In some embodiments, such a predetermined manufacturing layer or predetermined region or both may be selected by an entity such as a programmer or operator of the wafer verification system, or by the wafer verification system itself (e.g., the wafer verification system may randomly select a manufacturing layer or region or both in which the image may be included in the set of reference images).

[0026] In operation 210, the wafer verification system may acquire one or more images of the wafer in a manufacturing state. When the wafer is in a manufacturing state, the wafer may have some manufacturing layers less than a threshold number of layers. In some embodiments, the threshold number of layers may be the total number of manufacturing layers associated with a completed wafer (e.g., a wafer on which all pattern transfer processes have been completed). For example, in some embodiments, multiple pattern transfer processes may form a total of 25 manufacturing layers, or manufacturing levels, on the wafer. In this example, when the wafer has a first manufacturing layer, a second manufacturing layer, a third manufacturing layer, etc., the wafer is in a manufacturing state until all 25 manufacturing layers are formed on the wafer. In some embodiments, when the wafer has a number of manufacturing layers equal to the threshold number of manufacturing layers associated with a completed wafer, the wafer may be in a post-manufacturing state. Thus, in the above example, when the wafer has a total of 25 manufacturing layers, the wafer may be in a post-manufacturing state.

[0027] In some embodiments, operation 210 may include the wafer verification system acquiring a set of images of one or more manufacturing layers of the wafer. The set of images may indicate the actual manufacturing characteristics of the wafer. For example, the images may indicate characteristics such as the actual size, shape, pattern, position, orientation, or material, or a combination thereof, of features such as trenches, leads, conductors, insulators, pillars, or layers, or a combination thereof, on the wafer. Such characteristics may or may not conform to the design specifications for the wafer. In some embodiments, the set of images may include an image of the entire surface of the wafer, or an image of a predetermined region of the wafer, or both. In some embodiments, such a predetermined manufacturing layer or predetermined region, or both, may be selected by an entity such as a programmer or operator of the wafer verification system, or by the wafer verification system itself (e.g., the wafer verification system may randomly select a manufacturing layer or region, or both, in which the image may be included in the set of images).

[0028] In some embodiments, operation 210 may include the wafer verification system obtaining a set of images from an image capture device (e.g., image capture device 140 of FIG. 1). In some embodiments, operation 210 may include the wafer verification system instructing one or more image capture devices to capture one or more images of the wafer. For example, in some embodiments, the wafer verification system may instruct a digital camera to capture an image of a first region of the wafer and instruct a scanning electron microscope to capture ten images of ten different regions of the wafer. In some embodiments, the wafer verification system may obtain a set of images from a patterning device (e.g., patterning device 125 of FIG. 1). In some embodiments, the wafer verification system may obtain a set of images stored on a computing device (e.g., computing device 145 of FIG. 1).

[0029] In operation 215, the wafer verification system may obtain physical measurement data of the wafer in a manufactured state. The physical measurement data may include measurements of at least one physical characteristic of the wafer. In some embodiments, when the wafer is in a manufactured state, such physical characteristics may include visually perceivable characteristics such as distance (e.g., length, width, height, or thickness, or a combination thereof). For example, in some embodiments, when the wafer is in a manufactured state, the width of a conductor formed on a manufacturing layer may be visually perceivable, but the conductor may be blocked by subsequent manufacturing layers, and thus the conductor may be less visible (e.g., invisible) in a post-manufacture state. Thus, in some embodiments, an optical measurement device may measure the width of the conductor when the wafer is in a manufactured state, but measuring such width may be hindered when the wafer is in a post-manufacture state due to a decrease in the visibility of the conductor.

[0030] In some embodiments, the physical property to be measured may correspond to a target component of the verification structure. The verification structure may refer to the structure of the wafer in the post-manufacture state. Such a verification structure may be configured to provide a measurable electrical parameter corresponding to the physical property of the target component. For example, continuing with the above example, the verification structure may include a conductor formed on the fifth manufacturing layer of the wafer and a pair of conductive probe pads formed on the 50th final manufacturing layer of the wafer. In this example, the conductor may be the target component of the verification structure. As the target component, the conductor may have a physical property (in this example, width) corresponding to a measurable electrical parameter (for example, resistance). The measurable electrical parameter may be measured across the pair of conductive probe pads formed on the 50th manufacturing layer of the wafer (this aspect will be further discussed below in connection with operation 235). Continuing with this example, operation 215 may include the wafer verification system obtaining a width measurement of the conductor after the conductor is formed on the fifth manufacturing layer and before the visibility of the conductor is blocked by subsequent manufacturing layers.

[0031] In some embodiments, an operative feature (for example, a trench, a lead, a conductor, an insulator, or a pillar, or a combination thereof) of an electronic circuit formed on a wafer may be a component (for example, a target component) of the verification structure. In such embodiments, the verification structure may be integrated into the design of the electronic circuit. In some embodiments, the verification structure may be independent of the design of the electronic circuit and may function solely for verification as discussed in the present disclosure. For example, in some embodiments, the verification structure may not contribute to the operating performance of a computer chip formed on the wafer, but rather may function solely to verify that the wafer is genuine when the wafer is in the post-manufacture state.

[0032] In some embodiments, operation 215 may include the wafer verification system obtaining physical measurement data from a measurement device (e.g., measurement device 135 of FIG. 1). In some embodiments, operation 215 may include the wafer verification system instructing one or more measurement devices to obtain physical measurement data from the wafer. In some embodiments, an image capture device (e.g., image capture device 140 of FIG. 1) or a patterning device (e.g., patterning device 135 of FIG. 1) or both may be configured to obtain physical measurement data from the wafer. In such embodiments, operation 215 may include the wafer verification system obtaining physical measurement data from the image capture device or the patterning device or both. In some embodiments, operation 215 may include the wafer verification system instructing one or more image capture devices or patterning devices or both to obtain physical measurement data from the wafer.

[0033] By obtaining physical measurement data in operation 215, the wafer verification system can obtain a set of unique physical measurements of the wafer from one or more manufacturing layers of the wafer. For example, in some embodiments, operation 215 can include the wafer verification system obtaining a first physical measurement of a first target component on a second manufacturing layer of the wafer. In this example, the first physical measurement can be precisely measured (e.g., the first physical measurement can be measured on the order of nanometers). Thus, the first physical measurement can be unique in that different wafers are less likely to give the same physical measurement for their respective corresponding first target components. Continuing with this example, operation 215 can further include the wafer verification system obtaining a second physical measurement of a second target component on a tenth manufacturing layer of the wafer. Thus, in this example, the set of physical measurements (i.e., the first physical measurement and the second physical measurement) can be unique in that different wafers are less likely to give the same set of physical measurements for their respective first target components and second target components. Thus, in some embodiments, the physical measurement data obtained in operation 215 can act as a fingerprint that can substantially facilitate identifying and / or differentiating the wafer. Such identification or differentiation or both are discussed further below in connection with operation 245.

[0034] In operation 220, the wafer verification system may compare one or more images of the wafer obtained in operation 210 with one or more corresponding reference images of the wafer obtained in operation 205 to determine whether one or more matches exist. In some embodiments, when the characteristics of an image have a threshold degree of similarity to the characteristics of the corresponding reference image, the wafer verification system may determine that the image of the wafer matches the corresponding reference image of the wafer. For example, in some embodiments, when the shown size, shape, quantity, pattern, position, orientation, or material of features such as trenches, leads, conductors, insulators, pillars, or layers, or combinations thereof, for a wafer, have a threshold similarity between the image of the wafer and the corresponding reference image of the wafer, the wafer verification system may determine that a match exists. In a more specific example, when the percentage error between a first orientation angle of a conductor shown in an image of a wafer and a second orientation angle of the corresponding conductor shown in the reference image of the wafer does not exceed a threshold value of 1%, the wafer verification system may determine that the first orientation angle matches the second orientation angle. In some embodiments, such a threshold similarity may be selected by an entity such as a programmer or operator of the wafer verification system, or by the wafer verification system itself. In some embodiments, operation 220 may include the wafer verification system using one or both of image analysis techniques or a set of neural networks to identify one or more matches between one or more images of the wafer and one or more reference images of the wafer. If the wafer verification system determines that one or more images of the wafer match one or more corresponding reference images of the wafer, the wafer verification system may proceed to operation 230. Alternatively, if the wafer verification system determines that one or more images of the wafer do not match one or more corresponding reference images of the wafer, the wafer verification system may proceed to operation 225.

[0035] In operation 225, the wafer verification system may initiate a notification indicating that one or more images of the wafer obtained in operation 210 do not match one or more corresponding reference images of the wafer. In some embodiments, a non-matching image may indicate that the wafer contains malicious design modifications. In some embodiments, such a notification may indicate that one or more manufacturing layers of the wafer are not formed in accordance with a predetermined specification for the wafer. In some embodiments, operation 225 may include the wafer verification system generating an alphanumeric text message, an audible alert, or a visual alert, or a combination thereof. In some embodiments, operation 225 may include the wafer verification system issuing commands to a device, such as a computing device, to generate and / or issue such a text message or alert or both.

[0036] In operation 230, the wafer verification system may determine whether a threshold number of manufacturing layers have been formed on the wafer. The threshold number of manufacturing layers may be the total number of manufacturing layers associated with a completed wafer (e.g., a wafer on which all pattern transfer processes have been completed). In some embodiments, operation 230 may include the wafer verification system analyzing the reference data or image or both of the wafer to determine whether the wafer is in a manufactured state. For example, in some embodiments, the wafer verification system may determine that the wafer is in a manufactured state by identifying differences between an image of the wafer and a reference image of the wafer in a post-manufacture state. In this example, such differences may indicate that one or more manufacturing layers should be formed on the wafer before the wafer has a threshold number of manufacturing layers. In some embodiments, operation 230 may include the wafer verification system obtaining information regarding additional layers to be formed on the wafer from devices such as a patterning device (e.g., patterning device 125 of FIG. 1) or a computing device (e.g., computing device 145 of FIG. 1). Based on such information, the wafer verification system may determine whether a threshold number of manufacturing layers have been formed on the wafer. If the wafer verification system determines that a threshold number of manufacturing layers have been formed on the wafer, the wafer verification system may proceed to operation 235. Alternatively, if the wafer verification system determines that a threshold number of manufacturing layers have not been formed on the wafer, the wafer verification system may proceed to operation 210.

[0037] In operation 235, the wafer verification system may obtain a set of electrical parameter measurements for the received wafer. The "received wafer" may refer to a wafer in a post - manufacturing state to be verified or authenticated. In some embodiments, the received wafer may be received by a measurement device (e.g., measurement device 135 of FIG. 1) that obtains a set of electrical parameter measurements from the received wafer and transmits such measurements to the wafer verification system. In some embodiments, verifying the received wafer may include identifying the received wafer as the wafer inspected in operation 220. In some embodiments, verifying the received wafer may include distinguishing the received wafer from the wafer inspected in operation 220. As discussed below, the wafer verification system may use the set of electrical parameter measurements to verify the received wafer.

[0038] In an exemplary scenario, at a first time, the wafer verification system may inspect a first wafer by image comparison as discussed in connection with operation 220. Further at the first time, the wafer verification system may obtain physical measurements corresponding to the verification structure as discussed in connection with operation 215. Continuing with this example, at a second time after the first time, a measurement device may receive the wafer to be verified. The measurement device may measure electrical parameters (e.g., capacitance, resistance, current, etc.) of the verification structure on the received wafer. Thereafter, in operation 235, the wafer verification system may obtain the electrical parameter measurements from the measurement device.

[0039] In operation 240, the wafer verification system may calculate a set of physical parameter values based on the set of electrical parameter measurement values obtained in operation 235. In some embodiments, the physical parameter values calculated in operation 240 may correspond to physical measurement values of the target structure. For example, in some embodiments, operation 235 may include the wafer verification system obtaining capacitance measurement values of the verification structure of the received wafer. In this example, the capacitance measurement values may correspond to the thickness of the electrical insulator of the verification structure. Thus, in this example, operation 240 may include the wafer verification system calculating the thickness of the electrical insulator using known scientific principles.

[0040] In operation 245, the wafer verification system compares one or more physical parameter values calculated in operation 240 with one or more physical measurement values obtained in operation 215 to determine whether one or more matches exist. The existence of a match may verify that the received wafer had the physical measurement values obtained by the wafer verification system in operation 215. Thus, the existence of a match may indicate that the received wafer was inspected by the wafer verification system in operation 220. The absence of a match may indicate that the received wafer did not have the physical measurement values obtained by the wafer verification system in operation 215. Thus, the absence of a match may indicate that the received wafer was not inspected by the wafer verification system in operation 220. If the wafer verification system determines that one or more of the physical parameter values match one or more of the physical measurement values, the wafer verification system may proceed to operation 250. Alternatively, if the wafer verification system determines that one or more of the physical parameter values do not match one or more of the physical measurement values, the wafer verification system may proceed to operation 255.

[0041] In operation 250, the wafer verification system may generate a match verification response. The match verification response may indicate that the received wafer is the wafer inspected by the wafer verification system in operation 220. In some embodiments, operation 250 may include the wafer verification system generating an alphanumeric text message, an audible alarm, or a visual alarm, or a combination thereof, to indicate a match. In some embodiments, operation 250 may include the wafer verification system issuing commands to a device, such as a computing device, to generate and / or issue such a text message or alarm or both.

[0042] In operation 255, the wafer verification system may generate a no-match verification response. The no-match verification response may indicate that the received wafer is not the wafer inspected by the wafer verification system in operation 220. In some embodiments, operation 255 may include the wafer verification system generating an alphanumeric text message, an audible alarm, or a visual alarm, or a combination thereof, to indicate a lack of a match. In some embodiments, operation 255 may include the wafer verification system issuing commands to a device, such as a computing device, to generate and / or issue such a text message or alarm or both.

[0043] FIG. 3A shows a top view of an exemplary wafer 300 according to an embodiment of the present disclosure. Wafer 300 includes dies 301, 304, 308, 312. Die 301 is disposed within a first region 302 of wafer 300. Die 312 includes a second region 314 in which a verification structure discussed in connection with FIGS. 3D and 3E is disposed. Die 308 includes a third region 310 in which a verification structure discussed in connection with FIGS. 3F and 3G is disposed. Die 304 includes a fourth region 306 in which a verification structure discussed in connection with FIGS. 3H and 3I is disposed.

[0044] FIG. 3B shows image 316 of die 301 and reference image 318 corresponding to die 301. Image 316 can be obtained by the wafer verification system in operation 210 of FIG. 2. Reference image 318 can be obtained by the wafer verification system in operation 205 of FIG. 2. Both image 316 and reference image 318 show region 302 of wafer 300 in a manufactured state. Image 316 shows a set of conductors 320 of a first manufacturing layer formed on wafer 300. In some embodiments, conductors 320 can be functional features of an electronic circuit design. Reference image 318 shows a set of reference conductors 322 of a first reference manufacturing layer of wafer 300. Reference conductors 322 can indicate appropriate characteristics for the set of conductors 320. For example, reference conductors 322 can have a size that conforms to the design specifications for wafer 300. Thus, in this example, the wafer verification system can determine that the images match when comparing image 316 to reference image 318. In this example, the wafer verification system can make such a determination based on the percentage error between the size of conductors 320 and the size of reference conductors 322 not exceeding a threshold of 5%.

[0045] Figure 3C shows image 324 and reference image 326 corresponding to image 316 and reference image 318 respectively. Image 324 can be obtained by the wafer verification system in operation 210 of FIG. 2. Reference image 326 can be obtained by the wafer verification system in operation 205 of FIG. 2. Image 324 shows region 302 of wafer 300 after a set of conductors 328, 330 of a second manufacturing layer are formed on wafer 300. In some embodiments, conductor 328 can be a functional feature of an electronic circuit design. Reference image 326 shows a set of reference conductors 332, 334 of a second reference manufacturing layer of wafer 300. Similar to reference conductor 322, reference conductors 332, 334 can indicate appropriate characteristics for the set of conductors 328, 330. For example, reference conductors 332, 334 can have lengths that conform to the design specifications for wafer 300. Thus, in this example, the wafer verification system can determine that the images do not match when comparing image 324 to reference image 326. In this example, the wafer verification system can determine the lack of match based on the percentage error between the length of conductor 330 and the length of reference conductor 334 exceeding a threshold of 2%. In this example, the non-matching images can indicate that wafer 300 has a malicious design modification to the second manufacturing layer of wafer 300.

[0046] Figure 3D shows a cross-sectional view of an exemplary target component 338 within region 314 of wafer 300 according to an embodiment of the present disclosure. Target component 338 can be an insulator formed on conductive layer 340 of wafer 300. In FIG. 3D, wafer 300 is in a manufacturing state, and thus target component 338 can have a top surface 350 that is not blocked by subsequent manufacturing layers. Since the top surface 350 of target component 338 is not blocked, the wafer verification system can obtain physical measurements (e.g., thickness measurements) of target component 338. The wafer verification system can obtain physical measurements as described in connection with operation 215 of FIG. 2. In some embodiments, the wafer verification system can use an ellipsometer to obtain physical measurements.

[0047] Figure 3E is a cross-sectional view of an exemplary verification structure 342 including a target component 338 according to an embodiment of the present disclosure. In Figure 3E, the wafer 300 is in a post-manufacture state. Thus, the verification structure 342 includes a target component 338 formed on a conductive layer 340, as well as conductors 344, and probe pads 348, 346. The probe pads 348, 346 are included within a manufacturing layer formed on top of the manufacturing layer including the target component 338. Further, when the wafer 300 is in a post-manufacture state, the top surface 350 of the target component 338 may be blocked, and thus, physical measurements of the target component 338 by a device such as an ellipsometer may not be available. However, the verification structure 342 may be configured to provide electrical parameter measurements (e.g., the capacitance between probe pads 348 and 346). By utilizing known scientific principles, the wafer verification system may calculate the thickness of the target component 338 based on such capacitance, as described in connection with operation 240 of Figure 2. Using the calculated thickness, the wafer verification system may verify the wafer, as described in connection with operation 245 of Figure 2.

[0048] Figure 3F shows a cross-sectional view of an exemplary target component 356 within region 310 of wafer 300 according to an embodiment of the present disclosure. The target component 356 may be a conductor formed on an insulator 358 of the wafer 300. In Figure 3F, the wafer 300 is in a manufacturing state, and thus the target component 356 may have a visible top surface 354. Since the top surface 354 is visible, the wafer verification system may obtain physical measurements (e.g., width 363) of the target component 356.

[0049] Figure 3G shows a top view of an exemplary verification structure 360 that includes a target component 356, according to an embodiment of the present disclosure. In Figure 3G, the wafer 300 is in a post-manufacture state. Thus, the target component 356 is covered by subsequent layers of an insulator 358 that is not visible. In this example, the verification structure 360 can be configured to provide electrical parameter measurements (e.g., resistance between probe pads 362 and 364). By utilizing known scientific principles, a wafer verification system can calculate the width 363 of the target component 356 based on such resistance, as described in connection with operation 240 of Figure 2. Using the calculated width 363, the wafer verification system can verify the wafer, as described in connection with operation 245 of Figure 2.

[0050] Figure 3H shows a cross-sectional view of an exemplary target component 378 within region 306 of wafer 300, according to an embodiment of the present disclosure. The target component 378 can be the width of an insulator 370 between a first conductor 372 and a second conductor 368. In Figure 3H, the wafer 300 is in a manufacturing state, and thus during one or more pattern transfer processes, the target component 378 may have been visible. Thus, a wafer verification system can obtain the target component 378 width as a physical measurement.

[0051] Figure 3I shows a top view of an exemplary verification structure 374 that includes a target component 378, according to an embodiment of the present disclosure. In Figure 3I, the wafer 300 is in a post-manufacture state, and thus the target component 378 is not visible due to subsequent layers of insulator 370. In this example, the verification structure 374 can be configured to provide electrical parameter measurements (e.g., leakage current or capacitance between probe pads 366 and 376). By utilizing known scientific principles, a wafer verification system can calculate the width of the target component 378 based on such leakage current, as described in connection with operation 240 of Figure 2. Using the calculated width, the wafer verification system can verify the wafer, as described in connection with operation 245 of Figure 2.

[0052] In some embodiments, wafer 300 may include at least one of the verification structures described in connection with FIGS. 3A and 3D-3I. In some embodiments, wafer 300 may include a verification structure having components (e.g., target components) in different manufacturing layers of wafer 300. For example, in some embodiments, a target component for a first verification structure may be formed in the tenth manufacturing layer of wafer 300, and a target component for a second verification structure may be formed in the thirtieth manufacturing layer of wafer 300, where the thirtieth layer is formed over or on top of the tenth manufacturing layer. In some embodiments, the probe pads of one or more verification structures of wafer 300 may be formed in the same layer of wafer 300.

[0053] FIG. 4 shows representative main components of an exemplary computer system 401 that may be used in accordance with embodiments of the present disclosure. The particular components shown are presented for purposes of illustration only and are not necessarily the only variations. Computer system 401 may include a processor 410, a memory 420, an input / output interface (also referred to herein as an I / O or I / O interface) 430, and a main bus 440. Main bus 440 may provide a communication path for other components of computer system 401. In some embodiments, main bus 440 may be connected to other components such as a dedicated digital signal processor (not shown).

[0054] The processor 410 of the computer system 401 can be composed of one or more CPUs 412. The processor 410 can further be composed of one or more memory buffers or caches (not shown) that realize temporary storage of instructions and data for the CPU 412. The CPU 412 can execute instructions on the input provided from the cache or memory 420 and output the results to the cache or memory 420. The CPU 412 can be composed of one or more circuits configured to implement one or more methods conforming to the embodiments of the present disclosure. In some embodiments, the computer system 401 can include multiple processors 410 specific to relatively large-scale systems. However, in another embodiment, the computer system 401 can be a single processor having a single CPU 412.

[0055] The memory 420 of the computer system 401 can be composed of a memory controller 422 and one or more memory modules (not shown) for temporarily or permanently storing data. In some embodiments, the memory 420 can include a random access semiconductor memory, a storage device, or a storage medium (volatile or non-volatile) for storing data and programs. The memory controller 422 can communicate with the processor 410 and facilitate storage of information in the memory module and retrieval of information in the memory module. The memory controller 422 can communicate with the I / O interface 430 and facilitate storage and retrieval of input or output of the memory module. In some embodiments, the memory module can be a dual in-line memory module.

[0056] The I / O interface 430 may include an I / O bus 450, a terminal interface 452, a storage interface 454, an I / O device interface 456, and a network interface 458. The I / O interface 430 may connect the main bus 440 to the I / O bus 450. The I / O interface 430 may direct instructions and data from the processor 410 and the memory 420 to various interfaces of the I / O bus 450. The I / O interface 430 may also direct instructions and data from various interfaces of the I / O bus 450 to the processor 410 and the memory 420. The various interfaces may include a terminal interface 452, a storage interface 454, an I / O device interface 456, and a network interface 458. In some embodiments, the various interfaces may include a subset of the foregoing interfaces (e.g., an embedded computer system in an industrial application example may not include the terminal interface 452 and the storage interface 454).

[0057] Logical modules throughout the computer system 401, including but not limited to the memory 420, the processor 410, and the I / O interface 430, may communicate to a hypervisor or an operating system (not shown) failures and changes to one or more components. The hypervisor or the operating system may allocate the various resources available within the computer system 401 and may track the location of data within the memory 420 and the location of processes assigned to the various CPUs 412. In embodiments where elements are combined or rearranged, aspects of the functionality of the logical modules may be combined or redistributed. Such variations will be apparent to those skilled in the art.

[0058] This disclosure includes a detailed description regarding cloud computing, but it should be understood upfront that the implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the present invention can be implemented with any other type of computing environment, whether currently known or later developed.

[0059] Cloud computing is a service delivery model that enables convenient on-demand network access to a shared pool of configurable computing resources (such as networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0060] The characteristics are as follows. On-demand self-service: Cloud consumers can provision computing capabilities such as server time and network storage automatically as needed, without the need for human interaction with the service provider. Broad network access: The capabilities are available over a network and accessed through standard mechanisms that promote use by heterogeneous thin or thick client platforms (such as mobile phones, laptops, and PDAs). Resource pooling: Provider computing resources are pooled to serve multiple consumers using a multi-tenant model, and different physical and virtual resources are dynamically assigned and reassigned according to demand. Consumers generally have no control or knowledge over the exact location of the resources provided, but in a sense have location independence in that they can specify the location at a higher level of abstraction (such as a country, state, or data center). Rapid elasticity: To scale out rapidly, release quickly, and scale in rapidly, functions can be provisioned quickly and elastically, and in some cases automatically, for a case. For consumers, the functions available for provisioning are often unlimited and appear to be purchasable in any quantity at any time. Metering service: Cloud systems automatically control and optimize resource usage by leveraging a metering function for some level of abstraction appropriate for the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, achieving transparency for both providers and consumers of the services utilized.

[0061] The service model is as follows. Software as a Service (SaaS): The function provided to consumers is to use the provider's applications running on the cloud infrastructure. The applications are accessible from various client devices through a thin-client interface such as a web browser (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, and even individual application features, with the possible exception of limited user-specific application configuration settings. Platform as a Service (PaaS): The function provided to consumers is to place applications created or obtained by consumers, using programming languages and tools supported by the provider, on the cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but have control over the deployed applications and, in some cases, the application-hosting environment configuration. Infrastructure as a Service (IaaS): The functions provided to consumers are to provision processing, storage, networks, and other basic computing resources, and consumers can deploy and run any software that may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but have limited control over operating systems, storage, control of deployed applications, and, in some cases, selected networking components (such as host firewalls).

[0062] The deployment models are as follows. Private cloud: The cloud infrastructure is operated solely for an organization. The cloud infrastructure can be managed by the organization or a third party and can exist on-premises or off-premises. Community cloud: The cloud infrastructure is shared by several organizations and supports a specific community that has shared concerns (such as missions, security requirements, policies, and compliance considerations). The cloud infrastructure can be managed by the organization or a third party and can exist on-premises or off-premises. Public cloud: The cloud infrastructure is made available to the general public or a large industrial group and is owned by an organization that sells cloud services. Hybrid cloud: The cloud infrastructure remains a distinct entity but is a composition of two or more clouds (private, community, or public) that are linked together by standardized technologies or technologies that can assert ownership to enable data and application portability (such as cloud bursting for load balancing between clouds). A cloud computing environment is a service that aims to focus on statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is an infrastructure with a network of interconnected nodes.

[0063] Next, referring to FIG. 5, an exemplary cloud computing environment 50 is shown. As illustrated, the cloud computing environment 50 includes one or more cloud computing nodes 10 that can communicate with local computing devices used by cloud consumers, such as, for example, a personal digital assistant (PDA) or cellular phone 54A, a desktop computer 54B, a laptop computer 54C, or an automotive computer system 54N, or a combination thereof. The nodes 10 can communicate with each other. The nodes 10 can be physically or virtually grouped (not shown) within one or more networks, such as a private, community, public, or hybrid cloud as described above, or a combination thereof. This enables the cloud computing environment 50 to provide infrastructure, platform, or software, or a combination thereof, as a service such that a cloud consumer does not need to maintain resources on a local computing device therefor. It should be understood that the types of computing devices 54A - N shown in FIG. 5 are for illustrative purposes only, and that the computing nodes 10 and the cloud computing environment 50 can communicate with any type of computerized device via any type of network or network-addressable connection (e.g., using a web browser) or both.

[0064] Next, referring to FIG. 6, a set of functional abstractions provided by the cloud computing environment 50 (FIG. 5) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 6 are for illustrative purposes only and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided.

[0065] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based server 62, server 63, blade server 64, storage device 65, and network and networking components 66. In some embodiments, the software components include network application server software 67 and database software 68.

[0066] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 71, virtual storage 72, virtual network 73 including a virtual private network, virtual applications and operating systems 74, and virtual client 75.

[0067] In one example, the management layer 80 may provide the functions described below. Resource Provisioning 81 realizes the dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and Pricing 82 realizes cost tracking when resources are used within the cloud computing environment and billing or invoicing for the consumption of such resources. In one example, such resources may include application software licenses. Security realizes identification and verification for cloud consumers and tasks, as well as protection for data and other resources. The User Portal 83 realizes access to the cloud computing environment for consumers and system administrators. Service Level Management 84 realizes the allocation and management of cloud computing resources so that the required service levels are met. Service Level Agreement (SLA) Planning and Fulfillment 85 realizes the pre-adjustment and procurement of cloud computing resources whose future requirements are expected, in accordance with the SLA.

[0068] The workload layer 90 provides examples of functions that the cloud computing environment can utilize. Examples of workloads and functions that can be provided from this layer include mapping and navigation 91, software development and life cycle management 92, virtual classroom education delivery 93, data analysis processing 94, transaction processing 95, and inspection / verification logic 96.

[0069] As discussed in more detail herein, it is contemplated that some or all of the operations of some of the embodiments of the methods described herein may be performed in an alternative order or may not be performed at all, and further that multiple operations may be performed simultaneously or as part of an inner portion of a larger process.

[0070] The present invention can be a system, method, or computer program product, or a combination thereof, at any possible technical detail integration level. The computer program product can include a computer-readable storage medium having computer-readable program instructions that cause a processor to implement aspects of the present invention.

[0071] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards and raised structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. In this specification, a computer-readable storage medium should not be construed to be an essentially transient signal such as, for example, a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0072] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each respective computing / processing device.

[0073] The computer-readable program instructions for carrying out the operations of the present invention may be source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or any combination of object-oriented programming languages such as Smalltalk(R), C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to customize the electronic circuit for carrying out aspects of the present invention.

[0074] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0075] Such computer-readable program instructions create means for implementing the functions / operations specified in one or more blocks of a flowchart, a block diagram, or both by causing the instructions to be executed via the processor of a computer or other programmable data processing apparatus, and a machine can be created. Such computer-readable program instructions can also be stored in a computer-readable storage medium that stores instructions for implementing the functions / operations specified in one or more blocks of a flowchart, a block diagram, or both, and can be stored in a computer-readable storage medium that instructs a computer, a programmable data processing apparatus, or other device, or a combination thereof, to function in a particular manner so as to include a manufactured product that includes the instructions.

[0076] Computer-readable program instructions can also be loaded onto a computer, other programmable apparatus, or other device, and executed thereon to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device so as to implement the functions / operations specified in one or more blocks of a flowchart, a block diagram, or both, and a computer-implemented process can be generated.

[0077] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in an order different than that noted in the figures. For example, two blocks shown in succession may, in fact, be implemented as one step, executed simultaneously, substantially simultaneously, in a partially or wholly temporally overlapping manner, or the blocks may sometimes be executed in the reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams or flowchart diagrams, or combinations of blocks of the block diagrams or flowchart diagrams, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0078] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or technical improvements found in the marketplace over the technologies described, and to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. 1. A computer-implemented method comprising: acquiring a first reference image of a first wafer; acquiring a first image of the first wafer in a manufacturing state, the manufacturing state including a number of manufacturing layers less than a threshold number, the first wafer including a first verification structure; acquiring a first physical measurement corresponding to the first verification structure while the first wafer is in the manufacturing state; At a first time, determining that the first image matches the first reference image by comparing the first image to the first reference image; acquiring, at a second time after the first time, electrical parameter measurements corresponding to a verification structure of a received wafer in an as-manufactured state, wherein in the as-manufactured state, the received wafer has a second number of fabrication layers equal to the threshold number; calculating a physical parameter value based on the electrical parameter measurements; generating a validation response by comparing the physical parameter value with the first physical measurement; 10. A computer-implemented method comprising:

2. determining, based on comparing the physical parameter value to the first physical measurement, that the physical parameter value matches the first physical measurement; further comprising generating the verification response in response to determining that the physical parameter value matches the first physical measurement includes indicating that the received wafer is the first wafer in the as-manufactured state; The computer-implemented method of claim 1 , wherein in the post-fabrication state, the first wafer has the second number of fabricated layers equal to the threshold number.

3. the first verification structure comprises a target component; the first physical measurement is a measurement of a physical property of the target component; the target component has a first visibility when the first wafer is in the manufacturing state; the target component has a second visibility when the first wafer is in the post-manufacture state; The computer-implemented method of claim 2 , wherein the second visibility is less than the first visibility.

4. The computer-implemented method according to claim 1, wherein the first physical measurement value is selected from the group consisting of the thickness of an insulator material, the width of a conductor, and the distance between a first conductor and a second conductor.

5. Based on comparing the physical parameter value with the first physical measurement value, determining that the physical parameter value does not match the first physical measurement value further comprising generating the verification response in response to determining that the physical parameter value does not match the first physical measurement value, including indicating that the received wafer is not the first wafer, the computer-implemented method according to claim 1.

6. wherein the first reference image represents a first reference manufacturing layer of the first wafer, wherein the first image represents a first manufacturing layer of the first wafer, comparing the first image with the first reference image includes comparing the first manufacturing layer with the first reference manufacturing layer, the computer-implemented method according to claim 1.

7. obtaining a second image of the first wafer in the manufacturing state, wherein the second image represents the first manufacturing layer and the second manufacturing layer of the first wafer, the obtaining, obtaining a second reference image of the first wafer, wherein the second reference image represents the first reference manufacturing layer and the second reference manufacturing layer of the first wafer, the obtaining, comparing the second image with the second reference image to determine that the second image matches the second reference image further comprising, the computer-implemented method according to claim 6.

8. one or more processors, when executed by the one or more processors, causing the one or more processors to obtain a first reference image of a first wafer, obtain a first image of the first wafer in the manufacturing state, wherein in the manufacturing state, the first wafer has fewer than a threshold number of manufacturing layers and the first wafer has a first verification structure, the obtaining, when the first wafer is in the manufacturing state, obtain a first physical measurement value corresponding to the first verification structure At a first time, by comparing the first image with the first reference image, determining that the first image matches the first reference image; At a second time after the first time, obtaining an electrical parameter measurement value corresponding to a verification structure of a received wafer in a post-manufacture state, wherein in the post-manufacture state, the received wafer has a second number of manufacturing layers equal to the threshold number; Calculating a physical parameter value based on the electrical parameter measurement value; Generating a verification response by comparing the physical parameter value with the first physical measurement value; One or more computer-readable storage media storing program instructions configured to implement a method including the above steps; A system comprising the above.

9. The method further includes: Based on comparing the physical parameter value with the first physical measurement value, determining that the physical parameter value matches the first physical measurement value; In response to determining that the physical parameter value matches the first physical measurement value, generating the verification response includes indicating that the received wafer is the first wafer in the post-manufacture state; In the post-manufacture state, the first wafer has the second number of manufacturing layers equal to the threshold number. The system according to claim 8.

10. The first verification structure includes a target component; The first physical measurement value is a measurement value of a physical property of the target component; When the first wafer is in the manufacturing state, the target component has a first visibility; When the first wafer is in the post-manufacture state, the target component has a second visibility; The second visibility is less than the first visibility. The system according to claim 9.

11. The first physical measurement value is selected from the group consisting of the thickness of an insulator material, the width of a conductor, and the distance between a first conductor and a second conductor. The system according to claim 8.

12. The method further includes: Based on comparing the physical parameter value with the first physical measurement value, determining that the physical parameter value does not match the first physical measurement value; Including the above step; ​ In response to determining that the physical parameter value does not match the first physical measurement value, generating the verification response, including indicating that the received wafer is not the first wafer, the system according to claim 8.

13. The first reference image indicates a first reference manufacturing layer of the first wafer, The first image indicates a first manufacturing layer of the first wafer, Comparing the first image with the first reference image includes comparing the first manufacturing layer with the first reference manufacturing layer, the system according to claim 8.

14. A computer program product including one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media, wherein the program instructions cause one or more processors to, Obtain a first reference image of a first wafer, Obtain a first image of the first wafer in a manufacturing state, wherein in the manufacturing state, the first wafer has fewer than a threshold number of manufacturing layers and the first wafer has a first verification structure, the obtaining, When the first wafer is in the manufacturing state, obtain a first physical measurement value corresponding to the first verification structure, At a first time, determine that the first image matches the first reference image by comparing the first image with the first reference image, At a second time after the first time, obtain an electrical parameter measurement value corresponding to a verification structure of a received wafer in a post-manufacture state, wherein in the post-manufacture state, the received wafer has a second number of manufacturing layers equal to the threshold number, the obtaining, Calculate a physical parameter value based on the electrical parameter measurement value, Generate a verification response by comparing the physical parameter value with the first physical measurement value A computer program product including instructions configured to implement a method including.

15. The method includes, Based on comparing the physical parameter value with the first physical measurement value, determining that the physical parameter value matches the first physical measurement value Further including, In response to determining that the physical parameter value matches the first physical measurement value, generating the verification response includes indicating that the received wafer is the first wafer in the post-manufacture state. The computer program product according to claim 14, wherein in the post-manufacture state, the first wafer has the second number of manufacturing layers equal to the threshold number. **Claim 16** The first verification structure comprises a target component. The first physical measurement value is a measurement value of a physical characteristic of the target component. When the first wafer is in the manufacturing state, the target component has a first visibility. When the first wafer is in the post-manufacture state, the target component has a second visibility. The computer program product according to claim 15, wherein the second visibility is less than the first visibility. **Claim 17** The computer program product according to claim 14, wherein the first physical measurement value is selected from the group consisting of the thickness of an insulator material, the width of a conductor, and the distance between a first conductor and a second conductor. **Claim 18** The method further comprises: determining that the physical parameter value does not match the first physical measurement value based on comparing the physical parameter value with the first physical measurement value. The computer program product according to claim 14, wherein in response to determining that the physical parameter value does not match the first physical measurement value, generating the verification response includes indicating that the received wafer is not the first wafer. **Claim 19** The first reference image represents a first reference manufacturing layer of the first wafer. The first image represents a first manufacturing layer of the first wafer. The computer program product according to claim 14, wherein comparing the first image with the first reference image includes comparing the first manufacturing layer with the first reference manufacturing layer. **Claim 20** A computer-implemented method comprising: obtaining a first physical measurement value corresponding to a first verification structure of a first wafer in a manufacturing state, wherein in the manufacturing state, the first wafer has some manufacturing layers less than a threshold number; the obtaining; Obtaining electrical parameter measurement values corresponding to a verification structure of a received wafer in a post-manufacture state, wherein in the post-manufacture state, the received wafer has a second number of manufacturing layers equal to the threshold number, said obtaining, Calculating physical parameter values based on the electrical parameter measurement values, Generating a verification response by comparing the physical parameter values with the first physical measurement values A computer-implemented method comprising.

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