Semiconductor structure and method (3D funnel-shaped spin-transfer-torque MRAM cell with non-uniform thickness of each layer)

Abstract

To provide an approach for providing a funnel-shaped spin-transfer torque (STT) magnetoresistive random-access memory (MRAM) device with a dual magnetic tunnel junction.SOLUTION: The approach includes providing a metal pillar on a connection to a semiconductor device. The approach includes providing a first reference layer on the metal pillar and on a portion of a first interlayer dielectric adjacent to the metal pillar. The approach includes providing a first tunnel barrier on the first reference layer, and providing a free layer on the first tunnel barrier layer. The approach includes providing a second tunnel barrier on the free layer of the semiconductor structure of the funnel-shaped spin-transfer torque MRAM device, and providing a second reference layer on the second tunnel barrier.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor memory device technology, and more particularly to magnetoresistive random access memory devices. [Background technology]

[0002] Magnetoresistive random access memory (MRAM) is based on the fusion of silicon-based complementary silicon-oxide semiconductor (CMOS) and magnetic tunnel junction (MTJ) technologies. It is a promising nonvolatile memory technology that offers many advantages over other commercially available memory types, including SRAM, DRAM, and flash, in terms of write / read speed, power consumption, and lifetime. Conventional MRAM devices contain a magnetic tunnel junction (MTJ) structure with a magnetic layer separated by an intermediate nonmagnetic tunnel barrier layer. Digital information can be stored in the memory element and represented by the direction of the magnetization vector. In response to a current applied to the MTJ, the magnetic memory element exhibits a different resistance value, allowing the MRAM device to provide the information stored in the magnetic memory element. Typically, MRAM devices are fabricated with field-effect transistors (FETs) that can access the MRAM device.

[0003] A recent development in MRAM technology utilizes spin transfer torque (STT) to form MRAM devices. STTMRAM devices are formed using perpendicular MTJs where the spin of electrons is manipulated with a polarized current to change the magnetic state of the MTJ's free layer in order to write bits into the memory array. STTMRAM devices utilize spin transfer switching to generate a torque when spin-aligned or spin-polarized electrons in one layer flow onto a second layer, switching the spins in the second layer. Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention recognize that conventional structures and methods for forming spin-transfer torque (STT) magnetoresistive random access memory (MRAM) devices with perpendicular magnetic anisotropy (PMA) present many technical challenges. The present invention recognizes that conventional STT MRAM devices with PMA have low switching efficiency due to the difficulty of simultaneously achieving both high PMA and low damping. High-PMA materials typically contain heavy metal oxides and have high damping due to the strong spin-orbit coupling of heavy metal oxides. Meanwhile, low-damping materials do not provide a strong enough PMA to function with a barrier layer, such as a layer of MgO. The second method of achieving high PMA by increasing the number of MgO / ferromagnetic interfaces also does not work because the spin-transfer torque provided by the reference layer acts only on the first ferromagnetic layer and is not large enough to switch the entire composite free layer with additional MgO / ferromagnetic interfaces. [Means for solving the problem]

[0005]

[0006] An embodiment of the present invention provides a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device structure having a single or double magnetic tunnel junction. The semiconductor structure includes a metal pillar on a connection to the semiconductor device. The semiconductor structure includes a first reference layer on the metal pillar wall and on a portion of the first interlayer dielectric adjacent to the metal pillar. The semiconductor structure includes a first tunnel barrier on the first reference layer and a free layer on the first tunnel barrier layer. Additionally, the semiconductor structure includes a second tunnel barrier on the free layer and a second reference layer on the second tunnel barrier.

[0006] An embodiment of the present invention provides a method for forming a magnetoresistive random access memory (MRAM) device. The method includes depositing a free layer on an interlayer dielectric layer and on a metal pillar. The metal pillar has sloped sides and overlies a contact to a semiconductor device. The method includes depositing a tunnel barrier layer on the free layer. The method includes depositing a reference layer on the tunnel barrier layer. The method further includes removing the free layer, the tunnel barrier layer, a horizontal portion of the reference layer, and a top portion of the interlayer dielectric adjacent to the metal pillar, and forming a contact on the remaining portion of the reference layer. [Brief explanation of the drawings]

[0007] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0008] [Figure 1] 1A-1C are cross-sectional views of pillars used to form a funnel-shaped spin-transfer-torque MRAM device, according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor structure after forming a free layer over the pillars in accordance with one embodiment of the present invention.

[0009] [Figure 3] FIG. 2 is a cross-sectional view of a semiconductor structure after forming a barrier layer over the free layer in accordance with one embodiment of the present invention.

[0010] [Figure 4] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a reference layer over the barrier layer and passivating the reference layer, in accordance with one embodiment of the present invention.

[0011] [Figure 5] 2 is a cross-sectional view of a semiconductor structure after deposition of a top contact layer in accordance with one embodiment of the present invention.

[0012] [Figure 6]2 is a cross-sectional view of a semiconductor structure after etching the top contact layer to form bitlines in accordance with one embodiment of the present invention.

[0013] [Figure 7] 2 is a cross-sectional view of a semiconductor structure after depositing a layer of ILD material and performing chemical mechanical polishing (CMP) in accordance with one embodiment of the present invention.

[0014] [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor structure of a second funnel-shaped STTMRAM device after deposition of all layers required to form a DMTJ, according to one embodiment of the present invention.

[0015] [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor structure of a second funnel-shaped STTMRAM device with DMTJ after forming a top contact according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Embodiments of the present invention recognize that conventional structures and methods for forming spin-transfer torque (STT) magnetoresistive random access memory (MRAM) devices with perpendicular magnetic anisotropy (PMA) present many technical challenges. The present invention recognizes that conventional STT MRAM devices with PMA have low switching efficiency due to the difficulty of simultaneously achieving both high PMA and low damping. High-PMA materials typically contain heavy metal oxides and have high damping due to the strong spin-orbit coupling of heavy metal oxides. Meanwhile, low-damping materials do not provide a strong enough PMA to function with a barrier layer, such as a layer of MgO. The second method of achieving high PMA by increasing the number of MgO / ferromagnetic interfaces also does not work because the spin-transfer torque provided by the reference layer acts only on the first ferromagnetic layer and is not large enough to switch the entire composite free layer with additional MgO / ferromagnetic interfaces.

[0017] Embodiments of the present invention recognize that conventional STTMRAM with PMA exhibits a decrease in PMA in both the free and reference layers of the MTJ as the size of the STTMRAM device decreases. In very small size STTMRAM devices, both the free and reference layers become unstable. Instabilities in the reference layer can cause write errors at deep WER floor levels. An unstable free layer can cause retention errors. Embodiments of the present invention recognize that in conventional STTMRAM with PMA, these instabilities are more pronounced in smaller STTMRAM devices, thus making scaling of STTMRAM with very small complementary metal-oxide semiconductor (CMOS)-based devices or transistors difficult and / or limited.

[0018] Embodiments of the present invention recognize that conventional STTMRAM with PMA may also require a very complex structure for the reference layer. Embodiments of the present invention recognize that conventional STTMRAM with PMA typically utilizes a synthetic antiferromagnet (SAF) with multiple layers of magnetic material to minimize the local magnetic field coming from the reference layer and acting on the free layer. Depositing multiple layers of material, such as a synthetic antiferromagnet, to form the reference layer complicates the manufacturing process, increases costs, and reduces yields. Additionally, to ensure good PMA and stability, the reference layer must be very thick.

[0019] Embodiments of the present invention recognize that conventional STTMRAM with PMA has difficulty achieving both a high magnetoresistance ratio (MR) and fast STT switching. High MR materials that provide excellent data read capabilities typically have a high magnetic moment, which limits STT switching speeds. As a result, embodiments of the present invention recognize that conventional STTMRAM with PMA has difficulty providing a fast-switching device that also provides effective read capabilities when low MR materials are used to improve switching speeds. Ideally, materials with high magnetic saturation and thin thicknesses (e.g., in the range of 5 to 20 angstroms) can provide faster switching speeds along with excellent read capabilities.

[0020] Embodiments of the present invention recognize that the conventional STTMRAM with PMA for a given size CMOS transistor current is closely related to the MTJ area of the MRAM device, more specifically, the resistance in ohms per square micron area of the MTJ. Embodiments of the present invention recognize that the conventional STTMRAM with PMA is limited by the size and associated current of the CMOS transistor because smaller MTJs must have thinner tunnel barrier layers to accommodate the smaller currents of the CMOS transistors. Embodiments of the present invention recognize that the optimization and / or thickness of the tunnel barrier is limited by the size of the CMOS select transistor.

[0021] Embodiments of the present invention recognize that conventional STTMRAMs with PMAs are generally limited to forming memory cells with a free layer above the reference layer. Embodiments of the present invention recognize that it is difficult to form a stable reference layer above a tunnel barrier layer composed of MgO, especially when the reference layer is a SAF with multiple magnetic material layers. For this reason, in most conventional STTMRAMs with PMAs, the free layer is generally above the reference layer. However, embodiments of the present invention recognize that having the reference layer above the tunnel barrier layer provides better electrical matching with n-type CMOS transistors and provides a smoother tunnel barrier layer with better device magnetics and better switching efficiency.

[0022] Embodiments of the present invention recognize that the most efficient MRAM design for conventional STTMRAM with PMA may be a double MTJ (DMTJ) design including two reference layers and two tunnel barrier layers with a free layer, with a first reference layer and first tunnel barrier layer above them and a second reference layer and tunnel barrier layer below them. In conventional STTMRAM with PMA, forming a large number of magnetic layers in the various reference layers requiring SAF becomes extremely difficult.

[0023] Embodiments of the present invention provide a new MRAM geometry for STTMRAM devices and a method for forming a new STTMRAM device using a funnel-shaped semiconductor structure. Embodiments of the present invention use a highly uniform deposition process. Using highly parallel beam physical vapor deposition or ion beam deposition across a semiconductor substrate surface above a wafer surface, where the semiconductor substrate surface is a three-dimensional surface containing metal pillar structures, results in thickness non-uniformities within each layer due to the three-dimensional nature of the semiconductor substrate surface. The method for forming a funnel-shaped STTMRAM device creates variable thicknesses within each layer of a magnetic tunnel junction (MTJ) structure. A funnel-shaped STTMRAM with an MTJ has ferromagnetic layers separated by an intermediate nonmagnetic tunnel barrier layer. The funnel-shaped STTMRAM device includes an MTJ in which the material thickness of each MTJ layer on the side of the funnel above the metal pillars is different from the material thickness of each layer of the MTJ on the surface parallel to the semiconductor substrate or wafer surface. Embodiments of the present invention using the new funnel-shaped STTMRAM device allow for different thicknesses for each layer of the MTJ, as well as different thicknesses within each layer of the MTJ.

[0024] Embodiments of the present invention, using a novel funnel-shaped STTMRAM structure and a method for forming the funnel-shaped MRAM structure, provide a funnel-shaped STTMRAM device that can provide efficient, high switching speeds while overcoming or ameliorating each of the challenges associated with conventional STTMRAM technology described above. The non-uniform thickness within each layer of the MTJ layer is created by using oblique deposition angles for the layers of the MTJ. For various layers of the MTJ stack, the oblique deposition angles vary depending on the layer of the MTJ stack being deposited. Embodiments of the present invention provide a funnel-shaped STTMRAM device that can be formed directly on a connection or contact to a CMOS device or transistor.

[0025] Embodiments of the present invention, using a novel funnel-shaped STTMRAM device with a specific ratio of funnel tube radius to funnel tube height and appropriate thicknesses for each of the magnetic layers in the MTJ, can have a vortex state within the funnel-shaped STTMRAM device structure. The vortex state is a closed flux structure in which the local magnetization vector curls within the plane of the funnel-shaped tube and is parallel to the top and bottom surfaces of the funnel-shaped tube. The vortex state in the funnel-shaped STTMRAM structure is energetically stable and also provides adequate coercivity over a wide temperature range. Using a closed flux vortex state in a funnel-shaped STTMRAM device and a short nanofunnel in the funnel-shaped STTMRAM device allows for the formation of dynamic domain walls where spin transfer torque overcomes only the exchange force, allowing for bit flipping. In this case, good bit coercivity is maintained in very small or ultra-small funnel-shaped STTMRAM devices in the 1-5 nanometer range, limited only by superparamagnetism or spin quantum tunneling.

[0026] Due to the presence of vortex states within the funnel-shaped STTMRAM device, embodiments of the present invention do not require PMA materials with heavy metals or multipolar MgO / ferromagnet interfaces. 25 Fe 75 or Fe 50 Ni 50New funnel-shaped STTMRAM devices are formed using low-damping magnetic materials such as ZnSe. The use of low-damping magnetic materials in funnel-shaped STTMRAM devices enables high switching efficiency and speed. Furthermore, the closed magnetic flux structure forming a vortex state enables the funnel-shaped STTMRAM device structure to achieve good magnetic coercivity in small and very small memory cells. Thus, embodiments of the present invention provide funnel-shaped STTMRAM devices with low magnetic moment materials laminated with CoFeB (CBF) materials of various compositions as the free layer to obtain fast switching and good MR signals without the need for PMA or PMA materials. Embodiments of the present invention enable the use of funnel-shaped STTMRAM devices with good exchange magnetization or high magnetization while maintaining low local fields at the edges of the funnel-shaped tube.

[0027] Embodiments of the present invention provide a funnel-shaped STTMRAM device with vortex states in both the free and reference layers. The free layer tube has a relatively short exchange length longer than the dimensions of the funnel-shaped STTMRAM device. Specifically, modeling has shown that in funnel-shaped STTMRAM devices with an aspect ratio of the funnel tube height to the funnel tube radius less than approximately 1.81, the local magnetization of the nanofunnel curls within the funnel. In this case, the funnel-shaped STTMRAM device in the vortex state has a closed magnetic flux. The vortex states in both the free and reference layers minimize magnetostatic coupling between the free and reference layers, thereby simplifying the STT dynamic reversal of the free layer. In addition, a short nanofunnel with a thin free layer energetically favors the generation and propagation of a Néel wall along the outer periphery of the funnel tube during STT switching. When the local magnetic direction curls along the nanotube wall, STT switching can be fast and efficient. In addition, bit retention is good because spontaneous reversal of the entire vortex structure due to thermal fluctuations is highly unlikely or difficult.

[0028] Embodiments of the present invention provide a funnel-shaped STTMRAM device that offers both the ability to build a funnel-shaped STTMRAM device with a free layer on top of the reference layer and the ability to build an inverted STTMRAM device with a reference layer above or on top of the free layer. Embodiments of the present invention provide a funnel-shaped STTMRAM device with a double MTJ (DMTJ) device structure with both stable reference layers and a free layer with the highest possible coercivity for a given amount of magnetic volume. Additionally, embodiments of the present invention provide a method for forming STTMRAM devices with non-SAF reference layers that are thinner and easier to fabricate, thus offering advantages over various conventional STTMRAM designs.

[0029] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The embodiments can be implemented in conjunction with integrated circuit manufacturing techniques currently used in the art for MRAM devices, and only those commonly performed process steps necessary to understand the described embodiments are included. The figures represent cross-sectional portions of a fabricated MRAM device and are not drawn to scale; instead, they are drawn to illustrate features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to variously use the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0030] References herein to "one embodiment," "another embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments may necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is understood that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0031] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the drawings. The terms "overlying," "top," "on top," "over," "disposed on," or "disposed on top" mean that a first element is on a second element, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "direct contact" means that a first element and a second element are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0032] In the following detailed description, some processing steps, materials, or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. Additionally, for the sake of brevity and to maintain focus on the unique features of the elements of the present invention, descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other cases, some known processing steps or operations may not be described. It should be understood that the following description will instead focus on the unique features or elements of various embodiments of the present invention. For purposes of the present invention, the terms funnel-shaped STTMRAM device and funnel-shaped STTMRAM device are considered identical or interchangeable.

[0033] FIG. 1 is a cross-sectional view of a metal pillar used to form a funnel-shaped or funnel-shaped STTMRAM device according to one embodiment of the present invention. As shown, FIG. 1 includes a metal pillar on a surface, such as the surface of a portion of a semiconductor structure above a semiconductor wafer, or on a portion of a semiconductor wafer (not shown in FIG. 1). As shown in FIG. 1, the angle of the outer wall of the metal pillar with respect to a horizontal surface is angle α, and deposition angles θ1 and θ2 represent oblique deposition angles with respect to a reference direction that is normal or perpendicular to the horizontal surface. In various embodiments, angle α ranges from 90 degrees to 45 degrees from the horizontal surface of the semiconductor substrate or wafer (not shown) on which the metal pillar is formed. The metal pillar has a flat-topped funnel-shaped or flattened cone-shaped configuration. Deposition angles θ1 and θ2 are oblique deposition angles. Deposition angles θ1 and θ2 are measured with respect to a direction normal to the semiconductor substrate or wafer surface (or a direction perpendicular to the wafer surface). In various embodiments, a deposition angle θ1 is used for the deposition of the free layer and one or more reference layers on the metal pillars, while a deposition angle θ2 is used for the deposition of the tunnel barrier material. The semiconductor wafer (not shown) is rotated during the deposition of the various layers of the funnel-shaped STTMRAM device discussed with reference to FIGS.

[0034] FIG. 2 is a cross-sectional view of a semiconductor structure 200 after forming a free layer 2 on a metal pillar 10, according to one embodiment of the present invention. As shown, FIG. 2 includes an interlayer dielectric (ILD 8), a contact 9, a metal pillar 10, and a free layer 2 deposited on the metal pillar 10. In various embodiments, the ILD 8 is above a semiconductor device (not shown) in a semiconductor substrate or semiconductor wafer (not shown). The ILD 8 can be any dielectric material, such as SiO 2 , deposited over the semiconductor device for electrical isolation. The ILD 8 has a top horizontal surface above the semiconductor wafer (not shown). In various embodiments, the contact 9 is a via or metal connection to an underlying semiconductor device, such as a CMOS transistor. In some embodiments, the contact 9 is in direct contact with the source / drain or source / drain contacts of the semiconductor device.

[0035] In various embodiments, metal pillar 10 is formed directly above contact 9 at an angle α relative to the top surface of ILD 8. As previously discussed, angle α ranges from 90 degrees to 45 degrees. For example, a typical angle α for the funnel-shaped STTMRAM structures shown in FIGS. 2-9 can be in the range of 80 degrees for the typical thicknesses discussed for each layer, unless otherwise specified. As shown in FIG. 2, metal pillar 10 has a flat top that forms a funnel-like shape for metal pillar 10, although the top of the metal pillar may also be rounded. In various embodiments, a typical height of metal pillar 10 ranges from 4 nm to 40 nm, but is not limited to these heights.

[0036] In various embodiments, the free layer 2 is a layer of magnetic material deposited at a deposition angle θ1 while a semiconductor substrate or wafer (not shown) containing the semiconductor structure 200 is rotated or spun about an axis perpendicular to the semiconductor wafer surface. As discussed above with respect to FIG. 1 , the oblique deposition angle (i.e., deposition angle θ1) can typically be in the range of 70-80 degrees, measured relative to or in relation to a direction perpendicular to the semiconductor wafer surface, although the deposition angle θ1 is not limited to these angles. In various embodiments, the rotation of the semiconductor substrate or wafer ensures uniform deposition of material along the sides of the metal pillars 10. In various embodiments, a flow of atoms is deposited onto the top surfaces of the metal pillars 10 and ILD 8 using, for example, physical vapor deposition (PVD) or ion beam deposition (IBD).

[0037] Angled deposition of the free layer 2 using a deposition angle θ1 results in two different thicknesses of the free layer 2 deposited on the side of the metal pillar 10 compared to the thickness of the free layer 2 deposited on the horizontal surfaces of the semiconductor structure 200. In various embodiments, the free layer 2 is thicker on the side of the metal pillar 10 and much thinner on the top of the metal pillar 10 and on the ILD 8. For example, at a deposition angle θ1 in the range of 70-80 degrees, the thickness of the free layer 2 on the side of the metal pillar 10 is approximately 15-25 angstroms, while the thickness of the free layer 2 on the top surface of the ILD 8 and on the top of the metal pillar 10 is in the range of 3-5 angstroms. At a deposition angle θ1 of 80 degrees, the thickness of the free layer 2 on the side of the metal pillar 10 is approximately five times the thickness of the free layer 2 on the horizontal surfaces (e.g., on the top of the metal pillar 10 and on the exposed horizontal surface of the ILD 8 above the semiconductor wafer surface (not shown)). In other examples using different deposition parameters or metal pillars 10 with different angles α, the thickness of the free layer 2 can range from 10 to 50 angstroms on the sides of the metal pillar 10. As a result of the angled deposition of the free layer 2, the portions of the free layer 2 located on the ILD8 surface and on the top of the pillar 10 are essentially non-conductive due to the extremely thin layer of material deposited on the horizontal surfaces. As a result, only small or negligible current flows through the horizontal portions of the free layer 2. Additionally, the very thin horizontal portions of the free layer 2 essentially have little or no magnetization and therefore behave like non-ferromagnetic layers. Therefore, the thin horizontal portions of the free layer 2 do not disrupt the magnetic properties of the thicker portions of the free layer 2 located on the angled sidewalls of the pillar 10.

[0038] The free layer 2 can be composed of a variety of magnetic materials with different compositions and thicknesses. For example, the free layer 2 may be one or more compositions of cobalt, iron, and boron (CFB) with thicknesses ranging from 10 to 50 Angstroms. In another example, the free layer 2 may be composed of CFB for high MR and Co for low damping to provide fast switching in a funnel-shaped STTMRAM device. 25 Fe 75In another example, the free layer 2 can be a bilayer of a CFB and a Heusler alloy such as CoFeAl or NiMnSb for high MR. In yet another example, the free layer 2 can be a bilayer of a CFB and a soft magnetic material such as permalloy (i.e., a nickel-iron magnetic alloy) to avoid domain wall formation. The free layer 2 is not limited to these materials.

[0039] FIG. 3 is a cross-sectional view of a semiconductor structure 300 after forming a tunnel barrier 3 on the free layer 2, according to one embodiment of the present invention. As shown, FIG. 3 includes an ILD 8, a contact 9, a metal pillar 10, a free layer 2, and a tunnel barrier 3. As with the deposition of the free layer 2 and all subsequent depositions of the MTJ material layers, the semiconductor substrate or wafer is rotated during deposition. In various embodiments, a deposition angle θ2 is used to deposit the tunnel barrier 3. For example, the oblique deposition angle θ2 can be in the range of 10-15 degrees, resulting in a thinner tunnel barrier 3 thickness (approximately 10 Å) on the sides of the metal pillar 10 and approximately 16-40 Å on the top of the metal pillar 10 and on the top of the ILD 8 (assuming an angle α of 80 degrees). In other examples using different deposition parameters, the thickness of the tunnel barrier 3 can be in the range of 8 Å to 20 Å (depending on the various materials used as the tunnel barrier) on the sloped side of the free layer 2 above the side of the metal pillar 10. By depositing the tunnel barrier 3 material with a non-uniform thickness, a very thick layer of tunnel barrier 3 is formed on the horizontal surfaces of the free layer 2 above the ILD 8, and a thicker layer of tunnel barrier 3 is formed on the free layer 2 above the top or horizontal portions of the metal pillars 10. These thick portions of the tunnel barrier 3 can be considered essentially non-conductive. Current cannot flow through these thick horizontal portions of the tunnel barrier 3, and is negligible or close to zero. A thinner layer of tunnel barrier 3, approximately 8-20 angstroms thick, can be present on the free layer 2 on the sides of the metal pillars 10, allowing electrons to tunnel through these regions. The portions of the tunnel barrier 3 on the sidewalls of the metal pillars 10 are thin enough to allow electron tunneling, while the horizontal portions of the tunnel barrier 3 are thick enough to prevent electron tunneling.

[0040] In various embodiments, the tunnel barrier 3 is made of MgO. In some embodiments, the tunnel barrier 3 is made of TiO, CsO x , BaO x , SrO xThe tunnel barrier 3 may be composed of, but is not limited to, ZrO2, HfO2, Al2O3, MgAlO, or any combination or compound of these materials that can provide a good tunnel barrier, where x can be any number of oxygen atoms that form a compound material for a good tunnel barrier.

[0041] 4 is a cross-sectional view of a semiconductor structure 400 after depositing a reference layer 4 on the tunnel barrier 3 and passivating the reference layer 4, according to one embodiment of the present invention. The reference layer 4 is deposited on the tunnel barrier 3 using a deposition angle θ1. For example, when using a deposition angle θ1 of 80 degrees, the thickness of the deposited layer on the tunnel barrier 3 above the sides of the metal pillar 10 is in the range of 25-35 angstroms, while the reference layer 4 deposition on the horizontal surfaces of the tunnel barrier 3 (e.g., above the ILD 8 and above the top of the metal pillar 10) is in the range of 3-6 angstroms. In other examples, when using different deposition angles, the thickness of the reference layer 4 on the tunnel barrier 3 above the sloping sides of the metal pillar 10 can range from 20-100 angstroms. As a result of the different thicknesses of the reference layer 4 on the inclined sidewalls of the metal pillar and on the horizontal surfaces of the semiconductor structure 400, the reference layer 4 on the tunnel barrier 3 above the ILD 8 is essentially non-conductive (e.g., carries little or no current) because the reference layer 4 on the horizontal surfaces is an extremely thin layer.

[0042] In various embodiments, the reference layer 4 is composed of a CFB. In some embodiments, the reference layer 4 is composed of one or more bilayers of a CFB and a high-damping material (e.g., a heavy metal) to improve the stability of the reference layer 4 under STT switching. In other embodiments, the reference layer 4 is composed of a bilayer of a CFB and one or more antiferromagnetic layers to pin the CFB. In one embodiment, the reference layer 4 is composed of a bilayer of a CFB and an SAF layer to minimize stray dynamic fields arising from the reference layer 4 that may act on the free layer 2 during STT switching.

[0043] In the MTJ stack of a funnel-shaped STTMRAM device, the reference layer 4 can be more than twice as thick as the free layer 2 to ensure stability during STT switching. In another embodiment of the MTJ stack, the reference layer 4 is laminated with an antiferromagnetic (AFM) layer for good STT switching. In yet another embodiment of the MTJ stack, the reference layer 4 is laminated with a high damping layer such as Ta, W, Ir, and Pt.

[0044] In an alternative embodiment, the reference layer 4 is deposited directly on the metal pillar 10. In this embodiment, the tunnel barrier 3 can be deposited directly on the reference layer 4, and the free layer 2 can be deposited on the tunnel barrier 3, using the deposition angles described above (e.g., deposition angle θ1 for the reference layer 4 and the free layer 2 and deposition angle θ2 for the tunnel barrier 3). When the deposition of each layer of the MTJ stack (e.g., reference layer 4, tunnel barrier 3, and free layer 2) is completed, the MTJ stack forms an inverted funnel STTMRAM device. The MTJ stack for forming an inverted STTMRAM device can have the free layer 2 on the tunnel barrier 3 and the tunnel barrier 3 on the reference layer 4, with the reference layer 4 deposited directly on the metal pillar 10.

[0045] In various embodiments, passivation of the reference layer 4 is performed using a highly collimated oxygen ion beam when the reference layer 4 is thicker than 5 angstroms on the horizontal surface above the ILD 8 and when forming a DMTJ for a funnel-shaped STTMRAM device, as described below with reference to Figures 8-9. If the reference layer 4 is thicker than 5 angstroms on the horizontal portion above the ILD 8, a highly collimated oxygen ion beam can be directed toward the top surface of the semiconductor structure 400. The oxygen beam is perpendicular to the horizontal wafer surface, as shown in Figure 4. The thickness of the passivation layer of the reference layer 4 varies depending on the location of the reference layer 4. Passivation or oxidation of the reference layer reduces the electrical conductance of the reference layer 4. The passivated portion of the reference layer 4 becomes electrically resistive.

[0046] In the horizontal portions of the reference layer 4, passivation can penetrate completely through the thickness of the reference layer 4. For example, as shown in the cutaway portion on the left, the horizontal portion of the reference layer 4 above the ILD 8 is completely passivated and has very high electrical resistance. Complete passivation of the horizontal portion of the reference layer 4 limits the conductance of the horizontal portion of the reference layer 4, causing the horizontal portion to behave like a non-ferromagnetic material. The energy of the oxygen ion beam can be adjusted, for example, between 50 eV and 800 eV, to achieve the desired passivation penetration depth. For example, if the horizontal portion of the reference layer 4 is approximately 5 Å, the energy of the oxygen ion beam can be adjusted to achieve a passivation thickness of 5 Å in the horizontal portion of the reference layer 4.

[0047] In the semiconductor structure 400, the passivation thickness of the reference layer 4 over the side of the metal pillar 10 is very thin, for example, in the angstrom range, where the thickness of the reference layer 4 is about 25-35 angstroms over the sloping side of the metal pillar 10. The penetration depth of the passivation on the sloping or tilted side of the metal pillar 10 is affected by the angle α (i.e., the angle of the side of the metal pillar 10) and the energy of the oxygen ion beam. An example of the passivation thickness of the reference layer 4 over the side of the metal pillar 10 is shown in the cutaway to the right of the reference layer 4.

[0048] 5 is a cross-sectional view of a semiconductor structure 500 after depositing a top contact 66 according to one embodiment of the present invention. For example, a layer of metal for the top contact 66 may be deposited on the semiconductor structure 500. In some embodiments, the layer of top contact 66 material is selectively deposited. For example, the layer of top contact 66 is selectively deposited using known semiconductor processes to form the top contact 66 (e.g., to form one or more bit lines). The top contact 66 may be composed of any contact metal used in MRAM or CMOS devices.

[0049] FIG. 6 is a cross-sectional view of a semiconductor structure 600 after forming a top contact 66 according to one embodiment of the present invention. The top contact 66 can be selectively patterned and etched using conventional photolithography and etching processes to form the top contact 66. In various embodiments, the top contact 66 can be formed on the reference layer 4. The top contact 66 is above the magnetic layers of the MTJ of a funnel-shaped STTMRAM device. The etching of the top contact 66 can terminate below or extend to the bottom surface of the metal pillar 10. In various embodiments, the etching of the top contact 66 continues into the top of the ILD 8 adjacent to the metal pillar 10. If the horizontal portions of the MTJ (e.g., the reference layer 4, the tunnel barrier 3, and the free layer 2) are exposed, the horizontal portions of the MTJ can be passivated by exposing them to oxygen plasma. In various embodiments, the top contact 66 functions as a bit line.

[0050] FIG. 7 is a cross-sectional view of a semiconductor structure 700 after depositing a layer of ILD 70 and performing chemical-mechanical polishing (CMP) in accordance with one embodiment of the present invention. In various embodiments, ILD 70 is deposited on semiconductor structure 700, and CMP is performed until it contacts top contact 66 to remove the top of ILD 70. In some cases, CMP may remove the top of top contact 66. Semiconductor structure 700 illustrates one embodiment of a funnel-shaped STTMRAM. In various embodiments, semiconductor structure 700 illustrates a funnel-shaped STTMRAM having a single MTJ stack composed of a free layer 2, a tunnel barrier 3, and a reference layer 4, with free layer 2 resting on metal pillar 10. In various embodiments, the MTJ stack is covered by top contact 66. In various embodiments, the top surface of semiconductor structure 700 is exposed for further semiconductor processing, such as etching or deposition processes, to form additional connections, semiconductor devices, or interconnect layers on semiconductor structure 700. Additional metal, dielectric, or other material layers may be deposited over semiconductor structure 700 to complete the formation of one or more semiconductor chips.

[0051] As previously described, the semiconductor structure 700 forms a funnel-shaped STTMRAM device that provides a stable or closed vortex state in the funnel-shaped STTMRAM device. For the reasons previously described, a stable or closed vortex state is desirable in the funnel-shaped STTMRAM. Using the methods and structures described above in FIGS. 1-7, funnel-shaped STTMRAM devices can be formed in a variety of configurations to match specific transistor resistances. For example, a target resistance of 10 kOhms for a funnel-shaped STTMRAM device that matches the resistance of a specific CMOS transistor can be achieved for a variety of device geometries. By modifying tunnel barrier attributes, such as resistance per area, due to different tunnel barrier geometries and / or materials, the target resistance can be achieved by varying the height-to-diameter ratio of the funnel-shaped STTMRAM device. For example, a tunnel barrier with 20 Ohms per square micron, an average funnel radius of 20 nm, and a funnel height of 16 nm provides a highly stable vortex state, as does a tunnel barrier with 5 Ohms per square micron and a funnel height of 4 nm. This example shows that for a wide range of resistance per area of the tunnel barrier 3 (e.g., 5 to 20 ohms per square micron), the target resistance of the funnel-shaped STTMRAM device can be achieved by varying the height of the funnel-shaped STTMRAM device (i.e., adjusting the height of the nanofunnel).

[0052] 8 is a cross-sectional view of a semiconductor structure 800 of a second funnel-shaped or funnel-like STTMRAM device having a DMTJ, according to one embodiment of the present invention. In various embodiments, the semiconductor structure 800 has the layers of the DMTJ deposited on the metal pillars 10 using the methods described above in FIGS. 1-7.

[0053] In various embodiments, a reference layer 81 is deposited on the metal pillar 10. Deposition of the reference layer 81 can be performed using a deposition angle θ1. For example, as previously described, a deposition angle in the range of 80 degrees can provide a thicker deposition of the reference layer 81 (i.e., the first reference layer of the DMTJ) on the sloping side of the metal pillar 10. In some embodiments, the thickness of the reference layer 81 deposited on the sidewall of the metal pillar 10 is more than twice as thick as the portion of the reference layer 81 deposited on the horizontal surfaces above the semiconductor wafer surface (e.g., on the flat top of the metal pillar 10 and on the exposed horizontal surface or horizontal portion of the ILD 8). The materials and material thicknesses used for the reference layer 81 can be the same as or similar to the materials discussed for the reference layer 4 with respect to FIG. 4, but are not limited to these materials or material thicknesses.

[0054] A tunnel barrier 83 may be deposited on the reference layer 81. The tunnel barrier 83 is a first tunnel barrier layer that may be composed of MgO, but is not limited to this material. The tunnel barrier 83 may be deposited at a deposition angle θ2 to provide a thicker layer on the horizontal surfaces of the semiconductor structure 800 than on the upper inclined surfaces of the metal pillar 10.

[0055] The free layer 85 is deposited on the tunnel barrier 83 using a deposition angle θ1, thereby providing a thicker layer of the free layer 85 above the sloped sides of the metal pillar 10 and a much thinner layer of the free layer 85 on the horizontal surface of the tunnel barrier 83. In various embodiments, the free layer 85 is a synthetic antiferromagnet (SAF) composed of three layers. Each of the three layers of the free layer 85 is deposited at a deposition angle θ1. The free layer 85 can be composed of a first free layer material, such as a layer of a material such as those discussed with respect to free layer 2 in FIG. 2, and an intermediate layer of a non-magnetic spacer material to provide antiferromagnetic coupling between the first and second portions of the free layer. Both portions of the SAF free layer are composed of Co x Fe y B z / Co and Co / Co x Fe y B zThe SAF can be made of a magnetic bilayer such as Co, which has a strong antiferromagnetic coupling. A non-magnetic spacer is required to provide antiferromagnetic Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling between the first and second portions of the free layer 2. Commonly used non-magnetic spacer materials for the intermediate layer of the free layer 85 can be Ru and Ir. In one embodiment, the structure of the free layer 85 (e.g., the structure of the SAF for the free layer 85) can be Co. x Fe y B z / Co / Ir / Co / Co x1 Fe y1 B z1 or Co x Fe y B z / Co / Ru / Co / Co x1 Fe y1 B z1 where x, y, and z identify the number of atoms, and x1y1 and z1 identify different numbers of atoms, although the free layer 85 is not limited to these materials.

[0056] In some embodiments, if the thickness of the horizontal portion of the free layer 85 is greater than 5 angstroms, the free layer 85 can be passivated using an oxygen ion beam process. Passivation can be performed to minimize the conductance of the horizontal portion of the free layer 85. The passivation process previously described in detail with respect to FIG. 4 can be used. For example, the free layer 85 can be passivated using a highly collimated oxygen ion beam. Passivation can be performed after deposition of the first layer of the free layer 85 (e.g., the first free layer of the SAF) or after deposition of the second portion of the free layer 85 or the nonmagnetic layer.

[0057] Tunnel barrier 87 may be a second tunnel barrier layer. In various embodiments, tunnel barrier 87 is made of a different material and has a different thickness than tunnel barrier 83. For example, tunnel barrier 83 may be made of MgO, and tunnel barrier 87 may be made of MgAlO or another oxide other than MgO. A typical thickness of tunnel barrier 87 (e.g., for a deposition angle θ of 15 degrees) may be 16 to 40 angstroms on the horizontal portion of reference layer 85.

[0058] A typical thickness of the tunnel barrier 87 on the reference layer 85 above the inclined side of the metal pillar 10 (e.g., angle θ2=15 degrees) can be 8-20 angstroms. By depositing a different material for the tunnel barrier 87 and a different thickness than the tunnel barrier 83, the MR signal from the DMTJ and the spin torque generated by the DMTJ can be simultaneously optimized (e.g., both the MR signal and the spin torque can be maximized simultaneously).

[0059] In various embodiments, the reference layer 89 is deposited on the tunnel barrier 87 using a deposition angle θ2. Deposition of the reference layer 89 using a deposition angle θ2 provides a thicker layer of the reference layer 89 on the tunnel barrier 87 above the inclined sidewalls of the metal pillar 10 and a thinner layer of the reference layer 89 on the horizontal surfaces of the tunnel barrier 87. In some embodiments, the layer of the reference layer 89 deposited on the tunnel barrier 87 above the sidewalls of the metal pillar 10 is 2 to 6 times thicker than the portion of the reference layer 89 deposited on the horizontal surfaces of the tunnel barrier 87 (e.g., above the flat top of the metal pillar 10 and on the tunnel barrier 87 above the semiconductor wafer surface). As previously mentioned, in this manner, the thin horizontal portions of the reference layer 89 are essentially non-conductive or magnetically inactive. If the thickness of the horizontal portions of the second reference layer 89 is greater than 5 angstroms (e.g., conductive), the passivation step described in FIG. 4 can be used to minimize the conductance of the horizontal portions of the reference layer 89.

[0060] In various embodiments, the reference layer 89 is composed of a different material and has a different thickness than the reference layer 81. By varying the material and thickness of the reference layer 89 above the side of the metal pillar 10 (i.e., on the inclined side of the tunnel barrier 87) from the material and thickness of the reference layer 81, the magnetic stability of the reference layer 89 can be optimized. In addition, varying the material and thickness of the reference layer 89 relative to the reference layer 81 provides optimal conditions for setting the magnetization directions of the reference layer 89 and the reference layer 81. For example, if the reference layer 81 is a 30 angstrom thick layer of CFB on the inclined surface of the tunnel barrier 83 (i.e., above the inclined side of the metal pillar 10), the reference layer 89 can be 50 angstroms thick on the inclined side of the tunnel barrier 87. In this case, an antiparallel configuration of vortices can be achieved in both reference layers by cooling the structure in a weak external magnetic field perpendicular to the wafer surface. The thickness of the reference layer 89 on the sloped surface of the tunnel barrier 87 can be in the range of 10 to 50 angstroms, but is not limited to these thicknesses. Some example materials for the reference layer 89 include CFB, Permalloy, CoFe, and combinations of these materials laminated with heavy metals to increase damping. The selection of the specific material and material thickness for the reference layer 89 can be optimized in various ways. For example, the specific material and material thickness for the reference layer 89 can be selected to achieve one or more of the following: maximum MR signal, maximum device switching efficiency, provide good bit stability at high temperatures (e.g., in automotive applications), or ensure good stability of the reference layer.

[0061] FIG. 9 is a cross-sectional view of a semiconductor structure 900 after completion of the top contact 66, according to one embodiment of the present invention. The processes for depositing the top contact, etching the top contact 66, depositing ILD 70, and planarizing the top surface of the semiconductor structure 900 by CMP have been described above with reference to FIGS. 5-7. In FIG. 9, the top contact 66 can be formed around the reference layer 89 using known semiconductor processes for metal contact formation. For example, a metal layer can be deposited, patterned, and etched to form the top contact 66. In various embodiments, the top contact 66 is a bit line that extends vertically out of the plane of FIG. 9. The etching process for the top contact 66 can be terminated at a level below the bottom surface of the metal pillar 10. If this process is performed, horizontal portions of the DMTJ (e.g., the reference layer 81, the tunnel barrier 83, the free layer 85, the tunnel barrier 87, and the reference layer 89) that are not adjacent to the metal pillar 10 can be removed. Using known semiconductor processes, a second layer of interlevel dielectric material (i.e., ILD 70) can be deposited on the top surface of semiconductor structure 900. ILD 70 surrounds top contact 66 and can be on the exposed side of reference layer 89 of the DMTJ and on exposed portions of ILD 8. ILD 70 is planarized by CMP to reach the top surface of top contact 66, as described above with respect to FIG. 7 . Top contact 66 can function as a bit line for a funnel-shaped STTMRAM device with a DMTJ.

[0062] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. [Explanation of symbols]

[0063] 2 free layer 3 Tunnel Barriers 4 Reference layer 9. Contact 10 Metal Pillar 66 Top Contact 81 Standard layer 83 Tunnel Barrier 85 Reference layer 87 Tunnel Barrier 89 Reference layer 200 Semiconductor Structure 300 Semiconductor structure 400 Semiconductor Structure 500 semiconductor structures 600 Semiconductor Structure 700 Semiconductor Structure 800 Semiconductor Structures 900 Semiconductor Structure α angle θ1 deposition angle θ2 deposition angle

Claims

1. 1. A semiconductor structure of a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device having double magnetic tunnel junctions, comprising: a metal pillar on the connection to the semiconductor device; a first reference layer on the metal pillar and on a portion of the first interlayer dielectric adjacent to the metal pillar; a first tunnel barrier on the first reference layer; a free layer on the first tunnel barrier; a second tunnel barrier on the free layer; and a second reference layer on the second tunnel barrier; and Equipped with 1. A semiconductor structure, wherein a first portion of the first reference layer, the free layer, and the second reference layer on a sidewall of the metal pillar is thicker than a second portion of the first reference layer, the free layer, and the second reference layer on a horizontal surface above a semiconductor wafer surface and on a horizontal surface above a flat top of the metal pillar.

2. 2. The semiconductor structure of claim 1 , wherein said first portions of said first reference layer, said free layer, and said second reference layer on said sidewalls of said metal pillar are at least twice as thick as said second portions of said first reference layer, said free layer, and said second reference layer on said horizontal surfaces above said semiconductor wafer surface and above said horizontal surfaces above said flat tops of said metal pillars.

3. 3. The semiconductor structure of claim 1 or 2, wherein the first reference layer, the free layer, and the second portion of the second reference layer deposited on the horizontal surface above the semiconductor wafer surface and on the horizontal surface above the flat tops of the metal pillars are non-conductive and non-ferromagnetic.

4. A semiconductor structure for a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device having a double magnetic tunnel junction, comprising: a metal pillar on the connection to the semiconductor device; a first reference layer on the metal pillar and on a portion of the first interlayer dielectric adjacent to the metal pillar; a first tunnel barrier on the first reference layer; a free layer on the first tunnel barrier; a second tunnel barrier on the free layer; and a second reference layer on the second tunnel barrier; and Equipped with the first reference layer, the first tunnel barrier, the free layer, the second tunnel barrier, and the second reference layer are disposed above a planar top of the metal pillar.

5. 5. The semiconductor structure of claim 1, wherein said free layer is a synthetic antiferromagnet.

6. 6. The semiconductor structure of claim 5 wherein said free layer is comprised of a first free layer, a nonmagnetic spacer, and a second free layer.

7. 7. The semiconductor structure of claim 1, wherein a thickness of one or more horizontal portions of the first tunnel barrier and a thickness of one or more horizontal portions of the second tunnel barrier are thicker than a portion of the first tunnel barrier and a portion of the second tunnel barrier deposited on a sidewall of the metal pillar.

8. 8. The semiconductor structure of claim 1, wherein the first reference layer, the first tunnel barrier, the free layer, the second tunnel barrier, and the second reference layer form a double magnetic tunnel junction in the funnel-shaped spin transfer torque MRAM device.

9. a contact metal on the second reference layer, wherein a second interlayer dielectric surrounds the contact metal and on exposed sides of the second reference layer, the second tunnel barrier, the free layer, the first tunnel barrier, and the first reference layer and on exposed portions of the first interlayer dielectric; 10. The semiconductor structure of claim 1 further comprising:

10. 10. The semiconductor structure of claim 9 wherein said contact metal over said second reference layer functions as a bitline.

11. 1. A semiconductor structure of a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device, comprising: a metal pillar on the connection to the semiconductor device; a free layer on the metal pillar and on a portion of the first interlayer dielectric adjacent to the metal pillar; a tunnel barrier on the free layer; a reference layer on the tunnel barrier; Equipped with a first portion of the reference layer on a sidewall of the metal pillar and a first portion of the free layer above the sidewall of the metal pillar are thicker than one or more portions of the free layer and a second portion of the reference layer above a horizontal surface above a semiconductor wafer surface and above a horizontal surface above a flat top of the metal pillar.

12. 12. The semiconductor structure of claim 11 , wherein the thickness of said free layer on said sidewalls of said metal pillars is five times the thickness of said free layer on said horizontal surfaces above said semiconductor wafer surface and on said horizontal surfaces above said flat tops of said metal pillars.

13. A semiconductor structure for a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device, comprising: a metal pillar on the connection to the semiconductor device; a free layer on the metal pillar and on a portion of the first interlayer dielectric adjacent to the metal pillar; a tunnel barrier on the free layer; a reference layer on the tunnel barrier; Equipped with The semiconductor structure, wherein the free layer, the tunnel barrier, and the reference layer are disposed above the flat top of the metal pillar.

14. 14. The semiconductor structure of any one of claims 11 to 13, wherein said free layer is composed of one of the group of materials: cobalt iron boron, a bilayer of cobalt iron boron and cobalt iron, a light metal, a bilayer of cobalt iron boron and a Heusler alloy, or a bilayer of cobalt iron boron and a soft magnetic material.

15. 15. The semiconductor structure of claim 14 wherein said free layer is comprised of one of a bilayer of cobalt iron boron and cobalt iron aluminum, cobalt iron boron and nickel manganese antimony, or cobalt iron boron and permalloy.

16. 1. A method for forming a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device, comprising: depositing a free layer on the metal pillars and on the interlayer dielectric, the metal pillars overlying the contacts to the semiconductor device having sloped sides; depositing a tunnel barrier layer over the free layer; depositing a reference layer over the tunnel barrier layer; removing the free layer, horizontal portions of the tunnel barrier layer and the reference layer, and a top portion of the interlayer dielectric adjacent to the metal pillar; forming a contact on a remaining portion of the reference layer; Equipped with depositing the free layer and the reference layer at a first oblique deposition angle, the first oblique deposition angle being in a range of 70 to 80 degrees with respect to a reference direction perpendicular to a surface of the semiconductor wafer when the semiconductor wafer is rotated; the steps of depositing the free layer and the reference layer are performed using the same deposition angle to provide a thin portion of the free layer and a thin portion of the reference layer above a horizontal surface of the interlayer dielectric adjacent the metal pillar and above a top surface of the semiconductor wafer, and the thin portion of the free layer and the thin portion of the reference layer are non-conductive.

17. 17. The method of claim 16, wherein the tunnel barrier layer is deposited at a second oblique deposition angle, the second oblique deposition angle for the tunnel barrier layer being in the range of 10 to 15 degrees as measured with respect to the reference direction normal to a surface of the semiconductor wafer, and the semiconductor wafer is rotated during deposition of the tunnel barrier layer.

18. 18. The method of claim 17, wherein the tunnel barrier layer is deposited at the first oblique deposition angle, a first portion of the tunnel barrier layer on a sidewall of the metal pillar being thin enough to allow electron tunneling, and one or more horizontal portions of the tunnel barrier layer being thick enough to prevent electron tunneling.

19. A method for forming a funnel-shaped spin transfer torque (STT) magnetoresistive random access memory (MRAM) device, comprising: depositing a free layer on the metal pillar and the interlayer dielectric, the metal pillar overlying a contact to a semiconductor device having sloped sides; depositing a tunnel barrier layer over the free layer; depositing a reference layer over the tunnel barrier layer; removing the free layer, horizontal portions of the tunnel barrier layer and the reference layer, and a top portion of the interlayer dielectric adjacent to the metal pillar; forming contacts on the sidewalls of the metal pillars and on remaining portions of the reference layer above the planar tops of the metal pillars; A method comprising:

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