Power Conversion Device

Abstract

First and second semiconductor elements (Q1, Q2) are connected in series between a DC positive bus line (10) and a DC neutral point bus line (20). Third and fourth semiconductor elements (Q3, Q4) are connected in series between the DC neutral point bus line (20) and a DC negative bus line (30). Fifth and sixth semiconductor elements (Q5, Q6) are connected in series between a connection point of the first and second semiconductor elements (Q1, Q2) and a connection point of the third and fourth semiconductor elements (Q3, Q4). Each of the semiconductor elements includes at least one semiconductor switching element and at least one diode. The breakdown resistances of the first and fourth semiconductor elements (Q1, Q4) with respect to cosmic rays are higher than the breakdown resistances of the second and third semiconductor elements (Q2, Q3) with respect to the cosmic rays. The breakdown resistances of the fifth and sixth semiconductor elements (Q5, Q6) are higher than the breakdown resistances of the first and fourth semiconductor elements (Q1, Q4).

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2021-61692 (Patent Document 1) discloses a power conversion device that outputs power at three levels of potential (upper potential, intermediate potential, and lower potential). This power conversion device includes an upper potential semiconductor module incorporating at least one upper potential switching element, a lower potential semiconductor module incorporating at least one lower potential switching element, and an intermediate semiconductor module incorporating multiple intermediate switching elements. The withstand voltage of the intermediate semiconductor module is configured to be greater than the withstand voltage of the upper semiconductor module and the withstand voltage of the lower semiconductor module. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-61692 Summary of the Invention [Problem to be solved by the invention]

[0004] One of the causes of failure in power conversion equipment is the random failure of semiconductor elements due to neutrons from cosmic rays. If a neutron collides with a semiconductor element while a voltage is applied to the semiconductor element, the semiconductor element will be destroyed. This phenomenon is called SEB (Single Event Burnout).

[0005] The failure mode of semiconductor elements due to SEB is an open circuit failure of the semiconductor switching element included in the semiconductor element, which is a failure in which the semiconductor switching element does not turn on (remains off).

[0006] In the power conversion device described in Patent Document 1, the withstand voltage of the intermediate semiconductor module is configured to be higher than the withstand voltage of the upper semiconductor module and the lower semiconductor module, thereby increasing the breakdown resistance of the intermediate semiconductor module due to SEB. However, if an open circuit fault due to SEB occurs in at least one of the higher potential semiconductor module and the lower potential semiconductor module, the power conversion device will be unable to output the higher potential or the lower potential, making it impossible to continue power conversion operation.

[0007] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a power conversion device that can continue power conversion operation even in the event of an accidental failure caused by cosmic rays. [Means for solving the problem]

[0008] In one aspect of the present disclosure, a power conversion device is provided between a DC positive bus, a DC negative bus, and a DC neutral bus and an AC line, and performs power conversion between DC power and AC power. The power conversion device includes first to sixth semiconductor elements. The first semiconductor element has a first electrode connected to the DC positive bus. The second semiconductor element has a first electrode connected to the second electrode of the first semiconductor element and a second electrode connected to the DC neutral bus. The third semiconductor element has a first electrode connected to the DC neutral bus. The fourth semiconductor element has a first electrode connected to the third electrode of the third semiconductor element and a second electrode connected to the DC negative bus. The fifth semiconductor element has a first electrode connected to the first electrode of the second semiconductor element and a second electrode connected to the AC line. The sixth semiconductor element has a first electrode connected to the AC line and a second electrode connected to the second electrode of the third semiconductor element. Each of the first to sixth semiconductor elements includes at least one semiconductor switching element and at least one diode connected in anti-parallel to the at least one semiconductor switching element. The first and fourth semiconductor elements have a higher cosmic ray resistance than the second and third semiconductor elements. The fifth and sixth semiconductor elements have a higher cosmic ray resistance than the first and fourth semiconductor elements. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a power conversion device that can continue power conversion operation even in the event of an accidental failure caused by cosmic rays. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of an embodiment of a power conversion device according to the present disclosure. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a three-level circuit included in the power conversion device. [Figure 3] FIG. 2 is a diagram illustrating a hardware configuration of a control circuit. [Figure 4] 1 is a diagram schematically illustrating the relationship between the voltage applied to a semiconductor element and the failure rate of the semiconductor element due to SEB. [Figure 5] FIG. 1 is a diagram schematically showing the relationship between the voltage applied to a semiconductor element and the failure rate. [Figure 6] 1 is a diagram schematically illustrating the relationship between the voltage applied to a semiconductor element and the failure rate of the semiconductor element due to SEB. [Figure 7] FIG. 11 is a circuit diagram showing a configuration of a three-level circuit included in a power conversion device according to a fourth embodiment. [Figure 8] FIG. 2 is a diagram illustrating a functional configuration of a control circuit of the power conversion device. [Figure 9] FIG. 5 is a diagram illustrating the correlation between the element temperature and the failure rate of a fifth semiconductor element. [Figure 10] 10 is a flowchart illustrating an example of a procedure for adjusting the number of switching elements to be switched. [Figure 11] 10 is a time chart showing an example of a procedure for changing a switching element that stops switching in a fifth semiconductor element. [Figure 12] FIG. 13 is a circuit diagram showing a configuration of a three-level circuit included in a power conversion device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0012] Embodiment 1 <Configuration of power conversion device> FIG. 1 is a block diagram showing the configuration of an embodiment of a power conversion device according to the present disclosure.

[0013] 1, power conversion device 100 according to the first embodiment is a three-level inverter that converts DC power from a DC power supply 101 into three-phase AC power and supplies the power to a load. The load is, for example, a motor 180 mounted on an aircraft. Motor 180 generates propulsion power for the aircraft using the three-phase AC power supplied from power conversion device 100.

[0014] The power conversion device 100 includes a DC positive bus 10, a DC neutral bus 20, a DC negative bus 30, capacitors 111, 112, AC lines 40U, 40V, 40W, a U-phase arm 50u, a V-phase arm 50v, a W-phase arm 50w, and a control circuit 60.

[0015] A DC power supply 101 supplies power from terminals P and N. A DC positive bus 10 is connected to terminal P, and a DC negative bus 30 is connected to terminal N. Capacitors 111 and 112 are connected in series between the DC positive bus 10 and the DC negative bus 30 to smooth the voltage between the DC positive bus 10 and the DC negative bus 30. The capacitors 111 and 112 have the same rated capacity. A DC neutral point bus 20 is connected to a neutral point C, which is the connection point of the capacitors 111 and 112.

[0016] U-phase arm 50u, V-phase arm 50v, and W-phase arm 50w are provided in parallel between DC positive bus 10 and DC negative bus 30. Each phase arm is formed by a three-level circuit 50 shown in FIG.

[0017] FIG. 2 is a circuit diagram showing the configuration of a three-level circuit 50 included in the power conversion device 100. As shown in FIG. As shown in Fig. 2, the three-level circuit 50 includes six semiconductor elements Q1 to Q6. Each of the semiconductor elements Q1 to Q6 includes at least one semiconductor switching element (hereinafter also simply referred to as a "switching element") and at least one diode. In the example of Fig. 2, each semiconductor element includes one switching element and one diode. The switching element and the diode may be configured on a single chip or on separate chips.

[0018] In this embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the switching element. Note that an IGBT (Insulated Gate Bipolar Transistor) or the like can be used as the switching element. For example, a SiC (Silicon Carbide)-MOSFET, a Si (Silicon)-MOSFET, a SiC-IGBT, a Si-IGBT, a GaN-HEMT (High Electron Mobility Transistor), or the like can be used as the switching element.

[0019] At least one diode is connected in antiparallel to at least one switching element. If the switching elements are MOSETs, the diodes can be configured using the parasitic diodes (body diodes) of the MOSFETs. The diodes can be, for example, Si-diodes, SiC-diodes, SiC-SBDs (Schottky Barrier Diodes), etc.

[0020] The first semiconductor element Q1 has a first electrode connected to the DC positive bus 10 and a second electrode connected to a first electrode of the second semiconductor element Q2. The first semiconductor element Q1 includes a switching element S1 and a diode D1.

[0021] The second semiconductor element Q2 has a first electrode connected to the second electrode of the first semiconductor element Q1, and a second electrode connected to the DC neutral bus 20. The second semiconductor element Q2 includes a switching element S2 and a diode D2.

[0022] The third semiconductor element Q3 has a first electrode connected to the DC neutral bus 20 and a second electrode connected to a first electrode of the fourth semiconductor element Q4. The third semiconductor element Q3 includes a switching element S3 and a diode D3.

[0023] The fourth semiconductor element Q3 has a first electrode connected to the second electrode of the third semiconductor element Q3, and a second electrode connected to the DC negative bus 30. The fourth semiconductor element Q4 includes a switching element S4 and a diode D4.

[0024] The fifth semiconductor element Q5 has a first electrode connected to the first electrode of the second semiconductor element Q2, and a second electrode connected to the AC line 40. The fifth semiconductor element Q5 includes a switching element S5 and a diode D5.

[0025] The sixth semiconductor element Q6 has a first electrode connected to the AC line 40 and a second electrode connected to the second electrode of the third semiconductor element Q3. The sixth semiconductor element Q6 includes a switching element S6 and a diode D6.

[0026] The diodes D1, D4, D5, and D6 function as freewheeling diodes (FWD), and the diodes D2 and D3 function as clamp diodes.

[0027] Returning to Fig. 1, the control circuit 60 controls power conversion in the power conversion device 100. Fig. 3 is a diagram showing the hardware configuration of the control circuit 60. As shown in Fig. 3, the control circuit 60 includes a CPU (Central Processing Unit) 61, a RAM (Random Access Memory) 62, a ROM (Read Only Memory) 63, an I / F (Interface) device 64, and a storage device 65. The CPU 61, RAM 62, ROM 63, I / F device 64, and storage device 65 exchange various types of data via a communication bus 66.

[0028] The CPU 61 loads a program stored in the ROM 63 into the RAM 62 and executes it. The program stored in the ROM 63 describes the processes to be executed by the control circuit 60.

[0029] The I / F device 64 receives measurement data of various measurements including those from a GPS, an altimeter, and a thermometer, which will be described later, and also transmits control signals to the semiconductor elements Q1 to Q6 to control the switching of each of the semiconductor elements.

[0030] The storage device 65 is a storage for storing various types of information, and stores information about each semiconductor element. The storage device 65 also stores information about the failure rate of each semiconductor element relative to the SEB. The storage device 65 is, for example, a hard disk drive (HDD) or a solid state drive (SSD).

[0031] All or part of the functions realized by the CPU 61 executing the programs may be realized using a hard-wired circuit such as an integrated circuit, for example, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a CPLD (Complex Programmable Logic Device).

[0032] <Power conversion device operation> Next, the operation of the three-level circuit 50 shown in FIG. 2 will be described.

[0033] The three-level circuit 50 is configured to output three potentials, a high potential (+Vdc), a neutral point potential (0), and a low potential (-Vdc), to the AC line 40. The high potential (+Vdc) is the potential of the terminal P, the neutral point potential (0) is the potential of the neutral point C, and the low potential (-Vdc) is the potential of the terminal N.

[0034] During the period when a high potential (+Vdc) is output, control is performed to turn on the switching elements S1 and S5 of the first and fifth semiconductor elements Q1 and Q5, and to turn off the switching elements S2, S3, S4, and S6 of the second, third, fourth, and sixth semiconductor elements Q2, Q3, Q4, and Q6.

[0035] During the period when the neutral point potential (0) is output, control is performed to turn on the switching elements S2 and S5 of the second and fifth semiconductor elements Q2 and Q5, or control is performed to turn on the switching elements S3 and S6 of the third and sixth semiconductor elements Q3 and Q6.

[0036] During the period when a low potential (-Vdc) is output, control is performed to turn on the switching elements S4 and S6 of the fourth and sixth semiconductor elements Q4 and Q6, and to turn off the switching elements S1, S2, S3, and S5 of the first, second, third, and fifth semiconductor elements Q1, Q2, Q3, and Q5.

[0037] <Random failure of semiconductor devices> Next, random failures in semiconductor elements will be described.

[0038] One of the causes of failure in power conversion equipment is the random failure of semiconductor elements due to neutrons from cosmic rays. When cosmic rays penetrate the Earth's atmosphere, they collide with the atmosphere, generating neutrons. If these neutrons collide with semiconductor elements that have voltage applied, the semiconductor elements may fail. This phenomenon is also known as SEB (Single Event Burnout).

[0039] A possible failure of a semiconductor element due to SEB is an open circuit failure of the switching element included in the semiconductor element. An open circuit failure is a failure in which the switching element does not turn on (remains off). The failure rate of semiconductor elements due to SEB increases as the voltage applied to the semiconductor element increases.

[0040] 2, if an open circuit fault due to an SEB occurs in any one of the semiconductor elements Q1 to Q6, there is a possibility that the power conversion device 100 will be unable to continue its power conversion operation. In this case, the motor 180 will be unable to be driven, which raises concerns that it will be difficult to obtain propulsive force for the aircraft. In order to stably obtain propulsive force for the aircraft, it is required that the power conversion device 100 be able to continue its power conversion operation even if an open circuit fault due to an SEB occurs.

[0041] In this embodiment, from the viewpoint of realizing continuity of the power conversion operation of the power conversion device 100, the semiconductor elements Q1 to Q6 constituting the three-level circuit 50 are designed to have a breakdown resistance against cosmic rays (hereinafter also referred to as "cosmic ray resistance").

[0042] Specifically, the cosmic ray tolerance of the first and fourth semiconductor elements Q1 and Q4 is set to be higher than that of the second and third semiconductor elements Q2 and Q3, and the cosmic ray tolerance of the fifth and sixth semiconductor elements Q1 is set to be higher than that of the first and fourth semiconductor elements Q1 and Q4.

[0043] The failure rate of a semiconductor element due to SEB when a certain voltage is applied decreases as the cosmic ray tolerance of the semiconductor element increases. Therefore, when the voltages applied to the semiconductor elements Q1 to Q6 are equal, the failure rate of the first and fourth semiconductor elements Q1, Q4 is lower than the failure rate of the second and third semiconductor elements Q2, Q3. The failure rate of the fifth and sixth semiconductor elements Q5, Q6 is lower than the failure rate of the first and fourth semiconductor elements Q1, Q4.

[0044] By designing the cosmic ray tolerance of the semiconductor elements Q1 to Q6 as described above, even in an environment where the amount of neutrons originating from cosmic rays is high, it becomes possible to continue the power conversion operation of the power conversion device 100. This is because even if an open circuit failure occurs in at least one of the second and third semiconductor elements Q2, Q3, the occurrence of an open circuit failure is suppressed in the first and fourth semiconductor elements Q1, Q4 and the fifth and sixth semiconductor elements Q5, Q6, which have a lower failure rate than the second and third semiconductor elements Q2, Q3.

[0045] More specifically, even if an open circuit fault occurs in the second and third semiconductor elements Q2 and Q3, the three-level circuit 50 can output a high potential (+Vdc) by turning on the first and fifth semiconductor elements Q1 and Q5. Furthermore, the three-level circuit 50 can output a low potential (-Vdc) by turning on the fourth and sixth semiconductor elements Q4 and Q6. That is, even if an open circuit fault occurs in the second and third semiconductor elements Q2 and Q3, the three-level circuit 50 can operate as a two-level circuit. As a result, the power conversion device 100 can continue power conversion operation as a two-level inverter even in the event of an accidental fault due to cosmic rays.

[0046] Here, by equally increasing the cosmic ray tolerance of all semiconductor elements Q1 to Q6, it is possible to suppress open circuit failures of semiconductor elements Q1 to Q6 and continue power conversion operation in power conversion device 100. However, since semiconductor elements with high cosmic ray tolerance are used for all semiconductor elements Q1 to Q6, the cost of the semiconductor elements increases. As a result, there is a concern that the cost of power conversion device 100 will increase.

[0047] In contrast to this, in the first embodiment, as described above, a magnitude relationship is established between the cosmic ray tolerances of the semiconductor elements Q1 to Q6 so that operation as a two-level circuit can be maintained, and therefore, the increase in cost of the power conversion device 100 can be suppressed compared to a configuration in which the cosmic ray tolerances of all the semiconductor elements Q1 to Q6 are made high.

[0048] Embodiment 2 The above-described first embodiment describes a configuration in which a magnitude relationship is established between the cosmic ray tolerances of the semiconductor elements Q1 to Q6 that make up the three-level circuit 50. In the second to fourth embodiments, specific configurations of the three-level circuit 50 for realizing this configuration will be described.

[0049] Figure 4 is a diagram that shows a schematic diagram of the relationship between the voltage applied to a semiconductor element and the failure rate of the semiconductor element due to SEB. The vertical axis of Figure 4 shows the failure rate, and the horizontal axis shows the applied voltage. The failure rate can be calculated, for example, using an index called FIT (Failure-in-Time). FIT is a unit that expresses the failure rate, and indicates how many elements fail within 10 to the power of 9 hours. The smaller the FIT, the lower the failure rate.

[0050] 4 show the relationship between the voltage applied to the semiconductor element and the failure rate. According to these curves, the failure rate of the semiconductor element increases as the voltage applied to the semiconductor element increases.

[0051] Here, the failure rate of a semiconductor element correlates with the dielectric strength voltage of the semiconductor element. In Figure 4, curve L1 shows the relationship between the applied voltage and the failure rate of a semiconductor element having a first dielectric strength voltage. Curve L2 shows the relationship between the applied voltage and the failure rate of a semiconductor element having a second dielectric strength voltage. The second dielectric strength voltage is greater than the first dielectric strength voltage.

[0052] Comparing curves L1 and L2, the failure rate when voltage V1 is applied is lower for semiconductor elements with higher dielectric strength. Note that the correlation between the dielectric strength and failure rate of semiconductor elements shown in Figure 4 remains unchanged regardless of the amount of neutrons irradiated to the semiconductor elements.

[0053] 4, the two semiconductor elements with different dielectric strengths are both MOSFETs with the same element area. The only difference between these two semiconductor elements is the thickness or doping concentration of the drift layer that maintains the MOSFET's dielectric strength.

[0054] In the second embodiment, by utilizing the correlation between the breakdown voltage and failure rate of the semiconductor elements, a magnitude relationship is established among the breakdown voltages of the semiconductor elements Q1 to Q6, thereby establishing a magnitude relationship among the cosmic ray resistances of the semiconductor elements Q1 to Q6.

[0055] 5 is a diagram showing a relationship between the voltage applied to the semiconductor elements Q1 to Q6 and the failure rate, where the vertical axis represents the failure rate and the horizontal axis represents the applied voltage.

[0056] Curve L3 in Figure 5 shows the relationship between the applied voltage and the failure rate of the second and third semiconductor elements Q2, Q3. Curve L4 shows the relationship between the applied voltage and the failure rate of the first and fourth semiconductor elements Q1, Q4. Curve L5 shows the relationship between the applied voltage and the failure rate of the fifth and sixth semiconductor elements Q5, Q6. In all of curves L3 to L5, the failure rate of the semiconductor elements increases as the voltage applied to the semiconductor elements increases.

[0057] 5, when voltage V1 is applied, the failure rates of the first and fourth semiconductor elements Q1 and Q4 are lower than the failure rates of the second and third semiconductor elements Q2 and Q3, and the failure rates of the fifth and sixth semiconductor elements Q5 and Q6 are lower than the failure rates of the first and fourth semiconductor elements Q1 and Q4.

[0058] The failure rates of the semiconductor elements Q1 to Q6 shown in Figure 5 can be achieved by establishing a magnitude relationship among the withstand voltages of the semiconductor elements Q1 to Q6. Specifically, the withstand voltages of the first and fourth semiconductor elements Q1, Q4 are set to be higher than the withstand voltages of the second and third semiconductor elements Q2, Q3. The withstand voltages of the fifth and sixth semiconductor elements Q5, Q6 are set to be higher than the withstand voltages of the first and fourth semiconductor elements Q1, Q4.

[0059] When semiconductor elements Q1 to Q6 are all MOSFETs and have the same element area, the above-described relationship in the breakdown voltages can be achieved by adjusting the thickness or doping concentration of the drift layer.

[0060] Specifically, the thicker the drift layer of a MOSFET, the higher the dielectric strength voltage. Therefore, the drift layers of the first and fourth semiconductor elements Q1, Q4 should be made thicker than the drift layers of the second and third semiconductor elements Q2, Q3, and the drift layers of the fifth and sixth semiconductor elements Q5, Q6 should be made thicker than the drift layers of the first and fourth semiconductor elements Q1, Q4.

[0061] Alternatively, since the lower the doping concentration of the drift layer of a MOSFET, the higher the dielectric strength voltage. Therefore, the doping concentrations of the drift layers of the first and fourth semiconductor elements Q1, Q4 can be made lower than the doping concentrations of the drift layers of the second and third semiconductor elements Q2, Q3, and the doping concentrations of the drift layers of the fifth and sixth semiconductor elements Q5, Q6 can be made lower than the doping concentrations of the drift layers of the first and fourth semiconductor elements Q1, Q4.

[0062] Embodiment 3 6 is a diagram showing the relationship between the voltage applied to a semiconductor element and the failure rate of the semiconductor element due to SEB, where the vertical axis represents the failure rate and the horizontal axis represents the applied voltage.

[0063] Curves L6 and L7 shown in FIG. 6 each show the relationship between the applied voltage and the failure rate of a semiconductor element. The failure rate of a semiconductor element is also correlated with the element area of the semiconductor element. In FIG. 6, curve L6 shows the relationship between the applied voltage and the failure rate of a semiconductor element having a first element area. Curve L7 shows the relationship between the applied voltage and the failure rate of a semiconductor element having a second element area. The second element area is smaller than the first element area.

[0064] Comparing curves L6 and L7, the failure rate when voltage V1 is applied is lower for semiconductor elements with smaller element areas. This is because the smaller the element area of a semiconductor element, the lower the amount of neutrons irradiated onto the semiconductor element.

[0065] In the third embodiment, a relationship in size is established among the semiconductor elements Q1 to Q6 by utilizing the correlation between the element area and failure rate of the semiconductor elements shown in Figure 6, thereby establishing a relationship in size among the cosmic ray resistance of the semiconductor elements Q1 to Q6. Specifically, the element areas of the first and fourth semiconductor elements Q1, Q4 are made smaller than the element areas of the second and third semiconductor elements Q2, Q3. The element areas of the fifth and sixth semiconductor elements Q5, Q6 are made smaller than the element areas of the first and fourth semiconductor elements Q1, Q4.

[0066] In addition, reducing the element area of a semiconductor element can sometimes increase the current per unit area (current density) of the semiconductor element. In this case, as the current density of the semiconductor element increases, the on-resistance of the semiconductor element decreases, and the change in short-circuit current (dI / dt) flowing through the semiconductor element increases. In order to block the overcurrent flowing through the semiconductor element, it is necessary to provide the semiconductor element with a short-circuit protection circuit.

[0067] The protective short circuit can be configured to include a control unit that determines whether the current I is an overcurrent based on the amount of change (dI / dt) of the current I flowing through the source of the MOSFET and outputs the determination result to the MOSFET gate driver. In this configuration, the control unit compares the amount of change in the current I with a predetermined threshold and detects an overcurrent when the amount of change exceeds the threshold.

[0068] However, the control unit does not determine whether an overcurrent exists during the mask period, which is set so as not to detect an overcurrent during the period when the current I changes sharply immediately after the MOSFET is turned on.

[0069] The threshold value of the short-circuit protection circuit for the first and fourth semiconductor elements Q1, Q4 is set to a value lower than the threshold value of the short-circuit protection circuit for the second and third semiconductor elements Q2, Q3. The threshold value of the short-circuit protection circuit for the fifth and sixth semiconductor elements Q5, Q6 is set to a value lower than the threshold value of the short-circuit protection circuit for the first and fourth semiconductor elements Q1, Q4. This makes it possible to reliably shut off overcurrent flowing through each of the semiconductor elements Q1 to Q6.

[0070] Embodiment 4 FIG. 7 is a circuit diagram showing a configuration of a three-level circuit 50 included in a power conversion device 200 according to the fourth embodiment.

[0071] The three-level circuit 50 shown in Fig. 7 has the same basic configuration as the three-level circuit 50 shown in Fig. 2, but the configurations of the semiconductor elements Q1 to Q6 are different. The semiconductor elements Q1 to Q6 shown in Fig. 7 differ from the semiconductor elements Q1 to Q6 shown in Fig. 2 in that each semiconductor element has multiple switching elements and multiple diodes.

[0072] Specifically, the first semiconductor element Q1 includes three switching elements S11 to S13 connected in parallel, and three diodes D11 to D13 connected in anti-parallel to the three switching elements S11 to S13, respectively.

[0073] The second semiconductor element Q2 includes two switching elements S21 and S22 connected in parallel, and two diodes D21 and D22 connected in anti-parallel to the two switching elements S21 and S22, respectively.

[0074] The third semiconductor element Q3 includes two switching elements S31 and S32 connected in parallel, and two diodes D31 and D32 connected in anti-parallel to the two switching elements S31 and S32, respectively.

[0075] The fourth semiconductor element Q4 includes three switching elements S41 to S43 connected in parallel, and three diodes D41 to D43 connected in anti-parallel to the three switching elements S41 to S43, respectively.

[0076] The fifth semiconductor element Q5 includes four switching elements S51 to S54 connected in parallel, and four diodes D51 to D55 connected in anti-parallel to the four switching elements S51 to S54, respectively.

[0077] The sixth semiconductor element Q6 includes four switching elements S61 to S64 connected in parallel, and four diodes D61 to D64 connected in anti-parallel to the four switching elements S61 to S64, respectively.

[0078] 7, the number of switching elements included in each of the first and fourth semiconductor elements Q1, Q4 is greater than the number of switching elements included in each of the second and third semiconductor elements Q2, Q3. The number of switching elements included in each of the fifth and sixth semiconductor elements Q5, Q6 is greater than the number of switching elements included in each of the first and fourth semiconductor elements. The number of switching elements included in each of the semiconductor elements Q1 to Q6 is not limited to the number shown in FIG. 7, as long as the above-mentioned magnitude relationship is satisfied among the semiconductor elements Q1 to Q6.

[0079] By configuring a single semiconductor element with multiple switching elements connected in parallel, the failure rate of the semiconductor element can be reduced. This is because even if an open circuit failure occurs in one of the multiple switching elements, the remaining normal switching elements can continue to switch the semiconductor element. As the number of switching elements connected in parallel increases, the failure rate of the multiple switching elements as a whole decreases, and the failure rate of the semiconductor element can also be reduced.

[0080] Therefore, in the fourth embodiment, the number of switching elements included in each of the first and fourth semiconductor elements Q1, Q4 is made larger than the number of switching elements included in each of the second and third semiconductor elements Q2, Q3, thereby making the failure rate of the first and fourth semiconductor elements Q1, Q4 larger than the failure rate of the second and third semiconductor elements Q2, Q3. The number of switching elements included in each of the fifth and sixth semiconductor elements Q5, Q6 is made larger than the number of switching elements included in each of the first and fourth semiconductor elements Q1, Q4, thereby making the failure rate of the fifth and sixth semiconductor elements Q5, Q6 larger than the failure rate of the first and fourth semiconductor elements Q1, Q4.

[0081] That is, in the fourth embodiment, a magnitude relationship is established among the numbers of switching elements included in each of the semiconductor elements Q1 to Q6, thereby establishing a magnitude relationship among the cosmic ray tolerances of the semiconductor elements Q1 to Q6. This makes it possible to build a power conversion device that can continue power conversion operation even in the event of an accidental failure due to cosmic rays, using semiconductor elements configured with general-purpose switching elements.

[0082] Embodiment 5. In power conversion device 200 according to the above-described fourth embodiment, power conversion can be performed by switching all of the plurality of switching elements connected in parallel in each of semiconductor elements Q1 to Q6.

[0083] Alternatively, in each of the semiconductor elements Q1 to Q6, the number of switching elements to be switched among the plurality of switching elements connected in parallel may be changed depending on the state of the power conversion device 200.

[0084] In the fifth embodiment, a configuration will be described in which the number of switching elements to be switched on and off in power conversion device 200 according to the fourth embodiment is changed depending on the environment in which power conversion device 200 is placed and the element temperature of each semiconductor element.

[0085] Fig. 8 is a diagram showing the functional configuration of the control circuit 60 of the power conversion device 200. Fig. 8 shows a portion that controls the switching of the fifth semiconductor element Q5, which is included in the control circuit 60. Although not shown, the portions that control the switching of the other semiconductor elements Q1 to Q4, Q6 also have the same configuration as the configuration shown in Fig. 8.

[0086] As shown in FIG. 8, the control circuit 60 includes a GPS (Global Positioning System) 80, an altimeter 81, a computing unit 82, a thermometer 84, a control unit 88, four driving units 90, and a timer 86.

[0087] The GPS 80 measures the latitude and longitude of the current position of the power conversion device 200 and outputs the measured values to the calculator 82. The altimeter 81 measures the altitude of the current position of the power conversion device 200 and outputs the measured value to the calculator 82. For example, if the power conversion device 200 is mounted on an aircraft, the GPS 80 and the altimeter 81 measure the latitude, longitude, and altitude of the aircraft during flight. Note that if the altitude of the power conversion device 200 can be calculated from the measured values of the GPS 80, the altimeter 81 is not necessary.

[0088] The calculator 82 calculates the amount of neutrons at the current position of the power conversion device 200 based on the measured values input from the GPS 80 and the altimeter 81. The amount of neutrons is the number of neutrons per unit time and unit area, and varies depending on the latitude, longitude, and altitude of the current position of the power conversion device 200.

[0089] The neutron spectrum, which depends on altitude, latitude, and longitude, can be calculated using, for example, EXPACS (Excel-based Program for calculating Atmospheric Cosmic-ray Spectrum). EXPACS is a program that can calculate the cosmic ray flux and its energy at any point and time in the atmosphere. The neutron spectrum is data that represents the number of neutrons present per unit time and unit area across a wide energy band. From the neutron spectrum obtained by EXPACS, data can be obtained that shows the dependence of the number of neutrons with a given energy on latitude, longitude, and altitude.

[0090] The thermometer 84 measures the element temperature of the fifth semiconductor element Q5 and outputs the measured value to the control unit 88.

[0091] The amount of neutrons at the current location of the power conversion device 200 is directly related to the failure rate of the fifth semiconductor element Q5 due to SEB. As the amount of neutrons increases, the failure rate of the fifth semiconductor element Q5 increases. For example, as the altitude of the power conversion device 200 increases, the amount of neutrons increases, and therefore the failure rate of the fifth semiconductor element Q5 increases.

[0092] On the other hand, the failure rate of the fifth semiconductor element Q5 correlates with the element temperature. Figure 9 is a graph illustrating the correlation between the element temperature and the failure rate of the fifth semiconductor element Q5. The vertical axis of Figure 9 represents the failure rate, and the horizontal axis represents the applied voltage.

[0093] 9 shows curves L8 and L9 that indicate the relationship between the element temperature and failure rate of the fifth semiconductor element Q5. Curve L8 indicates the relationship between the voltage applied to the fifth semiconductor element Q5 and the failure rate when the element temperature is a first element. Curve L9 indicates the relationship between the voltage applied to the fifth semiconductor element Q5 and the failure rate when the element temperature is a second element. The second element temperature is higher than the first element temperature.

[0094] As shown in Figure 9, when voltage V1 is applied to the fifth semiconductor element Q5, the failure rate at the second element temperature is lower than the failure rate at the first element temperature. This is because, generally, as the element temperature (junction temperature) increases, the withstand voltage of a semiconductor element increases, and as the element temperature (junction temperature) decreases, the withstand voltage of a semiconductor element decreases. Therefore, when the element temperature is high, the withstand voltage increases, and the failure rate of the semiconductor element decreases. Conversely, when the element temperature is low, the withstand voltage decreases, and the failure rate of the semiconductor element increases. Note that this relationship between the element temperature (junction temperature) and failure rate of a semiconductor element remains constant regardless of the altitude of the semiconductor element's current location.

[0095] Returning to Figure 8, the control unit 88 controls the switching of the four switching elements S51 to S54 that make up the fifth semiconductor element Q5 based on the amount of neutrons calculated by the calculator 82 and the measured value of the element temperature of the fifth semiconductor element Q5 by the thermometer 84.

[0096] Specifically, four drive units 90 are provided corresponding to the four switching elements S51 to S54, respectively. Each drive unit 90 generates a gate signal for driving the corresponding switching element in accordance with a control signal provided by the control unit 88.

[0097] The control unit 88 changes the number of switching elements to be switched among the four switching elements S51 to S54 in accordance with the amount of neutrons and the element temperature of the fifth semiconductor element Q5. Fig. 10 is a flowchart showing an example of the procedure for adjusting the number of switching elements to be switched. The series of processes shown in this flowchart is executed by the control circuit 60 at predetermined intervals during operation of the power conversion device 200.

[0098] As shown in FIG. 10, first, the control circuit 60 acquires measurement data of the latitude and longitude of the current position of the power conversion device 200 measured by the GPS 80, and also acquires measurement data of the altitude of the current position of the power conversion device 200 measured by the altimeter 81 (step S01).

[0099] The control circuit 60 calculates the amount of neutrons at the current position of the power conversion device 200 using the acquired measurement data of the latitude, longitude, and altitude of the power conversion device 200 (step S02).

[0100] The control circuit 60 acquires measurement data of the element temperature of the fifth semiconductor element Q5 measured by the thermometer 84 (step S03).

[0101] The control circuit 60 uses the neutron amount calculated in S02 and the measurement data of the element temperature acquired in S03 to determine the number of switching elements to be switched on and off in the fifth semiconductor element Q5.

[0102] Specifically, the control circuit 60 determines whether the element temperature of the fifth semiconductor element Q5 is lower than a predetermined threshold temperature (step S04). If the element temperature of the fifth semiconductor element Q5 is lower than the threshold temperature (YES in S04), the control circuit 60 then determines whether the number of switching elements currently switching is two or more (step S05).

[0103] If the number of switching elements currently being switched is two or more (YES in S05), the control circuit 60 fixes one of the switching elements being switched in the off state, thereby stopping the switching of that switching element. That is, the control circuit 60 reduces the number of switching elements being switched by one (step S06). On the other hand, if the number of switching elements currently being switched is one (NO in S05), the control circuit 60 skips the process of S06 and maintains the number of switching elements being switched.

[0104] On the other hand, if the element temperature of the fifth semiconductor element Q5 is equal to or higher than the threshold temperature in S04 (NO in S04), the control circuit 60 compares the amount of neutrons calculated in S02 with a predetermined threshold (step S07).

[0105] If the amount of neutrons is greater than the threshold (YES in S07), the control circuit 60 then determines whether the number of switching elements currently being switched is less than four (step S08). If the number of switching elements currently being switched is less than four (YES in S08), the control circuit 60 turns on one of the switching elements that is in a stopped state, thereby starting the switching of that switching element. That is, the control circuit 60 increases the number of switching elements to be switched by one (step S09).

[0106] On the other hand, if the amount of neutrons is equal to or less than the threshold value (NO in S07), the control circuit 60 skips the processes of S08 and S09, thereby maintaining the number of switching elements that are currently switched on.

[0107] In the flowchart shown in Figure 10, when the element temperature of the fifth semiconductor element Q5 is lower than the threshold temperature, control is performed to reduce the number of switching elements to be switched. By reducing the number of switching elements to be switched, the current flowing through each switching element increases, increasing the amount of heat generated by the switching element. As a result, the element temperature of the fifth semiconductor element Q5 increases. As the element temperature increases, the withstand voltage of the fifth semiconductor element Q5 increases, reducing the failure rate of the fifth semiconductor element Q5.

[0108] 10, when the amount of neutrons at the current position exceeds a threshold, the number of switching elements to be switched is increased. In this way, when the amount of neutrons increases and the failure rate of each switching element increases, by increasing the number of switching elements to be switched, it is possible to continue switching the fifth semiconductor element Q5 even if an open circuit failure occurs in one of the multiple switching elements.

[0109] In the fifth embodiment, the process of adjusting the number of switching elements in the fifth semiconductor element Q5 has been described, but similar processes can be performed for the sixth semiconductor element Q6, the first and fourth semiconductor elements Q1 and Q4, and the second and third semiconductor elements Q2 and Q3, thereby reducing the failure rate of each of the semiconductor elements Q1 to Q6.

[0110] Embodiment 6 In the above-described fifth embodiment, a process has been described in which switching of some of a plurality of switching elements included in a semiconductor element is stopped in accordance with the element temperature of the semiconductor element included in power conversion device 200 according to the fourth embodiment. In a sixth embodiment, a process will be described in which the switching elements to be stopped from switching are changed at a predetermined cycle in this process.

[0111] 11 is a time chart showing an example of a procedure for changing the switching element to be stopped in the fifth semiconductor element Q5. In FIG. 11, it is assumed that the switching of one of the four switching elements S51 to S54 included in the fifth semiconductor element Q5 is to be stopped.

[0112] The control circuit 60 changes the switching element that stops switching at predetermined time intervals in accordance with the output signal of the timer 86 (see FIG. 8). Specifically, when time T1 starts at time t0, the control circuit 60 switches on switching elements S51, S52, and S53 and stops switching of switching element S54. At time t0, the control circuit 60 starts switching element S53 and then stops switching of switching element S54.

[0113] When time T2 starts at time t1, the control circuit 60 switches on the switching elements S52, S53, and S54 and stops the switching of the switching element S51. At time t1, the control circuit 60 starts the switching element S54 and then stops the switching of the switching element S51.

[0114] When time T3 starts at time t2, the control circuit 60 switches on the switching elements S51, S53, and S54 and stops the switching of the switching element S52. At time t2, the control circuit 60 starts the switching element S51 and then stops the switching of the switching element S52.

[0115] When time T4 starts at time t3, the control circuit 60 switches on the switching elements S51, S52, and S54 and stops the switching of the switching element S53. At time t3, the control circuit 60 starts the switching element S52 and then stops the switching of the switching element S53.

[0116] In this way, in the sixth embodiment, by changing the switching element that stops switching at a predetermined cycle, the continuous operation time of each switching element can be shortened. This reduces the deterioration of the switching elements, thereby reducing the failure rate of each switching element. Furthermore, the operation times of multiple switching elements can be made equal to each other.

[0117] Embodiment 7 FIG. 12 is a circuit diagram showing a configuration of a three-level circuit 50 included in a power conversion device 300 according to the seventh embodiment.

[0118] The three-level circuit 50 shown in Fig. 12 has the same basic configuration as the three-level circuit 50 shown in Fig. 7. The three-level circuit 50 shown in Fig. 12 differs from the three-level circuit 50 shown in Fig. 7 in that it includes power modules M1 and M2.

[0119] Specifically, the power module M1 incorporates second and third semiconductor elements Q2 and Q3. That is, the power module M1 incorporates four switching elements and four diodes (clamp diodes). The power module M1 corresponds to one embodiment of the "first semiconductor module."

[0120] The power module M2 incorporates fifth and sixth semiconductor elements Q5 and Q6. That is, the power module M2 incorporates eight switching elements and eight diodes (freewheeling diodes). The power module M2 corresponds to one embodiment of the "second semiconductor module."

[0121] In this way, in the seventh embodiment, by incorporating multiple semiconductor elements, each having multiple switching elements, into the same power module, the multiple semiconductor elements can be arranged closer to each other than in a configuration in which the multiple semiconductor elements are individually mounted. This allows for space saving in the mounting. Furthermore, the power conversion device 300 can be made smaller.

[0122] Furthermore, when attaching a heat sink to cool each semiconductor element, it is sufficient to attach the heat sink to the power module, which improves the workability of assembly. Also, the power module is easily available.

[0123] It should be noted that, with regard to the above-mentioned embodiments, it has been planned from the beginning of the application that the configurations described in the embodiments may be appropriately combined, including combinations not mentioned in the specification, within the scope that does not cause inconvenience or contradiction.

[0124] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0125] 10 DC positive bus, 20 DC neutral bus, 30 DC negative bus, 40, 40u, 40v, 40w AC line, 50 3-level circuit, 50u U-phase arm, 50v V-phase arm, 50w W-phase arm, 60 control circuit, 61 CPU, 62 RAM, 63 ROM, 64 I / F device, 65 storage device, 66 communication bus, 80 GPS, 81 altimeter, 82 calculator, 84 thermometer, 86 timer, 88 control unit, 90 drive unit, 100, 200, 300 power conversion device, 101 DC power supply, 111, 112 capacitor, 180 motor, Q1 to Q6 Semiconductor elements: S1 to S5, S11 to S13, S21, S22, S31, S32, S41 to S43, S51 to S54, S61 to S64; switching elements: D1 to D5, D11 to D13, D21, D22, D31, D32, D41 to D43, D51 to D54, D61 to D64; diodes: M1, M2; power modules.

Claims

1. A power conversion device that is provided between a DC positive bus, a DC negative bus, and a DC neutral bus and an AC line, and performs power conversion between DC power and AC power, a first semiconductor element having a first electrode connected to the DC positive bus; a second semiconductor element having a first electrode connected to the second electrode of the first semiconductor element and a second electrode connected to the DC neutral bus; a third semiconductor element having a first electrode connected to the DC neutral bus; a fourth semiconductor element having a first electrode connected to the third electrode of the third semiconductor element and a second electrode connected to the DC negative bus; a fifth semiconductor element having a first electrode connected to the first electrode of the second semiconductor element and a second electrode connected to the AC line; a sixth semiconductor element having a first electrode connected to the AC line and a second electrode connected to the second electrode of the third semiconductor element; each of the first to sixth semiconductor elements includes at least one semiconductor switching element and at least one diode connected in anti-parallel to the at least one semiconductor switching element; the first and fourth semiconductor elements have higher cosmic ray resistance than the second and third semiconductor elements; The fifth and sixth semiconductor elements have a higher breakdown resistance than the first and fourth semiconductor elements.

2. the withstand voltages of the first and fourth semiconductor elements are greater than the withstand voltages of the second and third semiconductor elements; 2. The power conversion device according to claim 1, wherein the fifth and sixth semiconductor elements have a higher dielectric strength than the first and fourth semiconductor elements.

3. the element areas of the first and fourth semiconductor elements are smaller than the element areas of the second and third semiconductor elements; 2. The power conversion device according to claim 1, wherein the fifth and sixth semiconductor elements have element areas smaller than the element areas of the first and fourth semiconductor elements.

4. the at least one semiconductor switching element includes a plurality of semiconductor switching elements connected in parallel between a first electrode and a second electrode of each semiconductor switching element; the at least one diode includes a plurality of diodes connected in anti-parallel to the plurality of semiconductor switching elements, respectively; the number of semiconductor switching elements included in the first and fourth semiconductor elements is greater than the number of semiconductor switching elements included in the second and third semiconductor elements; 2. The power conversion device according to claim 1, wherein the number of semiconductor switching elements included in the fifth and sixth semiconductor elements is greater than the number of semiconductor switching elements included in the first and fourth semiconductor elements.

5. a control circuit that drives the first to sixth semiconductor elements to control the power conversion; a temperature detector that detects the temperature of each of the first to sixth semiconductor devices during the power conversion; 5. The power conversion device according to claim 4, wherein the control circuit changes the number of semiconductor switching elements to be switched among the plurality of semiconductor switching elements in each of the first to sixth semiconductor elements, depending on the value of the element temperature detected by the temperature detector.

6. 6. The power conversion device according to claim 5, wherein the control circuit reduces the number of semiconductor switching elements to be switched by stopping some of the semiconductor switching elements that are being switched when the detected value of the element temperature is lower than a predetermined threshold temperature.

7. a control circuit that drives the first to sixth semiconductor elements to control the power conversion; a position detector for detecting position information indicating the altitude, latitude, and longitude of the power conversion device, 5. The power conversion device according to claim 4, wherein the control circuit changes the number of semiconductor switching elements to be switched among the plurality of semiconductor switching elements in each of the first to sixth semiconductor elements, depending on the position information detected by the position detector.

8. 8. The power conversion device according to claim 7, wherein the control circuit calculates a failure rate of the power conversion device due to cosmic rays using the position information, and when the calculated failure rate is higher than a predetermined threshold, activates semiconductor switching elements that are in a stopped state, thereby increasing the number of semiconductor switching elements to be switched.

9. The power conversion device according to claim 6 or 8, wherein the control circuit changes the semiconductor switching elements that stop switching at a predetermined cycle.

10. a first semiconductor module; a second semiconductor module; the first semiconductor module incorporates the second and third semiconductor elements; The power conversion device according to claim 4 , wherein the second semiconductor module incorporates the fifth and sixth semiconductor elements.

11. The power conversion device is mounted on an aircraft, a control circuit that drives the first to sixth semiconductor elements to control the power conversion; a temperature detector that detects the element temperatures of the first to sixth semiconductor elements during flight of the aircraft; a position detector for detecting position information indicating the altitude, latitude, and longitude of the aircraft; 5. The power conversion device according to claim 4, wherein, during flight of the aircraft, the control circuit changes the number of semiconductor switching elements to be switched among the plurality of semiconductor switching elements in accordance with at least one of a detection value of the element temperature by the temperature detector and the position information detected by the position detector.

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