Machine learning techniques for improving video conferencing applications

Abstract

To provide a system, a process and a technology that automatically detect and enlarge a participant who is uttering among a plurality of participants at one side in a video conference.SOLUTION: According to at least one embodiment, a participant who is uttering is identified using one or a plurality of heuristics and / or one or a plurality of neural networks.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] At least one embodiment relates to using machine learning techniques to improve user experience in video conferencing applications. For example, at least one embodiment relates to a processor or computing system used to automatically detect and augment a speaking participant according to various novel techniques described herein. [Background technology]

[0002] Videoconferencing is an effective means of communication between conference participants who may be physically remote from one another, or a mix of co-located and remote participants. In a typical videoconferencing application, multiple, potentially infinite, presences can simultaneously participate in a virtual videoconference or meeting. Each presence can represent a single attendee / participant, such as when a presence joins a videoconference using a personal webcam and personal computer. Alternatively, one or more presences can represent multiple attendees / participants, such as when a single presence includes multiple attendees in the same physical location (e.g., a meeting room or conference hall). A common use case involves a videoconference attended by a mix of individuals and groups of individuals. In a typical videoconferencing application, each participant is presented with a display that combines video streams (if available) from participants in the same videoconference in the same graphical user interface, often in a montage or picture-in-picture arrangement. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (eg, Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard) Summary of the Invention [Problem to be solved by the invention]

[0004] In scenarios where one or more groups of attendees join a video conference using the same presence, such as when a single presence includes a crowded meeting room or a large audience, the same single webcam and microphone array(s) may be used to capture video and audio from the physical meeting room and stream it to the other participants in the video conference. However, depending on the size of the group and the proximity of each individual to the webcam, each person's face may appear in a small display when streamed to the other conference participants. This can make it difficult to distinguish facial expressions and to understand who is actually speaking. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 illustrates an example of a video conferencing system configured to implement a video conference between a plurality of first conference participants and one or more second conference participants, according to at least one embodiment. [Figure 2] 2 illustrates an exemplary video segment including multiple frames each including an image region identified by the video conferencing system of FIG. 1, according to at least one embodiment. [Figure 3]FIG. 3 illustrates an exemplary set of facial landmarks determined for one of the image regions of FIG. 2, according to at least one embodiment. [Figure 4] FIG. 1 illustrates a user interface, according to at least one embodiment, that is displayed to a second conference participant(s) and includes a modified video segment in which the face of a first conference participant who is speaking is zoomed in on. [Figure 5] 2 is a flow diagram of a method that may be implemented, at least in part, by the video conferencing system of FIG. 1, according to at least one embodiment. [Figure 6] 2 is a block diagram illustrating exemplary components of a client application and / or a server application executing on at least one computing device of the videoconferencing system of FIG. 1, according to at least one embodiment. [Figure 7A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 7B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 8] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 9] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 10A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 10B] FIG. 10B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 10C] FIG. 10B is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 10D] 10B illustrates a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 11]FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 12] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 13] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 15F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 16] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 18A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 18B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 19] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 20A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 20B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 20C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 20D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 21] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 23] FIG. 1 is a block diagram illustrating a processor microarchitecture for a processor, according to at least one embodiment. [Figure 24] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 25] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 26] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 27] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 28] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 29] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor, according to at least one embodiment. [Figure 30] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 31A]FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 31B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 32] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 33] FIG. 1 illustrates a general processing cluster (“GPC”), according to at least one embodiment. [Figure 34] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 35] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 36] FIG. 1 illustrates an exemplary data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 37] FIG. 1 is a system diagram for an exemplary system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 38A] FIG. 1 is a data flow diagram for a process for training a machine learning model, according to at least one embodiment. [Figure 38B] FIG. 1 illustrates an exemplary diagram of a client-server architecture for extending an annotation tool with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] FIG. 1 illustrates an example video conferencing system 100 configured to implement a video conference between multiple first conference participants 102 and one or more second conference participants 104. The first conference participants 102 may be located at the same physical location and share a common video capture device 106 (e.g., a web camera). For ease of illustration, FIG. 1 illustrates the first conference participants 102 as including first conference participants 102A and 102B, but the first conference participants 102 may include any number of conference participants. Also, for ease of illustration, FIG. 1 illustrates the second conference participants 104 as including second conference participants 104A and 104B, but the second conference participants 104 may include any number of conference participants. The second conference participants 104 need not be located at the same physical location or share a common video capture device. In the illustrated example, second conference participants 104A and 104B are located remotely from each other and use video capture devices 108A and 108B, respectively. First conference participant 102 may be located remotely from second conference participant 104, although this is not a requirement. Each of video capture devices 106 and 108 may be implemented as a physical hardware camera and / or a virtual camera. Each of video capture devices 106 and 108 may be implemented as one or more video cameras, one or more web cameras, one or more ring cameras, etc. Each of video capture devices 106 and 108 may include one or more microphones configured to capture sound along with images.

[0007] Video capture device 106 is connected to first computing device 112 and configured to transmit video captured by video capture device 106 to first computing device 112. First computing device 112 is configured to process the captured video and transmit the first processed video signal over network 110 (e.g., the Internet) to second computing device(s) 114 operated by second conference participant 104. For example, in the illustrated embodiment, second conference participants 104A and 104B operate second computing devices 114A and 114B, respectively. Video capture device 108A is connected to second computing device 114A and configured to transmit video captured by video capture device 108A to second computing device 114A. Similarly, video capture device 108B is connected to second computing device 114B and configured to transmit video captured by video capture device 108B to second computing device 114B. Each of second computing device(s) 114B is configured to process the captured video and transmit a second processed video signal over network 110 to first computing device 112 operated by first conference participant 102.

[0008] The first computing device 112 is configured to receive the second processed video signal transmitted by each of the second computing devices 114 and generate a first user interface 122. A display device 116 is connected to the first computing device 112 and configured to display the first user interface 122 to the first conference participant 102. By way of non-limiting example, in the illustrated embodiment, the first user interface 122 displays the second processed video signals received from the second computing devices 114A and 114B such that the first conference participant 102 can view the second conference participants 104A and 104B, respectively, during the video conference (e.g., side-by-side). Optionally, the first user interface 122 may display video captured by the video capture device 106 and / or video processed by the first computing device 112 to the first conference participant 102. In at least one embodiment, display device 116 may be implemented as a computer monitor, a projector, etc. In at least one embodiment, display device 116 may include one or more speakers, one or more microphones, and / or video capture device 106.

[0009] Each of the second computing device(s) 114 is configured to receive the first processed video signal transmitted by the first computing device 112 and generate a second user interface 124. A display device 118 is connected to each of the second computing device(s) 114. The display device(s) 118 are configured to display the second user interface 124 to the second conference participants 104A and 104B. By way of non-limiting example, in the illustrated embodiment, the second computing devices 114A and 114B are connected to display devices 118A and 118B, respectively, which display the second user interface 124 to the second conference participants 104A and 104B, respectively. The second user interface 124 displays the first processed video signal received from the first computing device 112 so that the second conference participants 104A and 104B can view the first conference participant 102 during the video conference. Optionally, the second user interface 124 displayed by a particular one of the second computing devices 114 may display video captured by the particular second computing device, video processed by the particular second computing device, and / or second processed video signal(s) received from one or more of the other second computing device(s) 114.

[0010] In at least one embodiment, each of display device(s) 118 may be implemented as a computer monitor, a projector, etc. In at least one embodiment, display device(s) 118 may each include one or more speakers, one or more microphones, and / or one or more of video capture device(s) 108.

[0011] In some embodiments, videoconferencing may be implemented over network 110 by videoconferencing server application 130 running on one or more server computing devices 132. Alternatively, first computing device 112 and second computing device 114 may be configured to implement videoconferencing without the use of such an application.

[0012] Each of the first computing device 112 and the second computing device 114 is configured to implement a videoconferencing client application 134. When executed by the first computing device 112, the videoconferencing client application 134 is configured to receive video captured by the video capture device 106, process the captured video to produce a first processed video signal, and transmit the first processed video signal to each of the second computing device(s) 114. Similarly, when executed by one of the second computing device(s) 114, the videoconferencing client application 134 is configured to receive video captured by one of the video capture device(s) 108, process the captured video to produce a second processed video signal, and transmit the second processed video signal to the other of the first computing device 112 and the second computing device(s) 114.

[0013] 2 is a diagram of an example video segment 200 including multiple frames 202 and 204. As illustrated in FIG. 2, a first frame 202 occurs before a second frame 204 in the video segment 200. Frames 202 and 204 may be key frames (“K frames”) that do not reference previous or subsequent frames, although this is not a requirement. For ease of explanation, video segment 200 is described as having been captured by video capture device 106. However, video segment 200 may have been captured by any of the video capture devices of system 100 (see FIG. 1).

[0014] As described above, the client application 134 (see FIG. 1 ) executing on the first computing device 112 is configured to receive and process the video segment 200. This processing may include modifying the video segment 200 to include one or more enlarged image regions before transmitting the modified video segment to the second computing device(s) 114. Alternatively, the client application 134 executing on the first computing device 112 may identify speech image regions and transmit both the first processed video segment (but not modified to include the enlarged image regions) and the identification of those speech image regions to the second computing device(s) 114, which may modify the identified image regions in the first processed video segment to create a second processed video segment (and modified to include the enlarged image regions). In such an embodiment, each of the second computing devices 114 may receive user input indicating an amount of magnification, and the client application 134 may magnify the identified image region by that amount of magnification. In this manner, second processed video segments created by different ones of the second computing devices 114 may include different amounts of magnification.

[0015] As another non-limiting example, a client application 134 executing on a first computing device 112 may send a first processed video segment (but not modified to include the enlarged image region) to a client application 134 executing on a second computing device 114, which may modify the first processed video segment (e.g., video segment 200) to include the enlarged image region after receiving the first processed video segment from the first computing device 112. In such an example, each of the second computing devices 114 may receive user input indicating an amount of enlargement, and the client application 134 executing on the second computing device may enlarge the identified image region by that amount of enlargement. In this manner, second processed video segments created by different ones of the second computing devices 114 may include different amounts of enlargement.

[0016] Alternatively or additionally, server application 130 (see FIG. 1) may be configured to modify video segment 200. For example, client application 134 executing on first computing device 112 may send a first processed video segment (but not modified to include the enlarged image region) to server application 130, which may modify identified image regions in the first processed video segment to create a server-processed video segment (and modified to include the enlarged image region). As another non-limiting example, client application 134 executing on first computing device 112 may identify speech image regions and send both the first processed video segment and the identification of those speech image regions to server application 130, which may modify the identified image regions in the first processed video segment to create a server-processed video segment. The server application 130 may then transmit the server-processed video segments to the second computing device(s) 114. In such an embodiment, each of the second computing device(s) 114 may receive user input indicating an amount of magnification and transmit the amount of magnification to the server computing device 132. For each of the second computing device(s) 114, the server application 130 may magnify the identified image region by the amount of magnification received from the second computing device. In this manner, server-processed video segments received by different ones of the second computing device(s) 114 may include different amounts of magnification.

[0017] For ease of explanation, the client application 134 running on the first computing device 112 is described as modifying the video signal before transmitting it to the second computing device(s) 114, although, as noted above, this functionality may be provided by the server application 130 or may be performed by the receiver of the video segment 200 after it has been transmitted (e.g., in the first processed video segment).

[0018] Modifying the video segment 200 includes detecting image regions depicting faces 222A and 222B of the first conference participants 102A and 102B, respectively. As a non-limiting example, the client application 134 may detect image regions 212A and 212B in the first frame 202 and detect image regions 214A and 214B in the second frame 204. The image regions 212A-214B may each be defined by a bounding box 224. The client application 134 may determine that the image regions 212A and 214A depict the same face (e.g., face 222A) in both the frame 202 and the frame 204. Additionally, the client application 134 may determine that the image regions 212B and 214B depict the same face (e.g., face 222B) in both the frame 202 and the frame 204. Matching image regions depicting the same face in different frames may be achieved using image analysis techniques, face recognition techniques, and the like.

[0019] After detecting image regions 212A-214B, client application 134 detects facial landmarks 302 (see FIG. 3) in each of image regions 212A-214B. FIG. 3 shows an exemplary set of facial landmarks calculated or determined for image region 214B. Client application 134 may determine the same facial landmarks for image region 212A (see FIG. 2), which also depicts face 222B. Additionally, client application 134 may determine the same or similar facial landmarks for image regions 212A and 214A, which depict face 222A. For ease of illustration, in FIG. 3, facial landmarks 302 are depicted by solid black circles superimposed on image region 214B. However, facial landmarks 302 need not be visualized in this manner. Facial landmarks 302 may correspond to anatomical facial features, such as the upper lip, lower lip, nasolabial fold, jawline, eyes, eyebrows, nose, etc. As non-limiting examples, a face may include 64 or 104 landmarks. However, facial landmarks 302 may include any number of facial landmarks.

[0020] After facial landmarks 302 are determined in image regions 212A-214B, client application 134 determines whether the position of facial landmarks 302 in two or more of frames 202 and 204 indicates that either of faces 222A and 222B is speaking. For example, client application 134 may determine that the position of facial landmarks 302 corresponding to lips 304 has moved a sufficient amount to indicate that face 222B is speaking. When client application 134 determines that at least one of faces 222A and 222B is speaking, client application 134 selects image region(s) in which the face is speaking (e.g., image region 214B). Client application 134 then modifies the frame(s) in which the selected image region(s) were found by magnifying or zooming the selected image region(s) by a scaling factor (e.g., 1.3, 1.5, etc.). Optionally, the client application 134 may expand the selected image region(s) to fill the frame(s) in which the selected image region(s) are found.

[0021] The client application 134 then provides the modified video segment to the client application 134 running on each of the second computing device(s) 114. When neither of the first conference participants 102A nor 102B is speaking, the client application 134 may refrain from modifying the video segment and instead simply send the unmodified video segment to the client application 134 running on each of the second computing device(s) 114. Each of the second computing device(s) 114 generates a second user interface 124 and displays it to the second conference participant(s) 104. Thus, for the second conference participant(s) 104 viewing the second user interface 124, the speaker's face 222B is enlarged in (e.g., fills) the frame in which the first conference participant 102B is speaking. 4 shows one of the display devices 118 displaying the second user interface 124, which includes a modified video segment in which the face 222B of the second conference participant 102B is zoomed in. This may make the face 222B of the first conference participant 102B more visible, which may make it easier for the first conference participant 104 to tell which of the first conference participants 102B is speaking. It may also make it easier to observe facial expressions on the face 222B.

[0022] In an embodiment in which the video segment 200 is modified by a particular one of the second computing devices 114 after it is received from the first computing device 112, the particular second computing device modifies the video segment 200, generates a second user interface 124, and displays the second user interface 124 to the second conference participant operating the particular second computing device. Thus, to the second conference participant viewing the second user interface 124, the speaker's face 222B appears enlarged (e.g., fills the frame) within the frame in which the first conference participant 102B is speaking. For example, FIG. 4 illustrates one of the display devices 118 displaying the second user interface 124, including a modified video segment in which the face 222B of the second conference participant 102B is enlarged.

[0023] Client application 134 and / or server application 130 may be configured to process video segments, such as video segment 200, of a live video conference in real time. Client application 134 and / or server application 130 may be configured to perform this processing using conventional graphics processing units (“GPUs”) and / or similar hardware.

[0024] 5 is a flow diagram of a method 500 that may be implemented, at least in part, by system 100 (see FIG. 1). For example, method 500 may be implemented by client application 134 (see FIG. 1) when executed by either first computing device 112 or second computing device 114 (see FIG. 1), and / or by server application 130 (see FIG. 1) when executed by server computing device(s) 132 (see FIG. 1). For ease of explanation, method 500 is described as being implemented by client application 134 running on first computing device 112.

[0025] The method 500 is configured to enhance a video conference in which a first conference participant 102 (see FIG. 1 ) is co-located in a common physical space (e.g., a conference room) and communicates with one or more second conference participants 104 over a network 110 (see FIG. 1 ). For example, with reference to FIG. 1 , the first conference participants 102 may share a common video capture device 106 (e.g., a web camera). The method 500 (see FIG. 5 ) enhances the video conference for one or more second conference participants 104 by zooming in on one of the first conference participants 102 when that conference participant is speaking. For example, FIG. 4 illustrates one of the display devices 118 displaying a second user interface 124 including a modified video segment in which the face 222B of the second conference participant 102B is zoomed in. Thus, the system 100 (see FIG. 1) presents a magnified image of the speaking first conference participant 102B to the second conference participant(s) 104.

[0026] 5, in a first block 502, client application 134 (see FIG. 1) receives a video segment including a series of frames each depicting a first conference participant 102 (see FIG. 1). For example, referring to FIG. 2, client application 134 (see FIG. 1) may receive video segment 200 including frames 202 and 204 depicting first conference participants 102A and 102B, respectively. Client application 134 may store the newly received frames in a buffer.

[0027] Then, in block 504 (see FIG. 5 ), for each of at least a portion of the frames, the client application 134 detects image regions depicting the face of the first conference participant 102. For example, in FIG. 2 , the client application 134 may detect image regions 212A-214B. Further, the client application 134 may determine that image region 212A and image region 214A depict the same face 222A, and that image region 212B and image region 214B depict the same face 222B. By way of non-limiting example, the image regions may be detected using machine learning techniques, such as face detection developed by the Drive IX team at NVIDIA Corporation, another deep learning model, or the like. As described above, image regions in different frames depicting the same face may be matched using image analysis techniques, facial recognition techniques, or the like.

[0028] Next, in block 506 (see FIG. 5), the client application 134 (see FIG. 1) determines a predetermined number (e.g., 68, 126, etc.) of facial landmarks or a set of facial landmarks in each of the image regions. For example, in FIG. 3, the client application 134 (see FIG. 1) detected facial landmark 302. At least some of the facial landmarks correspond to parts of the face that may move when a person speaks. For example, some of the facial landmarks may correspond to the upper lip, lower lip, nasolabial fold, jawline, eyes, eyebrows, nose, etc. As a non-limiting example, the facial landmarks may be detected using machine learning techniques, such as facial landmark detection developed by NVIDIA Corporation, another deep learning model.

[0029] At decision block 508, the client application 134 (see FIG. 1) determines whether one of the first conference participants 102A and 102B (see FIG. 1) is speaking based on the set of facial landmarks. For example, the client application 134 may identify image regions corresponding to the first conference participant 102B who is speaking based on the relative movement of one or more of the facial landmarks between frames. For example, those facial landmarks corresponding to the lips 304 and / or mouth move between at least two of the frames when the first conference participant 102B is speaking. The movement of the facial landmarks may be detected using one or more heuristics, a binary speech classifier, machine learning techniques, etc.

[0030] In an embodiment using heuristics, the positions of the facial landmarks representing the upper and lower lips may be used to determine the distance between the lips 304. This distance may be used to determine whether a particular one of the first conference participants is speaking. Additionally, the rate at which the facial landmarks 302 move between successive frames may also help identify the speaker. For example, the client application 134 may identify an image region as depicting a speaker when the rate of movement determined between successive frames exceeds a threshold.

[0031] For example, the client application 134 (see FIG. 1 ) may determine that the first conference participant 102B is speaking by applying a set of heuristics to facial landmarks 302, referred to as lip landmarks 306, among the facial landmarks 302 that correspond to the lips 304. By way of non-limiting example, approximately 10-20 of the facial landmarks 302 may be considered lip landmarks 306. The set of heuristics may evaluate the video segment, one frame at a time, and determine the rate of movement of the lip landmark 306 corresponding to the upper lip relative to the lip landmark 306 corresponding to the lower lip. The set of heuristics may determine the change in distance between the lip landmark 306 among the lip landmarks 306 positioned along the bottom of the upper lip and the lip landmark 306 among the lip landmarks 306 positioned along the top of the lower lip. As another non-limiting example, the set of heuristics may determine that the first conference participant 102B is speaking when the lip landmark 306 of the lip landmarks 306 corresponding to the upper lip is at least a predetermined distance from the lip landmark 306 of the lip landmarks 306 corresponding to the lower lip in one or more of the image regions depicting the first conference participant 102B. Similarly, the set of heuristics may determine that the first conference participant 102A (see FIGS. 1 and 2) is not speaking when the lip landmark 306 of the lip landmarks 306 corresponding to the upper lip is less than a predetermined distance from the lip landmark 306 of the lip landmarks 306 corresponding to the lower lip in one or more of the image regions depicting the first conference participant 102A.

[0032] When the first conference participant 102B moves his or her head, the shape of the face 122B changes, which also changes the positions of the facial landmarks. The set of heuristics may take head orientation or head pose into account when determining whether the first conference participant 102B is speaking. For example, the set of heuristics may first determine the head pose and then identify one or more heuristics to use with that particular head pose.

[0033] As another non-limiting example, the client application 134 (see FIG. 1 ) may use optical flow to determine which of the first conference participants 102A and 102B is speaking. Using this technique, the client application 134 (see FIG. 1 ) uses the positions of lip landmarks 306 in two or more consecutive frames (e.g., frames 202 and 204) to create a flow vector for each of the lip landmarks 306 in the consecutive frames. The client application 134 (see FIG. 1 ) then uses the flow vectors to determine whether there was lip activity. For example, a binary classifier may be trained to detect whether the flow vector indicates there was lip activity or there was no lip activity. Alternatively, one or more thresholds may be used to determine whether the flow vector indicates there was lip activity or there was no lip activity. When the client application 134 (see FIG. 1) determines that there was lip activity, the client application 134 (see FIG. 1) classifies the lip activity and / or flow vector as indicating that speaking activity occurred or that non-speech activity (e.g., laughing, yawning, etc.) occurred. For example, a binary classifier may be trained to detect whether the lip activity and / or flow vector indicates that speaking activity or non-speech activity occurred. Whichever of the first conference participants 102A and 102B is associated with the speaking activity is determined to be speaking. Optionally, the intermediate step of determining whether there was lip activity may be omitted. In such an embodiment, the client application 134 may classify the flow vector as indicating that speaking activity or non-speech activity occurred.Whichever of the first conference participants 102A and 102B is associated with the speech activity is determined to be speaking. By way of non-limiting example, each of the binary classifiers may be implemented as a decision tree, a k-nearest neighbor classifier, a random forest, a Bayesian network (e.g., a naive Bayes classifier), a support vector machine, a neural network, a logistic regression, a probit model, etc.

[0034] As another non-limiting example, a voice classifier may be used instead of or in addition to a set of heuristics to detect which of the first conference participants 102A and 102B is speaking. The voice classifier is a binary classifier that may be trained to detect which image regions contain speaking conference participants and which do not. The voice classifier may be implemented using neural networks or other machine learning techniques.

[0035] Optionally, the client application 134 (see FIG. 1 ) may consider sound when identifying which of the first conference participants 102 is speaking. For example, the sound of each of the first conference participants 102A and 102B's voices may be associated with image regions depicting the first conference participants 102A and 102B. Then, when the client application 134 detects a particular voice associated with the first conference participant 102B, the client application 134 may determine that the first conference participant 102B is speaking. Such voice detection may be combined with image-based techniques to improve speaker detection. For example, an image-based technique may be used to detect when the first conference participant 102B is speaking, and the sound of the voice recorded at that time may be correlated with the image region depicting the first conference participant 102B. After this is done, whenever the same voice is detected, the client application 134 may determine that the first conference participant 102B is speaking. Such use of sound may help the client application 134 distinguish non-speech movements, such as laughing, yawning, etc., from actual speech movements and may help avoid false detection of non-speaking conference participants. Additionally, the client application 134 may use sound to determine when different ones of the first conference participants 102B begin speaking.

[0036] Optionally, the detected sound direction may be used to help associate sounds with their source. For example, in FIG. 2, the first conference participant 102B is positioned to the right of the first conference participant 102A from the perspective of the video capture device 106. Thus, sounds originating on the left side may be associated with the first conference participant 102A, and sounds originating on the right side may be associated with the first conference participant 102B. Furthermore, such sound direction information may be used to improve the efficiency of the client application 134. For example, when the client application 134 detects sounds originating from the left side, the client application 134 may refrain from processing those image regions positioned on the right side, and vice versa. As a non-limiting example, sound direction may be determined (e.g., triangulation) using multiple microphones.

[0037] To evaluate multiple frames, the client application 134 may store a predetermined number of frames in a buffer. Such a buffer allows the client application 134 to implement inertia that prevents rapid switching between frames. For example, the client application 134 may switch to a different one of the first conference participants 102 only when it determines that that participant has spoken for at least a predetermined number (e.g., two, three, etc.) of consecutive frames.

[0038] 5, the determination at decision block 508 is "yes" when the client application 134 determines that one of the first conference participants 102 is speaking. Otherwise, the determination at decision block 508 is "no."

[0039] If the determination at decision block 508 is "no," the client application 134 returns to block 502 to receive additional frames and / or another video segment. As described above, the newly received frames may be stored in a buffer.

[0040] If the determination at decision block 508 is "yes," then at block 510 the client application 134 selects those image regions in the frames in which the first conference participant 102B is speaking that depict the face 222B of the first conference participant 102B speaking.

[0041] Then, at block 512, the client application 134 enlarges the image region selected at block 510 to create a modified video segment. Optionally, when the second computing device(s) 114 or the server computing device(s) 132 are performing method 500 after receiving the video segment from the first computing device 112, one or more of the second conference participants 104 may provide the amount of scaling by which the image region is enlarged (e.g., 1.3 times or 1.5 times the original size of the image region). In this manner, the client application 134 and / or the server application 130 may enlarge the image region by different amounts for different second conference participants 104. As another non-limiting example, the client application 134 may upscale the image region to the image resolution of the frame. Optionally, the client application 134 may modify the video segment by cropping an image region depicting the first conference participant 102B speaking from the frame in which the first conference participant 102B is speaking (e.g., along a bounding box 224 that surrounds the image region), upscaling the cropped image region, and replacing the frame with the upscaled image region. The client application 134 may upscale the image region using one or more machine learning techniques (e.g., deep neural learning or deep neural network(s)). For example, the client application 134 may upscale a lower-resolution image region to a higher resolution (e.g., the resolution of frames 202 and 204) using one or more super-resolution imaging techniques. As a non-limiting example, the client application 134 may include a face enhancement super-resolution deep learning model configured to zoom the image region selected in block 510 and improve the resulting image quality of the modified video segment.

[0042] In optional block 514, the client application 134 may transmit the modified video segment to the second computing device(s) 114. Alternatively, if the second computing device(s) 114 are performing the method 500, block 514 may be omitted.

[0043] Next, in block 516, the client application 134 executing on each of the second computing device(s) 114 displays the modified video segment in the second user interface 124. The client application 134 then returns to block 502 to receive additional frames and / or another video segment. As described above, the newly received frames may be stored in a buffer.

[0044] 6 is a block diagram illustrating exemplary components of client application 134 and / or server application 130 (see FIG. 1). In the embodiment shown in FIG. 6, client application 134 and / or server application 130 includes a face detection module 620, a facial landmark network 622, a speaker detector module 624, and a video editing module 626. In at least one embodiment, modules 620, 622, 624, and 626 each include computer-executable instructions that are executable by a computing device, such as one or more of computing devices 112, 114, and 132 (see FIG. 1). In at least one embodiment, modules 620, 622, 624, and 626 each include one or more routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.

[0045] As described above, a video capture device (e.g., video capture device 106) captures live video (e.g., video segment 200 shown in FIG. 2) of at least a portion 650 of a video conference including first conference participant 102 (see FIG. 1). The face detection module 620 receives the live video segment from the video capture device. In other words, with reference to FIG. 5, the face detection module 620 may implement block 502 of method 500. For example, with reference to FIG. 6, the face detection module 620 may receive the video segment one frame at a time and buffer a predetermined number of frames.

[0046] Then, for each of at least a portion of the frames, the face detection module 620 detects an image region depicting the face of the first conference participant 102 (see FIG. 1 ). In other words, with reference to FIG. 5, the face detection module 620 may implement block 504 of method 500. With reference to FIG. 6, the face detection module 620 may include any software module or set of instructions capable of locating image regions containing faces (e.g., faces 222A and 222B shown in FIG. 2 ) within an image (e.g., frames 202 and 204 shown in FIG. 2 ) using any method or process. For example, the face detection module 620 may include known computer vision-based face detection processes that detect faces without using neural networks, such as edge detection methods, feature retrieval methods, probabilistic face models, graph matching, histogram of oriented gradients (“HOG”) fed into a classifier (e.g., support vector machines and HaarCascade classifiers). As another non-limiting example, the face detection module 620 may include neural network-based face recognition methods, such as those employing deep neural network (“DNN”) face recognition methods, as well as any others.

[0047] Image regions (e.g., image regions 212A-214B shown in FIG. 2) may then be cropped from the image and input into facial landmark network 622. Each of the image regions may have the same aspect ratio as the image from which they were cropped (e.g., frames 202 and 204 shown in FIG. 2), although this is not a requirement.

[0048] The facial landmark network 622 determines facial landmarks in each image region and calculates or determines a corresponding confidence value for each facial landmark. In other words, with reference to FIG. 5, the facial landmark network 622 may implement block 506 of method 500. With reference to FIG. 6, within each image region, each facial landmark includes the location (e.g., two-dimensional location) of a particular facial feature depicted in the image region. Thus, each facial landmark may be characterized as being a point or set of coordinates optionally labeled with or corresponding to a particular facial feature and assigned a corresponding confidence value.

[0049] Each confidence value corresponds to a detection probability for the corresponding facial landmark and represents the likelihood that the facial landmark is actually located at the particular facial feature to which it corresponds or which it represents. Because greater occlusion (or lower visibility) of the corresponding facial feature corresponds to a lower likelihood of correctly placing the facial landmark at that facial feature, the probability or confidence value assigned to a facial landmark may indicate a level of occlusion for that facial feature. As an illustration, when the facial landmark network 622 employs a classifier to determine the location of a facial landmark, the confidence value may be (or may correspond to) a confidence score generated by the classifier when determining the landmark classification.

[0050] The facial landmark network 622 may be implemented as any machine learning network, such as any one or more machine learning models, capable of determining facial landmarks within an image region containing a face. Such networks may include machine learning models built according to a holistic method for representing global facial appearance and shape information, models built according to a constrained local model method that builds local appearance models in addition to utilizing a global shape model, generative networks, CNNs, and regression-based models that determine landmark locations according to facial shape and appearance information. The models may be constructed using any architecture and method suitable for determining facial landmarks from an image region containing a face. For example, a CNN-based facial landmark network may be structured using any convolutional kernel and pooling layers suitable for extracting facial features that can be used to determine facial landmarks.

[0051] As described above, for each image region (e.g., image region 214B shown in FIGS. 2 and 3), the output of the facial landmark network 622 may include a set of facial landmarks and a confidence value for each facial landmark. These outputs are sent to the speaker detector module 624 to serve as inputs. Referring to FIG. 5, the speaker detector module 624 may implement decision blocks 508 and 510 of the method 500.

[0052] 6, speaker detector module 624 may include any number and types of networks, models, other software modules, etc. configured to identify speakers based at least in part on facial landmarks and confidence values. By way of non-limiting example, such networks may include a head pose network 628 configured to determine a head pose of a face in the image domain. Other networks configured to receive facial landmarks as input are also contemplated.

[0053] The exemplary head pose network 628 can be any network that determines a subject's head pose from at least landmark points on the subject's face. As one example, the head pose network 628 can be one or more machine learning models constructed to receive both landmark values and corresponding confidence values as inputs and output head pose values. Such networks can include known head pose networks configured to receive landmark values as inputs, where these networks are modified to incorporate confidence values as additional inputs. The confidence values can then be used to vary the weights of features determined from the input landmarks or the weights of the input landmarks themselves, for example, to reduce the contribution of features corresponding to landmark points with low confidence values and / or increase the contribution of features corresponding to landmark points with higher confidence values (the weight values of input landmarks are generally inversely proportional to the level of occlusion associated with the landmarks, i.e., proportional to their corresponding confidence values). As another example, the head pose network 628 can be one or more machine learning models constructed to receive landmark values as inputs. In this latter example, the confidence value may be used to filter out landmark points of insufficient confidence before input to head pose network 628. That is, the confidence value may be used as a filter before the facial landmarks are input to head pose network 628, such that only those landmark points with sufficient confidence values are input to head pose network 628. In this manner, head pose network 628 considers only non-occluded regions of the subject's head when determining head pose, and therefore may produce more accurate results when determining the subject's head pose compared to conventional head pose determination models that do not possess the ability to distinguish between occluded and non-occluded regions of the subject's head.

[0054] The speaker detector module 624 may include any number and types of networks, models, other software modules, etc. configured to correlate voice sounds with image regions and / or the first conference participant 102 (see FIG. 1) and / or determine the direction of sounds recorded by multiple microphones (e.g., triangulation). By way of non-limiting example, such a network may include a sound analysis network 630 configured to perform one or more of these functions.

[0055] The facial landmarks and confidence values may also serve as input or feedback to the face detection module 620. In such embodiments, the face detection module 620 may use the confidence values to select one or more image regions corresponding to sufficiently high confidence values. For example, the face detection module 620 may use the confidence values to select only sufficiently unoccluded portions of a face for inclusion in an image region. This may result in more accurate or more reliable determination of landmark points. In other words, the confidence values may provide feedback to the face detection module 620 to potentially improve the selection and / or positioning of facial landmarks.

[0056] The video editing module 626 enlarges the image region selected by the speaker detector module 624 as depicting the speaker to create a modified video segment. In other words, with reference to FIG. 5, the video editing module 626 may perform block 512 of method 500. The video editing module 626 may enlarge or upscale the selected image region using one or more machine learning techniques (e.g., deep neural learning or deep neural network(s)). For example, the video editing module 626 may upscale a lower-resolution image region to a higher resolution (e.g., the resolution of frames 202 and 204 shown in FIG. 2) using one or more super-resolution imaging techniques. As a non-limiting example, the video editing module 626 may include a face-enhancement super-resolution deep learning model configured to zoom the selected image region and improve the resulting image quality of the enlarged image region in the modified video segment.

[0057] With reference to FIG. 56, user interface generator 632 is configured to receive the modified video segment, generate second user interface 124 (see FIGS. 1 and 4), and transmit second user interface 124 to display device 640 (e.g., one of display devices 116 and 118 shown in FIG. 1) for display thereby. In other words, with reference to FIG. 5, user interface generator 632 may perform block 516 of method 500. In at least one embodiment, user interface generator 632 includes computer-executable instructions that are executable by a computing device, such as one or more of computing devices 112, 114, and 132 (see FIG. 1). In at least one embodiment, user interface generator 632 includes one or more routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.

[0058] Inference and Training Logic 7A illustrates inference and / or training logic 715 used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided below in conjunction with FIG. 7A and / or FIG. 7B.

[0059] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network to be trained and / or used for inference in one or more embodiments. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software for controlling the timing and / or order in which the weights and / or other parameter information should be loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads the weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data for each layer of a neural network that is trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0060] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the selection of whether code and / or data storage 701 is internal or external to a processor, for example, or includes DRAM, SRAM, flash, or some other storage type, may depend on available storage, on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inferencing and / or training of neural networks, or some combination of these factors.

[0061] In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, code and / or data storage 705 for storing back and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with aspects of one or more embodiments. In at least one embodiment, the code and / or data storage 705 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, training logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software for controlling timing and / or ordering, in which weights and / or other parameter information should be loaded to configure logic including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0062] In at least one embodiment, code, such as graph code, causes the loading of weight or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the selection of whether code and / or data storage 705 is internal or external to the processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other storage type, may depend on available storage, on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inferring and / or training the neural network, or some combination of these factors.

[0063] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be combined storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separate. In at least one embodiment, code and / or data storage 701 and any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0064] In at least one embodiment, the inference and / or training logic 715 may include one or more arithmetic logic units (“ALUs”) 710, including, but not limited to, integer and / or floating point units, for performing logical and / or mathematical operations based at least in part on or indicated by the training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values from layers or neurons in a neural network) that are stored in activation storage 720, where these activations are a function of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, the activations stored in activation storage 720 are generated according to linear algebra and / or matrix-based mathematics performed by ALU(s) 710 in response to executing instructions or other code, and the weight values stored in code and / or data storage 705 and / or data storage 701 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 705 or code and / or data storage 701, or in another storage, on-chip or off-chip.

[0065] In at least one embodiment, ALU(s) 710 are contained within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU(s) 710 may be external to the processor or other hardware logic device or circuit (e.g., a coprocessor) that uses them. In at least one embodiment, ALU 710 may be contained within an execution unit of a processor, or otherwise within a bank of ALUs accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share a processor or other hardware logic device or circuit, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic device or circuit and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retirement, and / or other logic circuitry.

[0066] In at least one embodiment, activation storage 720 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 720 may be completely or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the selection of whether activation storage 720 is internal or external to a processor, for example, or whether it comprises DRAM, SRAM, flash memory, or some other storage type, may depend on available storage, on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inferencing and / or training of neural networks, or some combination of these factors.

[0067] In at least one embodiment, the inference and / or training logic 715 shown in Figure 7A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 715 shown in Figure 7A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0068] FIG. 7B illustrates inference and / or training logic 715, according to at least one embodiment. In at least one embodiment, the inference and / or training logic 715 may include, but is not limited to, hardware logic in which computational resources are dedicated or otherwise used only in conjunction with weight values or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 715 illustrated in FIG. 7B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, the inference and / or training logic 715 illustrated in FIG. 7B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 7B , code and / or data storage 701 and code and / or data storage 705 are each associated with dedicated computational resources, such as computation hardware 702 and computation hardware 706, respectively. In at least one embodiment, computation hardware 702 and computation hardware 706 each include one or more ALUs that perform mathematical functions, such as linear algebra functions, solely on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, with the results stored in activation storage 720.

[0069] In at least one embodiment, each of the code and / or data storages 701 and 705 and corresponding computation hardware 702 and 706 correspond to a different layer of a neural network, whereby activations resulting from one storage / computation pair 701 / 702 of code and / or data storage 701 and computation hardware 702 are provided as input to a next storage / computation pair 705 / 706 of code and / or data storage 705 and computation hardware 706 to mirror the conceptual organization of the neural network. In at least one embodiment, the storage / computation pairs 701 / 702 and 705 / 706 may correspond to two or more neural network layers. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 715 after or in parallel with the storage / computation pairs 701 / 702 and 705 / 706.

[0070] Neural Network Training and Deployment FIG. 8 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and enables it to be trained using processing resources described herein to generate a trained neural network 808. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0071] In at least one embodiment, the untrained neural network 806 is trained using supervised learning, where the training dataset 802 includes inputs paired with desired outputs for the inputs, or the training dataset 802 includes inputs with known outputs, and the outputs of the neural network 806 are manually scored. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, where inputs from the training dataset 802 are processed and the resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights controlling the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools for monitoring how well the untrained neural network 806 is converging towards a model, such as the trained neural network 808, suitable for generating correct answers, such as in the results 814, based on input data, such as the new dataset 812. In at least one embodiment, the training framework 804 iteratively trains the untrained neural network 806 and adjusts the weights to improve the output of the untrained neural network 806 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 achieves a desired accuracy. In at least one embodiment, the trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0072] In at least one embodiment, the untrained neural network 806 is trained using unsupervised learning, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and determine how individual inputs relate to the untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate self-organizing maps in the trained neural network 808 that can perform operations useful in reducing the dimensionality of the new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 812 that deviate from the normal patterns of the new dataset 812.

[0073] In at least one embodiment, semi-supervised learning may be used, which is a technique that includes a mixture of labeled and unlabeled data in the training dataset 802. In at least one embodiment, the training framework 804 may be used to implement incremental learning, such as through a transfer learning technique. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to a new dataset 812 without forgetting knowledge instilled in the trained neural network 808 during initial training.

[0074] Data Center 9 illustrates an exemplary data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0075] In at least one embodiment, as shown in FIG. 9 , data center infrastructure layer 910 may include a resource orchestrator 912, grouped computing resources 914, and node computing resources (“node CRs”) 916(1) through 916(N), where “N” represents a positive integer (which may be a different integer “N” than that used in other figures). In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR 916(1)-916(N) may be a server having one or more of the computing resources described above.

[0076] In at least one embodiment, the grouped computing resources 914 may include distinct groupings of node CRs housed within one or more racks (not shown), or many racks housed in a data center at various geographic locations (also not shown). In at least one embodiment, the distinct groupings of node CRs within the grouped computing resources 914 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0077] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource orchestrator 912 may include hardware, software, or some combination thereof.

[0078] 9 , framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, framework layer 920 may include a framework for supporting software 932 in software layer 930 and / or one or more applications 942 in application layer 940. In at least one embodiment, software 932 or application(s) 942 may include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 920 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which may utilize distributed file system 928 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 932 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 900. In at least one embodiment, configuration manager 924 may be capable of configuring different tiers, such as software tier 930, as well as framework tier 920, which includes Spark and distributed file system 928 to support large-scale data processing. In at least one embodiment, resource manager 926 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 928 and job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 914 in data center infrastructure tier 910.In at least one embodiment, resource manager 926 may manage these mapped or allocated computing resources in coordination with resource orchestrator 912.

[0079] In at least one embodiment, software 932 included in software layer 930 may include software used by nodes CR 916(1)-916(N), grouped computing resources 914, and / or at least a portion of distributed file system 928 of framework layer 920. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0080] In at least one embodiment, the application(s) 942 included in the application layer 940 may include one or more types of applications used by the nodes CR 916(1)-916(N), the grouped computing resources 914, and / or at least a portion of the distributed file system 928 of the framework layer 920. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0081] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may free data center operators of data center 900 from determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0082] In at least one embodiment, data center 900 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, the trained machine learning models corresponding to the one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 900 by using the weight parameters calculated through one or more training techniques described herein.

[0083] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0084] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 9 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0085] In embodiments in which at least one of modules 620-626 (see FIG. 6) is implemented at least in part using one or more neural networks, inference and / or training logic 715 may be used to at least partially implement the neural network(s). For example, such inference and / or training logic 715 may be used to configure client application 134 (see FIGS. 1 and 6) before the client application 134 is deployed on computing devices 112 and 114 (see FIG. 1). As another non-limiting example, such inference and / or training logic 715 may be used to configure server application 130 (see FIG. 1) before the server application 130 is deployed on computing device(s) 132 (see FIG. 1).

[0086] Autonomous Vehicles 10A illustrates an example of an autonomous vehicle 1000, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1000 (alternatively referred to herein as “vehicle 1000”) may be a passenger vehicle, such as, but not limited to, a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-tractor-trailer truck used to transport cargo. In at least one embodiment, vehicle 1000 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0087] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE"), in their respective publications. In at least one embodiment, vehicle 1000 may be capable of functionality according to one or more of levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1000 may be capable of conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0088] In at least one embodiment, vehicle 1000 may include components such as, but not limited to, a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1000 may include a propulsion system 1050, such as, but not limited to, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 1050 may be connected to a drive train of vehicle 1000, which may include, but is not limited to, a transmission to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from throttle / accelerator(s) 1052.

[0089] In at least one embodiment, a steering system 1054, which may include, but is not limited to, a steering wheel, is used to steer the vehicle 1000 (e.g., along a desired path or route) when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is moving). In at least one embodiment, the steering system 1054 may receive signals from steering actuator(s) 1056. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to operate the vehicle brakes in response to receiving signals from brake actuator(s) 1048 and / or brake sensors.

[0090] In at least one embodiment, controller(s) 1036, which may include, but are not limited to, one or more system-on-chip (“SoC”) (not shown in FIG. 10A ) and / or graphics processing unit(s) (“GPU”)(s), provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, controller(s) 1036 may send signals to operate vehicle brakes via brake actuator(s) 1048, to operate steering system 1054 via steering actuator(s) 1056, and to operate propulsion system 1050 via throttle / accelerator(s) 1052. In at least one embodiment, the controller(s) 1036 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1000. In at least one embodiment, the controller(s) 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0091] In at least one embodiment, controller(s) 1036 provide signals to control one or more components and / or systems of vehicle 1000 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, the sensor data may be received from, for example, but not limited to, global navigation satellite system ("GNSS") sensor(s) 1058 (e.g., global positioning system sensor(s)), RADAR sensor(s) 1060, ultrasonic sensor(s) 1062, LIDAR sensor(s) 1064, inertial measurement unit(s) ("IMU") sensor(s), or other sensors. unit) sensors 1066 (e.g., accelerometer(s), gyroscope(s), magnetic compass(s), magnetometer(s), etc.), microphone(s) 1096, stereo camera(s) 1068, wide-angle camera(s) 1070 (e.g., fisheye camera(s), infrared camera(s) 1072, ambient camera(s) 1074 (e.g., 360-degree camera(s)), ), a long-range camera (not shown in FIG. 10A ), one or more mid-range cameras (not shown in FIG. 10A ), one or more speed sensors 1044 (e.g., for measuring the speed of the vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more brake sensors (e.g., as part of a brake sensor system 1046), and / or other sensor types.

[0092] In at least one embodiment, one or more of the controller(s) 1036 may receive input (e.g., represented by input data) from the instrument cluster 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high-definition map (not shown in FIG. 10A )), location data (e.g., the location of vehicle 1000 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object status sensed by controller(s) 1036, etc. For example, in at least one embodiment, HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0093] In at least one embodiment, vehicle 1000 further includes network interface 1024, which may use wireless antenna(s) 1026 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 1024 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. Also, in at least one embodiment, the wireless antenna(s) 1026 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network(s) such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area network(s) (“LPWAN”) such as protocols like LoRaWAN, SigFox, etc.

[0094] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 10A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0095] In at least one embodiment, vehicle 1000 may carry multiple passengers participating in a video conference with other remote participants. In such an embodiment, video capture device 106 may be implemented by one or more cabin cameras (not shown), and display device 116 may be implemented by an HMI display 1034.

[0096] 10B illustrates an example of camera locations and fields of view for autonomous vehicle 1000 of FIG. 10A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an illustrative example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 1000.

[0097] In at least one embodiment, the camera type for the camera may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1000. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0098] In at least one embodiment, one or more of the camera(s) may be used to implement advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more (e.g., all) of the camera(s) may simultaneously record and provide image data (e.g., video).

[0099] In at least one embodiment, the camera(s) may be mounted in a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from within the vehicle 1000 (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with camera image data capture capability. With reference to a door mirror mounting assembly, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, the camera(s) may be integrated into the door mirror. In at least one embodiment, for a side view camera, the camera(s) may be integrated into the four pillars at each corner of the cabin.

[0100] In at least one embodiment, a camera (e.g., a front-facing camera) with a field of view that includes a portion of the environment ahead of vehicle 1000 may be used for a surround view to help identify the path and obstacles ahead and, with the aid of one or more of controller(s) 1036 and / or control SoCs, provide information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many ADAS functions similar to LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS functions and systems, including, but not limited to, other functions such as Lane Departure Warning ("LDW"), Autonomous Cruise Control ("ACC"), and / or traffic sign recognition.

[0101] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1070 may be used to perceive objects (e.g., pedestrians, crossing traffic, or bicyclists) coming into view from the periphery. While only one wide-angle camera 1070 is shown in FIG. 10B , in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1000. In at least one embodiment, any number of long-range camera(s) 1098 (e.g., long-view stereo camera pairs) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera(s) 1098 may also be used for object detection and classification, as well as basic object tracking.

[0102] In at least one embodiment, any number of stereo cameras 1068 may also be included in the front-facing configuration. In at least one embodiment, one or more of the stereo camera(s) 1068 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic on a chip ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1000 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo camera(s) 1068 may include, but are not limited to, compact stereo vision sensor(s) that may include, but are not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that may measure distance from the vehicle 1000 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo camera(s) 1068 may be used in addition to or instead of those described herein.

[0103] In at least one embodiment, a camera with a field of view that includes portions of the environment to the sides of the vehicle 1000 (e.g., a side-view camera) may be used for the surroundings view, providing information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surroundings camera(s) 1074 (e.g., four surroundings cameras shown in FIG. 10B ) may be positioned on the vehicle 1000. In at least one embodiment, the surroundings camera(s) 1074 may include, without limitation, any number and combination of wide-angle cameras, fisheye camera(s), 360-degree camera(s), and / or the like. For example, in at least one embodiment, four fisheye cameras may be positioned in front, behind, and on the sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may use three surroundings cameras 1074 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surroundings view camera.

[0104] In at least one embodiment, a camera (e.g., a rear-view camera) with a field of view that includes a portion of the environment behind the vehicle 1000 may be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, a camera that is also suitable as a front-facing camera(s) (e.g., long-range camera 1098, and / or mid-range camera(s) 1076, stereo camera(s) 1068, infrared camera(s) 1072, etc.), as described herein.

[0105] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 10B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0106] In at least one embodiment, vehicle 1000 may carry multiple passengers participating in a video conference with other remote participants. In such an embodiment, video capture device 106 may be implemented by one or more cabin cameras (not shown), and display device 116 may be implemented by an HMI display 1034.

[0107] FIG. 10C is a block diagram illustrating an example system architecture for the autonomous vehicle 1000 of FIG. 10A , according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 in FIG. 10C is shown as being connected via a bus 1002. In at least one embodiment, the bus 1002 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, the CAN may be a network internal to the vehicle 1000 used to help control various features and functionality of the vehicle 1000, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1002 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 can be read to determine steering angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1002 can be an ASIL B compliant CAN bus.

[0108] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or as an alternative to CAN. In at least one embodiment, there may be any number of buses forming bus 1002, including, but not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1002 may communicate with one of the components of vehicle 1000, and two or more of buses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1004 (such as SoC1004(A) and SoC1004(B)), each of the controller(s) 1036, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0109] 10A , the vehicle 1000 may include one or more controllers 1036. In at least one embodiment, the controller(s) 1036 may be used for a variety of functions. In at least one embodiment, the controller(s) 1036 may be coupled to any of various other components and systems of the vehicle 1000 and may be used for control of the vehicle 1000, artificial intelligence of the vehicle 1000, infotainment for the vehicle 1000, and / or other functions.

[0110] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 may include, but is not limited to, a central processing unit ("CPU") 1006, a graphics processing unit ("GPU") 1008, processor(s) 1010, cache(s) 1012, accelerator(s) 1014, data store(s) 1016, and / or other components and features not shown. In at least one embodiment, SoC(s) 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, the SoC(s) 1004 may be combined in a system (e.g., a system in a vehicle 1000) with a high definition ("HD") map 1022 that may obtain map refreshes and / or updates via a network interface 1024 from one or more servers (not shown in FIG. 10C).

[0111] In at least one embodiment, the CPU(s) 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, the CPU(s) 1006 may include multiple cores and / or level 2 (“L2”) caches. For example, in at least one embodiment, the CPU(s) 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1006 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, the CPU(s) 1006 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of the CPU(s) 1006 to be active at any given time.

[0112] In at least one embodiment, one or more of the CPU(s) 1006 may implement power management capabilities, including, but not limited to, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when such core is not actively executing instructions by execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, the CPU(s) 1006 may further implement an advanced algorithm for managing power states, where the hardware / microcode determines what the best power state to enter for a core, cluster, and CCPLEX is, given allowed power states and expected wake-up times. In at least one embodiment, the processing core may support a simple power state entry sequence in software, with work offloaded to microcode.

[0113] In at least one embodiment, the GPU(s) 1008 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, the GPU(s) 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 1008 may use an extended tensor instruction set. In at least one embodiment, the GPU(s) 1008 may include one or more streaming microprocessors, each of which may include a level 1 (“L1”) cache (e.g., an L1 cache with at least 96 KB of storage capacity), and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, the GPU(s) 1008 may include at least eight streaming microprocessors. In at least one embodiment, the GPU(s) 1008 may use one or more compute application programming interfaces (APIs). In at least one embodiment, the GPU(s) 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0114] In at least one embodiment, one or more of the GPU(s) 1008 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 1008 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate several mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level 0 ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, a streaming microprocessor may include independent parallel integer and floating-point data paths for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, a streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation among parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0115] In at least one embodiment, one or more of the GPU(s) 1008 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide, in some instances, approximately 900 GB / s of peak memory bandwidth. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five synchronous random-access memory (“GDDR5”), may be used in addition to or as an alternative to HBM memory.

[0116] In at least one embodiment, the GPU(s) 1008 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow the GPU(s) 1008 to directly access the page tables of the CPU(s) 1006. In at least one embodiment, when the GPU 1008 memory management unit ("MMU") encounters a GPU miss, an address translation request may be sent to the CPU(s) 1006. In at least one embodiment, in response, one of the CPU(s) 1006 may look up a virtual-to-physical mapping for the address in its page table and send the translation back to the GPU(s) 1008. In at least one embodiment, the unified memory technology enables a single unified virtual address space for memory of both the CPU(s) 1006 and the GPU(s) 1008, which may simplify programming the GPU(s) 1008 and porting applications to the GPU(s) 1008.

[0117] In at least one embodiment, the GPU(s) 1008 may include any number of access counters that may track the frequency of accesses of the GPU(s) 1008 to the memory of other processors. In at least one embodiment, the access counter(s) may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0118] In at least one embodiment, one or more of the SoC(s) 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, the cache(s) 1012 may include a level 3 (“L3”) cache that is available to both the CPU(s) 1006 and the GPU(s) 1008 (e.g., connected to the CPU(s) 1006 and the GPU(s) 1008). In at least one embodiment, the cache(s) 1012 may include a write-back cache that may track line states, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more of memory, depending on the embodiment, although smaller cache sizes may be used.

[0119] In at least one embodiment, one or more of the SoC(s) 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may complement the GPU(s) 1008 and be used to offload some of the GPU(s) 1008's tasks (e.g., to free up more cycles of the GPU(s) 1008 to perform other tasks). In at least one embodiment, accelerator 1014 may be used for target workloads that are stable enough to abide by acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., as used for object detection), or other types of CNNs.

[0120] In at least one embodiment, the accelerator(s) 1014 (e.g., a hardware-accelerated cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, the DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, generally far exceeding the performance of a CPU. In at least one embodiment, the TPU(s) may perform several functions, including, for example, single-instance convolution functions, supporting INT8, INT16, and FP16 data types for both features and weights, and post-processor functions. In at least one embodiment, the DLA(s) may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety-related events.

[0121] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 1008; for example, by using an inference accelerator, a designer may target either the DLA(s) or the GPU(s) 1008 for any function. For example, in at least one embodiment, a designer may centralize CNN and floating-point operation processing in the DLA(s) and offload other functions to the GPU(s) 1008 and / or the accelerator(s) 1014.

[0122] In at least one embodiment, the accelerator(s) 1014 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, the PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVAs may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0123] In at least one embodiment, the RISC core may interact with an image sensor (e.g., the image sensor of any camera described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use any of several protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0124] In at least one embodiment, the DMA may enable components of the PVA to access system memory independently of the CPU(s) 1006. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0125] In at least one embodiment, the vector processor is a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and can provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the PVA's primary processing engine and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0126] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to improve the overall security of the system.

[0127] In at least one embodiment, the accelerator(s) 1014 may include a computer vision network-on-chip and static random-access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 1014. In at least one embodiment, the on-chip memory may include, for example, but not limited to, at least 4 MB of SRAM including eight field-configurable memory blocks, which may be accessible by both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access memory through a backbone that provides the PVA and DLA with high-speed access to memory. In at least one embodiment, the backbone may include a computer vision network-on-chip that interconnects the PVA and DLA to memory (e.g., using APBs).

[0128] In at least one embodiment, the computer vision network-on-chip may include an interface in which both the PVA and DLA provide ready and enable signals prior to the transmission of any control signals, addresses, or data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals, addresses, and data, as well as burst-type communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0129] In at least one embodiment, one or more of the SoC(s) 1004 may include a real-time ray tracing hardware accelerator that may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general waveform propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0130] In at least one embodiment, the accelerator(s) 1014 can have diverse uses for autonomous driving. In at least one embodiment, PVAs can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA capabilities are well-matched for algorithm domains that require predictable processing with low power and low latency. In other words, PVAs perform well on small data sets for semi-dense or dense regular calculations that may require predictable runtime with low latency and low power. In at least one embodiment, PVAs, such as in vehicle 1000, can be designed to run traditional computer vision algorithms because they can be efficient at object detection and integer arithmetic.

[0131] For example, according to at least one embodiment of the technology, the PVA is used to perform computer stereo vision. In at least one embodiment, semi-global matching-based algorithms may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0132] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing the raw time-of-flight data to provide processed time-of-flight data.

[0133] In at least one embodiment, DLA may be used to run any type of network for improving control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure allows the system to make further decisions regarding which detections should be considered true positives rather than false positives. In at least one embodiment, the system may set a confidence threshold and consider only detections above the threshold to be true positives. In embodiments where an automatic emergency braking (“AEB”) system is used, a false positive detection would cause the vehicle to automatically apply emergency braking, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered a trigger for AEB. In at least one embodiment, DLA may run a neural network to regress a confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, the bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), an output from the IMU sensor(s) 1066 that correlates with the orientation of the vehicle 1000, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., the LIDAR sensor(s) 1064 or the RADAR sensor(s) 1060).

[0134] In at least one embodiment, one or more of the SoC(s) 1004 may include data store(s) 1016 (e.g., memory). In at least one embodiment, the data store(s) 1016 may be on-chip memory of the SoC(s) 1004, which may store neural networks to be executed on the GPU(s) 1008 and / or DLA. In at least one embodiment, the data store(s) 1016 may be large enough in capacity to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, the data store(s) 1016 may comprise L2 or L3 cache(s).

[0135] In at least one embodiment, one or more of the SoC(s) 1004 may include number(s) of processor(s) 1010 (e.g., embedded processor(s)). In at least one embodiment, the processor(s) 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC(s) 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist with system low power state transitions, manage thermal and temperature sensors of the SoC(s) 1004, and / or manage the power state of the SoC(s) 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC(s) 1004 may use the ring oscillator to detect the temperature of the CPU(s) 1006, the GPU(s) 1008, and / or the accelerator(s) 1014. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC(s) 1004 in a low power state, and / or place the vehicle 1000 in a chauffeur to safe stop mode (e.g., bring the vehicle 1000 to a safe stop).

[0136] In at least one embodiment, the processor(s) 1010 may further include a set of embedded processors that may act as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0137] In at least one embodiment, the processor(s) 1010 may further include an always-on processor engine that may provide the hardware features necessary to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0138] In at least one embodiment, the processor(s) 1010 may further include a safety cluster engine, which may include, but is not limited to, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, the two or more cores, in at least one embodiment, may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor(s) 1010 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1010 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0139] In at least one embodiment, the processor(s) 1010 may include a video image composer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to produce a final image for the player window. In at least one embodiment, the video image composer may perform lens distortion correction for the wide-angle camera(s) 1070, the surrounding camera(s) 1074, and / or the in-cabin surveillance camera sensor(s). In at least one embodiment, the in-cabin surveillance camera sensor(s) is / are preferably monitored by a neural network running on another instance of the SoC 1004 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, but is not limited to, activate cellular service, make phone calls, write emails, change vehicle destinations, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, some features are available to the driver when the vehicle is operating in autonomous mode and are disabled at other times.

[0140] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, noise reduction appropriately weights spatial information and reduces the weight of information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0141] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may further be used for user interface compositing when the operating system desktop is in use, so that the GPU(s) 1008 are not required to continually render new surfaces. In at least one embodiment, when the GPU(s) 1008 are powered on, active, and performing 3D rendering, the video image composer may be used to offload the GPU(s) 1008 to improve performance and responsiveness.

[0142] In at least one embodiment, one or more of the SoC(s) 1004 may further include a mobile industry processor interface ("MIPI") camera serial interface, a high-speed interface for receiving video and input from a camera, and / or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoC(s) 1004 may further include input / output controller(s), which may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0143] In at least one embodiment, one or more of the SoC(s) 1004 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, the SoC(s) 1004 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), data from sensors (e.g., LIDAR sensor(s) 1064, RADAR sensor(s) 1060, etc., which may be connected via an Ethernet channel), data from bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from GNSS sensor(s) 1058 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoC(s) 1004 may further include dedicated high performance mass storage controllers, which may include their own DMA engines and may be used to offload the CPU(s) 1006 from routine data management tasks.

[0144] In at least one embodiment, the SoC(s) 1004 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and may provide a platform for a flexible and reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC(s) 1004 may be faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1014, when combined with the CPU(s) 1006, GPU(s) 1008, and data store(s) 1016, may provide a fast and efficient platform for a level 3-5 autonomous vehicle.

[0145] In at least one embodiment, computer vision algorithms may be executed on a CPU, which may be configured using a high-level programming language such as C to perform a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, including requirements related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, as used in in-vehicle ADAS applications and practical Level 3-5 autonomous vehicles.

[0146] The embodiments described herein allow multiple neural networks to be implemented simultaneously and / or sequentially, with the results being combined together to enable Levels 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU(s) 1020) can include text and word recognition, enabling the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA can further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0147] In at least one embodiment, multiple neural networks may be run simultaneously for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions" along with an electric light may be interpreted independently or collectively by several neural networks. In at least one embodiment, such a warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which, when the flashing light is detected, informs the vehicle's route planning software (preferably running on a CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the third deployed neural network informs the vehicle's route planning software of the presence (or absence) of the flashing light. In at least one embodiment, all three neural networks may be run simultaneously, such as within the DLA and / or on the GPU(s) 1008.

[0148] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, disable such vehicle when the owner leaves such vehicle. In this manner, the SoC(s) 1004 provide security against theft and / or carjacking.

[0149] In at least one embodiment, a CNN for emergency vehicle detection and identification may detect and identify emergency vehicle sirens using data from microphone 1096. In at least one embodiment, SoC(s) 1004 use CNNs to classify environmental and urban sounds as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor(s) 1058. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in North America, the CNN attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, the control program may be used to execute an emergency vehicle safety routine, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with the ultrasonic sensor(s) 1062 until the emergency vehicle has passed.

[0150] In at least one embodiment, vehicle 1000 may include CPU(s) 1018 (e.g., discrete CPU(s) or dCPU(s)), which may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 1018 may include, for example, an X86 processor. CPU(s) 1018 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC(s) 1004 and / or monitoring the status and health of controller(s) 1036 and / or infotainment system on a chip (“infotainment SoC”) 1030.

[0151] In at least one embodiment, vehicle 1000 may include GPU(s) 1020 (e.g., discrete GPU(s) or dGPU(s)), which may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU(s) 1020 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1000.

[0152] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, wireless antenna(s) 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connectivity to Internet cloud services (e.g., with server(s) and / or other network devices) with other vehicles and / or computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and the other vehicles and / or an indirect link may be established (e.g., across a network and via the Internet). In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information regarding vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1000). In at least one embodiment, such aforementioned functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1000.

[0153] In at least one embodiment, the network interface 1024 may include an SoC that provides modulation and demodulation functionality and enables the controller(s) 1036 to communicate over a wireless network. In at least one embodiment, the network interface 1024 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed through well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0154] In at least one embodiment, vehicle 1000 may further include data store(s) 1028, which may include, but are not limited to, off-chip storage (e.g., not on SoC(s) 1004). In at least one embodiment, data store(s) 1028 may include one or more storage elements, including, but not limited to, RAM, SRAM, dynamic random access memory ("DRAM"), video random-access memory ("VRAM"), flash memory, hard disks, and / or other components and / or devices capable of storing at least one bit of data.

[0155] In at least one embodiment, vehicle 1000 may further include GNSS sensor(s) 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, but not limited to, a GPS using a USB connector with an Ethernet-to-serial (e.g., RS-232) bridge.

[0156] In at least one embodiment, vehicle 1000 may further include RADAR sensor(s) 1060. In at least one embodiment, RADAR sensor(s) 1060 may be used by vehicle 1000 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor(s) 1060 may use a CAN bus and / or bus 1002 for control (e.g., to transmit data generated by RADAR sensor(s) 1060) and to access object tracking data, in some instances, along with access to an Ethernet channel for accessing raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, without limitation, RADAR sensor(s) 1060 may be suitable for forward, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensor(s) 1060 is a pulse-Doppler RADAR sensor.

[0157] In at least one embodiment, the RADAR sensor(s) 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range lateral coverage. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system may provide a wide field of view achieved by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, the RADAR sensor(s) 1060 may help distinguish between static and moving objects and may be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, the sensor(s) 1060 included in a long-range RADAR system may include, but are not limited to, multiple (e.g., six or more) fixed RADAR antennas and monostatic and multimodal RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the central four antennas may create a focused beam pattern designed to record the surroundings of vehicle 1000 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the other two antennas may increase the field of view, which may allow for quick detection of vehicles entering or exiting the lane of vehicle 1000.

[0158] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include any number of RADAR sensors 1060 designed to be mounted on either end of a rear bumper, without limitation. When mounted on either end of a rear bumper, in at least one embodiment, the RADAR sensor system may create two beams that constantly monitor the blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1038 for blind spot detection and / or lane change assistance.

[0159] In at least one embodiment, vehicle 1000 may further include ultrasonic sensor(s) 1062. In at least one embodiment, ultrasonic sensor(s) 1062, which may be positioned at front, rear, and / or side locations of vehicle 1000, may be used for parking assistance and / or to create and update an occupancy grid. In at least one embodiment, a variety of ultrasonic sensor(s) 1062 may be used, and different ultrasonic sensor(s) 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1062 may operate at a functional safety level of ASIL B.

[0160] In at least one embodiment, the vehicle 1000 may include one or more LIDAR sensors 1064. In at least one embodiment, the LIDAR sensor(s) 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1064 may operate at a functional safety level ASIL B. In at least one embodiment, the vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0161] In at least one embodiment, the LIDAR sensor(s) 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1064 may have an advertised range of approximately 100 meters, with an accuracy of 2 cm to 3 cm, and support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1064 may include small devices that may be integrated into front, rear, side, and / or corner locations of the vehicle 1000. In at least one embodiment, the LIDAR sensor(s) 1064 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters even for low-reflectivity objects. In at least one embodiment, the forward mounted LIDAR sensor(s) 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0162] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1000 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receptor that records the transit time of the laser pulse and the reflected light on each pixel, which corresponds to the range from the vehicle 1000 to the object. In at least one embodiment, flash LIDAR allows a highly accurate, distortion-free image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0163] In at least one embodiment, vehicle 1000 may further include IMU sensor(s) 1066. In at least one embodiment, IMU sensor(s) 1066 may be located at the center of a rear axle of vehicle 1000. In at least one embodiment, IMU sensor(s) 1066 may include, for example, but not limited to, accelerometer(s), magnetometer(s), gyroscope(s), magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, such as in a 6-axis application, IMU sensor(s) 1066 may include, but are not limited to, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, IMU sensor(s) 1066 may include, but are not limited to, an accelerometer, a gyroscope, and a magnetometer.

[0164] In at least one embodiment, the IMU sensor(s) 1066 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1066 enable the vehicle 1000 to estimate its heading by directly observing changes in velocity and correlating that from a GPS to the IMU sensor(s) 1066 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor(s) 1066 and the GNSS sensor(s) 1058 may be combined in a single, integrated unit.

[0165] In at least one embodiment, vehicle 1000 may include microphone(s) 1096 located in and / or around vehicle 1000. In at least one embodiment, microphone(s) 1096 may be used for, among other things, emergency vehicle detection and identification.

[0166] In at least one embodiment, vehicle 1000 may further include any number of camera types, including stereo camera(s) 1068, wide-angle camera(s) 1070, infrared camera(s) 1072, surrounding camera(s) 1074, long-range camera(s) 1098, mid-range camera(s) 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 1000. In at least one embodiment, which types of cameras are used depends on vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in more detail earlier herein with respect to FIGS. 10A and 10B.

[0167] In at least one embodiment, vehicle 1000 may further include vibration sensor(s) 1042. In at least one embodiment, vibration sensor(s) 1042 may measure vibration of a component of vehicle 1000, such as an axle(s). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., when the difference in vibration is between a powered axle and a free-spinning axle).

[0168] In at least one embodiment, vehicle 1000 may include an ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, in some instances, an SoC, without limitation. In at least one embodiment, the ADAS system 1038 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functionality.

[0169] In at least one embodiment, the ACC system may use RADAR sensor(s) 1060, LIDAR sensor(s) 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and advises the vehicle 1000 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0170] In at least one embodiment, the CACC system uses information from other vehicles, which may be received via a wireless link or indirectly, via a network connection (e.g., via the Internet), from other vehicles via the network interface 1024 and / or wireless antenna(s) 1026. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, and the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately preceding the vehicle 1000 and in the same lane), while I2V communication provides information about traffic ahead. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of the vehicle 1000 may make the CACC system more reliable, which may improve traffic flow and reduce congestion on roads.

[0171] In at least one embodiment, the FCW system is designed to alert the driver of a hazard so that such driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0172] In at least one embodiment, an AEB system may detect an imminent forward collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera(s) and / or a RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first alerts the driver to take corrective action to avoid the collision; if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the impact of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-crash braking.

[0173] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to alert the driver when the vehicle 1000 crosses a lane marker. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering inputs or brake control to correct the vehicle 1000 if the vehicle 1000 begins to leave its lane.

[0174] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver about the vehicles. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use rear-facing camera(s) and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration components.

[0175] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when the vehicle 1000 is backing up. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a crash. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components.

[0176] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but this is usually not a major issue because conventional ADAS systems alert the driver, allowing the driver to determine whether a safety condition truly exists and act accordingly. In at least one embodiment, the vehicle 1000 itself determines whether to follow the result from the primary computer (e.g., a first one of the controllers 1036) or the secondary computer (e.g., a second one of the controllers 1036) in the case of conflicting results. For example, in at least one embodiment, the ADAS system 1038 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant and diverse software on hardware components to detect perception and dynamic driving task failures. In at least one embodiment, output from the ADAS system 1038 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervising MCU determines how to reconcile the conflict to ensure safe operation.

[0177] In at least one embodiment, the primary computer may be configured to provide the supervising MCU with a reliability score indicating the primary computer's reliability in a selected outcome. In at least one embodiment, if the reliability score exceeds a threshold, the supervising MCU may follow the primary computer's instructions regardless of whether the secondary computers provide conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers exhibit different (e.g., conflicting) results, the supervising MCU may arbitrate between the computers to determine an appropriate outcome.

[0178] In at least one embodiment, the supervisory MCU can be configured to run neural network(s) trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on the output from the primary computer and the output from the secondary computer. In at least one embodiment, the neural network(s) in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network(s) in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the supervising MCU may include at least one of a DLA or a GPU suitable for running neural network(s) along with associated memory. In at least one embodiment, the supervising MCU may comprise and / or be included as a component of SoC(s) 1004.

[0179] In at least one embodiment, the ADAS system 1038 may include a secondary computer that implements ADAS functionality using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then), and the presence of neural network(s) in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may make the overall system more fault-tolerant, particularly to failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on the primary computer and non-identical software code running on the secondary computer provides a consistent overall result, the supervisory MCU may have higher confidence that the overall result is correct and that a bug in the software or hardware on the primary computer did not cause a critical error.

[0180] In at least one embodiment, the output of the ADAS system 1038 can be fed to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a frontal crash warning due to an upcoming object, the perception block can use this information when identifying the object. In at least one embodiment, the secondary computer can have its own neural network trained as described herein, thus reducing the risk of false positives.

[0181] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment (IVI) system). Although shown and described as an SoC, infotainment system SoC 1030, in at least one embodiment, may not be an SoC and may include, but is not limited to, two or more separate components. In at least one embodiment, infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that provides audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., For example, infotainment SoC 1030 may be used to provide vehicle 1000 with a variety of features, including but not limited to: a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), and / or information services (e.g., a navigation system, rear parking assist, a wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.). The infotainment SoC 1030 may include a display, an HMI display 1034, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1030 may further be used to provide information (e.g., visual and / or auditory) to the user(s) of the vehicle 1000, such as information from the ADAS system 1038, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0182] In at least one embodiment, infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1030 may communicate with other devices, systems, and / or components of vehicle 1000 via bus 1002. In at least one embodiment, infotainment SoC 1030 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions if primary controller(s) 1036 (e.g., vehicle 1000's primary and / or backup computers) fail. In at least one embodiment, infotainment SoC 1030 may place vehicle 1000 in a driver-safety shutdown mode as described herein.

[0183] In at least one embodiment, vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1032 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1032 may include any number and combination of instrumentation sets, such as, but not limited to, a speedometer, fuel level, oil pressure, a tachometer, an odometer, direction indicators, a shift lever position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between infotainment SoC 1030 and instrument cluster 1032. In at least one embodiment, the instrument cluster 1032 may be included as part of the infotainment SoC 1030, or vice versa.

[0184] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 10C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0185] In at least one embodiment, vehicle 1000 may carry multiple passengers participating in a videoconference with other remote participants. In such an embodiment, video capture device 106 may be implemented by cabin camera(s) (not shown), and display device 116 may be implemented by HMI display 1034. Additionally, computing device 112 may be implemented at least in part by SoC(s) 1004 and may use network interface 1024 to communicate with other components of system 100 (see FIG. 1) over network 110 (see FIG. 1). Alternatively, computing device 112 may be connected to network interface 1024 and may use network interface 1024 to communicate with other components of system 100 (see FIG. 1) over network 110 (see FIG. 1).

[0186] 10D is a diagram of a system 1076 for communication between cloud-based server(s) and the autonomous vehicle 1000 of FIG. 10A , according to at least one embodiment. In at least one embodiment, the system 1076 may include, but is not limited to, server(s) 1078, network(s) 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, the server(s) 1078 may include, but is not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, the GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected with a high-speed interconnect, such as, but not limited to, an NVLink interface 1088 and / or a PCIe connection 1086 developed by NVIDIA. In at least one embodiment, the GPUs 1084 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 1084 and PCIe switches 1082 are connected via a PCIe interconnect. While eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of the server(s) 1078 may include any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination, including, but not limited to, For example, in at least one embodiment, server(s) 1078 may each include 8, 16, 32, and / or more GPUs 1084.

[0187] In at least one embodiment, the server(s) 1078 may receive image data from the vehicle over the network(s) 1090 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, the server(s) 1078 may transmit updated or unupdated neural networks 1092 and / or map information 1094, including, but not limited to, information regarding traffic and road conditions, to the vehicle over the network(s) 1090. In at least one embodiment, updates to the map information 1094 may include updates to the HD map 1022, such as, but not limited to, information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1092 and / or map information 1094 may have arisen from new training and / or experience represented in data received from any number of vehicles in the environment and / or based at least in part on training performed at a data center (e.g., using server(s) 1078 and / or other servers).

[0188] In at least one embodiment, server(s) 1078 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or subjected to other preprocessing (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., sent to the vehicle via network(s) 1090) and / or used by server(s) 1078 to remotely monitor the vehicle.

[0189] In at least one embodiment, server(s) 1078 may receive data from vehicles and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, server(s) 1078 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s) 1078 may include a deep learning infrastructure using CPU-powered data centers.

[0190] In at least one embodiment, the deep learning infrastructure of server(s) 1078 may be capable of fast real-time inference and may use that capability to assess and verify the health of processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as a series of images and / or objects that vehicle 1000 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 1000; if the results do not match and the deep learning infrastructure concludes that the AI in vehicle 1000 has failed, server(s) 1078 may send a signal to vehicle 1000 instructing a fail-safe computer in vehicle 1000 to assume control, notify passengers, and complete a safe parking maneuver.

[0191] In at least one embodiment, server(s) 1078 may include GPU(s) 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of GPU-powered servers and inference acceleration may enable real-time response. In at least one embodiment, servers powered by CPUs, FPGAs, and other processors may be used for inference, such as when performance is less critical. In at least one embodiment, hardware architecture(s) 715 are used to implement one or more embodiments. Details regarding hardware architecture 715 are provided herein in conjunction with FIG. 7A and / or FIG. 7B.

[0192] Computer Systems 11 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1100 may include components such as processor 1102 to employ an execution unit that includes logic for implementing algorithms to process data according to the present disclosure, such as, but not limited to, the embodiments described herein. In at least one embodiment, computer system 1100 may include a processor such as the PENTIUM® Processor Family, Xeon™, Itanium®, XScale™, and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0193] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system-on-a-chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of implementing one or more instructions according to at least one embodiment.

[0194] In at least one embodiment, computer system 1100 may include, but is not limited to, a processor 1102, which may include one or more execution units 1108 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, while in other embodiments, computer system 1100 may be a multi-processor system. In at least one embodiment, processor 1102 may include, but is not limited to, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110 that may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0195] In at least one embodiment, processor 1102 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1102. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1106 may store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0196] In at least one embodiment, an execution unit 1108 including logic for performing integer and floating-point operations may also be present in the processor 1102. In at least one embodiment, the processor 1102 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for some macroinstructions. In at least one embodiment, the execution unit 1108 may include logic for dealing with a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109, along with associated circuitry for executing the instructions, in the instruction set of a general-purpose processor, operations used by many multimedia applications may be performed using packed data in the processor 1102. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0197] In at least one embodiment, the execution unit 1108 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1100 may include, but is not limited to, a memory 1120. In at least one embodiment, the memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, the memory 1120 may store instruction(s) 1119 and / or data 1121 represented by data signals that may be executed by the processor 1102.

[0198] In at least one embodiment, a system logic chip may be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and the processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may direct data signals between the processor 1102, the memory 1120, and other components in the computer system 1100, and may bridge data signals between the processor bus 1110, the memory 1120, and the system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to memory 1120 through a high-bandwidth memory path 1118, and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0199] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub ("flash BIOS") 1128, a wireless transceiver 1126, data storage 1124, a legacy I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 such as a Universal Serial Bus ("USB") port, and a network controller 1134. In at least one embodiment, data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0200] In at least one embodiment, Figure 11 illustrates a system including interconnected hardware devices or "chips," although in other embodiments, Figure 11 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 11 may be interconnected using proprietary interconnects, standard interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using a compute express link (CXL) interconnect.

[0201] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 11 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0202] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may each be implemented by one or more computing devices, such as computer system 1100. In such an embodiment, client application 134 and / or server application 130 may be stored as instruction(s) 1119 in memory 1120 and executed by processor 1102. Additionally, computing devices 112, 114, and / or 132 may use network controller 1134 and / or wireless transceiver 1126 to communicate with other components of system 100 (see FIG. 1 ) over network 110 (see FIG. 1 ). Display device 116 and / or display device(s) 118 (see FIG. 1 ) may be connected to processor 1102 via graphics / video card 1112. Video capture device 106 and / or video capture device(s) 108 may be connected to processor 1102 via serial expansion port 1127 .

[0203] 12 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210, according to at least one embodiment. In at least one embodiment, electronic device 1200 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0204] In at least one embodiment, electronic device 1200 may include, without limitation, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2 The devices may be coupled using a bus or interface, such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 12 illustrates a system including interconnected hardware devices or “chips,” although in other embodiments, FIG. 12 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 12 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 12 are interconnected using a Compute Express Link (CXL) interconnect.

[0205] In at least one embodiment, FIG. 12 illustrates a display 1224, a touch screen 1225, a touch pad 1230, a Near Field Communication ("NFC") unit 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset ("EC") 1235, a Trusted Platform Module ("TPM") 1238, a BIOS / firmware / flash memory ("BIOS,FW flash") 1222, a DSP 1260, a drive 1220, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network ("WLAN") unit 1250, a Bluetooth unit 1252, a wireless wide area network ("WWAN") unit 1254, a Bluetooth device 1256, a Bluetooth device 1258, a Bluetooth device 1259, a Bluetooth device 1260, a Bluetooth device 1261, a Bluetooth device 1262, a Bluetooth device 1263, a Bluetooth device 1264, a Bluetooth device 1265, a Bluetooth device 1266, a Bluetooth device 1268, a Bluetooth device 1269, a Bluetooth device 1270, a Bluetooth device 1272, a Bluetooth device 1274, a Bluetooth device 1276, a Bluetooth device 1278, a Bluetooth device 1279, a Bluetooth device 1280, a Bluetooth device 1282, a Bluetooth device 1284, a Bluetooth device 1286, a Bluetooth device 1288, a Bluetooth device 1288, a Bluetooth device 1289, a Bluetooth device 1290, a Bluetooth device 1292, a Bluetooth device 1294, a Bluetooth device 1296, a Bluetooth device 1298, a Bluetooth device 1298, a Bluetooth device 1299, a Bluetooth device 1300, a Bluetooth device 13 The memory may include a USB 3.0 camera ("USB 3.0 Camera") 1254, a USB 3.0 Network unit 1256, a Global Positioning System (GPS) unit 1255, a camera such as a USB 3.0 camera ("USB 3.0 Camera") 1254, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1215, implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0206] In at least one embodiment, other components may be communicatively coupled to processor 1210 through the components described herein. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touch pad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, headphones 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and class D amplifier”) 1262, which may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, SIM card ("SIM") 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250 and Bluetooth unit 1252, and WWAN unit 1256 may be implemented in a Next Generation Form Factor ("NGFF").

[0207] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 12 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0208] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may each be implemented by one or more electronic devices, such as electronic device 1200. In such an embodiment, client application 134 and / or server application 130 may be stored as instruction(s) in memory (not shown) and executed by processor 1310. Display device 116 and / or display device(s) 118 may be implemented by display 1224 and / or touch screen 1225. Additionally, computing devices 112, 114, and / or 132 may use WLAN unit 1250 and / or WWAN unit 1256 to communicate with other components of system 100 (see FIG. 1 ) via network 110 (see FIG. 1 ). Video capture device 106 and / or video capture device(s) 108 (see FIG. 1) may be implemented as camera 1254.

[0209] 13 illustrates, according to at least one embodiment, a computer system 1300. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0210] In at least one embodiment, computer system 1300 includes at least one central processing unit ("CPU") 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as, but not limited to, PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), with data stored in main memory 1304, which may take the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1322 provides an interface to other computing devices and networks for computer system 1300 to receive data from and transmit data to other systems.

[0211] In at least one embodiment, computer system 1300 includes, at least in one embodiment, but is not limited to, input device(s) 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode ("LED") display, a plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1308, such as a keyboard, mouse, touchpad, microphone, or the like. In at least one embodiment, each of the modules described herein may be on a single semiconductor platform to form a processing system.

[0212] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 13 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0213] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may each be implemented by one or more computers, such as computer 1300. In such an embodiment, client application 134 and / or server application 130 may be stored as instruction(s) in main memory 1304 and executed by parallel processing unit (“PPU”) 1314. Display device 116 and / or display device(s) 118 may be implemented by display device 1306. Additionally, computing devices 112, 114, and / or 132 may use network interface 1322 to communicate with other components of system 100 (see FIG. 1 ) via network 110 (see FIG. 1 ). Video capture device 106 and / or video capture device(s) 108 (see FIG. 1 ) may be implemented as input device 1308.

[0214] 14 illustrates a computer system 1400, according to at least one embodiment. In at least one embodiment, computer system 1400 may include, but is not limited to, a computer 1410 and a USB stick 1420. In at least one embodiment, computer 1410 may include, but is not limited to, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1410 may include, but is not limited to, a server, a cloud instance, a laptop, or a desktop computer.

[0215] In at least one embodiment, USB stick 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1430 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1430 comprises an application specific integrated circuit ("ASIC") optimized to perform any quantity and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1430 is a tensor processing unit ("TPC") optimized to perform machine vision inference operations. In at least one embodiment, processing unit 1430 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0216] In at least one embodiment, USB interface 1440 can be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 can include any amount and type of logic that enables processing unit 1430 to interface with a device (e.g., computer 1410) via USB connector 1440.

[0217] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 14 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0218] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may each be implemented by one or more computer systems, such as computer system 1410. In such an embodiment, client application 134 and / or server application 130 may be stored as instruction(s) on USB stick 1420.

[0219] FIG. 15A illustrates an exemplary architecture in which multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multicore processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values of which may vary from figure to figure.

[0220] Additionally, in at least one embodiment, two or more of the GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which may be implemented using similar or different protocols / links as used for the high-speed links 1540(1)-1540(N). Similarly, two or more of the multi-core processors 1505 may be connected via high-speed link 1528, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 15A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0221] In at least one embodiment, each multicore processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of illustration, and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of processor memory 1501 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0222] As described herein, various multicore processors 1505 and GPUs 1510 may each be physically coupled to specific memories 1501, 1520, and / or a unified memory architecture may be implemented in which a virtual system address space (also called an "effective address" space) is distributed among various physical memories. For example, processor memories 1501(1) through 1501(M) may each have a 64 GB system memory address space, and GPU memories 1520(1) through 1520(N) may each have a 32 GB system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values for N and M are possible.

[0223] 15B shows additional details of the interconnection between multi-core processor 1507 and graphics acceleration module 1546, according to one example embodiment. In at least one embodiment, graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to processor 1507 via high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1546 may alternatively be integrated into the package or chip with processor 1507.

[0224] In at least one embodiment, the processor 1507 includes multiple cores 1560A-1560D, each having a translation lookaside buffer (“TLB”) 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may comprise a level 1 (L1) cache and a level 2 (L2) cache. Additionally, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by the set of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more of the L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 interface with system memory 1514, which may include processor memories 1501(1) through 1501(M) of FIG. 15A.

[0225] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 via inter-core communication over coherence bus 1564. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith for communicating over coherence bus 1564 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1564 to snoop cache accesses.

[0226] In at least one embodiment, proxy circuit 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, which enables graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. In particular, in at least one embodiment, interface 1535 provides connectivity to proxy circuit 1525 over high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0227] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may alternatively comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU with multiple graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated into a common package, line card, or chip.

[0228] In at least one embodiment, accelerator integrated circuitry 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1538 may store commands and data for efficient access by graphics processing engines 1531(1)-1531(N). In at least one embodiment, data stored in cache 1538 and graphics memory 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556 and system memory 1514, possibly using fetch unit 1544. As noted, this may be accomplished via proxy circuitry 1525 on behalf of cache 1538 and memory 1533(1)-1533(M) (e.g., sending updates to and receiving updates from cache 1538 relating to modifications / accesses of cache lines in processor caches 1562A-1562D, 1556).

[0229] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and a context management circuit 1548 manages thread contexts. For example, the context management circuit 1548 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1548 may store current register values in a designated area in memory (e.g., identified by a context pointer). The context management circuit 1548 may then restore the register values when returning to the context. In at least one embodiment, the interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0230] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1531 are translated to real / physical addresses in the system memory 1514 by the MMU 1539. In at least one embodiment, the accelerator integration circuit 1536 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1546 may be dedicated to a single application running on the processor 1507 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1531(1)-1531(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0231] In at least one embodiment, the accelerator integrated circuitry 1536 acts as a bridge to the system for the graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuitry 1536 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1531(1)-1531(N).

[0232] In at least one embodiment, the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped into the real address space seen by host processor 1507, allowing any host processor to directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1536 is to physically separate graphics processing engines 1531(1)-1531(N) so that they appear as independent units to the system.

[0233] In at least one embodiment, one or more graphics memories 1533(1) through 1533(M) are coupled to each of the graphics processing engines 1531(1) through 1531(N), respectively, where N = M. In at least one embodiment, the graphics memories 1533(1) through 1533(M) store instructions and data being processed by each of the graphics processing engines 1531(1) through 1531(N). In at least one embodiment, the graphics memories 1533(1) through 1533(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0234] In at least one embodiment, to reduce data traffic over high-speed link 1540, biasing techniques may be used to ensure that the data stored in graphics memory 1533(1)-1533(M) will be most frequently used by graphics processing engines 1531(1)-1531(N) and preferably is data that is not used (or at least not frequently used) by cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (preferably not needed by graphics processing engines 1531(1)-1531(N)) in caches 1562A-1562D, 1556, and system memory 1514.

[0235] 15C shows another exemplary embodiment in which the accelerator integration circuitry 1536 is incorporated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly over high-speed link 1540 to the accelerator integration circuitry 1536 via interface 1537 and interface 1535 (which again may be any form of bus or interface protocol). In at least one embodiment, the accelerator integration circuitry 1536 may perform operations similar to those described with respect to FIG. 15B, but potentially at a higher throughput given its proximity to the coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1536 and a programming model controlled by the graphics acceleration module 1546.

[0236] In at least one embodiment, graphics processing engines 1531(1)-1531(N) may be dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may funnel other application requests to graphics processing engines 1531(1)-1531(N) to provide virtualization within a VM / partition.

[0237] In at least one embodiment, graphics processing engines 1531(1)-1531(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, graphics processing engines 1531(1)-1531(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0238] In at least one embodiment, graphics acceleration module 1546 or individual graphics processing engines 1531(1)-1531(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1514 and is addressable using the effective address-to-real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with graphics processing engines 1531(1)-1531(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0239] FIG. 15D illustrates an exemplary accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1536. In at least one embodiment, an application's effective address space 1582 in system memory 1514 stores a process element 1583. In at least one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. In at least one embodiment, the process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, a work descriptor (WD) 1584 included in the process element 1583 may be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the application's effective address space 1582.

[0240] In at least one embodiment, graphics acceleration module 1546 and / or individual graphics processing engines 1531(1)-1531(N) may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process state and submitting WD 1584 to graphics acceleration module 1546 to start jobs in a virtualized environment.

[0241] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1536 for the owning partition, and the operating system initializes the accelerator integration circuitry 1536 for the owning process when the graphics acceleration module 1546 is allocated.

[0242] In at least one embodiment, in operation, WD fetch unit 1591 in accelerator integrated slice 1590 fetches the next WD 1584, which contains instructions for work to be performed by one or more graphics processing engines of graphics acceleration module 1546. In at least one embodiment, as shown, data from WD 1584 is stored in registers 1545 and may be used by MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548. For example, one embodiment of MMU 1539 includes segment / page walk circuitry for accessing segment / page table 1586 within OS virtual address space 1585. In at least one embodiment, interrupt management circuitry 1547 may process interrupt events 1592 received from graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, effective addresses 1593 generated by graphics processing engines 1531(1)-1531(N) are translated into real addresses by MMU 1539.

[0243] In at least one embodiment, registers 1545 may be replicated for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. [Table 1]

[0244] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0245] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, WD 1584 contains all the information needed by graphics processing engine 1531(1)-1531(N) to perform work, or it may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0246] 15E illustrates additional details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 is accessible through a hypervisor 1596 that virtualizes a graphics acceleration module engine for an operating system 1595.

[0247] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0248] In at least one embodiment, in this model, system hypervisor 1596 owns graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, in order for graphics acceleration module 1546 to support virtualization by system hypervisor 1596, graphics acceleration module 1546 may adhere to several requirements, such as (1) an application's job requests must be autonomous (i.e., no state needs to be maintained between jobs) or graphics acceleration module 1546 must provide a context save and restore mechanism, (2) graphics acceleration module 1546 must guarantee that an application's job requests will complete in a specified amount of time, including any translation failures, or graphics acceleration module 1546 must provide the ability to preempt job processing, and (3) graphics acceleration module 1546 must ensure fairness between processes when operating in a specified shared programming model.

[0249] In at least one embodiment, application 1580 needs to make a system call to operating system 1596 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function of interest for the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for graphics acceleration module 1546 and may be in the form of a graphics acceleration module 1546 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by graphics acceleration module 1546.

[0250] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the accelerator integrated circuit 1536 (not shown) implementation and the graphics acceleration module 1546 implementation do not support a User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may optionally apply the current Authority Mask Override Register (AMOR) value before passing the AMR to the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of an area in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be preserved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be pinned system memory.

[0251] Upon receiving the system call, operating system 1595 may verify that application 1580 is registered and authorized to use graphics acceleration module 1546. In at least one embodiment, operating system 1595 then calls hypervisor 1595 with the information shown in Table 3. [Table 3]

[0252] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1596 verifies that the operating system 1595 is registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the hypervisor 1596 then places the process element 1583 in a process element linked list for the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0253] In at least one embodiment, the hypervisor initializes a number of accelerator integration slice 1590 registers 1545 .

[0254] As shown in FIG. 15F, at least one embodiment uses a unified memory addressable via a common virtual memory address space used to access physical processor memory 1501(1)-1501(N) and GPU memory 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access processor memory 1501(1)-1501(N), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion is allocated to second processor memory 1501(N), a third portion is allocated to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1501 and the GPU memory 1520, allowing either processor or GPU to access either physical memory where the virtual addresses are mapped to physical memory.

[0255] In at least one embodiment, bias / coherence management circuitry 1594A-1594E within one or more of the MMUs 1539A-1539E ensures cache coherence between caches of one or more host processors (e.g., 1505) and caches of the GPU 1510 and implements biasing techniques to indicate the physical memory in which some types of data should be stored. In at least one embodiment, although multiple instances of bias / coherence management circuitry 1594A-1594E are shown in FIG. 15F, bias / coherence circuitry may be implemented within the MMUs of one or more host processors 1505 and / or within the accelerator integration circuit 1536.

[0256] One embodiment allows GPU memory 1520 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, but without the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1520 as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this mechanism allows host processor 1505 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead can be essential to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1510. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offload.

[0257] In at least one embodiment, the selection of the GPU bias and the host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, and the bias table may be a page-granular structure containing one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1520, with or without a bias cache in GPU 1510 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0258] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 1520 is accessed prior to the actual access to the GPU memory, causing the following actions: In at least one embodiment, a local request from the GPU 1510 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1505 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1505 that finds the requested page in the host processor bias completes the request like a normal memory read. Alternatively, a request targeting a GPU-biased page may be forwarded to the GPU 1510. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0259] In at least one embodiment, one mechanism for changing the bias state employs an API call (e.g., OpenCL) that calls a GPU device driver, which sends a message (or queues a command descriptor) to the GPU instructing the GPU to change the bias state and, for some transitions, to perform a cache flushing operation at the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1505 bias to GPU bias, but not for transitions in the opposite direction.

[0260] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1505. In at least one embodiment, to access these pages, the processor 1505 may request access from the GPU 1510, which may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that GPU-biased pages are those that are needed by the GPU but not by the host processor 1505, and vice versa.

[0261] To implement one or more embodiments, hardware structure(s) 715 are used, and details regarding the hardware structure(s) 715 may be provided herein in conjunction with Figures 7A and / or 7B.

[0262] 16 illustrates an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0263] 16 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1600 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1600 includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I / O controller 1640. 2 2S / I 2 The integrated circuit 1600 may include peripheral or bus logic including a HDMI (High-Definition Multimedia Interface) controller 1640. In at least one embodiment, the integrated circuit 1600 may include a display device 1645 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for access to an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1670.

[0264] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in integrated circuit 1600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0265] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may each be implemented at least in part by one or more integrated circuits, such as integrated circuit 1600. In such an embodiment, client application 134 and / or server application 130 may be stored as instruction(s) in memory (not shown), accessed by memory controller 1665 and executed by application processor(s) 1605. Display device 116 and / or display device(s) 118 may be implemented by display device 1645. Additionally, computing devices 112, 114, and / or 132 may communicate with other components of system 100 (see FIG. 1 ) over network 110 (see FIG. 1 ) using UART controller 1630. Video capture device 106 and / or video capture device(s) 108 (see FIG. 1) may be connected (e.g., by USB controller 1625) to application processor(s) 1605, which may receive video signals therefrom.

[0266] 17A-17B illustrate an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0267] 17A and 17B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 17A illustrates an exemplary graphics processor 1710 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 17B illustrates an additional exemplary graphics processor 1740 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1710 of FIG. 17A is a low-power graphics processor core. In at least one embodiment, graphics processor 1740 of FIG. 17B is a higher-performance graphics processor core. In at least one embodiment, each of graphics processors 1710, 1740 may be a variation of graphics processor 1610 of FIG. 16.

[0268] In at least one embodiment, graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D-1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 can execute different shader programs through separate logic, whereby vertex processor 1705 is optimized to perform operations for vertex shader programs, and one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1705 performs the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processor(s) 1715A-1715N use the primitive and vertex data generated by vertex processor 1705 to create a frame buffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1715A-1715N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0269] In at least one embodiment, graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, cache(s) 1725A-1725B, and circuit interconnect(s) 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mapping for graphics processor 1710, including vertex processor 1705 and / or fragment processor(s) 1715A-1715N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1605, image processor 1615, and / or video processor 1620 of Figure 16, thereby allowing each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable graphics processor 1710 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0270] 17B, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F-1755N-1, and 1755N), where the one or more shader cores 1755A-1755N provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A-1755N, and a tiling unit 1758 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0271] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in integrated circuits 17A and / or 17B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0272] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may include graphics processor 1710 and / or graphics processor 1740. In such an embodiment, graphics processor 1710 may execute at least a portion of client application 134 (see FIG. 1 ) and / or server application 130 (see FIG. 1 ) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0273] 18A-18B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 18A illustrates a graphics core 1800, which, in at least one embodiment, may be included within graphics processor 1610 of FIG. 16, or, in at least one embodiment, may be unified shader cores 1755A-1755N as in FIG. 17B. FIG. 18B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU") 1830, which, in at least one embodiment, may be suitable for deployment on a multi-chip module.

[0274] In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820, which are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1801A-1801N, or partitions for each core, and a graphics processor may include multiple instances of graphics core 1800. In at least one embodiment, slices 1801A-1801N may include support logic including local instruction caches 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and sets of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional function units (AFUs) 1812A-1812N, floating-point units (FPUs) 1814A-1814N, integer arithmetic logic units (ALUs) 1816-1816N, address computational units (ACUs) 1813A-1813N, double-precision floating-point units (DPFPUs) 1815A-1815N, and matrix processing units (MPUs) 1817A-1817N.

[0275] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0276] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in graphics core 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0277] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may include a graphics core 1800. In such an embodiment, graphics core 1800 may execute at least a portion of client application 134 (see FIG. 1 ) and / or server application 130 (see FIG. 1 ) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0278] FIG. 18B illustrates a general-purpose processing unit (GPGPU) 1830, which, in at least one embodiment, can be configured to enable highly parallel compute operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 to enable connection with a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and, using a global scheduler 1834, distributes execution threads associated with those commands across a set of compute clusters 1836A-1836H. In at least one embodiment, the compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, the cache memory 1838 can act as a higher level cache for the cache memories within the compute clusters 1836A-1836H.

[0279] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0280] In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as graphics core 1800 of FIG. 18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, and a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0281] In at least one embodiment, multiple instances of GPGPU 1830 may be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1836A-1836H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate via host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to a GPU link 1840 that enables direct connection to other instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate data processing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU link 1840 may be configured to allow connection to a host processor in addition to, or as an alternative to, host interface 1832.

[0282] In at least one embodiment, the GPGPU 1830 may be configured to train a neural network. In at least one embodiment, the GPGPU 1830 may be used within an inference platform. In at least one embodiment, when the GPGPU 1830 is used for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H than when the GPGPU 1830 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B may differ between the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 may support inference-specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which may be used during inference operations for the deployed neural network.

[0283] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in GPGPU 1830 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0284] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1) may include a GPGPU 1830. In such an embodiment, GPGPU 1830 may execute at least a portion of client application 134 (see FIG. 1) and / or server application 130 (see FIG. 1) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0285] FIG. 19 is a block diagram illustrating a computing system 1900, according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 that communicate via interconnect paths that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be incorporated within the one or more processors 1902. In at least one embodiment, the memory hub 1905 couples to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that may enable the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 may enable a display controller, which may be included in the one or more processors 1902, to provide output to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A coupled with I / O hub 1907 may include local, internal, or embedded display devices.

[0286] In at least one embodiment, processing subsystem 1901 includes one or more parallel processors 1912 coupled to memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, communication link 1913 may use one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1912 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of the parallel processor(s) 1912 form a graphics processing subsystem, which can output pixels to one of one or more display devices 1910A coupled via I / O hub 1907. In at least one embodiment, the parallel processor(s) 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B.

[0287] In at least one embodiment, a system storage unit 1914 may connect to an I / O hub 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface mechanism to enable connections between the I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919, which may be embedded in the platform, as well as various other devices that may be added via one or more add-in devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0288] In at least one embodiment, computing system 1900 may include other components not expressly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may be connected to I / O hub 1907. In at least one embodiment, the communication paths interconnecting the various components in FIG. 19 may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol(s), or interconnection protocol, such as an NV-Link high-speed interconnect.

[0289] In at least one embodiment, the parallel processor(s) 1912 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, to form a graphics processing unit (GPU). In at least one embodiment, the parallel processor(s) 1912 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 1912, memory hub 1905, processor(s) 1902, and I / O hub 1907 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1900 may be incorporated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0290] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in computing system 1900 of Figure 19 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0291] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may each be implemented, at least in part, by one or more computing systems, such as computing system 1900. In such an embodiment, client application 134 and / or server application 130 may be stored as instruction(s) in system memory 1904 accessed by memory hub 1905 and executed by processor(s) 1902 and / or parallel processor(s) 1912. Display device 116 and / or display device(s) 118 may be implemented by display device(s) 1910. Additionally, computing devices 112, 114, and / or 132 may use network adapter 1918 and / or wireless network adapter 1919 to communicate with other components of system 100 (see FIG. 1 ) via network 110 (see FIG. 1 ). Video capture device 106 and / or video capture device(s) 108 (see FIG. 1) may be connected (e.g., as input device 1908) to processor(s) 1902 and / or parallel processor(s) 1912, from which they may receive video signals.

[0292] Processor 20A illustrates a parallel processor 2000, according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2000 is a variation of one or more parallel processors 1912 illustrated in FIG. 19, according to an example embodiment.

[0293] In at least one embodiment, parallel processor 2000 includes parallel processing units 2002. In at least one embodiment, parallel processing units 2002 include I / O units 2004 that enable communication with other devices, including other instances of parallel processing units 2002. In at least one embodiment, I / O units 2004 may be directly connected to other devices. In at least one embodiment, I / O units 2004 connect to other devices through the use of a hub or switch interface, such as memory hub 2005. In at least one embodiment, the connection between memory hub 2005 and I / O units 2004 forms communication link 2013. In at least one embodiment, I / O units 2004 connect to host interface 2006 and memory crossbar 2016, where host interface 2006 receives commands intended to perform processing operations and memory crossbar 2016 receives commands intended to perform memory operations.

[0294] In at least one embodiment, when host interface 2006 receives command buffers via I / O unit 2004, host interface 2006 can direct work operations to implement those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to distribute commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in a valid state before tasks are distributed to clusters in processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, allowing rapid preemption and context switching of threads executing on the processing array 2012. In at least one embodiment, host software can present workloads for scheduling on the processing cluster array 2012 via one of multiple graphics processing paths. In at least one embodiment, the workloads can then be automatically distributed across the processing array clusters 2012 by scheduler 2010 logic in the microcontroller that includes the scheduler 2010.

[0295] In at least one embodiment, processing cluster array 2012 can include up to “N” processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N), where “N” represents a positive integer (it may be a different integer “N” than used in other figures). In at least one embodiment, each cluster 2014A through 2014N of processing cluster array 2012 can execute multiple concurrent threads. In at least one embodiment, scheduler 2010 can allocate work to clusters 2014A through 2014N of processing cluster array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload occurring for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2010 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 may be allocated to process different types of programs or perform different types of calculations.

[0296] In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0297] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0298] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data produced by one or more of the clusters 2014A-2014N may be stored in a buffer to allow the intermediate data to be transmitted between the clusters 2014A-2014N for further processing.

[0299] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be performed via a scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, the processing tasks may include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, the scheduler 2010 may be configured to fetch the index corresponding to the task or may receive the index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0300] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via memory crossbar 2016, which may receive memory requests from processing cluster array 2012 as well as I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 may include multiple partition units (e.g., partition unit 2020A, partition unit 2020B through partition unit 2020N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 2022. In at least one embodiment, the number of partition units 2020A-2020N is configured to be equal to the number of memory units, such that a first partition unit 2020A has a corresponding first memory unit 2024A, a second partition unit 2020B has a corresponding memory unit 2024B, and an Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0301] In at least one embodiment, the memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2022, render targets, such as frame buffers or texture maps, may be stored across the memory units 2024A-2024N, allowing the partition units 2020A-2020N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2022 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0302] In at least one embodiment, any one of the clusters 2014A-2014N of the processing cluster array 2012 can process data that is to be written to any one of the memory units 2024A-2024N in the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to forward the output of each cluster 2014A-2014N to any partition unit 2020A-2020N that can perform additional processing operations on the output, or to another cluster 2014A-2014N. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has a connection to a memory interface 2018 for communicating with the I / O units 2004, as well as a connection to local instances of parallel processor memory 2022, which allows processing units in different processing clusters 2014A-2014N to communicate with system memory or other memory not local to the parallel processing units 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to separate traffic streams between the clusters 2014A-2014N and the partition units 2020A-2020N.

[0303] In at least one embodiment, multiple instances of parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2002 may include a higher precision floating-point unit relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0304] FIG. 20B is a block diagram of a partition unit 2020, according to at least one embodiment. In at least one embodiment, the partition unit 2020 is an instance of one of the partition units 2020A-2020N of FIG. 20A. In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache configured to perform load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, read misses and urgent writeback requests are output by the L2 cache 2021 to the frame buffer interface 2025 for processing. In at least one embodiment, updates may also be sent to the frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, frame buffer interface 2025 interfaces with one of the memory units in a parallel processor memory, such as memory units 2024A-2024N (e.g., in parallel processor memory 2022) of FIG.

[0305] In at least one embodiment, ROP2026 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2026 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2026 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP2026 may vary based on statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0306] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., clusters 2014A-2014N of FIG. 20A ) rather than within partition unit 2020. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2016. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1910 of FIG. 19 , routed for further processing by processor(s) 1902, or routed for further processing by one of the processing entities in parallel processor 2000 of FIG. 20A .

[0307] FIG. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit, according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2014A-2014N of FIG. 20A. In at least one embodiment, the processing cluster 2014 may be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single-instruction, multiple-data (SIMD) instruction issue technique is used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, a single-instruction, multiple-thread (SIMT) technique is used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster of the processing cluster.

[0308] In at least one embodiment, operation of the processing cluster 2014 may be controlled via a pipeline manager 2032 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of FIG. 20A and manages the execution of those instructions via the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included in the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included in the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed through the data crossbar 2040.

[0309] In at least one embodiment, each graphics multiprocessor 2034 in a processing cluster 2014 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, such that new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and the computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0310] In at least one embodiment, instructions sent to a processing cluster 2014 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in the graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2034, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 2034.

[0311] In at least one embodiment, the graphics multiprocessor 2034 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 can forgo the internal cache and use cache memory (e.g., L1 cache 2048) within the processing cluster 2014. In at least one embodiment, each graphics multiprocessor 2034 also has access to an L2 cache within a partition unit (e.g., partition units 2020A-2020N in FIG. 20A ), which is shared among all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 may include multiple instances of the graphics multiprocessor 2034 and share common instructions and data, which may be stored in the L1 cache 2048.

[0312] In at least one embodiment, each processing cluster 2014 may include an MMU 2045 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside in memory interface 2018 of FIG. 20A . In at least one embodiment, MMU 2045 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, MMU 2045 may include an address translation lookaside buffer (TLB) or cache, which may reside in graphics multiprocessor 2034, L1 cache 2048, or processing cluster 2014. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0313] In at least one embodiment, the processing cluster 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to the data crossbar 2040 to provide the processed tasks to another processing cluster 2014 for further processing, or to store the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 2016. In at least one embodiment, a pre-ROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to the ROP unit, which may be co-located with a partition unit as described herein (e.g., partition units 2020A-2020N in FIG. 20A ). In at least one embodiment, the pre-ROP 2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0314] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in graphics processing cluster 2014 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0315] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1) may include a parallel processor 2000 and related components illustrated in FIGURES 20A-20C. In such an embodiment, parallel processor 2000 may execute at least a portion of client application 134 (see FIGURE 1) and / or server application 130 (see FIGURE 1) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0316] 20D illustrates a graphics multiprocessor 2034, according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 couples with the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline that includes, but is not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066. In at least one embodiment, the GPGPU cores 2062 and the load / store units 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068.

[0317] In at least one embodiment, instruction cache 2052 receives a stream of instructions to execute from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched for execution by instruction unit 2054. In at least one embodiment, instruction unit 2054 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2056 can be used to translate addresses in the unified address space into individual memory addresses that can be accessed by load / store unit 2066.

[0318] In at least one embodiment, register file 2058 provides a set of registers to the functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU core 2062, load / store unit 2066) of graphics multiprocessor 2034. In at least one embodiment, register file 2058 is partitioned among each of the functional units such that each functional unit is allocated a dedicated portion of register file 2058. In one embodiment, register file 2058 is partitioned among the different warps being executed by graphics multiprocessor 2034.

[0319] In at least one embodiment, the GPGPU cores 2062 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be of similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement IEEE 754-2008 standard floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed or special-function logic.

[0320] In at least one embodiment, GPGPU core 2062 includes SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2062 physically executes SIMD4, SIMD8, and SIMD16 instructions and logically executes SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0321] In at least one embodiment, memory and cache interconnect 2068 is an interconnect network connecting each functional unit of graphics multiprocessor 2034 to register file 2058 and shared memory 2070. In at least one embodiment, memory and cache interconnect 2068 is a crossbar interconnect that allows load / store unit 2066 to implement load and store operations between shared memory 2070 and register file 2058. In at least one embodiment, register file 2058 can operate at the same frequency as GPGPU cores 2062, and therefore data transfers between GPGPU cores 2062 and register file 2058 can have very low latency. In at least one embodiment, shared memory 2070 can be used to enable communication between threads executing on functional units within graphics multiprocessor 2034. In at least one embodiment, cache memory 2072 can be used as a data cache, for example, to cache texture data communicated between functional units and texture unit 2036. In at least one embodiment, shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2062 can programmatically store data in the shared memory in addition to the automatically cached data stored in cache memory 2072.

[0322] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into a package or chip as a core and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, a processor core may allocate work to such a GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0323] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in graphics multiprocessor 2034 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0324] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1) may include parallel processor 2000 (see FIG. 20A) and related components illustrated in FIGs. 20A-20D. In such an embodiment, parallel processor 2000 may execute at least a portion of client application 134 (see FIG. 1) and / or server application 130 (see FIG. 1) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0325] FIG. 21 illustrates a multi-GPU computing system 2100, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2100 may include a processor 2102 coupled to multiple general-purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, the host interface switch 2104 is a PCI Express switch device that couples the processor 2102 to a PCI Express bus, via which the processor 2102 can communicate with the GPGPUs 2106A-D. In at least one embodiment, the GPGPUs 2106A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2116. In at least one embodiment, the GPU-to-GPU links 2116 connect to each of the GPGPUs 2106A-D via a dedicated GPU link. In at least one embodiment, P2P GPU link 2116 enables direct communication between each of GPGPUs 2106A-D without requiring communication via host interface bus 2104 to which processor 2102 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to P2P GPU link 2116, host interface bus 2104 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2100, for example, via one or more network devices. In at least one embodiment, GPGPUs 2106A-D connect to processor 2102 via host interface switch 2104, and in at least one embodiment, processor 2102 includes direct support for P2P GPU link 2116 and can connect directly to GPGPUs 2106A-D.

[0326] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the multi-GPU computing system 2100 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0327] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may include a multi-GPU computing system 2100. In such an embodiment, multi-GPU computing system 2100 may execute at least a portion of client application 134 (see FIG. 1 ) and / or server application 130 (see FIG. 1 ) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0328] 22 is a block diagram of a graphics processor 2200, according to at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors incorporated within a multi-core processing system.

[0329] In at least one embodiment, graphics processor 2200 receives batches of commands via ring interconnect 2202. In at least one embodiment, the incoming commands are interpreted by command streamer 2203 in pipeline front end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, command streamer 2203 supplies the commands to geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, command streamer 2203 supplies the commands to video front end 2234, which couples to media engine 2237. In at least one embodiment, the media engine 2237 includes a Video Quality Engine (VQE) 2230 for video and image post-processing and a multi-format encode / decode (MFX) 2233 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each spawn execution threads for thread execution resources provided by at least one graphics core 2280.

[0330] In at least one embodiment, graphics processor 2200 includes scalable thread execution resources characterized by graphics cores 2280A-2280N (which may be modular and sometimes referred to as core slices), each having multiple sub-cores 2250A-2250N, 2260A-2260N (which may also be referred to as core sub-slices). In at least one embodiment, graphics processor 2200 can have any number of graphics cores 2280A. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, graphics processor 2200 is a low-power processor with a single sub-core (e.g., 2250A). In at least one embodiment, graphics processor 2200 includes multiple graphics cores 2280A-2280N, each including a first set of sub-cores 2250A-2250N and a second set of sub-cores 2260A-2260N. In at least one embodiment, each sub-core in the first sub-cores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each sub-core in the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0331] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in graphics processor 2200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0332] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may include a graphics processor 2200. In such an embodiment, graphics processor 2200 may execute at least a portion of client application 134 (see FIG. 1 ) and / or server application 130 (see FIG. 1 ) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0333] FIG. 23 is a block diagram illustrating a microarchitecture for a processor 2300 that may include logic circuits for implementing instructions, according to at least one embodiment. In at least one embodiment, the processor 2300 may implement instructions including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), and the like. In at least one embodiment, the processor 2300 may include registers for storing packed data, such as 64-bit wide MMX™ registers in MMX technology-enabled microprocessors from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2300 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0334] In at least one embodiment, processor 2300 includes an in-order front end (“front end”) 2301 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2301 may include several units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and feeds the instructions to an instruction decoder 2328, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2328 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”), that the machine can execute. In at least one embodiment, instruction decoder 2328 parses instructions into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2330 may assemble decoded uops into program-order sequences, or traces, for execution in uop queue 2334. In at least one embodiment, when trace cache 2330 encounters a complex instruction, microcode ROM 2332 provides the uops necessary to complete the operation.

[0335] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to implement the instruction. In at least one embodiment, an instruction may be decoded into a fewer number of micro-ops for processing in the instruction decoder 2328. In at least one embodiment, an instruction may be stored in the microcode ROM 2332 if several micro-ops are required to accomplish such an operation. In at least one embodiment, the trace cache 2330 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2332, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2332 finishes sequencing micro-ops for an instruction, the machine front end 2301 may resume fetching micro-ops from the trace cache 2330.

[0336] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2303 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth the flow of instructions and reorder them to optimize performance as they move down the pipeline and are scheduled for execution. In at least one embodiment, out-of-order execution engine 2303 includes, but is not limited to, allocator / register renamer 2340, memory uop queue 2342, integer / floating point uop queue 2344, memory scheduler 2346, fast scheduler 2303, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2304, and simple floating point scheduler ("simple FP scheduler") 2306. In at least one embodiment, fast scheduler 2302, slow / general purpose floating point scheduler 2304, and simple floating point scheduler 2306 are also collectively referred to herein as "uop schedulers 2303, 2304, 2306." In at least one embodiment, allocator / register renamer 2340 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2340 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2340 also allocates an entry for each uop in one of two uop queues: memory uop queue 2342 for memory operations and integer / floating point uop queue 2344 for non-memory operations, before memory scheduler 2346 and uop schedulers 2302, 2304, 2306. In at least one embodiment, uop schedulers 2302, 2304, 2306 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 2302 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2304 and simple floating point scheduler 2306 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2302, 2304, 2306 arbitrate for dispatch ports to schedule uops for execution.

[0337] In at least one embodiment, execution block 2311 includes, but is not limited to, integer register file / bypass network 2308, floating point register file / bypass network (“FP register file / bypass network”) 2310, address generation units (“AGUs”) 2312 and 2314, fast arithmetic logic units (ALUs) (“fast ALUs”) 2316 and 2318, slower arithmetic logic unit (“slower ALU”) 2320, floating point ALU (“FP”) 2322, and floating point move unit (“FP move”) 2324. In at least one embodiment, integer register file / bypass network 2308 and floating point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310.” In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating-point ALU 2322, and floating-point move unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324." In at least one embodiment, execution block 2311 may include any number and type of register files, bypass networks, address generation units, and execution units (including, but not limited to, zero), in any combination.

[0338] In at least one embodiment, register networks 2308, 2310 may be disposed between uop schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating point register file / bypass network 2310 performs floating point operations. In at least one embodiment, each of register networks 2308, 2310 may include, but is not limited to, a bypass network, which may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register networks 2308, 2310 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2308 may include, but is not limited to, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64 to 128 bits wide, so floating-point register file / bypass network 2310 may include, but is not limited to, 128-bit wide entries.

[0339] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324 may execute instructions. In at least one embodiment, register networks 2308 and 2310 store integer and floating-point data operand values required by microinstructions to execute. In at least one embodiment, processor 2300 may include any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 may execute floating-point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2322 may include a 64-bit floating-point divider for performing, but not limited to, division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2316, 2318. In at least one embodiment, the high-speed ALUs 2316, 2318 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2320 may include integer execution hardware for long-latency type operations such as, but not limited to, multipliers, shifts, flag logic, and branching, so that most complex integer operations proceed to the low-speed ALU 2320. In at least one embodiment, memory load / store operations may be performed by the AGUs 2312, 2314. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 may be implemented to support various operands having various bit widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0340] In at least one embodiment, the uop schedulers 2302, 2304, 2306 dispatch dependent operations before the parent load finishes executing. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2300, the processor 2300 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0341] In at least one embodiment, a "register" may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0342] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or FIG. 7B . In at least one embodiment, portions or all of the inference and / or training logic 715 may be incorporated into the execution block 2311 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the execution block 2311. Moreover, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2311 for implementing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0343] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may include a processor 2300. In such an embodiment, processor 2300 may execute at least a portion of client application 134 (see FIG. 1 ) and / or server application 130 (see FIG. 1 ) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0344] 24 illustrates a deep learning application processor 2400, according to at least one embodiment. In at least one embodiment, the deep learning application processor 2400 uses instructions that, when executed by the deep learning application processor 2400, cause the deep learning application processor 2400 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2400 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2400 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2400 includes, but is not limited to, processing clusters 2410(1)-2410(12), inter-chip links ("ICL") 2420(1)-2420(12), inter-chip controllers ("ICC") 2430(1)-2430(2), high-bandwidth memory second generation ("HBM2") 2440(1)-2440(4), memory controllers ("Mem Ctrlr") 2442(1)-2442(4), and high-bandwidth memory physical layer ("HBM PHY") 2440(1)-2440(4). layer) 2444(1) to 2444(4), a management-controller central processing unit ("management-controller CPU") 2450, and serial peripheral interfaces, inter-integrated circuit, and general-purpose input / output ("SPI, I 2C, GPIO": Serial Peripheral Interface, Inter-Integrated Circuit, and General Purpose Input / Output) block 2460, Peripheral Component Interconnect Express Controller and Direct Memory Access ("PCIe Controller and DMA") block 2470, and 16-lane Peripheral Component Interconnect Express Port ("PCI Express x16") 2480.

[0345] In at least one embodiment, the processing clusters 2410 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 2400 may include any number and types of processing clusters 2400. In at least one embodiment, the inter-chip link 2420 is bidirectional. In at least one embodiment, the inter-chip link 2420 and the inter-chip controller 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information resulting from implementing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2400 may include any number and types (including zero) of ICLs 2420 and ICCs 2430.

[0346] In at least one embodiment, the HBM2 2440 provides a total of 32 Gigabytes (GB) of memory. In at least one embodiment, an HBM2 2440(i) is associated with both a memory controller 2442(i) and an HBM PHY 2444(i), where "i" is any integer. In at least one embodiment, any number of HBM2s 2440 may provide any type and total amount of high-bandwidth memory and may be associated with any number and type of memory controllers 2442 and HBM PHYs 2444 (including zero). In at least one embodiment, the SPI, I 2 C, GPIO 2460, PCIe controller and DMA 2470, and / or PCIe 2480 may be replaced with any number and types of blocks that enable any number and types of communication standards in any technically feasible manner.

[0347] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or FIG. 7B . In at least one embodiment, the deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2400. In at least one embodiment, the deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) trained by another processor or system or by the deep learning application processor 2400. In at least one embodiment, the processor 2400 may be used to implement one or more neural network use cases described herein.

[0348] In at least one embodiment, one or more of computing devices 112, 114, and 132 (see FIG. 1 ) may include a deep learning application processor 2400. In such an embodiment, deep learning application processor 2400 may execute at least a portion of client application 134 (see FIG. 1 ) and / or server application 130 (see FIG. 1 ) and / or perform one or more functions initiated by client application 134 and / or server application 130.

[0349] FIG. 25 is a block diagram of a neuromorphic processor 2500, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2500 may receive one or more inputs from sources external to the neuromorphic processor 2500. In at least one embodiment, these inputs may be sent to one or more neurons 2502 within the neuromorphic processor 2500. In at least one embodiment, the neurons 2502 and their components may be implemented using circuit elements or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, thousands or millions of instances of neurons 2502, although any suitable number of neur...

Claims

1. determining a plurality of first facial landmarks for each of two or more faces depicted in a first frame of the video segment; determining a plurality of second facial landmarks for each of the two or more faces depicted in a second frame of the video segment; identifying a speaking face among the two or more faces based at least in part on the plurality of first facial landmarks and the plurality of second facial landmarks, the speaking face being usable to modify the video segment by enlarging the speaking face in the second frame; Including, The step of identifying a speaking face comprises: assigning confidence values to the plurality of first facial landmarks and the plurality of second facial landmarks; reducing the contribution of features corresponding to the plurality of first facial landmarks and the plurality of second facial landmarks having low confidence values, and / or increasing the contribution of features corresponding to the plurality of first facial landmarks and the plurality of second facial landmarks having higher confidence values; Including, Computer-implemented methods.

2. detecting, within the first frame of the video segment, a plurality of first regions each corresponding to a different face of the two or more faces, wherein the plurality of first facial landmarks determined for each of the two or more faces are determined within a corresponding first region of the plurality of first regions; detecting, within the second frame of the video segment, a plurality of second regions each corresponding to a different face of the two or more faces, wherein the plurality of second facial landmarks determined for each of the two or more faces are determined within a corresponding second region of the plurality of second regions; The computer-implemented method of claim 1 , further comprising:

3. a portion of the plurality of first facial landmarks determined for each of the two or more faces being first lip landmarks, a portion of the plurality of second facial landmarks determined for each of the two or more faces being second lip landmarks, and the step of identifying a speaking face includes: generating a flow vector for each of the two or more faces using the position of the first lip landmark determined for the face and the position of the second lip landmark determined for the face; classifying the flow vectors generated for each of the two or more faces as indicating that speech activity has or has not occurred; identifying one of the two or more faces whose flow vectors are classified as indicating that speech activity has occurred as the speaking face; The computer-implemented method of claim 1 , further comprising:

4. modifying the second frame by enlarging the speaking face in the second frame, the second frame having an image resolution; enlarging the speaking face in the second frame, including creating an upscaled image by upscaling the speaking face to the image resolution; replacing the second frame with the upscaled image; The computer-implemented method of claim 1 , further comprising:

5. The computer-implemented method of claim 4 , wherein a deep learning model is used to upscale the speaking face to the image resolution.

6. The step of identifying a speaking face comprises: determining that at least a moving second facial landmark of the plurality of second facial landmarks has changed position relative to one or more of the plurality of first facial landmarks; The computer-implemented method of claim 1 , further comprising:

7. wherein identifying the speaking face further comprises determining that the moving second facial landmark has moved relative to a non-corresponding first facial landmark among the plurality of first facial landmarks; the moving second facial landmark corresponds to a corresponding first facial landmark among the plurality of first facial landmarks; the moving second facial landmark and the corresponding first facial landmark each represent a first lip of a lip pair; the non-corresponding first facial landmark represents a second lip of the pair of lips; The computer-implemented method of claim 6 , wherein the first lip is different from the second lip.

8. determining that the moving second facial landmark has changed position relative to the one or more first facial landmarks, determining a rate at which the moving second facial landmark changes position relative to the one or more first facial landmarks; when the rate exceeds a threshold, concluding that the moving second facial landmark has changed position relative to the one or more first facial landmarks; The computer-implemented method of claim 6 , comprising:

9. modifying the second frame by enlarging the speaking face in the second frame; transmitting the modified video segment to a receiving computing system for display thereby; The computer-implemented method of claim 1 , further comprising:

10. The computer-implemented method is performed by a computing system comprising a sending computing system and a receiving computing system, the method comprising: obtaining, by the sending computing system, the video segment; transmitting, by the sending computing system, the video segment to the receiving computing system, wherein the receiving computing system determines the plurality of first facial landmarks and the plurality of second facial landmarks, identifies the speaking face, and modifies the video segment; displaying, by the receiving computing system, the modified video segment; The computer-implemented method of claim 1 , further comprising:

11. receiving, by the receiving computing system, user input indicating an amount of magnification, wherein the receiving computing system modifies the video segment by magnifying the speaking face by the amount of magnification. The computer-implemented method of claim 10 further comprising:

12. The computer-implemented method is performed by a computing system comprising a sending computing system and a receiving computing system, the method comprising: receiving the video segment by the sending computing system, wherein the sending computing system determines the plurality of first facial landmarks and the plurality of second facial landmarks to identify the speaking face; transmitting, by the sending computing system, the video segment and an identification of the speaking face to the receiving computing system, wherein the receiving computing system modifies the video segment based at least in part on the identification of the speaking face; displaying, by the receiving computing system, the modified video segment; The computer-implemented method of claim 1 , further comprising:

13. 1. One or more processors for identifying a speaking first conferee of a plurality of first conferees on a first side of a video conference conducted with a second conferee on a second side of the video conference using one or more neural networks, wherein identifying the speaking first conferee comprises: identifying a first image region for each of the plurality of first conference participants in a first frame of the video conference and a second image region for each of the plurality of first conference participants in a second frame of the video conference; determining one or more first facial landmarks within the identified first image region for each of the plurality of first conference participants and one or more second facial landmarks within the identified second image region for each of the plurality of first conference participants; identifying the speaking first conference participant based at least in part on the one or more first facial landmarks determined for each of the plurality of first conference participants and the one or more second facial landmarks determined for each of the plurality of first conference participants; Including, The step of identifying a first speaking conference participant comprises: assigning confidence values to the one or more first facial landmarks and the one or more second facial landmarks; reducing the contribution of features corresponding to the one or more first facial landmarks and the one or more second facial landmarks with low confidence values, and / or increasing the contribution of features corresponding to the one or more first facial landmarks and the one or more second facial landmarks with higher confidence values; one or more processors, one or more memories for storing parameters corresponding to said one or more neural networks; A system comprising:

14. modifying the second frame by enlarging the second image region identified for the speaking first conference participant in the second frame; The system of claim 13 further comprising:

15. the one or more neural networks: at least one neural network trained to magnify the second image region identified for the speaking first conference participant; The system of claim 14 , comprising:

16. the one or more neural networks: at least one neural network trained to identify the first image region for each of the plurality of first conference participants in the first frame of the video conference and to identify the second image region for each of the plurality of first conference participants in the second frame of the video conference; The system of claim 13 , comprising:

17. the one or more neural networks: at least one neural network trained to determine the one or more first facial landmarks in the first image region identified for each of the plurality of first conference participants and the one or more second facial landmarks in the second image region identified for each of the plurality of first conference participants; The system of claim 13 , comprising:

18. The step of identifying a first speaking conference participant comprises: using at least one heuristic to determine that at least one of the one or more first facial landmarks determined for the speaking first conference participant has moved relative to at least one of the one or more second facial landmarks determined for the speaking first conference participant. The system of claim 13 , comprising:

19. the one or more neural networks: at least one first neural network trained to identify the speaking first conference participant based at least in part on the one or more first facial landmarks determined for each of the plurality of first conference participants and the one or more second facial landmarks determined for each of the plurality of first conference participants; The system of claim 13 , comprising:

20. When implemented by one or more processors, the one or more processors are configured to perform at least: acquiring a plurality of frames each depicting a plurality of first conference participants participating in a video conference, the plurality of first conference participants sharing a common physical location; detecting image regions in each of the plurality of frames depicting faces of the plurality of first conference participants; determining facial landmarks within each of the image regions; identifying a speaking first conference participant of the plurality of first conference participants in a subset of image regions based at least in part on the facial landmarks, the subset of image regions each detected in a corresponding frame of a subset of the plurality of frames, each of the subsets of the plurality of frames being modifiable by enlarging an image region of the subset of image regions detected in the frame; A machine-readable medium having stored thereon a set of instructions for causing a The step of identifying a first speaking conference participant comprises: assigning confidence values to the facial landmarks; reducing the contribution of features corresponding to the facial landmarks with low confidence values and / or increasing the contribution of features corresponding to the facial landmarks with higher confidence values.

1. A machine-readable medium comprising:

21. 21. The machine-readable medium of claim 20, wherein the set of instructions, when executed by the one or more processors, causes the one or more processors to modify each of the subsets of the plurality of frames by enlarging the image regions of the subset of the image regions detected in the frame.

22. 22. The machine-readable medium of claim 21, wherein the set of instructions, when executed by the one or more processors, cause the one or more processors to transmit each of the plurality of frames to at least one second conference participant after each of the subset of the plurality of frames is modified.

23. 21. The machine-readable medium of claim 20, wherein the set of instructions, when executed by the one or more processors, causes the one or more processors to generate a user interface that displays the plurality of frames including the modified subset of the plurality of frames.

24. a first one of the image regions depicting a face of the first speaking conference participant; a second one of the image regions depicts the face of the speaking first conference participant; the first image region is detected in a first frame of the plurality of frames; the second image region is detected in a second frame of the plurality of frames; the first frame occurs before the second frame; 21. The machine-readable medium of claim 20, wherein identifying the speaking first conference participant comprises determining, using at least one heuristic, that at least a second one of the facial landmarks determined in the second image region has moved relative to at least a first one of the facial landmarks determined in the first image region.

25. 25. The machine-readable medium of claim 24, wherein the second facial landmark corresponds to a portion of a first one of an upper lip and a lower lip of the face of the first conference participant who is speaking, and the first facial landmark corresponds to a portion of a different second one of the upper lip and the lower lip of the face of the first conference participant who is speaking.

26. 21. The machine-readable medium of claim 20, wherein the set of instructions, when executed by the one or more processors, cause the one or more processors to provide the facial landmarks to at least one neural network that identifies the speaking first conference participant in each of the subset of image regions.

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