Photoelectric device and method of manufacturing the same

Abstract

The present invention relates to an optoelectronic device and a semiconductor device. The characteristic dimension of the element or effective working area is 500 μm or less, and the photovoltaic device is a semiconductor substrate. a first transport layer formed in a first region of the semiconductor substrate; a first insulating layer is formed in the second partial region located at the first insulating layer; and a first transport layer is formed on the first insulating layer. An interface layer is formed on the first transport layer, and a light-emitting material layer including a perovskite material is formed on the interface layer. The light emitting layer is formed on the light emitting material layer in the second partial region and on the first partial region closer to the second partial region. A second insulating layer is formed on the light emitting material layer, thereby forming the photovoltaic device as a single light emitting device. The feature size of the light pixel point or effective active area can be adjusted, and the manufacturing cost is low and the process is simple. The low complexity and high spectral purity of the device make it suitable for mini- and micro-photoelectric devices. Effectively solves the problems of low external quantum efficiency, low brightness, and large leakage current of devices It is possible.

Description

[Technical Field]

[0001] The present invention relates to semiconductor technology, and more particularly to photovoltaic devices. [Background technology]

[0002] There is an ever-increasing demand for miniaturization, integration, and low power consumption of basic components in display products. As the size of light-emitting diodes and other micro-photoelectric devices increases, the unit size and power consumption of these devices will become smaller. In recent years, mini light-emitting diodes and micro light-emitting diodes have become popular. LEDs (mini-LED and micro-LED) are low power consumption, high contrast, and high It has been attracting attention due to its advantages such as brightness, high response speed, and high efficiency. Raywall "The Wall" and PlayNitride's "PixelLED Display" High-end micro light-emitting diode displays such as "LED Display" have appeared on the market, Currently, mini-LEDs and micro-LEDs have the above advantages. However, the quality requirements for III-V epitaxial semiconductors have become stricter, and During the manufacturing process, a large amount of non-radiative loss channels are generated on the sidewalls of the light-emitting layer, and large panel displays The problem of mass transportation of micro light-emitting diodes in the US has arisen, leading to an increase in the manufacturing costs of the products. Invite.

[0003] In recent years, metal halide perovskites have been used as new semiconductor materials, and have been considered to be as effective as III-V group materials. It has the same performance as silicon dioxide, and is an excellent semiconductor material that can be produced at low cost by solution processing. Improved photoelectric performance, e.g., tunable band gap, high fluorescence quantum yield, and ion transport In 2014, the first room-temperature electron Since realizing electroluminescent perovskite light-emitting diodes, The technology for fabricating perovskite fluoride light-emitting diodes (PeLEDs) is becoming increasingly mature. Recently, researchers have developed perovskites with external quantum efficiencies exceeding 20% ​​and internal quantum efficiencies approaching 100%. The light-emitting device was successfully fabricated, and PeLED has the potential to become a low-cost alternative to LED technology. However, how to build highly efficient PeLED technology with micropixel size is still unclear. However, this is difficult to achieve.

[0004] Currently, the technology for fabricating highly efficient perovskite light-emitting diodes is limited to low-dimensional and mixed-dimensional perovskite. by optimizing radiative recombination in the skite structure and in different material systems. There are two types of passive perovskite thin films: By innovating and optimizing the device structure, we have achieved perovskite luminescence with high external quantum efficiency. It is possible to fabricate highly efficient perovskite devices with micron-scale chip structures. There are limitations to fabricating micro light-emitting diodes. In order to create a print pattern, inkjet inks with suitable rheological properties, low-energy There are many drawbacks, such as the need to select an appropriate solution for the electron beam and surface tension. .

[0005] As mentioned above, how to achieve high performance in a low-cost process and achieve high pixel count or effective working area? The manufacturing of tunable light-emitting and photoelectric devices will determine the future technological direction of the industry and the market. There will be a real demand. Summary of the Invention

[0006] This application relates to a photoelectric device in which the characteristic dimension of a single light-emitting pixel point or effective active area is 500 μm or less. A method for manufacturing a chair, comprising: Step S1 of providing a semiconductor substrate; Step S2 of forming a photoresist layer; The photoresist layer is exposed and developed using a reticle, and the first portion of the semiconductor substrate is removed. The remaining region is protected by the photoresist layer, and the second region located around the first region is a step S3 of removing a second photoresist layer over the upper surface of the semiconductor substrate corresponding to the second partial region; Step S4: forming a first insulating layer having a thickness smaller than that of the photoresist layer; and, A photoresist removal process is performed to remove the remaining photoresist layer and the remaining photoresist layer. Step S5 of removing the overlying first insulating layer; A first transport layer is formed to cover the upper surface of the first insulating layer and the semiconductor substrate in the first partial region. Step S6 and Step S7 of forming an interface layer on the first transport layer; Step S8 of forming a light emitting material layer on the interface layer; The light emitting material layer in the second partial region is covered, and the light emitting material layer in the first partial region is closer to the second partial region. A second insulating layer is formed to cover the light emitting material layer, and a central region of the first partial region is covered with the second insulating layer. Step S9 of ensuring that the layer is not covered; Step S10 of forming an electron transport layer in the central region of the first partial region. A method for manufacturing a vise is provided.

[0007] Furthermore, the first partial region is formed so that the metal electrode extends onto the second insulating layer on one side of the central region. The method further includes a step S11 of forming a metal electrode on the electron transport layer in the central region of the region.

[0008] Furthermore, the first transport layer is a hole transport layer.

[0009] Furthermore, the interface layer is a lithium fluoride layer.

[0010] Furthermore, the material of the first insulating layer is silica, alumina, silicon nitride, silicon carbide, aluminum nitride. The material may be any one of the following materials or a combination of multiple materials:

[0011] Furthermore, the light emitting material layer is a perovskite material layer.

[0012] Furthermore, the light-emitting material layer may be made of a perovskite material, an organic material, a III-V material, or a II-V One of group I materials, group IV materials, rare earth materials, oxide materials, semiconductor nanomaterials, and insulating materials It is a species or a combination of multiple species.

[0013] Furthermore, the light emitting material layer is in direct contact with the interface layer.

[0014] Furthermore, by adjusting the dimensions of the light emitting material layer covered with the second insulating layer in the first partial region, The size of the central region of the first partial region that is not covered with the second insulating layer is adjusted by this. Adjust the dimensions of the layer.

[0015] Furthermore, the second insulating layer is a lithium fluoride layer.

[0016] Furthermore, only the light emitting material layer in the first partial region that is closer to the second partial region is covered with the second insulating layer. The position where the second insulating layer is to be formed is restricted by a reticle so that the second insulating layer can be formed.

[0017] Furthermore, the reticle is configured to form the electron transport layer only in the central region of the first partial region. Therefore, the position where the electron transport layer is formed is limited.

[0018] The present invention also provides a light emitting device having a single light emitting pixel point or effective active area with a characteristic dimension of 500 μm or less. An electrical device, a semiconductor substrate, a first transport layer formed in a first partial region of the semiconductor substrate, A first insulating layer is formed in the second peripheral region, and a first transport layer is formed on the first insulating layer. an interface layer is formed on the first transport layer, a light-emitting material layer is formed on the interface layer, and a second partial region a second layer on the light emitting material layer in the first partial region and on the light emitting material layer closer to the second partial region in the first partial region; An insulating layer is formed, and an electron transport layer is formed on the light emitting material layer in the central region of the first partial region. The present invention provides a photovoltaic device.

[0019] Furthermore, the first transport layer is a hole transport layer.

[0020] Furthermore, the interface layer and the second insulating layer are lithium fluoride layers.

[0021] Furthermore, the light emitting material layer is a perovskite material layer.

[0022] Furthermore, the light emitting material layer is in direct contact with the interface layer.

[0023] Furthermore, by adjusting the dimensions of the light emitting material layer covered with the second insulating layer in the first partial region, The size of the central region of the first partial region that is not covered with the second insulating layer is adjusted by the above-mentioned method. Adjust the dimensions of the transport layer.

[0024] Furthermore, the material of the first insulating layer is silica, alumina, silicon nitride, silicon carbide, aluminum nitride. The material may be any one of the following materials or a combination of multiple materials: [Brief explanation of the drawings]

[0025] [Figure 1]1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 2] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 3] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 4] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 5] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 6] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 7] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 8] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 9] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 10] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 11] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 12] 1A-1C are cross-sectional schematic diagrams illustrating an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. [Figure 13] 1 is a schematic diagram of a photoelectric device according to an embodiment of the present application and test data of the photoelectric performance of the photoelectric device manufactured by the manufacturing method of the photoelectric device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0026] The technical solution of the present invention will be described clearly and completely below with reference to the drawings. The embodiments described are only a part of the embodiments of the present invention, and are not all of the embodiments. All other embodiments obtained without creative effort based on the above embodiments are within the scope of the present invention. Belongs to a group.

[0027] This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete and will fully illustrate the invention. The drawings are provided to fully convey the scope of the present invention to those skilled in the art. The dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals are used throughout the drawings. However, if a component or layer is "located on" another component or layer, "adjacent to," "connected to," or "coupled to" refers to a component or may be located on, adjacent to, connected or bonded to, or may be intermediate Conversely, if a component is "directly" attached to another component or layer, "on," "directly adjacent to," "directly connected to," or "directly coupled to" There are no intermediate components or layers, except for the use of terms such as first, second, third, etc. Various components, members, regions, layers and / or sections may be described, but these components The terms "member," "region," "layer," and / or "portion" are not limited by such terms. Separating one component, member, region, layer or part from another component, member, region, layer or part Therefore, without departing from the teachings of the present invention, the following will be considered. a first component, member, region, layer or section as a second component, member, region, layer or section; It may be represented as:

[0028] Spatial terms, such as "below," "below," "below," "below," "of," The terms "above," "on," and the like are used herein to refer to one component or feature shown in the figures for convenience of explanation. It may be used to explain the relationship of a feature to another component or feature, provided that the illustrated orientation In addition, the spatial relationship terms are intended to encompass various orientations of the device during use and operation. For example, if a device in a figure is inverted, it may be "under other components" or "on its Any component or feature described as "below" or "below" is a component or feature that is below another component or feature. Thus, the exemplary terms "below" and "below" are The device may be in another orientation (rotated 90 degrees or at another orientation). and spatial references used herein should be construed accordingly.

[0029] The terminology used herein is used only for the purpose of describing particular embodiments and is not intended to limit the present invention. Unless the context clearly indicates otherwise, when used, the singular "one" and "one" are used interchangeably. The terms "one" and "said" are intended to include the plural. and / or "comprises" as used herein means to include said features, integers, steps, operations Identifies the presence of an operation, component and / or member, but does not include one or more other features, integers, steps, The term "group" does not preclude the presence or addition of steps, operations, components, members and / or groups. When used, the term "and / or" means any and all combinations of the associated items listed. This includes.

[0030] The technical solution of the present invention will be described clearly and completely below with reference to the drawings. The examples are only a part of the embodiments of the present invention, and are not all of the embodiments. All other embodiments that can be obtained based on the examples without creative effort are within the scope of the present invention. do.

[0031] In one embodiment of the present invention, the feature size of a single light-emitting pixel point or active area is less than 500 μm. A method for fabricating a photovoltaic device is provided. D) as an example, typically, the characteristic dimension of a single light-emitting pixel point or effective operating area is 200 μm Those with a thickness of 500 μm or more are called mini-perovskite light-emitting diodes (mini-PeLEDs) ) and a single light-emitting pixel point or effective operating area with a characteristic dimension of 200 μm or less is a micro The micro-perovskite light-emitting diode (micro-PeLED) is shown in Figures 1 to 12. 1 is a cross-sectional schematic view of an example of a manufacturing process for a photovoltaic device according to an embodiment of the present invention. Specifically, the method for manufacturing a photoelectric device according to an embodiment of the present invention includes steps S1 to S10. nothing.

[0032] S1: Provide a semiconductor substrate.

[0033] As shown in FIG. 1, a semiconductor substrate 1 is provided. The semiconductor substrate 1 is a substrate material. Any material, such as conductive glass (FTO), silicon substrate, polytetrafluoroethylene It may be made of a plastic material (PTFE), piezoelectric ceramics, etc.

[0034] Typically, semiconductor substrates are cleaned with deionized water, acetone, or isopropyl alcohol prior to use. , deionized water, and isopropyl alcohol for over 15 minutes in five steps. After cleaning, the semiconductor substrate is placed in a UV ozone cleaner and cleaned with ozone. Do this for 30 minutes.

[0035] S2: A photoresist layer is formed.

[0036] As shown in Figure 2, a photoresist layer 2 is formed on a semiconductor substrate 1. 2 may be formed using a negative photoresist solution or a positive photoresist solution. For example, 50 μL of negative photoresist may be dispensed using a 100 μL pipette gun. The solution is sucked and applied onto the semiconductor substrate 1, and the vacuum spin coater is started and rotated at 4000 rpm. Even if the photoresist layer 2 is spin-coated for 60 seconds at a rotation speed of 1000 rpm to obtain a photoresist layer 2 having a thickness of about 420 nm, Preferably, the thickness of the photoresist layer 2 is 420 nm. For the thickness of the photoresist layer 2 of 420 nm, the thickness of the photoresist layer 2 is 20%, preferably 10%, more preferably 5%. % deviation is acceptable. Specifically, this deviation can be any value between 380 nm and 460 nm. It's okay to have it.

[0037] S3: The photoresist layer is exposed and developed using a reticle, and the first The first partial region is protected by the remaining photoresist layer, and the second partial region located around the first partial region is Remove the area.

[0038] As shown in FIG. 4, the first partial region 11 of the semiconductor substrate 1 is protected by the remaining photoresist layer 21. The second partial region 12, which is located around the first partial region 11, is removed, i.e., the second partial region 12 is removed. The semiconductor substrate 1 in the partial region 12 is exposed.

[0039] Specifically, in the case of a negative photoresist, the structure formed in step S2 is and an ultraviolet light source (λ = 365 nm, 100 mJ cm -2 ) and expose for 7-8 seconds. , resulting in the exposed negative photoresist shown in Figure 3. Next, the photoresist is washed with isopropyl alcohol ( After washing with IPA several times to remove the unexposed negative photoresist, the substrate was heated on a hot plate at 85°C. The substrate was placed in a dry oven and baked for 20 minutes to obtain the structure shown in Figure 4.

[0040] S4: Cover the top surface of the remaining photoresist layer and the top surface of the semiconductor substrate corresponding to the second partial region. Thus, a first insulating layer having a thickness smaller than that of the photoresist layer is formed.

[0041] As shown in FIG. 5, the remaining photoresist layer 21 (i.e., the photoresist layer in the first partial region 11) The upper surface of the resist layer) and the exposed semiconductor substrate 1 (i.e., the semiconductor substrate corresponding to the second partial region 12) are A second photoresist layer 21 having a thickness smaller than that of the photoresist layer 21 is formed so as to cover the upper surface of the substrate. Specifically, in one embodiment, the thickness of the first insulating layer is 40 nm to 80 nm. The thickness of the first insulating layer may be any value between 100 nm and 200 nm. Preferably, the thickness of the first insulating layer is 60 nm.

[0042] In one embodiment, the material of the first insulating layer 3 is silica (SiO2), alumina (Al2O3), nitride (VN), or the like. silicon nitride (Si3N4), silicon carbide (SiC), and aluminum nitride (AlN) The first insulating layer 3 may be made of one or a combination of two or more materials. The material is silica (SiO2) or alumina (Al2O3). The first insulating layer 3 is formed by at least one process such as silicon sputtering, MOCVD, thermal evaporation, etc. may be formed.

[0043] S5: A photoresist removal process is performed to remove the remaining photoresist layer and the remaining photoresist. The first insulating layer located on the backing layer is removed.

[0044] As shown in FIG. 6, the remaining photoresist layer 21 and the photoresist layer 22 positioned on the remaining photoresist layer 21 The first insulating layer 3 is removed, thus exposing the semiconductor substrate 1 in the first partial region 11. The first insulating layer 3 in the second partial region 12 is held. The resulting structure was immersed in a photoresist removal solution for 12 hours to remove the photoresist. The structure shown in Figure 6 is obtained. Next, deionized water, acetone, and isopropyl alcohol are added in this order. Rinse for 5 minutes, then place in a UV ozone cleaner for 30 minutes of ozone cleaning.

[0045] S6: Forming a first transport layer to cover the upper surface of the first insulating layer and the semiconductor substrate in the first partial region. Complete.

[0046] Specifically, as shown in FIG. 7, the first transport layer 4 is formed on the upper surface of the first insulating layer 3 and the first partial region 1. 1 covers the semiconductor substrate 1 in the

[0047] In one embodiment, the first transport layer 4 is a hole transport layer. In one embodiment, the first transport layer 4 is a nickel oxide. Nickel (NiO x ) and poly(9-vinylcarbazole) (PVK). Nickel oxide (NiO x The powder was purchased from Beijing Huamin New Materials Technology Co., Ltd. and dispersed in deionized water. The concentration is 15 mg / mL. 50 μL of Ni was added using a 100 μL pipette gun. O x The solution is sucked and applied to the structure formed in step S5, and the vacuum spin coater is started. The NiO x The structure on which the solution was spin-coated was The sample was placed on a heating table and annealed at 150°C for 15 minutes. After that, the sample was placed in a chamber filled with high-purity nitrogen. The sample is then transferred to a glove box and PVK is spin-coated using a vacuum spin coater. It is purchased from GMA-Aldrich and has an average molecular weight of 25,000 to 50,000. It is dissolved in chlorobenzene (CB) at a concentration of 6 mg / mL. 50 μL of PVK solution was aspirated using a pet gun, and the vacuum spin coater was started at 4500 r After that, it was placed on a hot table and heated at 150°C for 30 min. n Annealing forms a hole transport layer.

[0048] The hole transport layer may be an organic hole transport layer or an inorganic hole transport layer, among which, an organic hole transport layer The transport layers are TFB, PTAA, TAPC, PEDOT:PSS, Poly-TPD, and PVK. , TCTA, CBP, TPD, CuPc, M-MTDATA, NPB, Rubrene The inorganic hole transport layer may include, but is not limited to, at least one of copper oxide (Cu O), nickel oxide (NiO x ), molybdenum trioxide (MoO3), tungsten trioxide (WO3), vanadium pentoxide (V2O5), but Not limited.

[0049] In one embodiment, the thickness of the first transport layer 4 may be set according to the needs of the device.

[0050] S7: Form an interface layer on the first transport layer.

[0051] As shown in Figure 8, an interface layer 5 is formed on the first transport layer 4. In one embodiment, the interface layer 5 is a The interface layer 5 is made of sodium fluoride (NaF), Potassium fluoride (KF), rubidium fluoride (RbF), cesium fluoride (CsF), One or more of magnesium (MgF2), calcium fluoride (CaF2), etc. In one embodiment, the thickness of the interface layer 5 is between 0.7 nm and 1.3 nm. The thickness of the interface layer 5 is arbitrary, preferably 1 nm. The structure formed in S6 is transferred to a vacuum coater to deposit a polar interface, for example, LiF. The atmospheric pressure of the vacuum deposition is 5 x 10 -4 The deposition rate is measured using a quartz crystal. The deposition is completed at a rate of 0.1 nm / s.

[0052] Here, the interface layer 5 plays an insulating role.

[0053] S8: A light-emitting material layer is formed on the interface layer.

[0054] As shown in Fig. 9, a light emitting material layer 6 is formed on the interface layer 5. The light emitting material layer 6 can be any type of material. It may be made of any suitable luminescent material, whether existing or developed as technology evolves. All electroluminescent materials are within the scope of this patent. The light emitting material layer 6 may be a bismuth-based material or a quantum dot material. is a perovskite material layer. Metal halide perovskite is a new semiconductor material. The performance of these materials is similar to that of III-V materials. As a conductive material, it has excellent photoelectric performance, such as adjustable band gap and high fluorescence quantum yield. The results showed characteristics such as high photoluminescence, long ion migration distance, and narrow emission band gap. In the example, the light-emitting material layer may be a combination of perovskite materials, organic materials, III-V materials, and II-VI materials. Group materials, Group IV materials, rare earth materials, oxide materials, semiconductor nanomaterials, insulating materials, etc. The organic materials may be any one of a variety of species or combinations thereof, where organic materials include small molecules and polymers.

[0055] For example, when the light emitting material layer 6 is a perovskite material layer, the structure after step S7 The body is then transferred to a glove box filled with high-purity nitrogen, where a layer of perovskite material is spin-coated. The resulting solution is used to form the light-emitting material layer 6. Specifically, the perovskite precursor solution is n Cs x FA 1-x Pb n Br 3n+1 110 mg of zinc bromide (PbBr2), cesium bromide CsBr 64 mg, formamidine hydroiodide (FABr) 6 mg, 2-(4 -Methoxyphenyl)ethylamine hydrobromide (MOPEABr) 28 mg, and 18 - 5.5 mg of crown ether-6 in 1 mL of dimethyl sulfoxide (DMSO) solution The solution concentration was adjusted to 0.3 M. Next, the prepared 0.3 M perovskite precursor solution was 50 μL of the liquid was aspirated and spin-coated onto the interface layer 5 at a rotation speed of 4000 rpm for 60 seconds. Anneal at 70°C for 10 minutes.

[0056] In one embodiment, the perovskite material layer has the formula ABX3, where the A position is a monovalent carbon atom. The A-position cation is a cesium ion, the B-position is a divalent cation, and the X-position is a halogen anion. Muon (Cs + ), methylamine ion (MA + ), formamidine ion (FA + ) , ethylamine ion (EA + ), hydrazine ion (HA + ), guanidine ion (G A + ), isopropylamine ion (IPA + ), imidazole ion (IA + ) etc. The B-position cation is lead ion (Pb 2+ ), tin ions (Sn2+ ), germanium ion Ge 2+ ), indium ions (In 2+ ), bismuth ions (Bi 2+ ) etc. The anion at the X position is a chloride ion (Cl - ), bromide ion (Br - ), iodine ion (I - ), and the perovskite material layer can be one of the following: one-dimensional, quasi-two-dimensional, and three-dimensional components. It may be a species or a combination of several species.

[0057] In one embodiment, the thickness of the light emitting material layer 6 may be set according to the needs of the device.

[0058] The light emitting material layer 6 is located on the interface layer 5. Specifically, the light emitting material layer 6 is directly attached to the interface layer 5. This allows the light-emitting material to spread more easily, and the light-emitting material, e.g., the perovskite solution, is tightly bonded to the interface layer 5 by the interface layer 5, and thus the light-emitting material layer 6 formed The surface flatness is further improved.

[0059] S9: Covering the light emitting material layer in the second partial region and covering the second partial region side of the first partial region. A second insulating layer is formed so as to cover the light emitting material layer close to the first partial region. Do not cover with the second insulating layer.

[0060] As shown in FIG. 10, the second insulating layer 7 covers the light emitting material layer 6 in the second partial region 12 and The light emitting material layer 6 is covered in the first partial region 11 near the second partial region 12 side, thereby , the central region 111 of the first partial region 11 (i.e., the second layer insulating layer of the first partial region 11) The light emitting material layer 6 in the area other than the area covered by the second insulating layer 7 is not covered by the second insulating layer 7. 111, exposing the light emitting material layer 6 in the central region 111. By adjusting the dimensions of the light emitting material layer 6 covered with the second insulating layer 7, the first partial region The dimensions of the central region 111 of the insulating layer 11 that is not covered with the second insulating layer 7 are adjusted.

[0061] In one embodiment, the second insulating layer 7 is a lithium fluoride (LiF) layer. are sodium fluoride (NaF), potassium fluoride (KF), and rubidium fluoride (RbF) , Cesium fluoride (CsF), Magnesium fluoride (MgF2), Calcium fluoride (C aF2) and the like. In one embodiment, the second layer The thickness of the insulating layer 7 may be any value between 24 nm and 36 nm. The thickness of the edge layer 7 is 30 nm. In one embodiment, the structure formed in step S8 is vacuum The substrate is placed in a coater and a lithium fluoride (LiF) insulating layer is deposited. The vacuum deposition pressure is 5×1 0 -4 The deposition rate is measured using a quartz crystal. In one embodiment, the entire first partial region 11 is covered with the second insulating layer 7. Instead, only the light emitting material layer near the second partial region 12 side is covered with the second insulating layer 7. As shown, the position where the second insulating layer 7 is to be formed is limited by the reticle.

[0062] S10: An electron transport layer is formed in the central region of the first partial region.

[0063] As shown in FIG. 11, the electron beam is applied to cover only the central region 111 of the first partial region 11. The transport layer 8 is formed.

[0064] In one embodiment, the electron transport layer 8 is formed by a vapor deposition process. ,2',2''-(1,3,5-benzimidazole)-tris(1-phenyl-1-H-benzimidazole) The vacuum deposition pressure was 5×10 -4 Pa, and evaporation The deposition rate is measured using a quartz crystal. The deposition is completed at a deposition rate of 0.4 nm / s. In the example, the thickness of the electron transport layer 8 is any value between 40 nm and 50 nm. The transport layer 8 has a thickness of 45 nm.

[0065] In one embodiment, the electron transport layer 8 is formed only in the central region 111 of the first partial region 11. In this way, the position where the electron transport layer 8 is formed is restricted by the reticle.

[0066] The electron transport layer 8 is mainly of two types: an organic electron transport layer and an inorganic electron transport layer. The organic electron transport layer contains TPBi, BAlq, Phen-m-PhDPO, and POPy2. , PO-T2T, Alq3, B3PYMPM, etc., Inorganic electron transport layers include, but are not limited to, Ga2O3, Si3N4, ZrO2, and VO 5, Al2O3, NiO x , MoO3, ZnO, MgO, NiO, SnO2, TiO2, etc. This includes, but is not limited to, at least one of:

[0067] As described above, in the present application, the dimensions of the light emitting material layer 6 covered with the second insulating layer 7 in the first partial region are By making the deposition method adjustable, the dimensions of the subsequently formed electron transport layer can be adjusted; This allows the size of the light-emitting area of ​​the photoelectric device to be adjusted, and also allows the size of a single light-emitting pixel point or effective The feature size of the active region can be adjusted, that is, the second insulating layer is used as a feature size limiting layer, and the first insulating layer is used as a feature size limiting layer. 1 Combined with an insulating layer, mini- and micro-photoelectric devices can be fabricated. In this way, the structure of the device can be optimized and miniature photoelectric devices and microelectronic devices can be realized. Solves the problems of low quantum efficiency, low brightness, and high leakage current of photovoltaic devices In addition, since an etching process is not required when manufacturing the photoelectric device of the present invention, The luminescent material is then etched by chemical etching, ion beam or electron beam etching in the etching process. The layer is severely damaged, and mass-produced photoelectric devices have many defective pixels, are difficult to process, and take time Solve the problems such as taking too long.

[0068] In one embodiment, the method of manufacturing a photovoltaic device of the present application further comprises: forming a metal electrode on one side of the central region; A gold layer is formed on the electron transport layer in the central region of the first partial region so as to extend onto the second insulating layer on the side. The method further includes a step S11 of forming a metal electrode.

[0069] As shown in FIG. 12, the metal electrode 9 has an electron transport layer in the central region 111 of the first partial region 11. 8 and extends to the second insulating layer 7 on the right side of the central region 111, thereby forming a metal strip An electrode 9 is formed.

[0070] In one embodiment, the metal electrode 9 is formed by a metal electrode evaporation process. The chicle limits the area where the metal electrode 9 is to be formed. In one embodiment, the width of the metal electrode 9 is In one embodiment, in the metal electrode deposition, the electrode The material LiF and metal Al were evaporated sequentially, and the evaporation rate was measured by a quartz crystal reticle. The deposition rate was 0.1 nm / s, and the thickness of LiF was set to any value between 0.8 nm and 1.2 nm. The thickness of the Al electrode is any value between 80 nm and 120 nm. The thickness of the metal electrode is 1 nm, and the thickness of the Al electrode is 100 nm. It includes conductive oxides and metal materials, and highly conductive oxides include ITO, FTO, TCO, etc. The transparent electrodes include Al, Mg, Ca, Ag, Cu, Mg:Ag, and Li. :Al, Mn, etc.

[0071] Also, as shown in FIG. 12, in one embodiment of the present invention, a single light-emitting pixel point or effective active area an optoelectronic device having a characteristic dimension of 500 μm or less, a semiconductor substrate 1; The first transport layer 4 is formed in the first partial region 11 of the semiconductor substrate 1, and the first transport layer 4 is formed around the first partial region 11. A first insulating layer 3 is formed in the second partial region 12 where the first insulating layer 3 is located, and a first transport layer 4 is formed on the first insulating layer 3. formed, An interface layer 5 is formed on the first transport layer 4; A light-emitting material layer 6 is formed on the interface layer 5, On the light emitting material layer 6 in the second partial region 12 and on the second partial region side 12 of the first partial region 11 The second insulating layer 7 is formed on the light emitting material layer 6 adjacent thereto, and the central region 11 of the first partial region 11 There is further provided a photovoltaic device in which an electron transport layer 8 is formed on the light emitting material layer 6 in the photovoltaic device.

[0072] In one embodiment, the thickness of the first insulating layer is any value between 40 nm and 80 nm, and the thickness of the interface layer is is an arbitrary value between 0.7 nm and 1.3 nm, and the thickness of the second insulating layer is 24 nm to 36 nm. The thickness of the electron transport layer is any value between 40 nm and 50 nm. The thickness of the first insulating layer is 60 nm, the thickness of the interface layer 5 is 1 nm, and the thickness of the second insulating layer The thickness of the electron transport layer 7 is 30 nm and the thickness of the electron transport layer 8 is 45 nm.

[0073] In one embodiment, the thickness of the first transport layer 4 and the light emitting material layer 6 are set according to the needs of the device. This may also be done.

[0074] In one embodiment, the semiconductor substrate 1 can be made of any material that can be used as a substrate material, such as conductive glass. Glass, silicon substrate, polytetrafluoroethylene material (PTFE), piezoelectric ceramics, etc. It may be manufactured in any manner.

[0075] In one embodiment, the material of the first insulating layer 3 is silica (SiO2), alumina (Al2O3), nitride (VN), or the like. silicon nitride (Si3N4), silicon carbide (SiC), and aluminum nitride (AlN) The first insulating layer 3 may be made of one or a combination of two or more materials. The material may be silica (SiO2) or alumina (Al2O3).

[0076] In one embodiment, the first transport layer 4 is a hole transport layer. In one embodiment, the first transport layer 4 is a nickel oxide. Nickel (NiO x ) and poly(9-vinylcarbazole) (PVK). The hole transport layer The hole transport layer may be an organic hole transport layer or an inorganic hole transport layer, and among them, the organic hole transport layer may be a layer containing T FB, PTAA, TAPC, PEDOT:PSS, Poly-TPD, PVK, TCTA , CBP, TPD, CuPc, M-MTDATA, NPB, Rubrene Inorganic hole transport layers include, but are not limited to, at least one of copper oxide (CuO) , nickel oxide (NiO x ), molybdenum trioxide (MoO3), tungsten trioxide (W O3), vanadium pentoxide (V2O5), but these Not limited.

[0077] In one embodiment, the interface layer 5 is a lithium fluoride (LiF) layer, but the interface layer 5 may also be a sodium fluoride layer. Sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF), cesium fluoride CaF, magnesium fluoride (MgF2), calcium fluoride (CaF2), etc. The interface layer 5 may be made of one or a combination of two or more of these materials. It is possible to do so.

[0078] The light-emitting material layer 6 may be formed of any electroluminescent material, and may be any known or novel material. All electroluminescent materials developed through technological advances are within the scope of this patent. Perovskite materials are preferred, but perovskite materials and organic materials, III-V materials are also Materials, II-VI materials, IV materials, rare earth materials, oxide materials, semiconductor nanomaterials, insulating materials It may be a combination of one or more of the materials. The light-emitting material layer 6 is a perovskite material layer. Perovskites have the same performance as III-V materials. As a semiconductor material that can be easily manufactured, it has excellent photoelectric properties, such as the ability to tune the band gap. It has features such as high fluorescence quantum yield, long ion migration distance, and narrow emission band gap. In one embodiment, the perovskite material layer has the formula ABX3, where is a monovalent cation, B is a divalent cation, and X is a halogen anion. , cesium ions (Cs + ), methylamine ion (MA + ), formamidine ion ( FA + ), ethylamine ion (EA + ), hydrazine ion (HA +), guanidine On (GA + ), isopropylamine ion (IPA + ), imidazole ion (IA + ) etc. The B-position cation is lead ion (Pb 2+ ), tin ions (Sn 2+ ), Germanium nium ion (Ge 2+ ), indium ions (In 2+ ), bismuth ions (Bi 2+ ) and the like. The anion at the X position is a chloride ion (Cl - ), bromide ion (Br - ), iodine Ion (I - ) and the perovskite material layer can be divided into one-dimensional components, quasi-two-dimensional components, and three-dimensional components. It may be one or a combination of more than one of the components.

[0079] The light emitting material layer 6 is located on the interface layer 5, and specifically, the light emitting material layer 6 is directly attached to the interface layer 5. This allows the light-emitting material to spread more easily, and the light-emitting material, e.g., the perovskite solution, is tightly bonded to the interface layer 5 by the interface layer 5, and thus the light-emitting material layer 6 formed The surface flatness is improved.

[0080] As shown in FIG. 12, the second insulating layer 7 covers the light emitting material layer 6 in the second partial region 12 and The light emitting material layer 6 is covered with the first partial region 11 in a region closer to the second partial region 12. The light emitting material layer 6 in the central region 111 of the first partial region 11 is not covered with the second insulating layer 7. In one embodiment, the first partial region 111 is formed by arranging the first partial region 111 in the luminescent material layer 6 so as to expose the luminescent material layer 6 in the central region 111. By adjusting the dimensions of the light emitting material layer 6 covered with the second insulating layer 7 in the region 11, The dimensions of a central region 111 of the partial region 11 that is not covered with the second insulating layer 7 are adjusted.

[0081] In one embodiment, the second insulating layer 7 is a lithium fluoride (LiF) layer. are sodium fluoride (NaF), potassium fluoride (KF), and rubidium fluoride (RbF) , Cesium fluoride (CsF), Magnesium fluoride (MgF2), Calcium fluoride (C aF2) or a combination of two or more thereof.

[0082] As shown in FIG. 12, the electron transport layer 8 covers only the central region 111 in the first partial region 11 . The electron transport layer 8 is mainly of two types: an organic electron transport layer and an inorganic electron transport layer. The organic electron transport layer contains TPBi, BAlq, Phen-m-PhDPO, and POPy2. , PO-T2T, Alq3, B3PYMPM, etc., Inorganic electron transport layers include, but are not limited to, Ga2O3, Si3N4, ZrO2, and VO 5, Al2O3, NiO x , MoO3, ZnO, MgO, NiO, SnO2, TiO2, etc. This includes, but is not limited to, at least one of:

[0083] In the present application, the size of the light emitting material layer covered with the second insulating layer in the first partial region can be adjusted. This allows for tailoring of the dimensions of the subsequently formed electron transport layer, i.e., optoelectronic devices. The size of the light-emitting area of ​​the pixel can be adjusted, and the characteristic size of the single light-emitting pixel point or the effective operating area can be adjusted. The method is adjustable, i.e., the second insulating layer is combined with the first insulating layer as a feature size limiting layer. By combining these, mini- and micro-photoelectric devices can be produced, thus Optimize the device structure and external dimensions of mini- and micro-optoelectronic devices. To solve the problems of low photoelectric efficiency, low brightness, and large leakage current.

[0084] In one embodiment, the photovoltaic device further comprises a photovoltaic element in the central region 111 of the first partial region 11. A metal electrode 9 is formed over the electron transport layer 8 and extends into the second insulating layer 7 on one side of the central region 111. Further includes:

[0085] In one embodiment, the photovoltaic device is a light emitting diode. solar cells, photoelectric detectors, fluorescent thin films, fluorescent powders, semiconductor transistors, laser photoelectron detectors The present invention may be applied to other photovoltaic device fields, such as devices and materials. The mini and micro LEDs manufactured by this method are used in display screens (high-end TVs, mobile phones, screens of electronic products such as mobile phones, computers and iPads, smart watches, It may be applied to wearable devices, AR smart glasses, micro projectors, etc. Mini- and micro-light-emitting diodes are combined with flexible substrates to create flexible Mini LEDs can be used for backlight displays (TV screens, etc.). It will also realize applications such as LCD and in-car displays, and RGB small pitch displays.

[0086] The photoelectric device according to the present application and the photoelectric device manufactured by the manufacturing method of the photoelectric device according to the present application Test the device. For example, if the photoelectric device is a light-emitting diode, When testing, the external quantum efficiency (EQE) is tested using an OLED photoelectric test system. This system includes a luminance meter, a KEITHLEY Source Measure Unit 2400, It consists of a master computer, an industrial camera CCD, a sample test station, etc. The luminance meter detects the spectrum and spectral power of the light-emitting diode, and KEITHLEY The source measure unit 2400 is the power source for the light emitting diodes, and provides power output and The positive and negative leads are pulled out from the 2400 and used as a light-emitting diode. The voltage range applied to the light-emitting device is 1V to 5V. The step interval is 0.1V, and the current through the LED is measured by the Kelvin probe method. The current detection range is 1nA to 100 mA, and the current density range is 10 - 4 ~10 3 mA cm -2 Therefore, it is possible to support current testing of light-emitting diodes. The master computer can measure the brightness of the luminance meter, KEITHLEY source measure unit, and It has the ability to communicate with the 2400 industrial camera CCD and collects spectra, Torque, voltage, current and detected image are acquired and displayed in real time for sample testing. The station allows you to place a light-emitting diode sample and adjust its position in three dimensions for clearer image. Observation and measurement can be performed more accurately, achieving the goal of optimizing performance testing. .

[0087] FIG. 13 shows a photoelectric device according to an embodiment of the present application and a method for manufacturing the photoelectric device according to an embodiment of the present application. 1A is a schematic diagram of the photoelectric performance test data of the photoelectric device manufactured by the method; The horizontal axis is the voltage applied across the LED, in volts. (V), and the vertical axis is the current density ( y) and its unit is mA cm -2 The light-emitting voltage of the micro LED is 2.8 At a voltage of 6.0 V, the current density is 923.8 mA cm -2 (b) The horizontal axis is the voltage applied to both ends of the LED, and the unit is volts. The vertical axis is the luminance of the LED, and the unit is cd m -2 At 5.7 V, the luminance of the LED is 1070.5 cd m - 2 The light-emitting area is 0.04mm 2 In (c), the horizontal axis is the light-emitting diode is the current density flowing through the -2 in The vertical axis is the external quantum efficiency (EQE) of the light-emitting diode, expressed in %. For light-emitting diode devices, the highest EQE is approximately 15.2% (4.11 × 10 -2 mA cm -2 ) As described above, the photoelectric device according to the present application and the photoelectric device according to the present application The photoelectric device manufactured by the manufacturing method realizes miniaturization and micronization, and The external quantum efficiency of photovoltaic devices and micro-photovoltaic devices is low, resulting in low brightness and leakage current. Solving the problem of being too big.

[0088] In one embodiment, the photovoltaic device and the method of manufacturing the photovoltaic device according to the present application are The present invention is applicable to photonic devices and micro-photonic devices, where the characteristics of a single light-emitting pixel point or active active area are Those with a characteristic dimension of 200 μm or more and 500 μm or less are mini-photoelectric devices, and are single light-emitting pixels. A micro-photoelectric device is one whose feature size of the element or effective working area is 200 μm or less. .

[0089] Furthermore, the photovoltaic device according to the present application may be fabricated by the following two methods: Method 1 2. Direct fabrication on mini- or micro-substrates with dimensions of 500 μm or less. The photoelectric device is manufactured by an etching method, the etching method being laser processing, This includes plasma etching, FIB etching, EBL etching, etc.

[0090] It should be noted that the above embodiments are merely for illustrating the technical solutions of the present invention and are not intended to be limiting. Although the present invention has been described in detail with reference to the above embodiments, it will be apparent to those skilled in the art that , the technical solutions described in the above examples are modified, or some or all of the technical features are equivalent. These modifications and substitutions may be made to the technical solution. It does not deviate from the scope of the technical solutions of each embodiment of the invention.

Claims

1. 1. A method of manufacturing a photovoltaic device having a feature dimension of a single light-emitting pixel point or effective active area of ​​500 μm or less, comprising: Step S1 of providing a semiconductor substrate; Step S2 of forming a photoresist layer; Step S3: performing an exposure and development process on the photoresist layer using a reticle to protect a first partial region of the semiconductor substrate with the remaining photoresist layer and remove a second partial region located around the first partial region; Step S4: forming a first insulating layer having a thickness smaller than that of the photoresist layer so as to cover the upper surface of the remaining photoresist layer and the upper surface of the semiconductor substrate corresponding to the second partial region; Step S5: performing a photoresist removal process to remove the remaining photoresist layer and the first insulating layer located on the remaining photoresist layer; Step S6: forming a first transport layer to cover the upper surface of the first insulating layer and the semiconductor substrate in the first partial region; Step S7 of forming an interface layer on the first transport layer; Step S8: forming a light-emitting material layer on the interface layer; Step S9: forming a second insulating layer so as to cover the light emitting material layer in the second partial region and to cover the light emitting material layer in the first partial region that is closer to the second partial region, and preventing the central region in the first partial region from being covered with the second insulating layer; and forming an electron transport layer in a central region of the first partial region.

2. 2. The method for manufacturing a photovoltaic device according to claim 1, further comprising the step of forming a metal electrode on the electron transport layer in the central region of the first partial region, such that the metal electrode extends onto the second insulating layer on one side of the central region.

3. 2. The method for manufacturing a photoelectric device according to claim 1, wherein the light emitting material layer is a perovskite material layer.

4. 2. The method for manufacturing a photoelectric device according to claim 1, wherein the light-emitting material layer is a combination of a perovskite material and one or more of an organic material, a III-V material, a II-VI material, a IV material, a rare earth material, an oxide material, a semiconductor nanomaterial, and an insulating material.

5. 2. The method of claim 1, wherein the first transport layer is a hole transport layer.

6. 2. The method for manufacturing a photoelectric device according to claim 1, wherein the material of the first insulating layer is one of silica, alumina, silicon nitride, silicon carbide, and aluminum nitride, or a combination of two or more of these materials.

7. 2. The method for manufacturing a photovoltaic device according to claim 1, wherein the light emitting material layer is in direct contact with the interface layer.

8. 2. The method for manufacturing a photoelectric device according to claim 1, wherein the size of the central region of the first partial region that is not covered with the second insulating layer is adjusted by adjusting the size of the light emitting material layer that is covered with the second insulating layer in the first partial region, thereby adjusting the size of the electron transport layer.

9. 2. The method for manufacturing a photoelectric device according to claim 1, wherein a position where the second insulating layer is formed is limited by a reticle so that only a portion of the light emitting material layer in the first partial region that is closer to the second partial region is covered with the second insulating layer.

10. 2. The method for manufacturing a photoelectric device according to claim 1, wherein a position where the electron transport layer is to be formed is limited by a reticle so that the electron transport layer is formed only in a central region of the first partial region.

11. 1. A photovoltaic device having a feature dimension of a single light-emitting pixel point or effective active area of ​​500 μm or less, a semiconductor substrate; A first transport layer is formed in a first partial region of a semiconductor substrate, a first insulating layer is formed in a second partial region located around the first partial region, and a first transport layer is formed on the first insulating layer; an interface layer formed on the first transport layer; a light-emitting material layer is formed on the interface layer; a second insulating layer formed on the light emitting material layer in the second partial region and on the light emitting material layer in the first partial region closer to the second partial region, and an electron transport layer formed on the light emitting material layer in the central region of the first partial region.

12. 12. The photovoltaic device of claim 11, wherein the light emitting material layer is a perovskite material layer.

13. 12. The photovoltaic device of claim 11, wherein the first transport layer is a hole transport layer.

14. 12. The photovoltaic device of claim 11, wherein the light emitting material layer is in direct contact with the interface layer.

15. 12. The photoelectric device of claim 11, wherein the material of the first insulating layer is one of silica, alumina, silicon nitride, silicon carbide, aluminum nitride, or a combination of two or more materials.

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