Automatic central processing unit (CPU) utilization optimization

Abstract

A method for automatic central processing unit (CPU) utilization optimization includes monitoring performance activity of a workload including multiple threads and modifying resource allocation of multiple cores to the multiple threads based on the performance activity.

Description

[Background technology]

[0001] The current fused preferred core algorithms are based on the highest frequency in the worst-case workload, but this ranking may not be the same for less threaded applications or non-worst-case customer workloads. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an exemplary computer for automatic central processing unit (CPU) usage optimization, according to some embodiments. [Figure 2] 1 is a flowchart of an exemplary method for automatic central processing unit (CPU) usage optimization, according to some embodiments. [Figure 3] 1 is a flowchart of an exemplary method for automatic central processing unit (CPU) usage optimization, according to some embodiments. [Figure 4] 1 is a flowchart of an exemplary method for automatic central processing unit (CPU) usage optimization, according to some embodiments. [Figure 5] 1 is a flowchart of an exemplary method for automatic central processing unit (CPU) usage optimization, according to some embodiments. [Figure 6] 1 is a flowchart of an exemplary method for automatic central processing unit (CPU) usage optimization, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0003] In some embodiments, a method for automated central processing unit (CPU) utilization optimization includes monitoring performance activity of a workload including multiple threads and modifying resource allocations of multiple cores for the multiple threads based on the performance activity.

[0004] In some embodiments, the method further includes identifying a first thread of the plurality of threads and a second thread of the plurality of threads associated with the first thread based on the performance activity, and modifying the resource allocation includes modifying the core assignment to reduce a physical distance between a first core of the plurality of cores to which the first thread is assigned and a second core of the plurality of cores to which the second thread is assigned. In some embodiments, the first core and the second core are located within the same computing core complex (CCX), the same core complex die (CCD), the same socket, the same non-uniform memory access (NUMA) domain, and / or the same compute node. In some embodiments, the method further includes identifying the first thread of the plurality of threads and a second thread of the plurality of threads assigned to the same core of the plurality of cores based on a degree of cache misses indicated by the performance activity, and modifying the resource allocation includes assigning one or more of the first thread and the second thread to different cores of the plurality of cores. In some embodiments, the method further includes monitoring additional performance activity after modifying the resource allocation and determining whether to revert the resource allocation change based on the additional performance activity. In some embodiments, the method further includes storing data indicative of the resource allocation in association with the workload and loading the data indicative of the resource allocation based on execution of the workload. In some embodiments, modifying the resource allocation includes modifying one or more thresholds for one or more cores of the plurality of cores, the one or more thresholds comprising a package power tracking (PPT) threshold, a thermal design current (TDC) threshold, an electrical design current (EDC) threshold, or a reliability limit comprising a threshold for the time that the core can safely spend at a voltage / temperature pair.

[0005] In some embodiments, an apparatus for automatic utilization optimization of a central processing unit (CPU) performs steps including monitoring performance activity of a workload including multiple threads and modifying resource allocation of multiple cores for the multiple threads based on the performance activity.

[0006] In some embodiments, the steps further include identifying a first thread of the plurality of threads and a second thread of the plurality of threads associated with the first thread based on the performance activity, and modifying the resource allocation includes modifying the core assignment to reduce a physical distance between a first core of the plurality of cores to which the first thread is assigned and a second core of the plurality of cores to which the second thread is assigned. In some embodiments, the first core and the second core are located within the same computing core complex (CCX), the same core complex die (CCD), the same socket, the same non-uniform memory access (NUMA) domain, and / or the same compute node. In some embodiments, the steps further include identifying the first thread of the plurality of threads and a second thread of the plurality of threads assigned to the same core of the plurality of cores based on a degree of cache misses indicated by the performance activity, and modifying the resource allocation includes assigning one or more of the first thread and the second thread to different cores of the plurality of cores. In some embodiments, the steps further include monitoring additional performance activity after modifying the resource allocation and determining whether to revert the resource allocation change based on the additional performance activity. In some embodiments, the steps further include storing data indicative of the resource allocation in association with the workload and loading the data indicative of the resource allocation based on execution of the workload. In some embodiments, modifying the resource allocation includes modifying one or more thresholds for one or more cores of the plurality of cores, the one or more thresholds comprising a package power tracking (PPT) threshold, a thermal design current (TDC) threshold, an electrical design current (EDC) threshold, or a reliability limit comprising a threshold for the time that the core can safely spend at a voltage / temperature pair.

[0007] In some embodiments, a computer program product for automated central processing unit (CPU) usage optimization disposed on a computer-readable medium includes computer program instructions that, when executed, cause a computer to monitor performance activity of a workload including multiple threads and modify resource allocations of multiple cores for the multiple threads based on the performance activity.

[0008] In some embodiments, the steps further include identifying a first thread of the plurality of threads and a second thread of the plurality of threads associated with the first thread based on the performance activity, and modifying the resource allocation includes modifying the core assignment to reduce a physical distance between a first core of the plurality of cores to which the first thread is assigned and a second core of the plurality of cores to which the second thread is assigned. In some embodiments, the first core and the second core are located within the same computing core complex (CCX), the same core complex die (CCD), the same socket, the same non-uniform memory access (NUMA) domain, and / or the same compute node. In some embodiments, the steps further include identifying the first thread of the plurality of threads and a second thread of the plurality of threads assigned to the same core of the plurality of cores based on a degree of cache misses indicated by the performance activity, and modifying the resource allocation includes assigning one or more of the first thread and the second thread to different cores of the plurality of cores. In some embodiments, the steps further include monitoring additional performance activity after modifying the resource allocation, and determining whether to revert the resource allocation change based on the additional performance activity. In some embodiments, the steps further include storing data indicative of the resource allocation in association with the workload, and loading the data indicative of the resource allocation based on execution of the workload.

[0009] The automated optimization of central processing unit (CPU) usage according to the present disclosure is generally implemented using a computer, i.e., an automated computing machine. Accordingly, for further explanation, Figure 1 illustrates a block diagram of an automated computing machine including an exemplary computer 100 configured for automated optimization of central processing unit (CPU) usage according to certain embodiments. The computer 100 of Figure 1 includes at least one computer processor 102, or "CPU," and random access memory 104 (RAM) connected to the processor 102 and other components of the computer 100 via a high-speed memory bus 106 and a bus adapter 108.

[0010] Stored in RAM 104 is operating system 110. Operating systems useful in computers configured for automatic central processing unit (CPU) utilization optimization include UNIX, Linux, Microsoft Windows, etc., as will occur to those skilled in the art. While the example operating system 110 of FIG. 1 is shown in RAM 104, many components of such software are typically stored in non-volatile memory, such as data storage 112, e.g., a disk drive. Also stored in RAM is configuration module 114, which is a module for automatic central processing unit (CPU) utilization optimization according to an embodiment of the present invention.

[0011] 1 includes a disk drive adapter 116 coupled to processor 102 and other components of computer 100 via expansion bus 118 and bus adapter 108. Disk drive adapter 116 connects non-volatile data storage to computer 100 in the form of data storage 112. Disk drive adapters useful in computers configured for automatic central processing unit (CPU) utilization optimization include integrated drive electronics (IDE) adapters, small computer system interface (SCSI) adapters, and the like, as will occur to those skilled in the art. In some embodiments, non-volatile computer memory is implemented as an optical disk drive, for example, electrically erasable programmable read-only memory (so-called "EEPROM" or "flash" memory), a RAM drive, and the like, as will occur to those skilled in the art.

[0012] The example computer 100 of Figure 1 includes one or more input / output (I / O) adapters 120. I / O adapters implement user-oriented input / output through software drivers and computer hardware for controlling, for example, output to a display device, such as a computer display screen, and user input from user input devices 122, such as a keyboard and mouse. The example computer 100 of Figure 1 also includes a video adapter 124, which is an example of an I / O adapter designed specifically for graphics output to a display device 126, such as a display screen or computer monitor. The video adapter 124 is connected to the processor 102 via a high-speed video bus 128, the bus adapter 108, and a front-side bus 130, which is also a high-speed bus.

[0013] The example computer 100 of FIG. 1 includes a communications adapter 132 for data communications with other computers and for data communications with a data communications network. Such data communications may be performed serially via an RS-232 connection, via an external bus such as a Universal Serial Bus (“USB”), over a data communications network such as an IP data communications network, and / or in any other manner as would occur to one skilled in the art. Communications adapters implement the hardware level of data communications by which one computer sends data communications directly to another computer or over a data communications network. Examples of communications adapters useful in computers configured for automatic central processing unit (CPU) utilization optimization include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0014] For further explanation, FIG. 2 depicts a flowchart illustrating an exemplary method for automated optimization of a central processing unit (CPU), which includes monitoring 202 (e.g., by configuration module 114) the performance activity of a workload including multiple threads. The workload may include an executed software application, a process, a service, or a combination thereof. Execution of the workload is facilitated by multiple threads. Each thread is assigned to a particular core of multiple cores (e.g., of a central processing unit (CPU)), and each core may support one or more threads of the multiple threads.

[0015] Monitoring 202 the performance activity of a workload includes identifying behaviors or metrics associated with the execution of the workload. Examples of performance activity include, for a given thread, the amount of traffic across the data fabric, latency, activity time (e.g., time the thread is active versus inactive), the number of functions or operations performed (e.g., number per second), the amount and type of memory or cache accesses, the amount or frequency of cache hits or misses, etc. In some embodiments, monitoring 202 the performance activity includes monitoring the performance activity over a particular time window (e.g., sampling). In other embodiments, monitoring 202 the performance activity includes continuously monitoring the performance activity and updating data indicative of the performance activity over time.

[0016] 2 also includes modifying 204 a resource allocation of the multiple cores for the multiple threads. In some embodiments, modifying 204 the resource allocation includes modifying one or more thresholds for one or more cores. Examples of modified thresholds include, for a particular core, a package power tracking (PPT) threshold (e.g., a threshold for the allowable socket power dissipation allowed across the voltage rails supplying the socket), a thermal design current (TDC) threshold (e.g., a maximum amount of current in amperes that a particular motherboard voltage regulator configuration can supply under thermally constrained conditions), an electrical design current (EDC) threshold (e.g., a maximum amount of current in amperes that a particular motherboard voltage regulator configuration can supply under short-term peak (spike) conditions), or a reliability limit (e.g., a maximum threshold for the amount of time a core can spend at a voltage / temperature pair that is considered safe for the silicon in the chip). For example, if a first thread is identified as being highly active relative to a second thread, one or more thresholds of a first core to which the first thread is assigned may be increased and one or more thresholds of a second core to which the second thread is assigned may be decreased, such that the first core to which the first thread is assigned receives more current than the second core to which the second thread is assigned.

[0017] In some embodiments, modifying 204 the resource allocation includes modifying the core assignment of one or more threads. As each thread is assigned to a particular core, one or more threads are reassigned to a different core. In some embodiments, modifying the core assignment includes modifying the core assignment to reduce the physical distance between cores to which particular threads are assigned. For example, parent and child threads, hero and helper threads, or other highly related threads may rely on extensive inter-thread communication across the data fabric. By reassigning one or more of the related threads to closer cores, the latency of inter-thread communication is reduced.

[0018] As another example, consider a first thread and a second thread running on the same core. Performance activity indicates that both the first thread and the second thread are very active in accessing the cache of this same core, and that both the first thread and the second thread are causing a large number of cache misses (e.g., because one thread writes to the cache due to a cache miss, which then causes a cache miss for the other thread). Next, the first thread and / or the second thread are reassigned such that the first thread and the second thread are each assigned to different cores with different caches. By isolating the cache-intensive threads onto different cores, the total number of cache misses is reduced, improving performance.

[0019] In existing solutions, multiple threads for a given workload are typically allocated equal resources. Furthermore, existing preferred core algorithms are typically based on maximum frequency in the worst case. For lightly threaded applications or workloads that do not approach the worst case scenario, these default resource allocations do not provide optimal performance for the workload. By monitoring (202) the performance activity of the workload and dynamically changing (204) the resource allocation, the workload benefits from optimal resource allocation.

[0020] For further explanation, FIG. 3 shows a flowchart illustrating an exemplary method for automatic optimization of a central processing unit (CPU), which includes monitoring 202 performance activity of a workload including multiple threads (e.g., by configuration module 114) and modifying 204 resource allocation of multiple cores for the multiple threads based on the performance activity.

[0021] The method of FIG. 3 also differs from FIG. 2 in that it includes identifying 302 a first thread of the plurality of threads and a second thread related to the first thread of the plurality of threads based on performance activity (e.g., by configuration module 114). In some embodiments, identifying 302 the first thread and the second thread includes identifying the second thread as being called or accessed by the first thread. For example, the second thread is identified as executing in response to a context switch from the first thread (e.g., the number or frequency of context switches exceeds a threshold). As another example, the second thread is identified as executing in response to a call from the first thread (e.g., the number or frequency of calls exceeds a threshold). As a further example, the second thread is identified as communicating with the first thread via the data fabric (e.g., for a period exceeding a threshold or while passing an amount of data exceeding a threshold). In other words, the second thread is identified as having some degree of intercommunication or interrelationship with the first thread.

[0022] The method of Figure 3 further differs from the method of Figure 2 in that modifying 204 the resource allocation of the multiple cores for the multiple threads based on the performance activity includes modifying 304 the core assignments to reduce the physical distance between a first core of the multiple cores to which the first thread is assigned and a second core of the multiple cores to which the second thread is assigned. The first thread and / or the second thread are assigned to new cores to reduce the data path distance between the cores executing the first thread and the second thread. For example, the first thread and / or the second thread are reassigned so that the first core and the second core are located in the same computing core complex (CCX), the same core complex die (CCD), the same socket, the same non-uniform memory access (NUMA) domain, and / or the same compute node.

[0023] For further explanation, FIG. 4 shows a flowchart illustrating an exemplary method for automatic optimization of a central processing unit (CPU), which includes monitoring 202 performance activity of a workload including multiple threads (e.g., by configuration module 114) and modifying 204 resource allocation of multiple cores for the multiple threads based on the performance activity.

[0024] 4 also differs from FIG. 2 in that it includes identifying 402 a first thread among the plurality of threads and a second thread among the plurality of threads that is assigned to the same core among the plurality of cores based on the degree of cache misses indicated by the performance activity (e.g., by configuration module 114). In other words, both the first thread and the second thread access the same cache of the same core. The first thread and the second thread are identified based on the degree of cache misses (e.g., within a time window) of both threads exceeding a threshold. Thus, cache misses occur in each of the first thread and the second thread, forcing each thread to write new data to the shared cache and contributing to cache misses in the other thread.

[0025] The method of FIG. 4 further differs from the method of FIG. 2 in that altering 204 the resource allocation of the multiple cores for the multiple threads based on performance activity includes assigning 404 one or more of the first thread and the second thread to different cores among the multiple cores. In other words, instead of being assigned to the same core, the first thread and the second thread are assigned to different cores. For example, either the first thread or the second thread is reassigned to a different core. As another example, both the first thread and the second thread are assigned to new, different cores. Thus, the first thread and the second thread no longer share the same cache, reducing the incidence of cache misses and thereby improving performance of both threads.

[0026] For further explanation, FIG. 5 shows a flowchart illustrating an exemplary method for automatic optimization of a central processing unit (CPU), which includes monitoring 202 performance activity of a workload including multiple threads (e.g., by configuration module 114) and modifying 204 resource allocation of multiple cores for the multiple threads based on the performance activity.

[0027] 5 also differs from FIG. 2 in that it includes monitoring 502 additional performance activity (e.g., by configuration module 114). In other words, after changing 204 the resource allocation, the performance activity of the workload is monitored 502. Thus, the additional performance activity reflects the performance of the workload after changing 204 the resource allocation.

[0028] The method of Figure 5 also differs from the method of Figure 2 in that it includes determining 504 whether to reverse the resource allocation change based on additional performance activity. For example, performance activity monitored 202 before changing 204 the resource allocation is compared to additional performance activity monitored 502 after changing 204 the resource allocation to determine whether performance has improved. If the additional performance activity indicates that performance has deteriorated, remained the same, or rises above a threshold, it is determined that the resource allocation change is reversed. If the additional performance activity indicates that performance has improved or rises above a threshold, it is determined that the change is not reversed.

[0029] Those skilled in the art will appreciate that in some embodiments, the method of Figure 5 is performed iteratively so that multiple changes are made to the resource allocation. If a given change results in improved performance, the change is maintained. Additional changes are then performed, and a decision is made as to whether to keep or revert the change.

[0030] For further explanation, FIG. 6 shows a flowchart illustrating an exemplary method for automatic optimization of a central processing unit (CPU), which includes monitoring 202 performance activity of a workload including multiple threads (e.g., by configuration module 114) and modifying 204 resource allocation of multiple cores for the multiple threads based on the performance activity.

[0031] The method of FIG. 6 also differs from FIG. 2 in that it includes storing 602 (e.g., by configuration module 114) data 604 indicative of resource allocation in association with a workload. The data 604 is stored in a storage location 606. In some embodiments, the storage location 606 is local storage (e.g., local non-volatile memory such as disk storage). In other embodiments, the storage location 606 is remote storage (e.g., a cloud storage system or a server). The data 604 indicates the resource allocation in association with the workload by identifying in the data 604 the particular workload for which the resource allocation was optimized. For example, the data 604 indicates a process name or identifier, an application name, or other identifier associated with the workload.

[0032] 6 also differs from FIG. 2 in that it includes loading 608 data 604 indicative of resource allocations based on the execution of a workload. For example, in some embodiments, the data 604 is loaded 608 in response to a request or command to execute a workload. In other embodiments, the configuration module 114 or another module monitors executed applications and services to determine that a workload is being executed. In some embodiments, after loading 608 the data 604, the resource allocations indicated in the data 604 are applied such that resources are optimally allocated for the particular workload.

[0033] In view of the above discussion, the reader will recognize that automatic central processing unit (CPU) utilization optimization according to embodiments of the present disclosure includes the following advantages: · Improve the performance of computing systems by optimizing resource allocation for specific workloads.

[0034] Exemplary embodiments of the present disclosure are described primarily in terms of a fully functional computer system for automated central processing unit (CPU) utilization optimization. However, skilled artisans will recognize that the present disclosure may also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact discs for optical drives, magnetic tape, and the like, as will occur to those skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means is capable of executing the steps of the methods of the present disclosure embodied in a computer program product. Those skilled in the art will also recognize that, while some of the exemplary embodiments described herein are adapted for software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0035] The present disclosure may be a system, a method, and / or a computer program product that may include computer-readable storage medium(s) having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0036] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or ridge structures in a groove having instructions recorded thereon, and any suitable combination of the above. As used herein, computer-readable storage media should not be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0037] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0038] The computer-readable program instructions for carrying out the operations of the present disclosure may be either assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, or conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to implement aspects of the present disclosure.

[0039] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0040] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium having instructions stored therein that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, including an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0041] Furthermore, computer-readable program instructions can be loaded into a computer, other programmable data processing apparatus, or other device to execute a series of operational steps on the computer, other programmable data processing apparatus, or other device, thereby creating a computer-implemented process in which the instructions executing on the computer, other programmable data processing apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0042] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or a combination of special-purpose hardware and computer instructions.

[0043] From the foregoing description, it will be understood that modifications and variations may be made in various embodiments of the present disclosure. The descriptions herein are for illustrative purposes only and are not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A method for automatic central processing unit (CPU) utilization optimization, comprising: the CPU includes multiple cores; Varying resource allocations of the plurality of cores to a workload including a plurality of threads based on performance activity of the workload; storing data indicative of the resource allocation in association with the workload; and loading data indicative of the resource allocation based on the execution of the workload. method.

2. further comprising identifying a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread based on the performance activity; changing the resource allocation includes changing core allocation to reduce a physical distance between a first core of the plurality of cores to which the first thread is assigned and a second core of the plurality of cores to which the second thread is assigned.

10. The method of claim 1.

3. the first core and the second core are located within the same computing core complex (CCX), the same core complex die (CCD), the same socket, the same non-uniform memory access (NUMA) domain, and / or the same compute node; The method of claim 2.

4. further comprising identifying a first thread of the plurality of threads and a second thread of the plurality of threads that is assigned to the same core of the plurality of cores based on a degree of cache misses indicated by the performance activity; changing the resource allocation includes allocating one or more of the first thread and the second thread to a different core of the plurality of cores; 10. The method of claim 1.

5. monitoring additional performance activity after modifying the resource allocation; determining whether to reverse the resource allocation change based on the additional performance activity.

10. The method of claim 1.

6. modifying the resource allocation includes modifying one or more thresholds of one or more cores of the plurality of cores; The one or more thresholds include reliability limits, including electrical design current (EDC) thresholds or thresholds for the amount of time a core can safely spend at a voltage / temperature pair.

10. The method of claim 1.

7. 1. An apparatus for automatic central processing unit (CPU) utilization optimization, comprising: the CPU includes multiple cores; Varying resource allocations of the plurality of cores to a workload including a plurality of threads based on performance activity of the workload; storing data indicative of the resource allocation in association with the workload; loading data indicative of the resource allocation based on execution of the workload; configured to: Device.

8. configured to identify a first thread of the plurality of threads and a second thread of the plurality of threads related to the first thread based on the performance activity; changing the resource allocation includes changing core allocation to reduce a physical distance between a first core of the plurality of cores to which the first thread is assigned and a second core of the plurality of cores to which the second thread is assigned.

8. The apparatus of claim 7.

9. the first core and the second core are located within the same computing core complex (CCX), the same core complex die (CCD), the same socket, the same non-uniform memory access (NUMA) domain, and / or the same compute node; 9. The apparatus of claim 8.

10. configured to identify a first thread among the plurality of threads and a second thread among the plurality of cores, the second thread being assigned to the same core of the plurality of cores, based on a degree of cache misses indicated by the performance activity; changing the resource allocation includes allocating one or more of the first thread and the second thread to a different core of the plurality of cores; 8. The apparatus of claim 7.

11. monitoring additional performance activity after modifying the resource allocation; determining whether to reverse the resource allocation change based on the additional performance activity; and configured to:

8. The apparatus of claim 7.

12. modifying the resource allocation includes modifying one or more thresholds of one or more cores of the plurality of cores; The one or more thresholds include reliability limits, including electrical design current (EDC) thresholds or thresholds for the amount of time a core can safely spend at a voltage / temperature pair.

8. The apparatus of claim 7.

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