Display device

Abstract

To reduce luminance irregularity while achieving high definition.SOLUTION: A drive circuit array substrate includes a drive circuit arranged in an array on a semiconductor substrate. In a drive circuit group composed of a plurality of adjacent drive circuits, a well tap is provided in part of the plurality of drive circuits included in the drive circuit group.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] A display device is known that includes a drive circuit array substrate on which drive circuits including transistors are arranged in a matrix, and light-emitting elements arranged in an array on the upper part of the drive circuit array substrate. For example, a small, high-definition self-luminous display in which drive circuits are formed on a silicon substrate and light-emitting elements including an organic light-emitting layer are arranged on the upper part of the drive circuits is called a micro OLED (M-OLED: Micro Organic Light Emitting Diode) display.

[0003] Micro OLED displays have the advantages of high brightness, high resolution, and small volume. For these reasons, they are increasingly being applied to electronic viewfinders for digital cameras and optical engines for head-mounted displays. A driving circuit consisting of a transistor and a capacitor is well known as a circuit for driving light-emitting elements (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-187672 Summary of the Invention [Problem to be solved by the invention]

[0005] As display devices become increasingly high-definition, the size of transistors used in driver circuits for driving light-emitting elements must also be reduced. However, as transistor size decreases, the threshold voltage of the transistor also varies. Therefore, qualitatively, the higher the resolution of display devices, the worse the degree of brightness unevenness becomes.

[0006] Therefore, an object of the present disclosure is to provide a display device that can reduce brightness unevenness while achieving high definition, an electronic device equipped with such a display device, and a drive circuit array substrate used in such a display device, etc. [Means for solving the problem]

[0007] In order to achieve the above object, a drive circuit array substrate according to the present disclosure comprises: including drive circuits arranged in an array on a semiconductor substrate; In a drive circuit group consisting of a plurality of adjacent drive circuits, the well tap is provided in some of the drive circuits included in the drive circuit group. This is a drive circuit array substrate.

[0008] In order to achieve the above object, the display device according to the present disclosure comprises: a drive circuit array substrate including drive circuits arranged in an array on a semiconductor substrate; light-emitting elements arranged in an array above the drive circuit and driven by the drive circuit; It is equipped with In a drive circuit group consisting of a plurality of adjacent drive circuits, the well tap is provided in some of the drive circuits included in the drive circuit group. It is a display device.

[0009] In order to achieve the above object, an electronic device according to the present disclosure includes: a drive circuit array substrate including drive circuits arranged in an array on a semiconductor substrate; light-emitting elements arranged in an array above the drive circuit and driven by the drive circuit; It is equipped with In a drive circuit group consisting of a plurality of adjacent drive circuits, the well tap is provided in some of the drive circuits included in the drive circuit group. The electronic device is equipped with a display device. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a conceptual diagram of a display device according to a first embodiment. [Figure 2] FIG. 2 is a schematic circuit diagram of the (n, m)th pixel (display element). [Figure 3] FIG. 3 is a schematic partial cross-sectional view of a portion including pixels (display elements) in a display device. [Figure 4] 4A and 4B are diagrams for explaining the relationship between the circuit diagram of the drive circuit and the actual circuit layout. Fig. 4A shows the circuit diagram. Fig. 4B is a plan view for explaining the basic element layout. [Figure 5] FIG. 5 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in a drive circuit array substrate of a reference example. [Figure 6] FIG. 6 is a schematic partial plan view of a substrate and the like for explaining the arrangement of various control lines in a drive circuit array substrate of a reference example. [Figure 7] FIG. 7 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in the drive circuit array substrate according to the first embodiment. [Figure 8] 8A and 8B are schematic plan views for explaining the arrangement relationship of the drive circuit groups in the drive circuit array substrate according to the first embodiment. [Figure 9] 9A and 9B are schematic plan views illustrating the arrangement of the drive circuit groups in the drive circuit array substrate according to the first embodiment, following FIG. 8B. [Figure 10] 10A and 10B are schematic plan views illustrating the arrangement of the drive circuit groups in the drive circuit array substrate according to the first embodiment, following FIG. 9B. [Figure 11] 11A and 11B are schematic plan views illustrating the arrangement of the drive circuit groups in the drive circuit array substrate according to the first embodiment, following FIG. 10B. [Figure 12] FIG. 12 is a schematic partial plan view of a substrate and the like for explaining the arrangement of various control lines in the drive circuit array substrate according to the first embodiment. [Figure 13] Continuing from FIG. 12, FIG. 13 is a schematic partial plan view of the substrate and the like for explaining the arrangement of various control lines in the drive circuit array substrate according to the first embodiment. [Figure 14] Continuing from FIG. 13, FIG. 14 is a schematic partial plan view of the substrate and the like for explaining the arrangement of various control lines in the drive circuit array substrate according to the first embodiment. [Figure 15] 15A and 15B are diagrams illustrating an example of the positional relationship between a drive circuit and light-emitting elements. Fig. 15A is a schematic partial plan view showing the circuit layout of a drive circuit. Fig. 15B is a schematic partial plan view showing the layout of light-emitting elements. [Figure 16] 16A and 16B are schematic partial plan views showing the arrangement of light-emitting elements, following FIG. 15B. [Figure 17] FIG. 17 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in a drive circuit array substrate according to a first modified example. [Figure 18] 18A and 18B are schematic plan views for explaining the arrangement relationship of drive circuit groups in a drive circuit array substrate according to a first modified example. [Figure 19] 19A and 19B are schematic plan views illustrating the arrangement of the drive circuit groups in a drive circuit array substrate according to a first modified example, following FIG. 18B. [Figure 20] FIG. 20 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in a drive circuit array substrate according to a second modified example. [Figure 21] 21A and 21B are diagrams illustrating an example of the positional relationship between a drive circuit and light-emitting elements. Fig. 21A is a schematic partial plan view showing the circuit layout of a drive circuit. Fig. 21B is a schematic partial plan view showing the layout of light-emitting elements. [Figure 22] 22A and 22B are schematic partial plan views showing the arrangement of light-emitting elements, following FIG. 21B. [Figure 23] FIG. 23 is a schematic partial plan view showing the arrangement of light-emitting elements, continuing from FIG. 22B. [Figure 24] FIG. 24 shows the appearance of a single-lens reflex digital still camera with interchangeable lenses, with FIG. 24A showing a front view and FIG. 24B showing a rear view. [Figure 25] FIG. 25 is an external view of a head-mounted display. [Figure 26] FIG. 26 is an external view of a see-through head-mounted display. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, the present disclosure will be described based on embodiments with reference to the drawings. The present disclosure is not limited to the embodiments, and various numerical values ​​and materials in the embodiments are examples. In the following description, the same elements or elements having the same functions will be designated by the same reference numerals, and redundant description will be omitted. The description will be given in the following order. 1. General Description of the Drive Circuit Array Substrate, Display Device, and Electronic Device According to the Present Disclosure 2. First embodiment 3. First Modification 4. Second Modification 5. Description of electronic devices 6.Other

[0012] [General Description of the Drive Circuit Array Substrate, Display Device, and Electronic Device According to the Present Disclosure] In the following description, the drive circuit array substrate according to the present disclosure, the drive circuit array substrate used in the display device according to the present disclosure, and the drive circuit array substrate used in the display device provided in the electronic device according to the present disclosure may be simply referred to as the "drive circuit array substrate according to the present disclosure." Furthermore, the display device according to the present disclosure and the display device used in the electronic device according to the present disclosure may be simply referred to as the "display device according to the present disclosure."

[0013] As described above, the drive circuit array substrate of the present disclosure has: including drive circuits arranged in an array on a semiconductor substrate; In a drive circuit group consisting of a plurality of adjacent drive circuits, well taps are provided in some of the drive circuits included in the drive circuit group.

[0014] In a configuration in which well taps are provided for only some of the drive circuits in a drive circuit group, as opposed to a configuration in which well taps are provided for all of the drive circuits, the proportion of the area occupied by the well taps can be reduced, thereby allowing for an expansion of the area in which transistors and the like are arranged.

[0015] In the drive circuit array substrate of the present disclosure, among the plurality of drive circuits included in the drive circuit group, the transistors constituting a predetermined drive circuit may be configured to be larger in size than the transistors of the other drive circuits, and in this case, the current supply transistors constituting the predetermined drive circuit may be configured to be larger in size.

[0016] In the drive circuit array substrate of the present disclosure including the various preferred configurations described above, the well taps can be provided in predetermined drive circuits among the plurality of drive circuits included in the drive circuit group.

[0017] In the drive circuit array substrate of the present disclosure including the various preferred configurations described above, the drive circuit group includes a first drive circuit, a second drive circuit, and a third drive circuit; the second drive circuit is disposed between the first drive circuit and the third drive circuit, The well tap is provided in the second drive circuit, The transistors constituting the second drive circuit may be configured to be larger in size than the transistors of the first drive circuit and the third drive circuit.

[0018] In this case, in the group of drive circuits, the third drive circuit can be configured to have a circuit layout that is vertically and horizontally inverted from that of the first drive circuit.

[0019] Alternatively, in this case, a pair of adjacent drive circuit groups aligned in the longitudinal direction of the drive circuits can be arranged to form a repeating unit. The first drive circuit and the third drive circuit belonging to one of the pair of drive circuit groups can be configured to have circuit arrangements that are vertically inverted relative to the first drive circuit and the third drive circuit belonging to the other drive circuit group, respectively. Furthermore, the second drive circuit belonging to one of the pair of drive circuit groups can be configured to have a circuit arrangement that is horizontally inverted relative to the second drive circuit belonging to the other drive circuit group, or a circuit arrangement that is vertically and horizontally inverted.

[0020] Alternatively, in this case, the group of drive circuits may further include a fourth drive circuit.

[0021] In the drive circuit array substrate of the present disclosure including the various preferred configurations described above, the arrangement of the drive circuits is not particularly limited, and may be, for example, a stripe arrangement, a mosaic arrangement, or a delta arrangement. From the viewpoint of facilitating the circuit formation process, it is preferable that the drive circuits be arranged in a stripe arrangement.

[0022] As described above, the display device of the present disclosure includes: a drive circuit array substrate including drive circuits arranged in an array on a semiconductor substrate; light-emitting elements arranged in an array above the drive circuit and driven by the drive circuit; It is equipped with In a drive circuit group consisting of a plurality of adjacent drive circuits, well taps are provided in some of the drive circuits included in the drive circuit group.

[0023] In the display device of the present disclosure, the drive circuit group includes a first drive circuit, a second drive circuit, and a third drive circuit; the second drive circuit is disposed between the first drive circuit and the third drive circuit, The well tap is provided in the second drive circuit, The transistors constituting the second driving circuit are enlarged in size relative to the transistors of the first driving circuit and the third driving circuit; The first driving circuit and the third driving circuit are connected to the light emitting elements corresponding to the red pixels and the blue pixels, respectively; The second driving circuit may be connected to a light emitting element corresponding to a green pixel.

[0024] By increasing the size of the current supply transistors in the second driving circuit, the variation in threshold voltage of the transistors that pass current to the light-emitting elements corresponding to the green pixels is reduced.Since green has a high luminosity factor, brightness unevenness can be reduced more effectively.

[0025] In the display device of the present disclosure having the above-described preferred configuration, the group of drive circuits may further include a fourth drive circuit connected to the light-emitting element corresponding to the white pixel.

[0026] In the display device of the present disclosure including the various preferred configurations described above, the light-emitting elements can be arranged in a stripe array, a mosaic array, a square array, or a delta array.

[0027] In the display device of the present disclosure including the various preferred configurations described above, for example, a current-driven light-emitting element whose light emission luminance changes depending on the value of the current flowing therethrough can be used. Examples of current-driven light-emitting elements include organic electroluminescence elements, LED elements, and semiconductor laser elements. These elements can be constructed using well-known materials and methods. From the perspective of constructing a flat display device, it is particularly preferable that the light-emitting element be an organic electroluminescence element.

[0028] An organic electroluminescence element is formed by disposing an organic layer, which is made up of multiple material layers stacked between an anode electrode and a cathode electrode. The organic layer emits light when a voltage is applied between the anode electrode and the cathode electrode. The organic layer can be configured, for example, by stacking a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer in this order from the anode electrode side. The hole transport material, hole transport material, electron transport material, and organic light-emitting material that constitute the organic layer are not particularly limited, and well-known materials can be used.

[0029] The organic electroluminescent element can be configured to emit white light, for example. This configuration has the advantage that the organic layer can be formed as a common layer. The white-emitting organic layer may be configured in a so-called tandem structure, in which multiple organic light-emitting layers are connected via a charge-generating layer or an intermediate electrode. For example, a light-emitting element that emits white light can be configured by stacking red-, green-, and blue-emitting organic light-emitting layers, or by stacking yellow- and blue-emitting organic light-emitting layers. For color display, color filters corresponding to the colors to be displayed can be appropriately arranged corresponding to each light-emitting element. The color filters can be formed, for example, using a resin material containing a pigment or dye.

[0030] Alternatively, the organic electroluminescent element may be configured to emit red, green, or blue light. This configuration complicates the process for forming the organic layer, but has the advantage of superior luminous efficiency. Even in this case, a color filter corresponding to the color to be displayed may be disposed to improve color purity.

[0031] The display device may be configured to display monochrome images or color images. Examples of pixel values ​​of the display device include U-XGA (1600, 1200), HD-TV (1920, 1080), Q-XGA (2048, 1536), as well as some image resolutions such as (3840, 2160), (7680, 4320), but are not limited to these values.

[0032] The electronic device of the present disclosure may be configured to include the display device of the present disclosure including the various preferred configurations described above. Examples of the electronic device include direct-view and projection display devices, as well as various electronic devices equipped with an image display function.

[0033] Hereinafter, the drive circuit array substrate of the present disclosure, the display device of the present disclosure, and the electronic device of the present disclosure may be simply referred to as [the present disclosure].

[0034] The semiconductor substrate used in the present disclosure may be, for example, a semiconductor substrate made of silicon, or a substrate in which a semiconductor material layer such as a silicon single crystal layer is formed on a substrate such as quartz.

[0035] The conductivity type of the transistors used in the driver circuit is not particularly limited. For example, they may be p-channel transistors or n-channel transistors. For example, a well region may be provided in a silicon single crystal layer, and the transistors may be formed in the well region.

[0036] The materials constituting the various wirings and electrodes used in the present disclosure are not particularly limited as long as they do not interfere with the implementation of the present disclosure. For example, metal materials such as copper (Cu), aluminum (Al), aluminum alloys such as AlCu and AlSi, tungsten (W), and tungsten alloys such as tungsten silicide (WSi) can be used.

[0037] The materials constituting the insulating layer and insulating film used in the present disclosure are not particularly limited as long as they do not interfere with the implementation of the present disclosure. For example, silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ), or organic insulating materials such as polyimide resin, acrylic resin, or novolac resin can be used.

[0038] The method for forming the wiring, electrodes, insulating layers, insulating films, etc. is not particularly limited, and any known film forming method can be used as long as it does not interfere with the implementation of the present disclosure. The same applies to the patterning method of these.

[0039] The various conditions in this specification are satisfied not only when they are strictly met, but also when they are substantially met. Various variations that occur in design or manufacturing are allowed. Furthermore, the drawings used in the following description are schematic and do not represent actual dimensions or proportions.

[0040] [First embodiment] The first embodiment relates to a drive circuit array substrate, a display device, and an electronic device according to the present disclosure.

[0041] FIG. 1 is a conceptual diagram of a display device according to a first embodiment.

[0042] The display device according to the first embodiment is an active matrix display device. The display device 1 includes pixels 10 arranged in a matrix, and various circuits for controlling the pixels 10, such as a horizontal drive circuit 11, a vertical drive circuit 12, an initialization circuit 13, and a light emission control circuit 14. Symbol SCL denotes a scanning line for scanning the pixels 10, and symbol DTL denotes a signal line for supplying various voltages to the pixels 10. Symbol DS denotes a control line for controlling whether the pixels 10 emit light or not, and symbol AZ denotes a control line for initializing the pixels 10.

[0043] The pixels 10 are connected to scan lines SCL, data lines DTL, control lines AZ, and control lines DS, and are arranged in a matrix, for example, M in the row direction (X direction in the figure) and N in the column direction (Y direction in the figure), for a total of M×N pixels. The pixels 10 arranged in a two-dimensional matrix form a display area for displaying an image.

[0044] The number of scanning lines SCL, control lines AZ, and control lines DS is M. The pixel 10 in the m-th row (where m=1, 2, . . . , M) is connected to the m-th scanning line SCL. m , control line AZ m and control line DS m , which constitute one pixel row. The number of data lines DTL is N. The pixel 10 in the n-th column (where n=1, 2, . . . , N) is connected to the n-th data line DTL n Although not shown in Fig. 1, the display device 1 is provided with a common power supply line connected to all the pixels 10 in common.

[0045] The pixels 10, horizontal drive circuit 11, vertical drive circuit 12, initialization circuit 13, and light emission control circuit 14 are integrally formed on a substrate, that is, the display device 1 is a driver circuit-integrated display device.

[0046] A digital signal representing a gradation corresponding to an image to be displayed is supplied to the vertical drive circuit 12 from, for example, a device not shown. The vertical drive circuit 12 generates an analog signal corresponding to the gradation value and supplies it to the data line DTL as a video signal. The maximum value of the generated analog signal is approximately equal to the power supply voltage supplied to the vertical drive circuit 12, and the amplitude is a signal of about several volts.

[0047] The initialization circuit 13 supplies a control signal to the control line AZ. This control signal initializes the potential of the light-emitting element included in the pixel 10. Then, the horizontal drive circuit 11 supplies a scanning signal to the scanning line SCL. This scanning signal causes the pixels 10 to be line-sequentially scanned, for example, row by row. An analog signal from the data line DTL is written into the scanned pixel 10.

[0048] The light emission control circuit 14 supplies a control signal to the control line DS, which controls whether the pixel emits light or not.

[0049] The light-emitting device 1 is capable of color display. In FIG. 1, light-emitting elements corresponding to red, green, and blue displays are designated by the symbols R, G, and B, respectively. This is also true in FIG. 15B and other figures described later. A group of three pixels 10 arranged in the row direction constitutes one color pixel. Therefore, if N' = N / 3, then the display area will have N' color pixels arranged in the row direction and M color pixels arranged in the column direction, for a total of N' x M color pixels.

[0050] As described above, the pixels 10 are scanned line-by-line in units of rows by the scanning signal of the horizontal drive circuit 11. The pixel 10 located in the m-th row and n-th column will be referred to as the (n, m)-th pixel 10 hereinafter.

[0051] In the display device 1, N pixels 10 arranged in the mth row are driven simultaneously. In other words, the timing of light emission / non-emission of N pixels 10 arranged along the row direction is controlled for each row to which they belong. If the display frame rate of the display device 1 is represented as FR (times / second), the scanning period per row (so-called horizontal scanning period) when the display device 1 is line-sequentially scanned row by row is less than (1 / FR) × (1 / M) seconds.

[0052] The above is a summary of the display device 1. Next, the basic configuration of the pixel 10 will be described.

[0053] FIG. 2 is a schematic circuit diagram of the (n, m)th pixel (display element).

[0054] As shown in FIG. 2, the pixel 10 includes a current-driven light-emitting element ELP and a drive circuit DL for driving the light-emitting element ELP.

[0055] As will be explained in detail later with reference to Figures 3 to 14, the drive circuits DL are arranged in an array on a semiconductor substrate. The semiconductor substrate has a common well region, and the drive circuits DL are arranged in the common well region. In a drive circuit group consisting of a plurality of adjacent drive circuits DL, well taps are provided in some of the drive circuits included in the drive circuit group.

[0056] As shown in Fig. 2, the driving circuit DL includes four transistors and two capacitance parts. W indicates a write transistor for writing a video signal, and symbol TR DRV indicates a driving transistor that passes a current through the light-emitting element ELP. AZ denotes an initialization transistor for initializing the anode voltage of the light-emitting element ELP, and symbol TR DS is the driving transistor TR DRV and driving voltage V CC The light-emitting control transistor TR is arranged between the power supply line and the power supply line to which the power is supplied. These are made of p-channel transistors.

[0057] Light-emitting control transistor TR DS In this case, one of the source / drain regions is driven by a driving voltage V CC The power supply line is supplied with the capacitance part C Sub The other source / drain region is connected to one electrode of the driving transistor T DRV One of the source / drain regions and the capacitance part C Sub The other electrode of the light-emitting control transistor TR DS The conductive / non-conductive state of the control line DS m is controlled by a control signal supplied to

[0058] Drive transistor T DRV Between the gate electrode and one of the source / drain regions, there is a capacitance C S is connected. Also, the driving transistor T DRVThe other source / drain region is connected to the anode electrode of the light-emitting element ELP. The cathode electrode of the light-emitting element ELP is connected to the anode electrode of the light-emitting element ELP. Cat The light-emitting element ELP is an organic electroluminescent element.

[0059] Write transistor TR W In this case, one of the source / drain regions is connected to the data line DTL n The other source / drain region is connected to the driving transistor T DRV The gate electrode of the write transistor TR W The conductive / non-conductive state of the scan line SCL m The scanning signal is supplied to the

[0060] Initialization transistor TR AZ In this case, one of the source / drain regions is connected to a predetermined voltage V SS The other source / drain region is connected to the anode electrode of the light emitting part ELP. AZ The conductive / non-conductive state of the control line AZ connected to the gate electrode m is controlled by a control signal supplied to

[0061] The basic operation of the drive circuit DL will now be described. DS is in a non-conductive state, the initialization transistor TR AZ is turned on, and the anode voltage of the light emitting element ELP is initialized. W is turned on, and a signal voltage is applied from the data line DTL to the driving transistor TR DRV The voltage is applied to the gate electrode of the capacitor C S holds a voltage corresponding to the signal voltage. S By this, the driving transistor TR DRV V gs (the potential difference between the gate electrode and the source region) is maintained.

[0062] Next, the write transistor TR W is turned off, and the light-emitting control transistor TR DS The driving transistor TR is turned on. DRV The capacitance part C S V held at gs In response to this, a current shown in the following equation (1) flows. In addition, the drive transistor TR DRV Regarding μ: Effective mobility L: Channel length W: Channel width V gs : potential difference between the gate electrode and the source region V th : Threshold voltage C ox : (dielectric constant of gate insulating layer) × (dielectric constant of vacuum) / (thickness of gate insulating layer) k≡(1 / 2)·(W / L)·C ox Let's say.

[0063] I ds =k μ (V gs -V th ) 2 (1)

[0064] This drain current I ds When this drain current I flows through the light emitting element ELP, the light emitting element ELP emits light. ds The light emitting state (brightness) of the light emitting element is controlled depending on the magnitude of the value of .

[0065] The above has described the basic configuration of the pixel 10. Next, the three-dimensional arrangement of the various components that make up the display device 1 will be described.

[0066] FIG. 3 is a schematic partial cross-sectional view of a portion including pixels (display elements) in a display device.

[0067] First, the drive circuit array substrate 20 will be described. Reference numeral 21 denotes a p-type substrate made of, for example, silicon. An n-type common well region 22 is formed on the substrate 21. Various transistors of the drive circuit DL are arranged in the common well region 22. For convenience of illustration, in FIG. 3, only the drive transistor TR DRV Reference numeral 23 denotes an element isolation region that separates the transistors, and reference numerals 24A and 24B denote the driving transistors TR W The portion sandwiched between the pair of source / drain regions 24A and 24B forms a channel region.

[0068] A gate insulating film 25 is formed on the channel region, and a gate electrode 26 is formed thereon. The gate insulating film 25 is made of, for example, silicon oxide (SiO x ) and silicon nitride (SiN x An interlayer insulating film 27 is formed on the entire surface including the gate electrode 26. The interlayer insulating film 27 can be formed of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ) or the like. The source / drain electrodes 28A, 28B are connected to the source / drain regions of the transistor via openings provided in the interlayer insulating film 27. A planarizing film 31 is formed on the entire surface including the source / drain electrodes 28A, 28B. The planarizing film 31 is configured by laminating various material layers, and also includes various wirings and electrodes, which are omitted in the figure.

[0069] An anode electrode 32 of the light-emitting element ELP is formed on the planarization film 31. The anode electrode 32 is connected to the driving transistor TR through an opening provided in the planarization film 31. DRV The anode electrodes 32 are connected to the other source / drain electrode 28B. Reference numeral 33 denotes a partition wall that separates the adjacent anode electrodes 32 from each other.

[0070] An organic layer 40 formed by laminating a plurality of material layers and a cathode electrode 51 made of a transparent conductive material are formed on the entire surface including the anode electrode 32 and the partition wall 33. The anode electrode 32, the organic layer 40, and the cathode electrode 51 are laminated together to form a light-emitting element ELP. In the display device 1, the portion where the light-emitting element ELP is formed is denoted by the symbol FP.

[0071] A protective film 52 is formed on the cathode electrode 51. The protective film 52 is made of, for example, an organic insulating film such as a polyimide resin, an acrylic resin, or a novolac resin, or a silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y The organic layer 40 can be formed using an inorganic insulating film such as a transparent substrate 62. A color filter 61 corresponding to the color to be displayed and a transparent substrate 62 are sequentially stacked on the protective film 52. Light emitted in the organic layer 40 passes through the color filter 61 and the transparent substrate 62 and is emitted to the outside.

[0072] The above has described the three-dimensional arrangement of the various components that make up the display device 1. Next, the circuit arrangement of the drive circuits on the drive circuit array substrate will be described.

[0073] 4A and 4B are diagrams for explaining the relationship between the circuit diagram of the drive circuit and the actual circuit layout. Fig. 4A shows the circuit diagram. Fig. 4B is a plan view for explaining the basic element layout.

[0074] FIG. 4B shows the basic layout of the transistors included in the driver circuit DL. The transistors included in the driver circuit DL are formed in predetermined sections in a common well region. The shaded areas indicate gate electrodes located above the channel regions of each transistor. The symbol WTP indicates a well tap for supplying voltage to the well region.

[0075] Here, to facilitate understanding of the present disclosure, the circuit layout and the like of a drive circuit array substrate of a reference example will be described.

[0076] Fig. 5 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in a drive circuit array substrate of a reference example. Fig. 6 is a schematic partial plan view of a substrate and the like for explaining the arrangement of various control lines in a drive circuit array substrate of a reference example.

[0077] 5, in the drive circuit array substrate 920 of the reference example, drive circuits DL are arranged in an array as shown in FIG. 4B. Each drive circuit has the same layout relationship, and well taps WTP are provided in the areas of all drive circuits DL.

[0078] The inventors noticed that the potential of the well region can be maintained even if the well taps WTP are omitted from some of the driving circuits, and that by reducing the area occupied by the well taps WTP, the size of the transistors in the driving circuits can be increased.

[0079] FIG. 7 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in the drive circuit array substrate according to the first embodiment.

[0080] As shown in FIG. 7, in the drive circuit array substrate 20, in a drive circuit group consisting of a plurality of adjacent drive circuits, well taps WTP are provided in some of the drive circuits included in the drive circuit group.

[0081] Among the plurality of drive circuits included in the drive circuit group, the transistors constituting a predetermined drive circuit are enlarged in size relative to the transistors of the other drive circuits. Furthermore, among the plurality of drive circuits included in the drive circuit group, well taps are provided in a predetermined drive circuit. The drive circuits are arranged in a stripe pattern extending in the column direction.

[0082] As will be described below, in the drive circuit array substrate 20, the drive circuit group includes a first drive circuit, a second drive circuit, and a third drive circuit, the second drive circuit is disposed between the first drive circuit and the third drive circuit, The well tap is provided in the second drive circuit, The transistors constituting the second drive circuit are enlarged in size relative to the transistors of the first drive circuit and the third drive circuit.

[0083] That is, in the drive circuit group designated by symbol Type A, which is made up of a first drive circuit DL_1A, a second drive circuit DL_2A, and a third drive circuit DL_3A, the well tap WTP is provided only in the second drive circuit DL_2A. Also, in the drive circuit group designated by symbol Type B, which is made up of a first drive circuit DL_1B, a second drive circuit DL_2B, and a third drive circuit DL_3B, the well tap WTP is provided only in the second drive circuit DL_2B.

[0084] In the drive circuit array substrate 20, the third drive circuit in the drive circuit group has a circuit layout that is vertically and horizontally inverted from that of the first drive circuit. That is, the third drive circuit DL_3A has a circuit layout that is vertically and horizontally inverted from that of the first drive circuit DL_1A. Also, the third drive circuit DL_3B has a circuit layout that is vertically and horizontally inverted from that of the first drive circuit DL_1B.

[0085] A pair of adjacent drive circuit groups (a Type A drive circuit group and a Type B drive circuit group) aligned in the longitudinal direction of the drive circuit (Y direction in the drawing) are arranged to form a repeating unit.

[0086] The first and third drive circuits belonging to one of a pair of drive circuit groups have a circuit arrangement that is the vertically inverted version of the first and third drive circuits belonging to the other drive circuit group. That is, the first and third drive circuits DL_1B and DL_3B of the Type B drive circuit group have a circuit arrangement that is the vertically inverted version of the first and third drive circuits DL_1A and DL_3A of the Type A drive circuit group.

[0087] Furthermore, the second drive circuit belonging to one of the pair of drive circuit groups has a circuit layout that is the vertical and horizontal inversion of the second drive circuit belonging to the other drive circuit group. That is, the second drive circuit DL_2B of the Type B drive circuit group has a circuit layout that is the vertical and horizontal inversion of the second drive circuit DL_2A of the Type A drive circuit group.

[0088] In the region where the well taps WTP are omitted in the drive circuits DL_1A and DL_1B, drive transistors whose size is enlarged are arranged in the second drive circuit DL_2A. Similarly, in the region where the well taps WTP are omitted in the drive circuits DL_3B and DL_3A, drive transistors whose size is enlarged are arranged in the second drive circuit DL_2B. In this way, the size of the current supply transistors among the transistors constituting a predetermined drive circuit is enlarged.

[0089] Variation in transistor threshold voltage σV th The general formula for this is shown in the following formula (2).

[0090] σV th =(q / 3ε0) 1 / 2 ·(T INV ·(V th +V0) / (L W)) 1 / 2 (2) still, q: elementary charge ε0: Dielectric constant of vacuum T INV :Oxide film thickness V th : Threshold voltage V0:-V FB -2Φ (V FB is the flat band potential, and Φ is the difference between the Fermi level and the intrinsic Fermi level) L: Channel length W: Channel width Let's say.

[0091] As is clear from the above formula (2), by increasing the size of the transistor and thereby increasing the channel length L and channel width W, it is possible to reduce the variation in threshold voltage.

[0092] In the display device 1 shown in Fig. 1, the first drive circuits DL_1A, DL_1B and the third drive circuits DL_3A, DL_3B are connected to light-emitting elements corresponding to red pixels and light-emitting elements corresponding to blue pixels, respectively, and the second drive circuits DL_2A, DL_2B are connected to light-emitting elements corresponding to green pixels. Green has a relatively high visibility compared to red and blue. Therefore, the drive transistors TR included in the second drive circuits DL_2A, DL_2B that supply current to the green light-emitting elements DRV By increasing the size of the pixel, the brightness unevenness can be reduced more effectively.

[0093] Next, the transition from the arrangement of the drive circuits in the reference example to the arrangement of the drive circuits in the first embodiment will be described with reference to FIGS.

[0094] As shown in Figure 8A, the third drive circuit DL_3A located on the right side of the upper drive pixel group of a pair of drive pixel groups in the reference example is considered as a reference. As shown in Figure 8B, the first drive circuit DL_1A of the upper drive pixel group has a circuit arrangement that is vertically and horizontally inverted from the third drive circuit DL_3A. Furthermore, the first drive circuit DL_1B and the third drive circuit DL_3B of the lower drive pixel group each have a circuit arrangement that is vertically inverted from the circuit of the upper drive pixel group. In the example shown in Figure 8B, the well taps WTP of the first drive circuits DL_1A and DL_1B in the upper and lower drive pixel groups are adjacent to each other.

[0095] Next, as shown in FIG. 9A, the well taps WTP of each drive circuit are omitted. This creates room in the area where the second drive circuit should be installed. The space created by omitting the well taps WTP is indicated by the symbol Room. After that, as shown in FIG. 9B, the third drive circuits DL_3A and DL_3B are shifted a predetermined amount in the column direction relative to the first drive circuits DL_1A and DL_1B.

[0096] 10A, a second drive circuit DL_2A having a well tap WTP and an enlarged drive transistor size is placed between the first drive circuits DL_1A, 1B and the third drive circuits DL_3A, 3B, thereby forming a drive circuit group denoted by symbol Type A as shown in FIG.

[0097] FIG. 11 is a diagram illustrating a drive circuit group located above or below a drive circuit group indicated by symbol Type A. In the example shown in FIG. 11A, the well taps WTP of the third drive circuits DL_3B, 3A in the upper and lower drive pixel groups are omitted while they are adjacent to each other. As shown in FIG. 11B, a second drive circuit DL_2B having a well tap WTP and enlarged drive transistor size is disposed between the first drive circuit DL_1B, 1A and the third drive circuit DL_3B, 3A. In the example shown in FIG. 11B, a drive circuit group indicated by symbol Type B is formed.

[0098] In the drive circuit array substrate 20, the planar layout of each drive circuit is not the same. Therefore, the layout of control lines and the like is more complex than in the drive circuit array substrate 920 of the reference example. Figures 12 to 15 show the layout of control lines and the like. Figure 12 shows the layout of scanning lines SCL, Figure 13 shows the layout of control lines AZ, and Figure 14 shows the layout of control lines DS. Note that the signal lines DTL are not shown in the figures.

[0099] The circuit layout of the drive circuits on the drive circuit array substrate has been described above.

[0100] The planar arrangement of the light-emitting elements may or may not match the planar arrangement of the driving circuit. Depending on the routing of the wiring between the anode electrode and the driving circuit, the light-emitting elements can be arranged in any planar arrangement. The light-emitting elements can be arranged, for example, in a stripe arrangement, a mosaic arrangement, a square arrangement, or a delta arrangement.

[0101] Fig. 15 is a diagram for explaining an example of the positional relationship between a drive circuit and light-emitting elements. Fig. 15A is a schematic partial plan view showing the circuit layout of a drive circuit. Fig. 15B is a schematic partial plan view showing the layout of light-emitting elements. Fig. 16A and Fig. 16B are schematic partial plan views showing the layout of light-emitting elements, following Fig. 15B.

[0102] As shown in Fig. 15A, the pitch of each drive circuit in the drive circuit group is shifted in the column direction. Fig. 15B shows an example in which display elements are arranged in a stripe array with no pitch shift. Fig. 16A shows an example in which display elements are arranged in a mosaic array. Fig. 16B shows an example in which display elements are arranged in a delta array.

[0103] Although the first embodiment has been described above, the configuration of the drive circuit that controls the light emission of the light-emitting element ELP is not particularly limited. Therefore, the drive circuit and circuit arrangement described above are merely examples. The display device according to this embodiment can have various configurations.

[0104] [First Modification] Various modifications are possible in the first embodiment, and a first modification will be described below.

[0105] FIG. 17 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in a drive circuit array substrate according to a first modified example.

[0106] In the first embodiment, it has been described with reference to Fig. 7 that the second drive circuit belonging to one of a pair of drive circuit groups has a circuit arrangement that is vertically and horizontally inverted from the second drive circuit belonging to the other drive circuit group. In contrast, in the first modified example, the second drive circuit belonging to one of the pair of drive circuit groups has a circuit arrangement that is horizontally inverted from the second drive circuit belonging to the other drive circuit group.

[0107] Next, the transition from the arrangement of the drive circuits in the reference example to the arrangement of the drive circuits in the first modified example will be described with reference to FIGS.

[0108] Fig. 18A shows the state after the processes shown in Fig. 8A, Fig. 8B, and Fig. 9A have been performed. The space created by omitting the well taps WTP of the drive circuits is indicated by the symbol Room. vinegar.

[0109] 18B, a second drive circuit DL_2A having a well tap WTP and an enlarged size of the drive transistor is disposed between the first drive circuits DL_1A, 1B and the third drive circuits DL_3A, 3B. In the example shown in the figure, a drive circuit group designated by the symbol Type A is formed.

[0110] FIG. 19 is a diagram illustrating a drive circuit group located above or below a drive circuit group indicated by symbol Type A. In the example shown in FIG. 19A, the well taps WTP of the third drive circuits DL_3B, 3A in the upper and lower drive pixel groups are omitted while they are adjacent to each other. As shown in FIG. 19B, a second drive circuit DL_2B having a well tap WTP and an enlarged drive transistor size is placed between the first drive circuit DL_1B, 1A and the third drive circuit DL_3B, 3A. In the example shown in the figure, a drive circuit group indicated by symbol Type B is formed.

[0111] As described above, in the first modified example, it is not necessary to shift the third drive circuit by a predetermined amount in the column direction relative to the first drive circuit, and only the second drive circuit is shifted by a predetermined amount in the column direction.

[0112] [Second Modification] In a second modification, the display device further includes a white pixel, and the drive circuit group further includes a fourth drive circuit connected to the light-emitting element corresponding to the white pixel.

[0113] FIG. 20 is a schematic partial plan view of a substrate and the like for explaining the circuit arrangement in a drive circuit array substrate according to a second modified example.

[0114] Figure 20 shows an example in which a fourth drive circuit is added to the drive circuit group shown in Figure 7. The symbol DL_4A indicates a fourth drive circuit added to the Type A drive circuit group, and the symbol DL_4B indicates a fourth drive circuit added to the Type B drive circuit group. Both the fourth drive circuits DL_4A and DL_4B have well taps WTP, and the fourth drive circuit DL_4B has a circuit layout in which the fourth drive circuit DL_4A is upside down.

[0115] The second modified example is not limited to this. For example, a configuration can be adopted in which a fourth drive circuit is added to the drive circuit group shown in FIG. 17 as a base. Also, a configuration can be adopted in which the well tap is omitted from the fourth drive circuit. The area where the well tap is omitted can be used to further increase the size of the transistors in the drive circuit.

[0116] In the second modification, the planar arrangement of the light-emitting elements may be the same as or different from the planar arrangement of the driving circuit. The light-emitting elements can be arranged in any planar arrangement depending on the routing of the wiring between the anode electrode and the driving circuit. The light-emitting elements can be arranged in, for example, a stripe array, a mosaic array, a square array, or a delta array.

[0117] An example of the layout relationship between the drive circuit and the light emitting element will be described with reference to FIGS.

[0118] As shown in Fig. 21A, the second and third drive circuits in the drive circuit group are offset in pitch in the column direction. Fig. 21B shows an example in which display elements are arranged in a stripe array with no pitch offset. Fig. 22A shows an example in which display elements are arranged in a mosaic array. Fig. 22B shows an example in which display elements are arranged in a square array. Fig. 23 shows an example in which display elements are arranged in a delta array.

[0119] [Electronic device description] The display device according to the present disclosure described above can be used as a display unit (display unit) for electronic devices in various fields that display a video signal input to the electronic device or a video signal generated within the electronic device as an image or video. For example, it can be used as a display unit for a television set, a digital still camera, a notebook personal computer, a portable terminal device such as a mobile phone, a video camera, a head-mounted display, etc.

[0120] The display device of the present disclosure also includes a sealed modular device. The display module may include a circuit section or a flexible printed circuit (FPC) for inputting and outputting signals from the outside to the pixel array section. Below, a digital still camera and a head-mounted display are given as specific examples of electronic devices that use the display device of the present disclosure. However, the specific examples given here are merely examples and are not intended to be limiting.

[0121] (Example 1) Figure 24 shows the appearance of a single-lens reflex digital still camera with an interchangeable lens, with Figure 24A showing a front view and Figure 24B showing a rear view. A single-lens reflex digital still camera with an interchangeable lens has, for example, an interchangeable taking lens unit (interchangeable lens) 412 on the right side of the front of a camera main body 411, and a grip 413 on the left side of the front for the photographer to hold.

[0122] A monitor 414 is provided in the approximate center of the back of the camera body 411. A viewfinder (eyepiece window) 415 is provided above the monitor 414. By looking through the viewfinder 415, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 412 and determine the composition.

[0123] In the lens-interchangeable single-lens reflex digital still camera having the above configuration, the display device of the present disclosure can be used as its viewfinder 415. That is, the lens-interchangeable single-lens reflex digital still camera according to this example is produced by using the display device of the present disclosure as its viewfinder 415.

[0124] (Example 2) 25 is an external view of a head-mounted display. The head-mounted display has, for example, ear hooks 512 on both sides of a glasses-shaped display unit 511 for wearing on the user's head. In this head-mounted display, the display device of the present disclosure can be used as the display unit 511. That is, the head-mounted display according to this example is produced by using the display device of the present disclosure as the display unit 511.

[0125] (Example 3) 26 is an external view of a see-through head mounted display 611. The see-through head mounted display 611 is made up of a main body 612, an arm 613, and an eyepiece tube 614.

[0126] The main body 612 is connected to the arm 613 and the eyeglasses 600. Specifically, an end of the long side of the main body 612 is coupled to the arm 613, and one side of the main body 612 is connected to the eyeglasses 600 via a connecting member. The main body 612 may also be worn directly on the head of the human body.

[0127] The main body 612 incorporates a control board for controlling the operation of the see-through head mounted display 611 and a display unit. The arm 613 connects the main body 612 to the lens barrel 614 and supports the lens barrel 614. Specifically, the arm 613 is coupled to an end of the main body 612 and an end of the lens barrel 614, respectively, and fixes the lens barrel 614. The arm 613 also incorporates a signal line for communicating data related to images provided from the main body 612 to the lens barrel 614.

[0128] The lens barrel 614 projects image light provided from the main body 612 via the arm 613 through an eyepiece lens toward the eyes of a user wearing the see-through head mounted display 611. In this see-through head mounted display 611, the display device of the present disclosure can be used for the display unit of the main body 612.

[0129] [others] The technology of the present disclosure can also be configured as follows.

[0130] [A1] including drive circuits arranged in an array on a semiconductor substrate; In a drive circuit group consisting of a plurality of adjacent drive circuits, the well tap is provided in some of the drive circuits included in the drive circuit group. Drive circuit array board. [A2] Among the plurality of drive circuits included in the drive circuit group, transistors constituting a predetermined drive circuit are enlarged in size relative to transistors of other drive circuits. The drive circuit array substrate according to the above [A1]. [A3] Among the transistors constituting a predetermined driving circuit, the size of a current supply transistor is increased. The drive circuit array substrate according to the above [A2]. [A4] Among the plurality of drive circuits included in the drive circuit group, the well tap is provided in a predetermined drive circuit. The drive circuit array substrate according to the above [A2] or [A3]. [A5] the drive circuit group includes a first drive circuit, a second drive circuit, and a third drive circuit; the second drive circuit is disposed between the first drive circuit and the third drive circuit, The well tap is provided in the second drive circuit, The transistors constituting the second drive circuit are enlarged in size relative to the transistors of the first drive circuit and the third drive circuit. A drive circuit array substrate according to any one of the above [A2] to [A4]. [A6] In the drive circuit group, the third drive circuit has a circuit arrangement that is vertically and horizontally inverted from that of the first drive circuit. The drive circuit array substrate according to [A5] above. [A7] A pair of adjacent drive circuit groups arranged in the longitudinal direction of the drive circuits are arranged to form a repeating unit. A drive circuit array substrate according to [A5] or [A6] above. [A8] the first drive circuit and the third drive circuit belonging to one of the pair of drive circuit groups have circuit arrangements that are vertically inverted from the first drive circuit and the third drive circuit belonging to the other drive circuit group, respectively; The drive circuit array substrate according to the above [A7]. [A9] a second drive circuit belonging to one of the pair of drive circuit groups has a circuit arrangement that is a left-right inversion or a top-bottom and left-right inversion of a second drive circuit belonging to the other drive circuit group; The drive circuit array substrate according to the above [A8]. [A10] The drive circuit group further includes a fourth drive circuit. The drive circuit array substrate according to any one of [A5] to [A9] above. [A11] The drive circuits are arranged in a stripe pattern. The drive circuit array substrate according to any one of [A5] to [A10] above.

[0131] [B1] a drive circuit array substrate including drive circuits arranged in an array on a semiconductor substrate; light-emitting elements arranged in an array above the drive circuit and driven by the drive circuit; It is equipped with In a drive circuit group consisting of a plurality of adjacent drive circuits, the well tap is provided in some of the drive circuits included in the drive circuit group. Display device. [B2] In the plurality of drive circuits included in the drive circuit group, the size of a current supply transistor among transistors constituting a predetermined drive circuit is increased. The display device according to [B1] above. [B3] In the plurality of drive circuits included in the drive circuit group, the size of a current supply transistor among transistors constituting a predetermined drive circuit is increased. The display device according to [B2] above. [B4] Among the plurality of drive circuits included in the drive circuit group, the well tap is provided in a predetermined drive circuit. The display device according to [B2] or [B3] above. [B5] the drive circuit group includes a first drive circuit, a second drive circuit, and a third drive circuit; the second drive circuit is disposed between the first drive circuit and the third drive circuit, The well tap is provided in the second drive circuit, The transistors constituting the second driving circuit are enlarged in size relative to the transistors of the first driving circuit and the third driving circuit; The first driving circuit and the third driving circuit are connected to the light emitting elements corresponding to the red pixels and the blue pixels, respectively; The second driving circuit is connected to the light emitting element corresponding to the green pixel. The display device according to any one of [B2] to [B4] above. [B6] The driving circuit group further includes a fourth driving circuit connected to a light-emitting element corresponding to a white pixel. The display device according to [B5] above. [B7] The light-emitting elements are arranged in a stripe array, a mosaic array, a square array, or a delta array. The display device according to any one of [B1] to [B6] above. [B8] The light-emitting element is an organic electroluminescence element. The display device according to any one of [B1] to [B7] above.

[0132] [C1] a drive circuit array substrate including drive circuits arranged in an array on a semiconductor substrate; light-emitting elements arranged in an array above the drive circuit and driven by the drive circuit; It is equipped with In a drive circuit group consisting of a plurality of adjacent drive circuits, the well tap is provided in some of the drive circuits included in the drive circuit group. An electronic device equipped with a display device. [C2] In the plurality of drive circuits included in the drive circuit group, the size of a current supply transistor among transistors constituting a predetermined drive circuit is increased. The electronic device according to [C1] above. [C3] In the plurality of drive circuits included in the drive circuit group, the size of a current supply transistor among transistors constituting a predetermined drive circuit is increased. The electronic device according to [C2] above. [C4] Among the plurality of drive circuits included in the drive circuit group, the well tap is provided in a predetermined drive circuit. The electronic device described in [C2] or [C3] above. [C5] the drive circuit group includes a first drive circuit, a second drive circuit, and a third drive circuit; the second drive circuit is disposed between the first drive circuit and the third drive circuit, The well tap is provided in the second drive circuit, The transistors constituting the second driving circuit are enlarged in size relative to the transistors of the first driving circuit and the third driving circuit; The first driving circuit and the third driving circuit are connected to the light emitting elements corresponding to the red pixels and the blue pixels, respectively; The second driving circuit is connected to the light emitting element corresponding to the green pixel. The electronic device according to any one of [C2] to [C4] above. [C6] The driving circuit group further includes a fourth driving circuit connected to a light-emitting element corresponding to a white pixel. The electronic device described in [C5] above. [C7] The light-emitting elements are arranged in a stripe array, a mosaic array, a square array, or a delta array. The electronic device according to any one of [C1] to [C6] above. [C8] The light-emitting element is an organic electroluminescence element. The electronic device according to any one of [C1] to [C7] above. [Explanation of symbols]

[0133] 1 display device, 11 horizontal drive circuit, 12 vertical drive circuit, 13 initialization circuit, 14 light emission control circuit, 20,920 drive circuit array substrate, 21 substrate, 22 common well region, 23 element isolation region, 24A, 24B source / drain region, 25 gate insulating film, 26 gate electrode, 27 interlayer insulating film, 28A, 28B source / drain electrode, 31 planarization film, 32 anode electrode, 33 Partition wall, 40...organic layer, 51...cathode electrode, 52...protective film, 61...color filter, 62...transparent substrate, 411...camera body, 412...taking lens unit, 413...grip section, 414...monitor, 415...viewfinder, 511...glasses-shaped display section, 512...ear hook section, 600...glasses, 611...see-through head-mounted display, 612...main body, 613...arm, 614...lens barrel

Claims

1. a semiconductor substrate; a first drive circuit provided on the semiconductor substrate; a second driving circuit provided on the semiconductor substrate; a third driving circuit provided on the semiconductor substrate; a first light-emitting element driven by the first drive circuit; a second light-emitting element driven by the second driving circuit; a third light emitting element driven by the third driving circuit; Equipped with each of the first drive circuit, the second drive circuit, and the third drive circuit includes a write transistor, a drive transistor, a first transistor, and a second transistor; a source region or a drain region of the first transistor is electrically connected to an anode electrode of a corresponding light-emitting element among the first light-emitting element, the second light-emitting element, and the third light-emitting element; a source region or a drain region of the second transistor is electrically connected to the anode electrode of a corresponding one of the first light emitting element, the second light emitting element, and the third light emitting element; the second drive circuit is disposed between the first drive circuit and the third drive circuit; the second driving circuit is adjacent to the first driving circuit and the third driving circuit; a single well tap is provided for supplying a voltage to a well region of the semiconductor substrate for the first drive circuit, the second drive circuit, and the third drive circuit; the well tap is disposed between the gate electrode of the drive transistor of the first drive circuit and the gate electrode of the drive transistor of the third drive circuit; Display device.

2. the second drive circuit is disposed between the first drive circuit and the third drive circuit, the well tap is disposed between the gate electrode of the drive transistor of the second drive circuit and the gate electrode of the drive transistor of the third drive circuit; The display device according to claim 1 .

3. the first driving circuit, the second driving circuit, and the third driving circuit are arranged in a striped array. The display device according to claim 1 or 2.

4. the first light-emitting element, the second light-emitting element, and the third light-emitting element are arranged in a stripe array, a mosaic array, a square array, or a delta array; The display device according to any one of claims 1 to 3.

5. the first light-emitting element, the second light-emitting element, and the third light-emitting element include organic electroluminescence elements; The display device according to any one of claims 1 to 4.

6. the second transistor is a light-emitting control transistor, the display device includes a control line electrically connected to a gate electrode of the second transistor via a first contact portion; the first contact portion is disposed offset from a center line parallel to a channel length direction of the second transistor; The display device according to any one of claims 1 to 5.

7. the control line overlaps the gate electrode of the light-emission control transistor in the thickness direction of the semiconductor substrate; The display device according to claim 6.

8. the write transistor, the drive transistor, the first transistor, and the second transistor are transistors of the same conductivity type; The display device according to any one of claims 1 to 7.

9. a scanning line electrically connected to the gate electrode of the write transistor via a second contact portion; the second contact portion is disposed offset from a center line parallel to a channel length direction of the write transistor. The display device according to any one of claims 1 to 8.

10. the scanning line overlaps the gate electrode of the write transistor in a thickness direction of the semiconductor substrate; The display device according to claim 9 .

11. the first driving circuit is electrically connected to a light emitting element corresponding to a red pixel; the second driving circuit is electrically connected to a light emitting element corresponding to a green pixel; the third driving circuit is electrically connected to a light emitting element corresponding to a blue pixel; The display device according to any one of claims 1 to 10.

12. each of the first drive circuit, the second drive circuit, and the third drive circuit includes a capacitance unit; The display device according to any one of claims 1 to 11.

13. the capacitance section is electrically connected to the gate electrode of the driving transistor; The display device according to claim 12.

14. the second transistor is electrically connected to a power supply line; The display device according to any one of claims 1 to 13.

15. a source region or a drain region of the second transistor is electrically connected to a source region or a drain region of the drive transistor; The display device according to any one of claims 1 to 14.

Images