Maintain timing accuracy with reduced power during system sleep

Abstract

Embodiments of the present disclosure provide systems and methods for maintaining timing accuracy across different operating modes of a device (e.g., a wireless node). A timing circuit can switch a clock signal between two different modes (e.g., high power and low power) while maintaining timing accuracy. In the high power mode, the timing circuit can provide a high frequency clock signal, and in the low power mode, the timing circuit can provide a low frequency clock signal. Furthermore, switching between the different clock signals may be synchronized and select an edge of the low frequency clock signal.

Description

[Technical Field]

[0001] Priority claims This patent application claims the benefit of priority to U.S. Provisional Patent Application No. 17 / 385,536, entitled "TIMING PRECISION MAINTENANCE WITH REDUCED POWER DURING SYSTEM SLEEP," filed July 26, 2021, and U.S. Provisional Patent Application No. 63 / 061,370, entitled "TIMING PRECISION MAINTENANCE WITH REDUCED POWER DURING SYSTEM SLEEP," filed August 5, 2020, each of which is incorporated by reference in its entirety.

[0002] The present disclosure generally relates to timing switch circuits for maintaining timing accuracy in different power modes. [Background technology]

[0003] The world is becoming more connected every day. For example, the Internet of Things (IoT) allows various devices (e.g., home appliances, speakers, etc.) to be connected to the Internet so that, among other things, they can be controlled remotely. Wireless nodes can be embedded in the devices to connect them to a wireless network. Thus, the devices can communicate using the wireless nodes and the wireless network.

[0004] Furthermore, wireless nodes may be battery-powered, depending on the size and location of the wireless node. To conserve power and extend battery life, wireless nodes may reduce power consumption by operating in a low-power mode (e.g., sleep mode) when not in active communication. For example, a wireless node may wake up from sleep mode, enter active mode, and perform communication (e.g., transmitting and / or receiving data) using a synchronized or coordinated communication protocol, where the wireless node communicates for a designated time. That is, the wireless node may wake up at a designated time for communication and then re-enter sleep mode to conserve power. However, timing drift within a wireless node during sleep mode may affect the reliability of such communication. Clock drift may also lead to other issues, such as accurate scheduling activities, accurate acquisition of timestamps, etc. Furthermore, compensating for the drift may require operating in active mode for a longer period of time, which may reduce the benefits of operating in sleep mode.

[0005] The various accompanying drawings depict only exemplary embodiments of the present disclosure and are not to be considered as limiting its scope. [Brief explanation of the drawings]

[0006] [Figure 1] 1 illustrates a wireless communication network. [Figure 2] 1 shows a wireless node. [Figure 3] 1 shows a clock switching circuit. [Figure 4] 1 is a flow diagram for transitioning from a high power mode to a low power mode. [Figure 5] 1 is a flow diagram for transitioning from a low power mode to a high power mode. [Figure 6] 1 illustrates a clock circuit having multiple low power modes. [Figure 7] A clock circuit is shown. [Figure 8A]1 illustrates a timing diagram for transitioning from a high power mode to a low power mode. [Figure 8B] 1 shows a timing diagram for transitioning from a low power mode to a high power mode. DETAILED DESCRIPTION OF THE INVENTION

[0007] Embodiments of the present disclosure provide systems and methods for maintaining timing accuracy across different operating modes of a device. For example, a timing circuit may be provided within a device that can switch clock signals between different modes (e.g., between a relatively higher power consumption mode and a relatively lower power consumption mode compared to the higher power consumption mode) while maintaining timing accuracy across such modes. In some embodiments, the ratio of digital logic power consumption in the higher power consumption mode is more than twice the power consumption in the low power mode. In the high power mode, the timing circuit may provide a high frequency clock signal, and in the low power mode, it may provide a low frequency clock signal. The low frequency clock signal may be synthesized from the high frequency clock signal, so that the high frequency clock signal and the low frequency clock signal are substantially synchronized. Furthermore, switching between different clock signals may be synchronized to select a designated clock edge. This switching scheme may maintain frequency stability and accuracy. Furthermore, the timing circuit may drive a system time-of-day counter, which switches time bases depending on the mode to maintain timing accuracy, for example, for use in a cooperative or synchronized communication protocol.

[0008] 1 illustrates an example of a portion of a wireless communication network 100. The wireless communication network 100 may include multiple wireless nodes 102, 104, 106 and a master node 108. The wireless nodes 102, 104, 106 may be communicatively coupled to the master node 108, which may in turn be coupled to the Internet. The wireless nodes 102, 104, 106 may communicate with the master node based on a communication protocol. The communication protocol may be for short-range wireless communication or long-range wireless communication. For short-range wireless communication, the protocol may include Bluetooth (e.g., Low Energy Bluetooth), Zigbee, IrDa, or another suitable protocol.

[0009] The wireless nodes 102, 104, 106 may be coupled to or embedded in various devices, such as sensors, fixtures, lighting systems, speakers, etc. The wireless nodes 102, 104, 106 may transmit and / or receive data to / from the master node 108. The master node 108 may send control information to the wireless nodes 102, 104, 106. The wireless nodes 102, 104, 106 may send data (e.g., measurement data or status data) to the master node 108. Communications between the wireless nodes 102, 104, 106 and the master node 108 may be coordinated based on a communication protocol (e.g., a synchronized, contention-free network). That is, the master controller 108 may send data to the wireless nodes 102, 104, 106 at designated times, and the wireless nodes 102, 104, 106 may send data to the master node 108 at other designated times. Thus, timing between the wireless nodes 102, 104, 106 and the master node 108 may be synchronized based on the communication protocol used by the network. In some embodiments, the wireless nodes 102, 104, 106 may communicate with each other or may connect directly to the Internet (e.g., the master node may be optional). The wireless network 100 may be provided as different types, such as a star network, a multi-hop mesh network, and other known network types.

[0010] 2 illustrates an example of a portion of a wireless node 200. The wireless node 200 may include a clock circuit 202, a processor 204, a wireless network interface 206, a memory 208, and a power supply 210. The wireless node 200 may operate in different power modes or operating modes. For example, the wireless node 200 may operate in a high power mode (e.g., a wake mode or an active mode) and one or more low power modes (e.g., sleep, dormant, etc.). The clock circuit 202 may generate different clock signals used in the different power modes. As described in further detail below, the clock circuit 202 may generate a high frequency clock signal used in the high power mode and one or more low frequency clock signals used in the low power mode. The processor 204 may be coupled to the memory 208 and may execute instructions stored in the memory 208 to perform operations. The processor 204 may operate in different power modes.

[0011] The wireless network interface 206 may include radio frequency (RF) circuitry to provide wireless communication. The wireless network interface 206 may communicate with other devices, such as a master device, using a coordinated communication protocol, as described herein. The wireless network interface 206 may operate in different modes, as described herein. For example, the wireless network interface 206 may be powered off or placed in a sleep mode during a low power mode and powered on for full operation during a high power mode.

[0012] Power source 210 may be provided as a battery, a capacitor, an energy harvesting device, or other suitable power source. Power source 210 may also provide power to other components within wireless node 200. For example, power source 210 may be provided as a lithium cell battery. Charging power source 210 may consume more power when wireless node 200 is operating in a high power mode compared to a low power mode. Therefore, charging power source 210 may be extended by operating in a low power mode.

[0013] FIG. 3 illustrates an example portion of a clock switching circuit 300. The clock switching circuit 300 may include an oscillator 302, a clock gate 304, a clock divider 306, a multiplexer 308, a system time counter 310, and a controller 312. The oscillator 302 may generate a high-frequency clock signal. The oscillator 302 may be implemented as a crystal oscillator. For example, the oscillator 302 may generate a clock signal of ∼40 MHz. The oscillator 302 may consume low power while generating the high-frequency clock signal. As described below, the high-frequency clock signal may be generated in both a high-power mode and a low-power mode. The oscillator 302 may be part of a reference clock generator.

[0014] Clock gate 304 may receive a high-frequency clock signal and may provide the high-frequency clock signal to multiplexer 308 in response to an enable signal. For example, when the enable signal is high, clock gate 304 may provide the high-frequency clock signal to multiplexer 308. However, when the enable signal is low, clock gate 304 may block the high-frequency clock signal from multiplexer 308. As described in more detail below, clock gate 304 may provide the high-frequency clock signal to multiplexer 308 during high-power mode and disable or block it during low-power mode, except for a short period prior to transitioning from low-power mode to high-power mode. Clock gate 304 may be located in close spatial proximity to crystal oscillator 302 (as shown using dashed lines in FIG. 3) to minimize wiring parasitics that can consume power. 3)

[0015] The clock divider 306 may also receive a high-frequency clock signal and divide or scale the high-frequency clock signal by an integer number (e.g., 400) to generate a low-frequency clock signal (e.g., 100 kHz). The clock divider 306 may generate a low-frequency clock signal that is substantially synchronous with the corresponding edge of the high-frequency clock signal, except for perhaps a small delay (e.g., 2-4 nanoseconds) due to delays inherent in the clock divider 306 circuitry. The clock divider 306 may also be located in close spatial proximity to the crystal oscillator 302 to minimize wiring parasitics that can consume power. In embodiments described in more detail below (e.g., FIG. 6), the clock divider 306 may comprise multiple dividers to generate multiple low-frequency clock signals used in multiple different low-power modes. A ripple divider may be provided as a low-power component, and the ripple divider may, of course, divide in a binary ratio. This binary high / low relationship may enable counter segmentation based on binary subsections.

[0016] Multiplexer 308 (sometimes referred to as a clock switching block) may receive a high-frequency clock signal (e.g., from clock gate 304) and a low-frequency clock signal (e.g., from clock divider 306). Multiplexer 308 may output either the high-frequency clock signal during high-power mode or the low-frequency clock signal during low-power mode to system time counter 310 and other components. System time counter 310 may maintain system time used by a timer scheduler, for example, for coordinated communication as described herein. During high-power mode, multiplexer 308 may provide the high-frequency clock signal, and system time counter 310 may maintain system time using the high-frequency clock. During low-power mode, multiplexer 308 may provide the low-frequency clock signal, and system time counter 310 may maintain system time using the low-frequency clock. Low-power mode may correspond to sleep mode. System time counter 310 may also count according to different bases depending on the power mode. For example, using a "16" integer divider, the system time count may be in 16 x 25 ns increments per low frequency clock during low power mode, and in 25 ns increments per high frequency clock during high power mode. The system time may be used to schedule activities such as sampling sensors or input pins, toggling output pins, triggering actuators, triggering sequences of actions, etc.

[0017] The controller 312 may control the switching of the multiplexer 308 in a synchronized manner to maintain timing accuracy. During a transition from a high-power mode to a low-power mode, the controller 312 may switch the output of the multiplexer 308 from the high-frequency clock signal to a low-frequency clock signal synchronized to the next designated edge of the low-frequency clock. The designated edge for transition synchronization may be selected as either a rising edge or a falling edge. Thus, if a rising edge is selected, the controller 312 may wait until the next designated rising edge of the low-frequency clock signal to switch the clock signal to maintain system time accuracy. The next designated rising edge may be a subsequent rising edge, or the controller 312 may skip one or more cycles for the next designated rising edge. Similarly, during a transition from a low-power mode to a high-power mode, the controller 312 may switch the output of the multiplexer 308 from the low-frequency clock signal to a high-frequency clock signal synchronized to the next designated edge of the low-frequency clock. Again, if a rising edge is selected, controller 312 may wait until the next designated rising edge of the low frequency clock signal to switch the clock signal to maintain system time accuracy. The next designated rising edge may be a subsequent rising edge, or controller 312 may skip one or more cycles for the next designated rising edge. Controller 312 may be implemented as a digital logic circuit.

[0018] FIG. 4 shows a flow diagram of an example portion of a method 400 for transitioning from a high power mode to a low power mode. The method 400 may be performed by, for example, the clock circuit 300. At 402, a command may be received to transition from the high power mode to the low power mode. The command may be sent by a central processing unit (e.g., processor 204) of the device. At 404, a next designated edge of the low frequency clock signal may be detected. The selected edge may be set to a rising edge or a falling edge of the low frequency clock signal. At 406, in response to detecting the next designated edge of the low frequency clock signal, the output of the clock switching block may be switched from the high frequency clock signal to the low frequency clock signal. At 408, the high frequency clock may be blocked (e.g., by the clock gate 304) from reaching the clock switching block (e.g., the multiplexer 308). Components of the device may then operate using the low frequency clock signal. For example, the device may enter a sleep mode. Additionally, system time may be tracked by incrementing its steps based on the low frequency clock period.

[0019] FIG. 5 shows a flow diagram of an example portion of a method 500 for transitioning from a low power mode to a high power mode. The method 500 may be performed by the clock circuit 300. At 502, a command to transition from the low power mode to the low-high mode may be received. The command may be sent by a central processing unit (e.g., processor 204) of the device. At 504, the high frequency clock signal may be enabled, e.g., the high frequency clock signal may be allowed to reach a clock switching block (e.g., multiplexer 308) (e.g., by clock gate 304). At 506, a next designated edge of the low frequency clock signal may be detected. The selected edge may be set to a rising edge or a falling edge of the low frequency clock signal. At 508, in response to detecting the next designated edge of the low frequency clock signal, the output of the clock switching block may be switched from the low frequency clock signal to the high frequency clock signal. Components of the device may then operate using the high frequency clock signal. Furthermore, system time may be tracked by incrementing its steps based on the high frequency clock period. In some embodiments, the least significant bit (LSB) of the counter may be held static and the most significant bit (MSB) may be incremented.

[0020] The system time may then be used to control other operations such as scheduling communications, obtaining timestamps, etc. For example, the device may enter an active mode to send and / or receive messages based on the agreed-upon communications protocol, with communications scheduled at specified times. In a low power mode, the device may use the system time to obtain accurate timestamps.

[0021] Timing accuracy is maintained by synchronizing high-to-low and low-to-high mode transitions with designated low-frequency clock edges. The device's timer scheduler can maintain the timing accuracy of the high-frequency oscillator even when the high-frequency clock signal is unavailable in low-power mode. Thus, timing errors due to clock domain crossings can be reduced or eliminated.

[0022] As discussed above, the device may operate in different low-power modes. Each low-power mode may operate using a different low-frequency clock signal. FIG. 6 shows an example of a portion of a clock circuit 600 for use in the high-power mode and the different low-power modes. The clock circuit 600 may include the crystal oscillator 302, clock gate 304, multiplexer 308, and system time counter 310, as discussed above with reference to FIG. 3. The clock circuit 600 may also include a clock divider circuit 606 and a controller 612 to provide the different low-frequency clock signals.

[0023] The clock divider circuit 606 may include a clock divider and a second multiplexer. The clock divider circuit 606 may receive a high-frequency clock signal. The clock divider in the clock divider circuit 606 may divide or scale the high-frequency clock signal by different integers to generate different low-frequency clock signals, and the second multiplexer may output a selected low-frequency clock signal. The output of the second multiplexer may be controlled by the controller 612. The low-frequency clock signals may be multiples of each other. For example, a first low-frequency clock signal may be generated by dividing the high-frequency clock signal by a first integer. A second low-frequency clock signal may be generated by dividing the first low-frequency clock signal by a second integer. A third low-frequency clock signal may be generated by dividing the second low-frequency clock signal by a third integer. The clock divider circuit 606 may generate a low frequency clock signal that is substantially synchronous with corresponding edges of the high frequency clock signal, except for perhaps a small delay (e.g., 2-4 nanoseconds) due to delays inherent in the circuitry of the clock divider circuit 606. The clock divider circuit 606 may also be located in close spatial proximity to the crystal oscillator 302 to minimize wiring parasitics that can consume power.

[0024] As described above, multiplexer 308 (sometimes referred to as a clock switching block) may receive a high-frequency clock signal (e.g., from clock gate 304) and a selected low-frequency clock signal (e.g., from clock divider circuit 606). Multiplexer 308 may output either the high-frequency clock signal during the high-power mode or the selected low-frequency clock signal during the low-power mode to system time counter 310 and other components. System time counter 310 may maintain a system time used by a timer scheduler, for example, for coordinated communications as described herein. During the high-power mode, multiplexer 308 may provide the high-frequency clock signal, and system time counter 310 may maintain system time using the high-frequency clock signal. During each of the low-power modes, multiplexer 308 may provide a selected low-frequency clock signal, and system time counter 310 may maintain system time using the selected low-frequency clock signal. Different low-power modes may correspond to different levels of low operating mode (e.g., sleep mode, standby mode, dormant mode, etc.).

[0025] The controller 612 may control the selection of the low-frequency clock signal and the switching of the multiplexer 308 in a synchronized manner to maintain timing accuracy, as described herein (e.g., FIGS. 4 and 5). For example, during a transition from a high-power mode to a low-power mode, the controller 612 may switch the output of the multiplexer from the high-frequency clock signal to a low-frequency clock signal synchronized to the next designated edge of the low-frequency clock. The edge for the transition synchronization may be selected to be either a rising edge or a falling edge. Similarly, during a transition from a low-power mode to a high-power mode, the controller 612 may switch the output of the multiplexer from the low-frequency clock signal to a high-frequency clock signal synchronized to the next designated edge of the low-frequency clock. The controller 612 may be implemented as a digital logic circuit.

[0026] As described herein, the controller may be implemented using different configurations of logic circuits, processors, etc. Figure 7 shows an example of a portion of a clock circuit 700 having digital logic circuitry of a controller. The clock circuit 700 may include a crystal oscillator 702, a clock gate 704, a clock divider 706, a multiplexer 708, a system time counter 710, and a controller 712. The crystal oscillator 702 may generate a high frequency clock signal as described herein (e.g., 302).

[0027] Clock gate 704 may receive a high-frequency clock signal and may provide a high-frequency clock signal (hf_xtal_clk) to multiplexer 708 based on an enable signal (xo_40mhz_clk_out_en_lv). Clock gate 704 may be implemented as a NAND gate. Controller 712 may generate an enable signal to control clock gate 704. As described in further detail below with reference to FIGS. 8A and 8B, clock gate 704 may provide the high-frequency clock signal to multiplexer 708 during high power mode and may disable or block it during low power mode, except for a short period prior to the transition from low power mode to high power mode. Clock gate 704 may be located in close spatial proximity to crystal oscillator 702 to minimize wiring parasitics that may consume power.

[0028] Clock divider 706 may also receive a high-frequency clock signal and may divide or scale the high-frequency clock signal by an integer number (e.g., 400) to generate a low-frequency clock signal (lf_xtal_clk). Clock divider 706 may generate a low-frequency clock signal that is substantially synchronous with particular edges of the high-frequency clock signal, except for perhaps a small delay (e.g., 2-4 nanoseconds) due to delays inherent in the circuitry of clock divider 706. Clock divider 706 may also be located in close spatial proximity to crystal oscillator 702 to minimize wiring parasitics that can consume power.

[0029] Multiplexer 708 (or clock switching block) may receive a high-frequency clock signal (e.g., from clock gate 704) and a low-frequency clock signal (e.g., from clock divider 706). Multiplexer 708 may output either the high-frequency clock signal during high-power mode or the low-frequency clock signal during low-power mode to system time counter 710 and other components. System time counter 710 may maintain system time used by a timer scheduler, for example, for coordinated communications as described herein. During high-power mode, multiplexer 708 may provide the high-frequency clock signal, and system time counter 710 may maintain system time using the high-frequency clock. During low-power mode, multiplexer 708 may provide the low-frequency clock signal, and system time counter 710 may maintain system time using the low-frequency clock. The low-power mode may correspond to a sleep mode.

[0030] The controller 712 may control the switching of the multiplexer 708 in a synchronized manner to maintain timing precision. The controller 712 may include a NOT gate 712.1, a first D flip-flop 712.2, a second D flip-flop 712.3, and a NAND gate 712.4. The NOT gate 712.1 may invert the hf_osc_pd_enb signal, which may indicate a command for whether the device is in high-power mode or low-power mode, and the output of the NOT gate 712.2 may be provided as an input to the first D flip-flop 712.2 and the NAND gate 712.4. A low-frequency clock signal (lf_xtal_clk) may also be provided as an input to the first D flip-flop 712.3. The output of the first D flip-flop (hf_osc_pd_en_lf_negedge) may control the switching of the multiplexer 708. The output of the multiplexer is represented by clk_var. In this example, switching between different modes occurs on the falling (negative) edge of the low frequency clock signal, as described herein. A first D flip-flop 712.2 and a second flip-flop 712.3, which may receive the output of the low frequency clock (lf_xtal_clk), and a NAND gate 712.4, may generate an enable signal to control the clock gate 706.

[0031] FIG. 8A is a timing diagram illustrating a transition from a high-power mode to a low-power mode of a clock circuit described herein. For example, the timing diagram may illustrate the operation of the clock circuit 300 of FIG. 3 during a transition from the high-power mode to the low-power mode. The timing diagram shows a low-frequency clock 802, which may be the output of the clock divider 306; a gated high-frequency clock output 804, which may be the output of the clock gate 304; a switch clock command 806; a sync command 808, which may represent a command to switch the clock synchronized to the falling edge of the low-frequency clock; an enable command 810 for the clock gate 304; and an output 812, which may be the output of the multiplexer 308. As described above, the transition from the high-power mode to the low-power mode occurs on the falling edge of the low-frequency clock. That is, the transition occurs on the subsequent falling edge of the low-frequency clock (802) after receiving the command to go to the low-power mode (806). Furthermore, after the transition, the clock gate 810 may disable the high-frequency clock signal (804).

[0032] 8B is a timing diagram illustrating a transition from a low power mode to a high power mode of a clock circuit described herein. For example, the timing diagram may illustrate the operation of clock circuit 300 of FIG. 3 during a transition from a low power mode to a high power mode. As shown and described above, the transition from the low power mode to the high power mode occurs on the falling edge of the low frequency clock. That is, the transition occurs on the subsequent falling edge of the low frequency clock (802) after receiving a command to go to high power (806). Additionally, prior to the transition, clock gate 810 may enable the high frequency clock signal (804).

[0033] Although several embodiments are specifically illustrated and / or described herein, it will be understood that modifications and variations of the invention, in light of the above teachings, are encompassed within the scope of the accompanying aspects without departing from the intended scope of the invention.

[0034] While embodiments of the present disclosure have been described with reference to specific exemplary embodiments, it will be apparent that various modifications and changes can be made to these embodiments without departing from the broader scope of the inventive subject matter. Accordingly, the specification and drawings are to be regarded in an illustrative and not a restrictive sense. The accompanying drawings, which form a part of this specification, show, by way of example, and not by way of limitation, specific embodiments in which the subject matter may be practiced. The illustrated embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. Accordingly, this detailed description is not to be construed in a limiting sense, and the scope of various embodiments is defined solely by the accompanying aspects, along with the full range of equivalents to which such aspects are entitled.

Claims

1. 1. A clock circuit comprising: a clock generating a first clock signal having a first frequency; a clock divider that divides the first clock signal to generate a second clock signal output at a second frequency, the first frequency being higher than the second frequency; a multiplexer receiving the first and second clock signals as inputs; a controller coupled to the multiplexer, the controller for controlling the multiplexer to output the first clock signal during a first mode and the second clock signal during a second mode, the multiplexer switching directly between the first clock signal and the second clock signal based on a select edge of the second clock signal; a system time counter coupled to the multiplexer to maintain a system time count, the system time counter configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode.

2. 2. The clock circuit of claim 1, wherein in response to a command to switch from the first mode to the second mode, the controller is configured to switch the output of the multiplexer from the first clock signal to the second clock signal at the selected edge of the second clock signal.

3. 2. The clock circuit of claim 1, wherein in response to a command to switch from the second mode to the first mode, the controller is configured to switch the output of the multiplexer from the second clock signal to the first clock signal at the selected edge of the second clock signal.

4. 2. The clock circuit of claim 1, further comprising a clock gate coupled to an output of said first clock signal to connect and disconnect said first clock signal to said multiplexer.

5. 5. The clock circuit of claim 4, wherein the clock gate and the clock divider are located in spatial proximity to the clock, the clock including a crystal oscillator.

6. 2. The clock circuit of claim 1, wherein the clock divider generates a plurality of second clock signals, each second clock signal configured to oscillate at a different frequency.

7. A method for maintaining timing between different modes, performed by a clock circuit, said method comprising: receiving a command to switch from a first power mode to a second power mode; In response to receiving the command, detecting a next designated edge of a low frequency clock signal included in a plurality of clock pulses corresponding to a low power mode; switching directly to a clock signal corresponding to the second power mode at the detected edge of the low frequency clock signal; maintaining a system time count based on a second clock signal corresponding to the first power mode; in response to switching to the clock signal corresponding to the second power mode, maintaining the system time count based on the clock signal corresponding to the second power mode.

8. 8. The method of claim 7, wherein the first power mode is a high power mode, the second power mode is a low power mode, and the clock signal corresponding to the second power mode is the low frequency clock signal.

9. 9. The method of claim 8, further comprising: in response to switching to the clock signal corresponding to the second power mode, blocking a second clock signal corresponding to the first power mode.

10. 8. The method of claim 7, wherein the first power mode is a low power mode, the second power mode is a high power mode, and the clock signal corresponding to the second power mode is a high frequency clock signal.

11. 11. The method of claim 10, further comprising enabling the high frequency clock signal before switching to the clock signal corresponding to the second power mode.

12. 11. The method of claim 10, further comprising using the high frequency clock signal to generate the low frequency clock signal.

13. 1. A device for maintaining timing between modes, said device comprising: a wireless interface for communicating with another device; 1. A clock circuit comprising: a clock generating a first clock signal having a first frequency; a clock divider that divides the first clock signal to generate a second clock signal at a second frequency, the first frequency being greater than the second frequency; a multiplexer receiving the first and second clock signals as inputs; a controller coupled to a multiplexer, the controller for controlling the multiplexer to output the first clock signal during a first mode and the second clock signal during a second mode, the multiplexer switching directly between the first clock signal and the second clock signal based on a select edge of the second clock signal; a system time counter coupled to the multiplexer to maintain a system time count, the system time counter configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode; and a clock circuit.

14. 14. The device of claim 13, wherein in response to a command to switch from the first mode to the second mode, the controller is configured to switch the output of the multiplexer from the first clock signal to the second clock signal at the selected edge of the second clock signal.

15. 14. The device of claim 13, wherein in response to a command to switch from the second mode to the first mode, the controller is configured to switch the output of the multiplexer from the second clock signal to the first clock signal at the select edge of the second clock signal.

16. 14. The device of claim 13, further comprising a clock gate coupled to the clock to connect and disconnect the first clock signal to the multiplexer.

Images