gaming machines

Abstract

To provide a game machine with a substrate configuration enhanced in efficiency, for driving various performances.SOLUTION: A game machine includes: a first substrate in which first performance driving means implemented by a chip component, a first input connector to input a clock and performance driving control data for the first performance driving means, and an output connector to output the clock and the performance driving control data are provided; and a second substrate in which second performance driving means implemented by a chip component, a second input connector to input a clock and performance driving control data for the second performance driving means are provided. The output connector and the second input connector are connected by a cross cable. Assignment of respective terminals of the second input connector is set in a reverse order of assignment of respective terminals of the first input connector. The first performance driving means and the first input connector are arranged on the same surface of the first substrate. The second performance driving means and the second input connector are arranged on different surfaces of the second substrate..SELECTED DRAWING: Figure 83

Description

[Technical Field]

[0001] The present invention relates to a gaming machine and to a technique that contributes to improving the performance of the gaming machine. [Background technology]

[0002] In pinball and rotary gaming machines, various devices such as LCD screens, speakers, LEDs, gadgets, vibrators, and blowers are used to enhance the gaming experience. The following patent documents disclose techniques for controlling various performance actions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-64693 Summary of the Invention [Problem to be solved by the invention]

[0004] In such gaming machines, it is desirable to realize more exciting presentations without increasing the number of circuit boards or making the wiring more complicated or difficult. Therefore, an object of the present invention is to propose a configuration that can obtain effective dramatic effects without making these configurations complicated. [Means for solving the problem]

[0005] The gaming machine of the present invention has a substrate on which a performance drive means is provided, and the performance drive means is configured to have a power input terminal to which a first power supply voltage is input, a plurality of address terminals to set slave addresses, and a power output terminal to output a reference voltage in the performance drive means which is a voltage value different from the first power supply voltage, and the address terminal set to H level is on a surface of the substrate different from the mounting surface of the performance drive means. No. 1 The address terminals connected to the power supply output terminals via pattern wiring and set to the L level are Betta Connected to ground The line length of the second pattern wiring from the address terminal set to the L level to the solid ground is shorter than the line length of the first pattern wiring. [Effects of the Invention]

[0006] The gaming machine of the present invention has an efficient configuration and can provide highly entertaining effects. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a front perspective view showing the appearance of a gaming machine according to an embodiment of the present invention; [Figure 2] 1 is a diagram showing the configuration of a gaming board of a gaming machine according to an embodiment; [Figure 3] 2 is a block diagram showing the control configuration of the gaming machine according to the embodiment; [Figure 4] An explanatory diagram of an example of a preview performance in an embodiment. [Figure 5] 1 is a perspective view of a gaming machine according to an embodiment with the door open. [Figure 6] 1 is an oblique view of an embodiment of the gaming machine with the inner frame open. FIG. [Figure 7] FIG. 2 is an explanatory diagram of the board arrangement on the back side of the game board according to the embodiment. [Figure 8] An explanatory diagram of the board arrangement of the door and inner frame of the gaming machine of the embodiment. [Figure 9] 10 is an explanatory diagram of the board arrangement of the inner frame of the gaming machine of the embodiment. FIG. [Figure 10] FIG. 2 is an explanatory diagram of the arrangement of various devices. [Figure 11] FIG. 2 is a block diagram of the connection configuration of the board. [Figure 12] 3 is an explanatory diagram of power supply system input / output for the power supply board 300. FIG. [Figure 13] 10 is a circuit diagram of the inner frame LED relay board 400. FIG. [Figure 14] 10 is a circuit diagram of the inner frame LED relay board 400. FIG. [Figure 15] 10 is a circuit diagram of the front frame LED connection board 500. FIG. [Figure 16] 10 is a circuit diagram of the front frame LED connection board 500. FIG. [Figure 17] 10 is a circuit diagram of the front frame LED connection board 500. FIG. [Figure 18] 10 is a circuit diagram of the front frame LED connection board 500. FIG. [Figure 19] 10 is a circuit diagram of the front frame LED connection board 500. FIG. [Figure 20] 10 is a circuit diagram of the front frame LED connection board 500. FIG. [Figure 21] 10 is a block diagram showing the flow of signals in the front frame LED connection board 500. FIG. [Figure 22] 10 is a block diagram showing the flow of signals in the front frame LED connection board 500. FIG. [Figure 23] FIG. 10 is a circuit diagram of a relay board 550. [Figure 24] FIG. 10 is a circuit diagram of the upper right LED board 600 of the side unit. [Figure 25] FIG. 10 is a circuit diagram of the upper right LED board 600 of the side unit. [Figure 26] FIG. 10 is a circuit diagram of the upper right LED board 600 of the side unit. [Figure 27] FIG. 10 is a circuit diagram of the upper right LED board 600 of the side unit. [Figure 28] FIG. 10 is a circuit diagram of the upper right LED board 600 of the side unit. [Figure 29] FIG. 10 is a circuit diagram of the upper right LED board 600 of the side unit. [Figure 30] FIG. 10 is a circuit diagram of the lower right LED board 620 of the side unit. [Figure 31] FIG. 10 is a circuit diagram of the lower right LED board 620 of the side unit. [Figure 32] FIG. 10 is a circuit diagram of the LED board 630 on the side unit. [Figure 33] FIG. 10 is a circuit diagram of a button LED connection board 640. [Figure 34] FIG. 10 is a circuit diagram of a button LED board 660. [Figure 35] FIG. 10 is a circuit diagram of a button LED board 660. [Figure 36] FIG. 2 is a circuit diagram of an LED connection board 700. [Figure 37]FIG. 2 is a circuit diagram of an LED connection board 700. [Figure 38] FIG. 2 is a circuit diagram of an LED connection board 700. [Figure 39] FIG. 2 is a circuit diagram of an LED connection board 700. [Figure 40] FIG. 2 is a circuit diagram of an LED connection board 700. [Figure 41] FIG. 2 is a circuit diagram of an LED connection board 700. [Figure 42] 10 is a circuit diagram of the rear left relay board 720 of the board. [Figure 43] FIG. 7 is a circuit diagram of a decorative substrate 740. [Figure 44] FIG. 10 is a circuit diagram of a relay board 760. [Figure 45] FIG. 7 is a circuit diagram of an LED substrate 780. [Figure 46] FIG. 10 is a circuit diagram of an LED substrate 790. [Figure 47] FIG. 10 is a circuit diagram of the under-board relay board 800. [Figure 48] FIG. 10 is a circuit diagram of the decorative substrate 820. [Figure 49] FIG. 10 is a block diagram of another connection configuration of the board. [Figure 50] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 51] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 52] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 53] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 54] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 55] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 56] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 57] FIG. 15 is a circuit diagram of an LED connection board 1500. [Figure 58] FIG. 16 is a circuit diagram of an LED substrate 1600. [Figure 59] FIG. 1 is an explanatory diagram of configuration A1-1. [Figure 60] 10 is an explanatory diagram of the pattern of the surface layer of the LED substrate 780. FIG. [Figure 61] 10 is an explanatory diagram of the pattern of the back surface layer of the LED substrate 780. FIG. [Figure 62] FIG. 2 is an explanatory diagram of the terminals of the LED driver. [Figure 63] 10 is an explanatory diagram of the pattern of the surface layer of the LED substrate 790. FIG. [Figure 64] 10 is an explanatory diagram of the pattern of the back surface layer of the LED substrate 790. FIG. [Figure 65] FIG. 10 is an explanatory diagram of configuration A1-2. [Figure 66] 10 is an explanatory diagram of the pattern of the surface layer of the LED substrate 630 on the side unit. FIG. [Figure 67] 10 is an explanatory diagram of the pattern of the back surface layer of the LED substrate 630 on the side unit. FIG. [Figure 68] FIG. 10 is an explanatory diagram of configuration A2-1. [Figure 69] FIG. 10 is an explanatory diagram of configuration A2-2. [Figure 70] FIG. 10 is an explanatory diagram of configuration A3-1. [Figure 71] 15 is an explanatory diagram of an example of the arrangement of the surface layer of an LED connection board 1500. FIG. [Figure 72] 15 is an explanatory diagram of an example of the arrangement of the back surface layer of the LED connection board 1500. FIG. [Figure 73] 10 is an explanatory diagram of an example of the arrangement of the surface layer of the upper right LED substrate 600 of the side unit. FIG. [Figure 74] 10 is an explanatory diagram of an example of the arrangement of the back surface layer of the upper right LED substrate 600 of the side unit. FIG. [Figure 75] 15 is an explanatory diagram of another example of the arrangement of the surface layer of the LED connection board 1500. FIG. [Figure 76] FIG. 10 is an explanatory diagram of configuration A3-2. [Figure 77] FIG. 10 is an explanatory diagram of configuration A4-1. [Figure 78] 16 is an explanatory diagram of the pattern of the surface layer of the LED substrate 1600. FIG. [Figure 79] 16 is an explanatory diagram of the pattern of the back surface layer of the LED substrate 1600. FIG. [Figure 80]FIG. 16 is an explanatory diagram of the terminals of the LED driver 1601. [Figure 81] FIG. 10 is an explanatory diagram of configuration A5. [Figure 82] FIG. 15 is a circuit diagram of an LED connection board 1500A. [Figure 83] FIG. 10 is an explanatory diagram of configuration A6. [Figure 84] FIG. 10 is a circuit diagram of an LED substrate 790A. [Figure 85] FIG. 10 is an explanatory diagram of configuration A7-1. [Figure 86] FIG. 10 is an explanatory diagram of configuration A7-2. [Figure 87] FIG. 10 is an explanatory diagram of configuration A7-3. [Figure 88] FIG. 8 is an explanatory diagram of configurations A8-1 and A8-2. [Figure 89] FIG. 8 is an explanatory diagram of configurations A8-1 and A8-2. [Figure 90] FIG. 10 is an explanatory diagram of configuration A9-1. [Figure 91] FIG. 10 is an explanatory diagram of configuration A9-2. [Figure 92] FIG. 10 is an explanatory diagram of configuration A9-3. [Figure 93] FIG. 10 is an explanatory diagram of slave address setting. [Figure 94] FIG. 10 is an explanatory diagram of wiring for setting a slave address. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings. <1. Structure of the gaming machine> <2. Control configuration of gaming machine> [2.1 Main control board] [2.2 Performance control board] <3. Overview of operation> [3.1 Game Status] [3.2 Game with changing symbols] [3.3 About winning] [3.4 Production] <4. Opening and closing structure and board layout> <5. Board connection configuration> [5.1 Connection status of each board] [5.2 Inner frame LED relay board 400] [5.3 Front Frame LED Connection Board 500] [5.4 Relay board 550] [5.5 Side unit upper right LED board 600] [5.6 Side unit bottom right LED board 620] [5.7 Side unit LED board 630] [5.8 Button LED connection board 640] [5.9 Button LED Board 660] [5.10 LED connection board 700] [5.11 Back left relay board 720] [5.12 Decorative Substrate 740] [5.13 Relay board 760] [5.14 LED board 780] [5.15 LED board 790] [5.16 Under-panel relay board 800] [5.17 Decorative board 820] <6. Other examples of board connection configurations> [6.1 Connection status of each board] [6.2 LED connection board 1500] [6.3 LED board 1600] <7. Description of noteworthy components> [7.1 Relationship between connector terminals and terminals of performance driving means] [7.2 Slave Address] [7.3 Other]

[0009] <1. Structure of the gaming machine> The structure of a pachinko gaming machine 1 as an embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a perspective view of the front side showing the appearance of the pachinko gaming machine 1, and Figure 2 is a view showing the front side of a game board 3 that the pachinko gaming machine 1 has. The pachinko gaming machine 1 has a frame member, a door member that is provided so as to be able to open and close relative to the frame member, and an exchange member that is attached so as to be able to be exchanged relative to the frame member. The pachinko gaming machine 1 described below has an inner frame 2 as a component equivalent to a frame member, a door 6 as a component equivalent to a door member, and a gaming board 3 as a component equivalent to a replacement member.

[0010] The pachinko gaming machine 1 shown in Figure 1 (hereinafter sometimes abbreviated as "gaming machine 1") has a picture-frame-shaped inner frame 2 attached to the front of a wooden outer frame 4 so that it can be opened and closed, a gaming board 3 (see Figure 2) mounted in a gaming board storage frame (not shown) attached to the back of the inner frame 2, and a gaming area 3a formed on the surface of this gaming board 3 faces the opening of the inner frame 2. The gaming board 3 can be called an exchangeable part because it can be attached and detached to the inner frame 2 exchangeably. A door 6 supporting transparent glass is provided at the front of the game area 3a. Also, various control boards (see FIG. 3) for controlling game operations are provided at the rear side of the game board 3.

[0011] On the front side (player side) of the door 6, a side unit 10 is formed as a decorative unit that surrounds the entire periphery of the game board 3 or a part of it, for example. The side unit 10 itself is given a decorative shape that matches the theme of the gaming machine 1, and may be equipped with LEDs, accessories, and other presentation elements inside, thereby achieving a presentation effect that conveys the atmosphere of the game to the player. This side unit 10 is a unit that is attached to the door 6 in an interchangeable manner.

[0012] A key cylinder (not shown) for unlocking the door is provided on the front side of the door 6; by inserting a key into this key cylinder and operating it to one side, the locked state of the door 6 relative to the inner frame 2 can be released, allowing the door 6 to be opened to the front; and by operating it to the other side, the locked state of the inner frame 2 relative to the outer frame 4 can be released, allowing the inner frame 2 to be opened to the front.

[0013] A front operation panel 7 is disposed below the door 6 and is pivotally supported on the inner frame 2 by a hinge (not shown) so as to be able to be opened and closed freely. An upper tray unit 8 is provided on the front operation panel 7, and this upper tray unit 8 is formed with an upper tray 9 for storing the discharged gaming balls.

[0014] The upper tray unit 8 is also provided with a ball removal button 14 for removing game balls stored in the upper tray 9 downward from the gaming machine 1, a ball lending button 11 for requesting the game ball lending device (not shown) to dispense game balls, and a card return button 12 for requesting the return of any valuable medium inserted into the game ball lending device. Additionally, an effect button 13 (operation means) that can be operated by a player is provided on the upper tray unit 8. This effect button 13 becomes operable (input acceptable) when a built-in lamp (button LED 75) lights up during a predetermined input acceptance period, and it is possible to bring about a change in the effect by performing a predetermined operation (pressing, repeatedly pressing, long pressing, etc.) while the built-in lamp is lit. The upper tray unit 8 is also provided with controls such as a cross key 15a that allows users such as players and hall staff to select various items and give direction instructions, and a decision button 15b that allows users to decide on a selected item.

[0015] Further, on the right end side of the front operation panel 7, a firing operation handle 15 for operating the firing device 32 (see FIG. 3) is provided.

[0016] Also Door 6 On both sides of the upper part of the gun and on the upper side of the firing operation handle 15, speakers 46 are provided to produce sound effects (sound effects). Door 6 Only the top two speakers 46 are shown. The plurality of speakers 46 allows so-called stereophonic sound reproduction or multi-channel sound reproduction for sounds related to the performance.

[0017] Furthermore, a plurality of decorative lamps 45 (for example, full-color LEDs for light effects: see FIG. 3) that create a light effect through light decoration are provided in appropriate positions on the door 6. A plurality of full-color LEDs (light effects LEDs) as the decorative lamps 45 are provided around the pachinko gaming machine 1, for example, on the periphery of the door 6 or inside the side unit 10.

[0018] The configuration of the game board 3 will be described with reference to FIG. The illustrated game board 3 has a ball guide rail 5 attached in a ring shape as a board surface partition member to guide the launched game balls, and the approximately circular area surrounded by this ball guide rail 5 is the game area 3a, while the four corners are non-game areas.

[0019] Approximately in the center of this game area 3a, there is provided a liquid crystal display device (LCD) 36 which is capable of independently displaying (variable display and stationary display) multiple types of decorative patterns (for example, left pattern (corresponding to the left display area), middle pattern (corresponding to the middle display area), right pattern (corresponding to the right display area)) using numbers, characters, symbols, etc. in, for example, three (left, middle, right) display areas (pattern variable display areas). This liquid crystal display device 36 displays various effects as images, in addition to the changing display operation of decorative symbols, under the control of the effect control board 30 described later.

[0020] Also, within the gaming area 3a, a center ornament 48 is provided in a manner that surrounds the display surface of the liquid crystal display device 36 at a distance. The center ornament 48 is provided along the front side of the gaming board 3, and protects the display surface of the liquid crystal display device 36 from surrounding gaming balls, and also functions as a flow path sorting means that enables the flow path of the gaming balls to be sorted to the left or right depending on the strength or stroke length of the gaming ball's launch. In this embodiment, the center ornament 48 is disposed in the approximate center of the play area 3a so that flow paths for game balls are formed on both upper sides (left and right sides) of the play area 3a due to the presence of the center ornament 48. Game balls shot into the upper side of the play area 3a by the launching device 32 are sorted to the left and right at the upper side of the armor frame portion 48b, and flow down either the left flow path 3b on the left side of the center ornament 48 or the right flow path 3c on the right side.

[0021] In addition, the non-play area at the bottom of the game board 3 is a display area for various functions, and is provided with a special pattern display device 38a (first special pattern display means) and a special pattern display device 38b (second special pattern display means) using dot displays. The various function display sections including the special symbol display devices 38a and 38b are shown enlarged in FIG.

[0022] The special symbol display devices 38a, 38b are configured to execute a special symbol variable display game by varying the display operation of "special symbols" represented by dot displays. The liquid crystal display device 36 is configured to variably display decorative symbols by images in synchronization with the variable display of special symbols by the special symbol display devices 38a, 38b, and to execute a decorative symbol variable display game together with various preview effects (effect images) (these symbol variable display games will be explained in detail later).

[0023] The various function display section also includes a composite display device (LED display for reserved composite display) 38c, which is made up of dot displays similar to the special symbol display devices 38a and 38b. It is called a composite because it is a reserved, time-saving, and high-probability composite display device (hereinafter simply referred to as the "composite display device") that has five display functions: displaying special symbols 1 and 2, the number of reserved balls for normal symbols, and notifying the status when the variable time-saving function is in operation (during time-saving) and when in a high-probability state (during high probability).

[0024] The various function display section is also provided with a composite display device 38d, which is also made up of dot displays. In this composite display device 38d, a round number display is performed to notify the specified number of rounds (maximum number of rounds) related to a jackpot by a combination of the on / off states of four LEDs. For example, the specified number of rounds (maximum number of rounds) related to a jackpot is notified by a combination of the on / off states of four LEDs. In addition, in the composite display device 38d, a normal symbol variable display game is executed by a variable display operation of a normal symbol represented by one LED as a normal symbol display. Furthermore, the composite display device 38d is configured to display right-hit information using three LEDs.

[0025] A start hole 34 (first special symbol start hole: first start means) is provided inside the center ornament 48 in Fig. 2. A detection sensor 34a (start hole sensor 34a, see Fig. 3) that detects the passage of the game ball is formed inside the start hole 34. In addition, a start port 35 (second special pattern start port: second start means) that opens and closes is provided in the right flow path 3c, and a detection sensor 35a (start port sensor 35a: see Figure 3) that detects the passage of the game ball is formed inside.

[0026] The first special symbol starting hole 34 is a winning hole related to the starting condition of the variable display operation of the first special symbol (hereinafter, the first special symbol will be referred to as "special symbol 1" and sometimes abbreviated as "special symbol 1") in the special symbol display device 38a, and is configured as a fixed winning rate winning device that does not have a starting hole opening / closing means (means for opening or enlarging the starting hole). In this embodiment, due to the action of a game ball fall direction changing member (for example, a game nail, a windmill 44, a center ornament 48, etc.) in the game area 3a, the starting hole 34 is configured so that game balls that have flowed down the left flow path 3b can easily enter (win), but it is configured so that game balls that have flowed down the right flow path 3c can hardly or cannot enter.

[0027] The starting port 35 is a winning port related to the starting conditions for the variable display operation of the second special pattern (hereinafter, the second special pattern will be referred to as "special pattern 2" and sometimes abbreviated as "special pattern 2") in the special pattern display device 38b, and the winning area of ​​this starting port 35 is configured to be able to open and close between an open state in which a winning is possible and a closed state in which a winning is not possible.

[0028] The start opening 35 is a winning opening related to the start conditions for the variable display operation of the special symbol 2 in the special symbol display device 38b, and is configured as a variable start opening whose opening and closing is controlled by the normal electric device 41. The normal electric accessory 41 is controlled to an open state that allows a game ball to enter the starting hole 35 and a closed state that makes it difficult or impossible for the game ball to enter the starting hole 35.

[0029] Two general winning openings 43 are provided on the left and right lower sides of the game area 3a, and a general winning opening sensor 43a for detecting the passage of a gaming ball is formed inside each of them. Additionally, within the area of ​​the game board, movable accessories (not shown) that create visual effects are arranged in positions that do not interfere with the flow of the game balls.

[0030] Additionally, diagonally above the normal electric device 41, i.e., above the middle of the right flow path 3c, there is provided a normal symbol start port 37 (third start means) consisting of a passage gate (specific passage area) through which game balls can pass. This normal symbol start port 37 is a winning port related to the variable display operation of the normal symbol on the composite display device 38d, and inside it is formed a normal symbol start port sensor 37a (see FIG. 3) that detects game balls passing through. Note that in this embodiment, the normal symbol start port 37 is formed only on the right flow path 3c side, and not on the left flow path 3b side. However, the present invention is not limited to this, and it may be formed only on the left flow path 3b, or on both flow paths.

[0031] A special variable prize winning device 52 (special electric device) is provided midway along the path from the normal pattern starting port 37 in the right flow path 3c, which is configured to be able to open or expand the large prize winning port 50 using an opening door 52b, and inside it is formed a large prize winning port sensor 52a (see Figure 3) which detects game balls that have entered the large prize winning port 50. Around the big prize opening 50, there are provided a guide section 55 and a windmill 53 which function to guide the game balls flowing down in the direction of the big prize opening 50.

[0032] The process of the game ball entering the big prize opening 50 is as follows. The gaming ball passes through the free movement area between the upper surface of the center ornament 48 and the ball guide rail 5 and then passes through the right flow path 3c, and is guided in the direction of the big prize opening 50 by the guide section 55. If the big prize opening 50 is in an open state (big prize opening open state), the gaming ball is guided into the big prize opening 50.

[0033] In the gaming machine 1 of this embodiment, when the player aims the launch position toward the special variable winning device 52 (when the player aims so that the gaming ball passes through the right flow path 3c), the gaming ball is difficult to guide or cannot be guided toward the starting hole 34. Therefore, if the "big winning hole closed state", it is difficult or impossible for the gaming ball to enter the starting hole 34. In addition, when the game state is entered with the electric support state described below, the starting port 35 operates in an opening and closing pattern that is more advantageous than in the normal state.

[0034] In this embodiment, the type of hitting technique that is advantageous for the player varies depending on the game state. Specifically, in a game state that includes a "no electric support state" described below, a "left hit" that aims the game ball to pass through the left flow path 3b is considered advantageous, and in a game state that includes a "electric support state" described below, a "right hit" that aims the game ball to pass through the right flow path 3c is considered advantageous.

[0035] In the gaming machine 1 of this embodiment, when a winning ball is won in a winning hole other than the normal symbol start hole 37 among the various winning holes provided in the gaming area 3a, the number of prize balls per winning ball promised for each winning hole (for example, 3 balls for start hole 34 or start hole 35, 13 balls for the large prize hole 50, and 10 balls for the general prize hole 43) is paid out from the gaming ball payout device 19 (see FIG. 3). Gaming balls that do not win in the above winning holes are discharged from the gaming area 3a through the outlet hole 49.

[0036] Here, "winning" refers to a game ball being drawn into a winning opening, or, if the winning opening is a gate-type winning opening (e.g., normal symbol start opening 37) rather than a winning opening that draws in game balls, a game ball passing through the gate. In practice, when a game ball is detected by the winning detection switch formed for each winning opening, that winning opening is considered to have "won." The winning ball is also referred to as a "winning ball." Note that, since a game ball entering a winning opening will be detected by the winning detection switch, unless otherwise specified, the term "winning" may be used in this specification to refer to a game ball entering a winning opening, regardless of whether the game ball is detected by the winning detection switch.

[0037] <2. Control configuration of gaming machine> The configuration (control configuration) for realizing the gaming operation control of the gaming machine 1 will be described with reference to the block diagram of FIG. The gaming machine 1 of this embodiment is configured to include a main control board (main control means) 20 that comprehensively controls all game operations (game operation control), a presentation control board 30 (presentation control means) that receives presentation control commands from the main control board 20 and comprehensively controls the execution control (appearance control) of presentations by the presentation means, a payout control board (payout control means) 29 that controls the payout of prize balls, and a power supply board (power supply control means (not shown)) that generates and supplies the power required for the gaming machine 1 from an external power source (not shown). In FIG. 3, the power supply routes to each part are omitted.

[0038] [2.1 Main control board] The main control board 20 is equipped with a microprocessor that incorporates a CPU (Central Processing Unit) 20a (main control CPU), as well as a ROM (Read Only Memory) 20b (main control ROM) that stores a control program that describes the game operation control procedures, as well as various data necessary for game operation control, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, and as a whole constitutes a microcomputer.

[0039] Although not shown, the main control board 20 also includes a CTC (Counter Timer Circuit) for implementing periodic interrupts, a function for generating pulse outputs at fixed intervals (bit rate generator), and a time measurement function, an interrupt controller circuit that performs interrupt enable / disable functions such as timer interrupts that issue interrupt signals to the main control CPU 20a, a reset circuit that can detect power-on / power-off and power supply abnormalities and output a system reset signal to reset the main control CPU 20a, a watchdog timer (WDT) circuit that monitors for abnormal operation of the control program, an IAT (Inhibit Outside Designated Area) circuit that monitors whether the program is being executed correctly within a preset address range, and a counter circuit for generating random numbers within a certain range in hardware.

[0040] The counter circuit is comprised of a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timing, and functions as a 16-bit counter as a whole. The main control CPU 20a sends instructions to the sampling circuit according to the processing status to obtain the number indicated by the random number generation circuit as a random number value for internal lottery (random number for determining jackpot (size of random number: 65536)), and uses this random number value for the jackpot lottery. Note that the random number for internal lottery is obtained by adding a software random number value generated by appropriate software processing and a hard random number value to prevent cheating such as aiming for a jackpot.

[0041] Connected to the main control board 20 are a start gate sensor 34a that detects winning (ball entry) into start gate 34, a start gate sensor 35a that detects winning into start gate 35, a normal pattern start gate sensor 37a that detects passage through normal pattern start gate 37, a special prize gate sensor 52a that detects winning into special prize gate 50, a general prize gate sensor 43a that detects winning into general prize gate 43, and an OUT monitoring switch 49a that detects game balls (out balls) discharged from outlet 49, and the main control board 20 is capable of receiving detection signals output from these. Based on the detection signals from each sensor, the main control board 20 is able to determine which prize gate the game ball has entered.

[0042] In addition, the main control board 20 is connected to a normal electric role solenoid 41c for controlling the opening and closing of the movable wing piece of the starting opening 35, and a large prize opening solenoid 52c for controlling the opening and closing of the opening door 52b of the large prize opening 50, and the main control board 20 is capable of transmitting control signals for controlling these.

[0043] Furthermore, the main control board 20 is connected to a special symbol display device 38a and a special symbol display device 38b, and the main control board 20 is capable of transmitting control signals for controlling the display of special symbols 1 and 2. Furthermore, the main control board 20 is connected to a composite display device 38c, and is capable of transmitting control signals for controlling the display of the number of reserved symbols and the status display.

[0044] In addition, a composite display device 38d is connected to the main control board 20, and the main control board 20 is capable of transmitting control signals for controlling the display of the normal pattern display, right-hit display, and round display displayed on the composite display device 38d.

[0045] Furthermore, an external centralized terminal board 21 for the frame is connected to the main control board 20, and the main control board 20 is capable of transmitting predetermined game information (e.g., jackpot information, number of winning balls information, pattern change execution information, etc.) to a hall computer HC installed outside the gaming machine via the external centralized terminal board 21 for the frame. The hall computer HC is an information processing device (computer device) that monitors game information from the main control board 20 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0046] Furthermore, a payout control board (payout control unit) 29 is connected to the main control board 20, and when it is necessary to pay out prize balls, a control command regarding the payout (a payout control command specifying the number of prize balls) can be sent to the payout control board 29.

[0047] A launch control board (launch control unit) 28 that controls the launch device 32, and a game ball payout device (game ball payout means) 19 that pays out game balls are connected to the payout control board 29. The main role of this payout control board 29 is to receive payout control commands from the main control board 20, control the payout of prize balls by the game ball payout device 19 based on the payout control commands, and send status signals to the main control board 20.

[0048] The game ball payout device 19 is provided with a supply shortage detection sensor 19a that detects a shortage of game balls and a ball counting sensor 19b that detects the game balls (prize balls) to be paid out, and the payout control board 29 is capable of receiving these detection signals. The game ball payout device 19 is also provided with a payout motor 19c that drives a ball payout mechanism (not shown) for paying out game balls, and the payout control board 29 is capable of transmitting a control signal for controlling the payout motor 19c.

[0049] Furthermore, the payout control board 29 is connected to a fullness detection sensor 60 (in this embodiment, a detection sensor that detects the storage state of game balls stored in the upper tray 9) that detects whether the upper tray 9 is full of game balls, and a front door open sensor 61 (for example, a detection sensor that detects the open state of the door 6 or inner frame 2).

[0050] The payout control board 29 can transmit various status signals to the main control board 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the out-of-supply detection sensor 19a, and the ball count sensor 19b. These status signals include a ball jam signal indicating a full state, a door open signal indicating that at least the inner frame 2 is open, an out-of-supply signal indicating a shortage of game balls from the game ball payout device 19, a count error signal indicating a shortage of prize balls or an abnormality in the ball count sensor 19b, and a payout completion signal indicating the completion of the payout operation. Based on these status signals, the main control board 20 monitors the open state of the inner frame 2 (door open error), whether the payout operation of the game ball payout device 19 is normal (out-of-supply error), and whether the upper tray 9 is full (ball jam error).

[0051] Furthermore, the payout control board 29 is connected to a launch control board 28, which is capable of transmitting an authorization signal to the launch control board 28 to authorize launching. Based on the authorization signal output from the payout control board 29, the launch control board 28 controls the energization of a launch solenoid (not shown) provided in the launcher 32, thereby realizing the launch of a gaming ball by operating the launch operation handle 15. Specifically, the launch of a gaming ball is permitted under the following conditions: a launch authorization signal is output from the payout control board 29 (launch authorization signal ON state), a touch sensor provided on the launch operation handle 15 detects that the player is touching the handle, and a launch stop switch (not shown) provided on the launch operation handle 15 has not been operated. Therefore, when the launch authorization signal is not output (launch authorization signal OFF state), the launch operation is not executed even if the launch operation handle 15 is operated, and the gaming ball is not launched. Furthermore, the strength of the launch of the gaming ball can be changed depending on the amount of operation of the launch operation handle 15. Furthermore, when the payout control board 29 detects the above-mentioned ball jam error, it sends a ball jam signal to the main control board 20 and stops outputting the launch permission signal to the launch control board 28 (launch permission signal OFF), and controls the firing operation to stop until the upper tray 9 is no longer full. In addition, the payout control board 29 outputs a launch permission signal to the launch control board 28 on the condition that the main control board 20 has instructed the launch permission.

[0052] A RAM clear switch 98 is connected to the main control board 20, and detection signals from these switches can be received.

[0053] The RAM clear switch 98 is, for example, a push button switch for inputting an instruction to initialize a predetermined area of ​​the main control RAM 20c.

[0054] The RAM clear switch 98 is turned on / off in response to the operation of a RAM clear button that is provided so as to be operable when the inner frame 2 is open. The RAM clear switch 98 is provided at an appropriate location inside the gaming machine 1. For example, it is disposed on the main control board 20.

[0055] Furthermore, a performance indicator 97 is connected to the main control board 20. The performance indicator 97 is configured to have, for example, a 7-segment display, and functions as a display means capable of displaying performance information (described later). The performance indicator 97 is mounted, for example, at an easily visible position on the main control board 20.

[0056] (Performance display) The main control board 20 is capable of transmitting a control signal to the performance display 97 to cause the performance display 97 to display predetermined performance information. Performance information is information that pachinko halls and relevant authorities want to confirm, and typical examples include information regarding the presence or absence of illegal prize ball cheating, such as excessive prize balls in the gaming machine 1, and the original ball output performance of the gaming machine 1. Therefore, unlike preview effects, the performance information itself is information that is not directly related to the progress of the game itself when a player is enjoying the game.

[0057] For this reason, the performance display 97 is provided inside the gaming machine 1, for example, on the main control board 20, payout control board 29, launch control board 28, the relay board, the performance control board 30, or in the board case (protective cover that protects the board), in a position where the display information can be seen when the inner frame 2 is in the open state.

[0058] Here, the performance information may specifically include the following information:

[0059] (1) Information (specific ratio information) based on the value (α / β) obtained by dividing the total number of payout balls paid out as a result of winning during a specific state (total number of prize balls during a specific state: α) by the total number of balls discharged from the game area 3a during the specific state (number of balls discharged during a specific state: β) can be adopted as performance information. The "total number of payouts" is the total number of game balls (prize balls) paid out when a ball enters a prize slot (starting slot 34, starting slot 35, general prize slot 43, large prize slot 50). In this embodiment, the number of payouts is 3 for starting slot 34 or starting slot 35, 13 for large prize slot 50, and 10 for general prize slot 43. Furthermore, which state is adopted as the specific state can be determined as appropriate depending on the state under which performance information is desired to be grasped. In the case of this embodiment, any of the normal state, the potential probability state, the time-saving state, the probability variable state, and the state during a jackpot game can be adopted. Furthermore, multiple types of states may be used as the measurement target. For example, the normal state and the probability variable state, or all game states except during a jackpot game, etc., and the type to be measured can be determined as appropriate. Furthermore, the period during the specific state may be a period during which the probability of winning a jackpot is either low or high. In addition, the total number of payouts may be calculated by excluding one or more specific winning ports from the measurement target (total number of payouts excluding specific winning ports). For example, the total number of payouts may be calculated by excluding the large winning port 50 from the measurement target among the winning ports.

[0060] (2) Alternatively, the total number of payouts, the total number of payouts excluding specific winning slots, or the total number of balls that have been released may be measured, and the measurement results may be used as performance information.

[0061] In this embodiment, the total number of dispensed balls in the normal state (number of dispensed balls in normal state) and the total number of balls out in the normal state (number of out balls in normal state) are measured in real time, and the value obtained by dividing the number of dispensed balls in normal state by the number of out balls in normal state and multiplying this value by 100 (value calculated as number of dispensed balls in normal state ÷ number of out balls in normal state × 100) is displayed as performance information (hereinafter referred to as "normal state ratio information"). Note that the displayed value at this time is rounded to one decimal place. Therefore, the data on the number of payouts during normal play, the number of outs during normal play, and the normal play ratio information are stored (memorized) in the corresponding areas of the main control RAM 20c (the storage area for the total number of prize balls during specific play, the storage area for the number of outs during specific play, and the specific ratio information storage area). However, rather than simply measuring continuously and displaying performance information, measurement is temporarily terminated when the total number of out balls reaches a predetermined number (e.g., 60,000). This specified number is not the total number of out balls during normal play, but the total number of out balls during all play states (including during winning play) (hereinafter referred to as the "number of outs in all states"). This number of outs in all states is also measured in real time and stored in the corresponding areas of the main control RAM 20c (the storage area for the number of outs in all states). For ease of explanation, the storage area for the total number of prize balls during specific play, the storage area for the number of outs during specific play, the specific ratio information storage area, and the storage area for the number of outs in all states will be abbreviated as the "measurement information storage area."

[0062] Then, the normal time ratio information at the end point is stored in a predetermined area (performance display storage area) of the main control RAM 20c (the current normal time ratio information is stored), and then the measurement information storage area (the number of balls dispensed during normal time, the number of balls out during normal time, and the number of balls out under all conditions) is cleared, and measurement begins again (measurement of the number of balls dispensed during normal time, the number of balls out during normal time, the normal time ratio information, and the number of balls out under all conditions begins).The performance display 97 then displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. Note that the configuration is not limited to the previous information, and history from the time before that or the time before that (three times before) may also be displayed, and the number of previous times of information to be displayed can be determined as appropriate.

[0063] (Performance control command) Depending on the processing status, the main control board 20 can transmit various performance control commands, including information about the special symbol variation display game and information about errors, to the performance control board 30. However, in order to prevent fraudulent activities such as cheating, the main control board 20 is configured for one-way communication, where it can only transmit signals to the performance control board 30 and cannot receive signals from the performance control board 30.

[0064] Here, the performance control command defines its function using a two-byte structure consisting of a one-byte mode (MODE) and a one-byte event (EVENT). To distinguish between MODE and EVENT, Bit 7 of MODE is ON and Bit 7 of EVENT is OFF. When this information is transmitted as valid, a strobe signal is output corresponding to each mode (MODE) and event (EVENT). That is, when there is a command to transmit, the main control CPU 20a sets and outputs mode (MODE) information for transmitting the command to the performance control board 30, and transmits the first strobe signal a predetermined time after this setting. Furthermore, after a predetermined time has passed since transmitting this strobe signal, it sets and outputs event (EVENT) information, and transmits a second strobe signal a predetermined time after this setting. The strobe signal is controlled to an active state by the main control CPU 20a for a predetermined period of time to ensure that the performance control CPU 30a can receive commands reliably.

[0065] [2.2 Performance control board] The performance control board 30 is equipped with a microprocessor that incorporates a performance control CPU 30a, and is composed mainly of a microcomputer that is equipped with a performance control ROM 30b that stores the performance data required for performance control processing, and a performance control RAM 30c that functions as a work area and buffer memory.In addition, it is equipped with an audio control unit (sound source IC), an RTC (Real Time Clock) function unit, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc., which control the overall performance operation.

[0066] The performance control CPU 30a performs calculations for various performance operations and controls each performance means based on the performance control program and performance control commands received from the main control unit 20. In the case of the pachinko gaming machine 1 of this embodiment, the performance means are the liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), the light display device 45a, the sound generating device 46a, and movable role objects not shown.

[0067] The performance control ROM 30b stores a control program for the performance operation by the performance control CPU 30a and various data required for performance operation control. The performance control RAM 30c is used as a work area used by the performance control CPU 30a for various calculation processes, a table data area, a buffer area for various input / output data and processing data, etc. The performance control board 30 is configured to have, for example, a one-chip microcomputer and its peripheral circuits mounted on it, but various configurations are possible for the performance control board 30. For example, in addition to the microcomputer, it may also have an interface circuit with each section, a random number generation circuit that generates random numbers for lottery use in performances, a CTC for counting various times, a watchdog timer (WDT) circuit, an interrupt controller circuit that gives an interrupt signal to the performance control CPU 30a, and the like.

[0068] The main roles of this performance control board 30 are to receive performance control commands from the main control unit 20, select and decide on performances based on the performance control commands, control the display of the LCD display device 36 (supply of display data), control the sound output of the sound generating device 46a, control the light emission of the light display device 45a (LED), and control the operation of the movable body role device (drive control of the movable body role device motor 80c).

[0069] This performance control board 30 also functions as a control device for the liquid crystal display device 36, so the performance control board 30 also has the functions of a so-called VDP (Video Display Processor), image ROM, and VRAM (Video RAM), and the performance control CPU 30a also functions as a liquid crystal control unit. VDP refers to the function that controls all video output processes, such as image expansion and image drawing. Image ROM refers to memory that stores image data (performance image data) that the VDP uses for image development processing. VRAM is an image memory area that temporarily stores image data developed by the VDP.

[0070] With this configuration, the performance control board 30 generates various image data based on commands from the main control unit 20 and outputs it to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various performance images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S. 2 is the "main liquid crystal display device 36M." The sub liquid crystal display device 36S is not shown in FIG.

[0071] Furthermore, the performance control board 30 has an audio control section (for example, sound controller 230 in FIG. 4) for an audio generating device 46a including multiple speakers 46, and the audio signals output by the audio control section are amplified by an amplifier section 46d and supplied to the speakers 46. Note that while the sound controller 230 as the audio control section will be described as being built into the performance control board 30, the audio control section may also use a sound source IC separate from the performance control board 30. In addition, a lamp driver section 45d that functions as a light display control section for the light display device 45a including the decorative lamps 45 and various LEDs, and a motor driver section 80d (motor drive circuit) that functions as a drive control section for the movable body role motor 80c that operates the movable body (not shown) are connected to the performance control board 30. The performance control board 30 issues instructions to the lamp driver section 45d and the motor driver section 80d to control the light display operation by the light display device 45a and the operation of the movable body role motor 80c.

[0072] The performance control board 30 is also connected to an origin switch 81 and a position detection sensor 82 for monitoring the operation of the movable props. The origin switch 81 is composed of, for example, a photointerrupter, and detects whether the movable body role motor 80c is at the origin position. The origin position is, for example, a position where the movable body is not normally exposed on the board surface of Figure 2. The performance control board 30 is capable of determining whether the movable body role motor 80c is at the origin position based on the detection information of this origin switch 81. In addition, the performance control board 30 controls the operation mode while monitoring the current operating position of the movable role object (for example, the amount of movement from the origin position) based on the detection information from the position detection sensor 82. Furthermore, the performance control board 30 monitors malfunctions in the operation of the movable role object based on the detection information from the position detection sensor 82, and if a malfunction occurs, it detects it as an error.

[0073] In addition, the performance control board 30 is connected to the switches for the performance button 13, cross key 15a, and decision button 15b, which are shown as operation unit 17 in the figure, i.e., the operation detection switches for the performance button 13, cross key 15a, and decision button 15b, and the performance control board 30 is capable of receiving operation detection signals from the performance button 13, cross key 15a, and decision button 15b, respectively.

[0074] Furthermore, the performance control board 30 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the firing operation handle 15 shown in Fig. 1 is being touched by a user such as a player. Based on the detection information of this handle sensor 83, the performance control board 30 is able to determine whether or not the firing operation handle 15 is being touched by a user.

[0075] Based on the performance control command sent from the main control unit 20, the performance control board 30 selects (determines) a performance pattern by lottery or uniquely from multiple types of performance patterns prepared in advance, and controls various performance means at the required timing to produce the desired performance. This realizes the display of a performance image on the liquid crystal display device 36 corresponding to the performance pattern, the playback of sound from the speaker 46, and the lighting and flashing of the decorative lamps 45 and LEDs, and the chronological development of various performance patterns (such as decorative symbol variation display operations and preview performances), thereby realizing a "performance scenario" in the broad sense.

[0076] Here, for the performance control command, the performance control board 30 (performance control CPU 30a) receives and analyzes it by generating an interrupt process based on the input of the above-mentioned strobe signal sent by the main control unit 20 (main control CPU 20a). Specifically, the performance control CPU 30a executes a control program for command reception interrupt processing based on the input of the above-mentioned strobe signal, and in the interrupt process realized by this, it obtains the performance control command and analyzes the command content. In this case, if an interrupt occurs based on the input of a strobe signal, the performance control CPU 30a interrupts the interrupt processing based on another interrupt (a timer interrupt processing that is executed periodically) even if that processing is in progress, and performs command reception interrupt processing, and even if other interrupts occur at the same time, the command reception interrupt processing is given priority.

[0077] <3. Overview of operation> Next, an outline of the gaming operation of the gaming machine 1 realized by the above-described control configuration (FIG. 3) will be described.

[0078] [3.1 Game Status] The gaming machine 1 is configured to be able to set a plurality of types of gaming states in addition to the jackpot game, which is a special gaming state. To facilitate understanding of this embodiment, first, various gaming states will be described.

[0079] In the gaming machine 1, a game progresses in one of the game states that combines either a low probability state or a high probability state with either a non-time-shortening state or a time-shortening state.

[0080] The low probability state is a state in which the probability of winning the jackpot lottery is relatively low, and the high probability state is a state in which the probability of winning the jackpot lottery is relatively high. The non-time-shortening state is a state in which it is relatively difficult for a gaming ball to enter the starting hole 35, and the time-shortening state is a state in which it is relatively easy for a gaming ball to enter the starting hole 35. For example, the opening time of the starting hole 35 when the regular winning lottery is won is set longer in the time-shortening state than in the non-time-shortening state. However, if it is easier for a gaming ball to enter the starting hole 35 in the time-shortening state than in the non-time-shortening state, the time-shortening state may, for example, have a higher probability of winning the regular winning lottery or a shorter fluctuation time of the regular symbol than in the non-time-shortening state.

[0081] In this embodiment, the "normal state" refers to a low probability state and a non-time-saving state, and corresponds to the initial state.

[0082] [3.2 Game with changing symbols] The variable symbol display game will now be described.

[0083] (Special pattern change display game) In the pachinko gaming machine 1 of this embodiment, a "jackpot lottery" is conducted by random number lottery on the main control board 20 based on a predetermined starting condition, specifically, based on the game ball entering (winning) the start hole 34 or the start hole 35. Based on the lottery result, the main control board 20 variably displays special patterns 1 and 2 on the special pattern display devices 38a and 38b to start the special pattern variable display game, and after a predetermined time has passed, the result is derived and displayed on the special pattern display device, thereby ending the special pattern variable display game.

[0084] In this embodiment, the jackpot lottery based on winning at starting hole 34 and the jackpot lottery based on winning at starting hole 35 are conducted separately and independently. For this reason, the jackpot lottery result for starting hole 34 is derived on the special pattern display device 38a side, and the jackpot lottery result for starting hole 35 is derived on the special pattern display device 38b side. Specifically, on the special pattern display device 38a side, on the condition that a gaming ball has entered starting hole 34, special pattern 1 is variably displayed and a first special pattern variable display game is started, while on the special pattern display device 38b side, on the condition that a gaming ball has entered starting hole 35, special pattern 2 is variably displayed and a second special pattern variable display game is started. Then, when the special pattern variable display game is started on the special pattern display device 38a or the special pattern display device 38b, after a predetermined variable display time has elapsed, if the result of the jackpot lottery is a "jackpot", the special pattern being displayed in a static state will be displayed in a predetermined "jackpot" mode, or in a predetermined "miss" mode otherwise, thereby deriving the game result (jackpot lottery result).

[0085] For convenience of explanation, the first special symbol change display game on the special symbol display device 38a side will be referred to as "special symbol change display game 1," and the second special symbol change display game on the special symbol display device 38b side will be referred to as "special symbol change display game 2." Unless otherwise necessary, "special symbol 1" and "special symbol 2" will be simply referred to as "special symbols" (sometimes abbreviated to "special symbols"), and "special symbol change display game 1" and "special symbol change display game 2" will be simply referred to as "special symbol change display games."

[0086] (Decorative pattern changing game) Furthermore, when the above-mentioned special symbol variation display game is started, the decorative symbol variation display game is started by variably displaying decorative symbols (game symbols for dramatic effects) on the main liquid crystal display device 36M, and various effects are developed in association with this. When the special symbol variation display game ends, the decorative symbol variation display game also ends, and a predetermined special symbol indicating the result of the jackpot lottery is displayed on the special symbol display device, and a decorative symbol reflecting the result of the jackpot lottery is derived and displayed on the main liquid crystal display device 36M. In other words, the result of the special symbol variation display game is reflected and displayed by the decorative symbol variation display game for dramatic effects, including the variably displaying operation of the decorative symbols.

[0087] Therefore, for example, if the result of the special symbol variation display game is a "jackpot" (if the result of the jackpot lottery is a "jackpot"), an effect that reflects that result will be developed in the decorative symbol variation display game. Then, when the special symbol is stopped and displayed in a display mode that indicates a jackpot (for example, the 7-segment display shows "7") on the special symbol display device, the decorative symbols are stopped and displayed in a display mode that reflects the "jackpot" in each of the "left," "center," and "right" display areas on the main liquid crystal display device 36M (for example, three decorative symbols are displayed as "7," "7," and "7") in each of the "left," "center," and "right" display areas.

[0088] When this "jackpot" occurs, specifically, the special pattern change display game ends, followed by the decorative pattern change display game, and as a result, the pattern form of the "jackpot" is derived and displayed, and then the large prize opening solenoid 52c of the special variable prize winning device 52 is activated and the opening door 52b opens and closes in a predetermined pattern, thereby opening and closing the large prize opening 50, and a special game state (jackpot game) which is more advantageous to the player than the normal game state is generated. In this jackpot game, the opening door 52b opens or expands the prize area until the opening time of the large prize opening has elapsed for a predetermined time (maximum opening time: for example, 29.8 seconds) or until the number of game balls that have entered the large prize opening (prize balls entering the large prize opening 50) reaches a predetermined number (maximum number of prizes: the upper limit of the number of prize balls allowed for the opening or expanded prize opening with one operation of the device: for example, 9), and when either of these conditions is met, the large prize opening is closed. This "round game" is repeated for a predetermined number of rounds (for example, up to 16 rounds).

[0089] When the jackpot game starts, an opening effect is first performed to notify the player that the jackpot has started, and after the opening effect ends, round games are played multiple times up to a predetermined number of rounds. After the specified number of rounds have ended, an ending effect is performed to notify the player that the jackpot has ended, thereby ending the jackpot game.

[0090] Regarding the information necessary to execute the decorative pattern change display game, first, the main control board 20 conducts a jackpot lottery that includes a 'win / lose lottery (win / lose type lottery)' to draw whether there will be a jackpot or a 'loss', and a 'pattern lottery (win type (win type) lottery)' to draw the type of jackpot if there is a jackpot, and the type of loss if there is a loss, based on the game ball entering (winning) the start port 34 or the start port 35, specifically, on the condition that the game ball is detected by the start port sensor 34a or the start port sensor 35a and the start condition (start condition related to the special pattern) is met (if there is only one type of loss, there is no need to draw a type lottery for the loss, so that lottery can be omitted), and based on the lottery result information, determines the change pattern of the special pattern and the special pattern (hereinafter referred to as the 'special stop pattern') to be finally stopped and displayed depending on the type of win.

[0091] Then, the main control board 20 transmits a "variation pattern designation command" including at least special symbol variation pattern information (for example, information on the jackpot lottery result and the variation time of the special symbols) to the performance control board 30 as a performance control command that specifies the processing state. This sends basic information required for the decorative symbol variation display game to the performance control board 30. In this embodiment, in order to increase the variety of performances, a "decorative symbol designation command" including special stop symbol information (symbol lottery result information (information on the type of win)) is also transmitted to the performance control board 30.

[0092] The special symbol variation pattern information can include information specifying whether or not a specific preview effect (such as a "reach effect" or "pseudo consecutive effect" described below) will occur. Specifically, the variation patterns of the special symbols are roughly divided into a "win variation pattern" in the case of a win and a "miss variation pattern" in the case of a miss, depending on the result of the jackpot lottery. These variation patterns include, for example, a "reach variation pattern" that specifies the occurrence of a reach effect (described below), a "normal variation pattern" that does not specify the occurrence of a reach effect, a "reach variation pattern with pseudo consecutive effects" that specifies the occurrence (overlapping occurrence) of a pseudo consecutive effect and a reach effect, and a "normal variation pattern with pseudo consecutive effects" that specifies the occurrence of a pseudo consecutive effect but does not specify the occurrence of a reach effect. Note that, in order to ensure the duration of the reach effect or pseudo consecutive effect, the variation time of a variation pattern that specifies a reach effect or pseudo consecutive effect is usually set to be longer than that of a normal variation pattern.

[0093] Based on information contained in the effect control commands (here, the variation pattern designation command and the decorative symbol designation command) sent from the main control board 20, the effect control board 30 determines the effect content (effect scenario, such as preview effects) to be developed in chronological order during the decorative symbol variation display game and the decorative symbols (decorative stop symbols) to be ultimately displayed. The effect control board 30 then executes the decorative symbol variation display game by displaying the decorative symbols in a variable manner according to a time schedule based on the variation pattern of the special symbols. As a result, the decorative symbols displayed by the main LCD display device 36M are displayed in a variable manner in time with the variable display of the special symbols by the special symbol display devices 38a and 38b, so that the duration of the special symbol variation display game and the duration of the decorative symbol variation display game are substantially the same. The effect control board 30 also controls the main LCD display device 36M, the light display device 45a, or the sound generating device 46a in accordance with the effect scenario to develop various effects in the decorative symbol variation display game. This allows the main liquid crystal display device 36M to reproduce images (image effects), reproduce sound effects (sound effects), and light and flash the decorative lamps 45, LEDs, etc. (light effects).

[0094] In this way, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and the display results of the special symbol variation display game are reflected in the decorative symbol variation display game, so these two symbol variation display games can be considered as equivalent symbol games. In this specification, unless otherwise necessary, the above two symbol variation display games may be simply referred to as "pattern variation display games."

[0095] (Normal pattern change display game) Furthermore, in the gaming machine 1, when a gaming ball passes (wins) through the normal symbol starting hole 37, a "auxiliary win lottery" is conducted by random number lottery on the main control board 20. Based on the result of this lottery, the normal symbol represented by the LED is displayed variably on the composite display device 38d to start the normal symbol variable display game, and after a certain time has passed, the result is displayed as a combination of lit and unlit LEDs. For example, if the result of the normal symbol variable display game is a "auxiliary win," the normal symbol display section of the composite display device 38d is displayed as a static display in a specific lighting state (for example, all two LEDs 39 are lit, or of the LEDs representing a "circle" and an "x," only the LED on the "circle" side is lit).

[0096] When this "auxiliary win" occurs, the normal electric accessory solenoid 41c (see Figure 3) is activated, which opens the movable wing piece and opens or enlarges the starting hole 35, making it easier for game balls to flow in (starting hole open state), creating an auxiliary game state (hereinafter referred to as "normal electric open game") that is more advantageous to the player than the normal game state. In this normal electric open game, the movable wing piece opens or enlarges the winning area until the opening time of the starting hole 35 has elapsed for a predetermined time (e.g., 0.2 seconds) or until the number of game balls that have entered the starting hole 35 reaches a predetermined number (e.g., 4), and when either of these conditions is met, the starting hole 35 is closed, and this operation is repeated a predetermined number of times (e.g., up to twice).

[0097] (Regarding reservations) In this embodiment, when a winning entry occurs in the start slot 34, 35, or 37 during a special / decorative symbol change display game, a normal symbol change display game, a jackpot game, or a normal power-on game, i.e., when a detection signal is input from the start slot sensor 34a, 35a, or 37a and the corresponding start condition (symbol game start condition) is met, this data is reserved and stored as data related to the right to start the change display game, up to a predetermined maximum number of reserved data (e.g., up to four), excluding data related to the change display. This reserved data not used for the change display operation, or the game balls related to this reserved data, are also referred to as "activated reserved balls." To inform the player of the number of activated reserved balls, a dedicated reserved ball indicator (not shown) located in an appropriate location on the gaming machine 1 or a reserved ball indicator displayed as an icon image on the LCD display 36 (main LCD display 36M or sub LCD display 36S) is illuminated.

[0098] In this embodiment, up to four activation reserved balls for each of special symbol 1, special symbol 2, and normal symbol are reserved and stored in the corresponding storage area of ​​the main control RAM 20c, and are reserved as the number of times the special symbol or normal symbol changes. Note that there is no particular limit on the maximum number of activation reserved balls (maximum reserved memory number) for special symbol 1, special symbol 2, and normal symbol. Also, all or part of the maximum reserved memory number for each symbol may be different, and the number can be determined appropriately depending on the gameplay.

[0099] [3.3 About winning] Next, a "win" in the gaming machine 1 will be described. In the gaming machine 1 of this embodiment, a jackpot lottery (winning lottery) is conducted for multiple types of winnings. In this example, the winning types include, for example, "normal 4R," "normal 6R," "probable 6R," and "probable 10R" belonging to the jackpot type. The above notation "R" means the specified number of rounds (maximum number of rounds).

[0100] The type of jackpot is the hit that triggers the activation of the conditional device. Here, the "conditional device" refers to a device whose operation is a necessary condition for the activation of the consecutive device for playing rounds, and which is activated when a specific combination of special symbols is displayed or when the game ball passes through a specific area inside the jackpot opening.

[0101] The probability variable state is a so-called "number cut probability variable machine (ST machine)" that ends the high probability state and transitions to a low probability state when the special symbol variation display game has been executed a predetermined number of times (for example, 70 times: the specified ST number of times) without winning a jackpot type, and when the specified ST number of times has been completed, the next game will transition to a normal state. However, it may also be a "general probability variable machine" that continues until the next jackpot is won.

[0102] The number of times the special symbol variation display game is executed may be the total number of times the special symbol variation display game 1 and the special symbol variation display game 2 are executed (the total number of changes in special symbol 1 and special symbol 2), or it may be the number of times either one of them is executed (for example, the number of times the special symbol variation display game 2 is executed). In addition, the number of times the time-saving state is executed is not limited to 60 times or 100 times, and can be determined appropriately depending on the gameplay. In addition, there is no particular restriction on the type of winning to be set, and it can be determined appropriately.

[0103] In this example, similar to the jackpot types, multiple types of "losses" are provided. Specifically, three types of losses, "loss 1," "loss 2," and "loss 3," are provided. As mentioned above, if the result of the lottery is a "lose," a lottery for the type of loss will be held in the pattern lottery.

[0104] [3.4 Production] (Performance mode) Next, the presentation modes (presentation states) will be explained. The gaming machine 1 of this embodiment is provided with a plurality of presentation modes for producing presentations related to the game state, and is configured to be able to switch between these presentation modes. Specifically, a normal presentation mode, a time-saving presentation mode, a potential probability presentation mode, and a probability variable presentation mode are provided, which correspond to the normal state, the time-saving state, the potential probability state, and the probability variable state, respectively. In each presentation mode, the background display as the background of the decorative pattern variation display screen is displayed with a different background presentation, so that the player can understand what game state he or she is currently in.

[0105] The presentation control board 30 (presentation control CPU 30a) has a functional unit (presentation state transition control means) that controls transitions between multiple presentation modes. The presentation control board 30 (presentation control CPU 30a) is configured to grasp the current game state and control transitions between multiple presentation modes in a manner that maintains consistency with the game state managed by the main control board 20 based on specific presentation control commands sent from the main control board 20 (main control CPU 20a), specifically, presentation control commands that include game state information managed by the main control board 20. Examples of such specific presentation control commands include a variation pattern designation command, a decorative symbol designation command, and a game state designation command sent when a change occurs in the game state.

[0106] (Preview performance) Next, the preview effects will be explained. The effect control board 30 is configured to be able to control the appearance of various "preview effects" related to the current presentation mode and the result of the jackpot lottery, based on the contents of the presentation control command from the main control board 20, specifically, based on at least the variation pattern information included in the variation pattern designation command. Such preview effects suggest (preview) the expected probability of winning a particular type of win (hereinafter referred to as "expected probability of winning"), and act as "hype effects" to heighten the player's anticipation of winning. Typical preview effects include "reach effects," "pseudo consecutive effects," and even "predictive preview effects." The effect control board 30 functions as a preview effect control means capable of controlling the execution (appearance) of these effects.

[0107] "Reach effect" refers to an effect mode accompanying a reach state (variable display mode accompanying a reach state: reach variation pattern), and more specifically, an effect mode in which the final game result is derived and displayed via a reach state. Reach effects include multiple types of reach effects associated with the probability of winning. For example, there are some in which the probability of winning is relatively higher than when a normal reach effect appears. Such reach effects are called 'super reach effects'. Many of these "super reaches" have a relatively longer presentation time (variation time) than normal reaches to increase the expectation of winning. Furthermore, normal reaches and super reaches include multiple types of reach effects. In this example, super reaches include multiple types of reach effects, namely Super Reach 1, 2, 3, and 4, and the probability of winning of these Super Reaches 1 to 4 has the following relationship: "Super Reach 1 < Super Reach 2 < Super Reach 3 < Super Reach 4."

[0108] "Pseudo consecutive effects" refers to an effect mode accompanied by a pseudo continuous change display state (pseudo consecutive changes) of decorative symbols, and "pseudo consecutive changes" refers to a change display mode in which, during a decorative symbol change display game, some or all of the decorative symbols are temporarily stopped, and then a change display operation of the decorative symbols is executed again from that temporary stop state, and this display operation is repeated once or multiple times. In this respect, it differs from the "prediction notice effect (continuous notice effect)" described below, which is developed across multiple symbol change display games. The occurrence rate (appearance rate) of such "pseudo consecutive effects" is basically set so that the more pseudo changes there are, the higher the probability of winning. For example, depending on the number of pseudo changes, effects that stimulate expectations such as a super reach are more likely to be selected.

[0109] "Prediction prediction effect" (hereinafter sometimes abbreviated as "prediction prediction" or "prediction effect") refers to an effect that notifies the player of the possibility of being controlled to an advantageous state before the variable display of the symbol to be judged is carried out based on the results of the prediction judgment. "Advantageous state" means a state that is advantageous to the player. Specifically, the pre-reading effect in this example is performed in a presentation mode that can notify the winning expectation in advance of an activation reserved ball (an unconsumed activation reserved ball) that has not yet been used for the execution of a pattern change display game (the operation of displaying the variation of special patterns), by mainly utilizing the reserved display mode and the background presentation of the pattern change display game that is executed first, before the activation reserved ball is used for the pattern change display game. In addition to the above-mentioned "reach presentation," various presentations such as the so-called "SU (step-up) notice presentation," "timer notice presentation," "revival presentation," and "premium notice presentation" are generated in the pattern change display game, to liven up the game content.

[0110] Here, with reference to FIG. 4, the "hold change notice effect" will be described as an example of the above-mentioned look-ahead notice effect. In the gaming machine 1 of this embodiment, the upper display area of ​​the screen of the main liquid crystal display device 36M is provided with a display area for displaying the decorative symbol change display game (a display area for displaying decorative symbol change display effects and preview effects), and the lower display area of ​​the screen is provided with a reserved display area 76 (reserved display sections a1 to d1) that displays the number of activated reserved balls on the special symbol 1 side, and a reserved display area 77 (reserved display sections a2 to d2) that displays the number of activated reserved balls on the special symbol 2 side. The presence or absence of activated reserved balls is notified by a predetermined reserved display mode. Figure 5 shows an example in which the presence or absence of activated reserved balls is indicated by a lit state (activated reserved ball present: "○ (white circle)" shown in the figure) or an unlit state (no activated reserved ball present: dashed circle shown in the figure), and information regarding the current number of activated reserved balls is notified.

[0111] The display (reserved display) indicating the presence or absence of activated reserved balls is displayed sequentially in the order of occurrence (winning order), and in each reserved display area 76, 77, the leftmost activated reserved ball is displayed as the activated reserved ball that occurred first on the time axis (i.e., the oldest) among all activated reserved balls in that reserved display. Also, to the left of the reserved display areas 76, 77, a changing display area 78 is provided to indicate the activated reserved ball currently being used in the special symbol variable display game. In this embodiment, the changing display area 78 is configured to display an image in which the icon of the game-in-progress reserved ball K currently being used in the game is placed on the icon of the seat J. That is, when the variable display of special symbol 1 or special symbol 2 begins, the icon (icon image) of the oldest reserved ball a1 or a2 displayed in the reserved display area 76, 77 moves to the icon of the seat J in the changing display area 78 as the icon of the game-in-progress reserved ball K, and this state is maintained for a predetermined display time.

[0112] When an activated pending ball occurs, the main control board 20 sends a "pending addition command" to the performance control board 30, which specifies the advance reading judgment information related to the jackpot lottery result and the number of activated pending balls at the time of advance reading judgment (the number of currently existing activated pending balls, including the activated pending ball that has occurred this time) (see steps S1309 to S1312 in Figure 28). In this embodiment, the above-mentioned reserve addition command is composed of two bytes, and the reserve addition command is composed of data on the upper byte side that enables the number of active reserved balls to be identified at the time of the pre-reading judgment, and data on the lower byte side that enables the pre-reading judgment information to be identified.

[0113] As can be understood from the above explanation, in this embodiment, when a winning entry occurs in the start hole 34 or the start hole 35 and a new reserved ball is generated, a jackpot lottery is held for the symbol variation display game related to the reserved ball as a pre-reading judgment for the reserved ball. As will be described later, the main control board 20 reserves and stores information representing the result of the jackpot lottery held as such a pre-reading judgment in a corresponding storage area of ​​the main control RAM 20c. The information on the jackpot lottery result obtained at the time of the look-ahead judgment is used to select (lottery) the pattern variation pattern in the pattern variation display game, and can be said to be "variation pattern selection information." Therefore, it can be said that the main control board 20 performs the look-ahead judgment and reserves and stores the "variation pattern selection information" obtained as a result in a predetermined area of ​​the main control RAM 20c.

[0114] When the performance control board 30 receives the above-mentioned hold addition command sent by the main control board 20, it performs performance control processing for the "pre-reading notice performance" as part of the display control processing related to the above-mentioned hold display based on the pre-reading judgment information contained therein. Specifically, it performs a "pre-reading notice lottery" to draw whether or not the pre-reading notice performance can be executed, and if it is won, it makes the pre-reading notice performance appear.

[0115] Here, the pre-reading judgment information is specifically game information obtained by pre-reading the jackpot lottery result (jackpot lottery result at the start of the variation) executed when the activation reserved ball is provided to the pattern variation display game in the main control board 20 and the variation pattern at the start of the variation. That is, this information includes at least information that pre-reads and judges the lottery result at the start of the variation (pre-reading win / loss information), and can also include information that pre-reads and judges the pattern lottery result (pre-reading pattern information) and information that pre-reads and judges the variation pattern at the start of the variation (pre-reading variation pattern information). The information included in the reserved addition command to be sent to the performance control board 30 can be determined appropriately depending on the content to be notified in the pre-reading notice. In this example, the pending addition command includes pre-reading winning / losing information, pre-reading pattern information, and pre-reading variation pattern information.

[0116] It should be noted that the "pre-read fluctuation pattern" obtained by the pre-read judgment when the activation pending ball occurs does not necessarily have to be the "fluctuation pattern at the start of fluctuation" itself obtained when the activation pending ball is actually used for the fluctuation display operation. For example, to explain a representative case where the fluctuation pattern at the start of fluctuation is a fluctuation pattern that specifies "Super Reach 1", in this case, it is possible to specify that the content specified by the pre-read fluctuation pattern is not the type of reach performance itself called "Super Reach 1", but rather its essential "Super Reach type".

[0117] In this embodiment, if the advance notice lottery is won, a "hold display change" advance notice performance (also referred to as a "hold change notice") is performed in which the hold icon that is the subject of the advance notice among the hold icons in the hold display sections a1 to d1, a2 to d2 is changed from the white of the normal hold display (normal hold display mode) to a hold display (special hold display mode) with a notice display of blue, green, red, or a danger pattern (or special colors or patterns such as rainbow colors). In Figure 5, the hatched reserved ball in the reserved display section b1 is shown as an example of a change to a special reserved display. Here, the display of the reserved icon in blue, green, red, and danger pattern indicates a higher probability of winning in this order, and the display of the reserved icon in danger pattern is a premium reserved icon that indicates an extremely high probability of winning a jackpot.

[0118] (Direction means) Various effects in the gaming machine 1 are produced by the effect means provided in the gaming machine 1. These effect means may be any stimulus transmission means capable of producing effects by appealing to human senses, such as sight, hearing, or touch. Representative examples include light-generating means (light display device 45a: light effect means) such as decorative lamps 45 and LED devices, sound-generating devices (sound generating device 46a: sound effect means) such as speakers 46, effect display devices (display means) such as the main LCD display device 36M and the sub-LCD display device 36S, pressure devices that transmit contact pressure to the operator's body, wind pressure devices that apply wind pressure to the player's body, and movable gadgets that produce visual effects through their movement. Here, effect display devices, like image display devices, are visually appealing displays, but differ from image display devices in that they also include devices that do not rely on images (e.g., 7-segment displays). The term "image display device" primarily refers to a type that produces effects by displaying images; devices that produce effects through means other than images, such as 7-segment displays, are included within the concept of effect display devices.

[0119] <4. Opening and closing structure and board layout> The configuration shown in Figure 3 is actually realized via multiple boards. Below, we will explain the arrangement of some of the boards installed in the gaming machine 1. We will also explain the opening and closing structure of the gaming machine 1 in relation to the installation position of the boards.

[0120] FIG. 5 shows the door 6 in an open state. When the door 6 is opened, the inner frame 2 and the game board 3 attached to the inner frame 2 are directly exposed. The board arranged on the door 6 and the board arranged on the inner frame 2 are connected by wiring using a harness as a transmission line H8.

[0121] The gaming machine 1 is also configured so that the inner frame 2 can be opened relative to the outer frame 4. Figure 6 shows the state in which the inner frame 2 is open. When the inner frame 2 is opened, the game board 3 attached to the inner frame 2 is also released from the outer frame 4. Figure 6 shows the state in which the back cover 18 attached to the position on the back side of the game board 3 is visible. Although the game board 3 is not shown in Figure 6, the back side of the game board 3 is exposed when the back cover 18 is removed (opened). In reality, the back cover 18 is transparent or semi-transparent, so the back side of the game board 3 can be seen in the state shown in Figure 6. The game board 3 can also be removed from the inner frame 2.

[0122] Thus, the gaming machine 1 is broadly composed of an outer frame 4, an inner frame 2 attached to the outer frame 4, a gaming board 3 attached to the inner frame 2, and a door 6 located in front of the gaming board 3 and the inner frame 2. Various boards are attached to either the gaming board 3, the inner frame 2, or the door 6.

[0123] Figure 7 shows the positions of some of the boards attached to the game board 3. Note that Figure 7 shows the boards attached to the back side of the play area 3a when the game board 3 is viewed from the rear side. Therefore, the right side of the figure is the left side when the game board 3 is viewed from the front side. In the figure, the outline of the frame of the game board 3 is shown with a dashed line to indicate the position.

[0124] As shown in the figure, on the back side of the game board 3, the performance control board 30 is placed slightly above the center, and the main control board 20 is placed below that. In addition, a liquid crystal control board 901 is placed so as to overlap with the performance control board 30, and a ROM board 902 and a liquid crystal interface board 903 are placed nearby.

[0125] An LED connection board 700 is disposed on the left side of the rear surface of the game board 3, and a power supply module board 904 is disposed near the top thereof. In addition, an upper connection board 905 is disposed above the game board 3.

[0126] Near the main control board 20, a relay board 760, a decorative board 740, a left backside relay board 720, a game board connection board 906, a bottom backside relay board 800, and a frame LED relay board 840 are arranged.

[0127] Furthermore, LED boards 780 and 790 and a decorative board 820 are available as boards that are attached to movable accessories (not shown) that are attached to the game board.

[0128] 8 shows the positions of some of the circuit boards attached to the door 6 as seen from the front side of the gaming machine 1. As a guide to the positions of the components inside the gaming machine 1, the door 6, the effect button 13, the firing operation handle 15, and the upper speaker 46 are shown by dashed lines.

[0129] A relay board 550 is provided above the door 6 . Similarly, a side unit upper LED board 630 is provided above the door 6, a side unit upper right LED board 600 is provided at the top right of the door 6, and a side unit lower right LED board 620 is provided below that. The side unit upper right LED board 600, side unit lower right LED board 620, and side unit upper LED board 630 are attached inside the side unit 10 (see FIG. 1), and when the side unit 10 is attached to the door 6, each board is positioned as shown in FIG.

[0130] A frame left LED board 907 is disposed at the upper left side of the door 6, and a frame left lower LED board 908 is disposed below it. In addition, a front frame LED connection board 500 is disposed below the door 6. In addition, a button LED connection board 640 is arranged at the bottom right, and a button LED board 660 is arranged inside the performance button 13.

[0131] Next, we will explain the position of the board attached to the inner frame 2. Figure 9 is a view of the gaming machine 1 as seen from the back. Most of the back side of the gaming machine 1 is protected by a transparent or semi-transparent back cover 18. Below this rear side, a power supply board 300 and a dispensing control board 29 are arranged in front and behind. Also, an inner frame LED relay board 400 is attached to the lower right side when viewed from the rear side.

[0132] 10 shows the positions of various devices arranged on the door 6 and the game board 3. The outlines of the game board 3 and the door 6 are shown by dashed lines to indicate the position of each device.

[0133] 10, the devices provided in the side unit 10 of the door 6 are a side unit device 101, a side unit lower right movable object position detection switch 102, a side unit lower right movable object motor 103, a side unit upper right movable object motor 104, a side unit upper right movable object solenoid 105, a blower 106, and photocouplers PC1F, PC2F, and PC3F, which are arranged at the positions shown in the figure. The photocouplers PC1F, PC2F, and PC3F are attached to the side unit lower right LED board 620.

[0134] In addition, in Figure 10, the devices attached to the game board 3 include a lower rear movable object upper position detection switch 120, a lower rear movable object right position detection switch 121, a distribution position detection switch 122, a lower front movable object position detection switch 123, a lower front movable object motor 124, a lower rear movable object left position detection switch 125, a lower rear movable object left motor 126, a lower rear movable object lower right position detection switch 127, a lower rear movable object lower left position detection switch 128, an upper movable object left motor 129, an upper movable object left position detection switch 130, a left movable object motor 131, an upper movable object position detection switch 132, an upper movable object right motor 133, a left movable object position detection switch 134, and a lower rear movable object right motor 135, each of which is arranged at the positions shown in the figure.

[0135] 7, 8, and 9 are merely a portion of the boards provided in the gaming machine 1. In particular, they illustrate the main boards that will be the subject of the following explanation. Furthermore, the devices shown in FIG. 10 are only a part of the devices provided in the gaming machine 1.

[0136] <5. Board connection configuration> [5.1 Connection status of each board] The connection configuration of each board arranged as described above will be explained, and the supply path of the power supply voltage will be mentioned.

[0137] FIG. 11 shows an example of the boards arranged on the game board 3, the inner frame 2, and the door 6, respectively. In this case, the boards mounted on the game board 3 are the main control board 20, the performance control board 30, the frame LED relay board 840, the LED connection board 700, the left relay board 720 behind the board, the decorative board 740, the relay board 760, the LED board 780, the LED board 790, the lower relay board 800 behind the board, and the decorative board 820. The boards mounted on the inner frame 2 include a power supply board 300, a dispensing control board 29, and an inner frame LED relay board 400. The boards mounted on the door 6 include a front frame LED connection board 500, a relay board 550, a side unit upper right LED board 600, a side unit lower right LED board 620, a side unit upper LED board 630, a button LED connection board 640, and a button LED board 660.

[0138] Each of these boards is a part of the boards mounted on the gaming machine 1, and there are various types of boards other than those shown in the figure that are mounted on the gaming board 3, inner frame 2, and door 6. This Figure 11 shows the connection system of selected boards for use in explaining the technology as an embodiment of the present invention, and does not show all of the boards.

[0139] The power supply board 300 is a board that supplies DC voltage as operating power to each part based on AC input power. The main control board 20, the performance control board 30, and the payout control board 29 are as described in Figure 3.

[0140] The front frame LED connection board 500 is a board for supplying operation control signals and power supply voltage to the LEDs provided on the door 6, the motors of the movable bodies, the solenoids, the blowers, and other performance means.

[0141] The side unit upper right LED board 600, the side unit lower right LED board 620, and the side unit upper LED board 630 are boards arranged inside the side unit 10, and constitute a drive control system for the LEDs and the modes of the movable props. These boards also constitute a detection system that transmits detection signals from the motor position sensors, touch sensors, and various other sensors to the performance control board 30. As described above, the side unit 10 is attached to the door 6 as one of the decorative units, and the side unit 10 is detachable and replaceable with respect to the door 6. The side unit upper right LED board 600, the side unit lower right LED board 620, and the side unit upper LED board 630 are detachable along with the side unit 10. When the side unit 10 is mounted and the relay board 550 and the transmission line H10 of the upper right LED board 600 of the side unit are connected, the electrical configuration shown in FIG. 11 is obtained.

[0142] The button LED board 660 configures the LEDs in the effect buttons 13 and their light emission drive system, and also includes circuits for transferring detection signals from various detection sensors. The button LED connection board 640 relays control signals and power supply voltage to the button LED board 660, and also transfers detection signals from various sensors.

[0143] The inner frame LED relay board 400 relays signals between the frame LED relay board 840, which is connected to the performance control board 30, and the front frame LED connection board 500, and also performs the necessary signal processing and generates and supplies power supply voltage. The frame LED relay board 840 relays the signal path between the inner frame LED relay board 400 and the performance control board 30.

[0144] The LED boards 780 and 790 are mounted with LEDs on the game board 3 and drive the LEDs to emit light. The relay board 760 relays the LED light emission drive signals. The LED boards 780 and 790 and the relay board 760 are attached to the movable accessory. The decorative board 740 relays and drives other LED boards. The rear left relay board 720 performs relaying. The decorative substrate 820 carries an LED. The under-board relay board 800 performs relaying. The LED connection board 700 performs various signal processing required to drive the light emission of performance means such as LEDs and motors based on control signals from the performance control board 30.

[0145] These boards are electrically connected by harnesses and cables via transmission lines H. "Transmission lines H" is a general term for the transmission lines H1, H2, ... H31 shown in the figure. In each transmission line H, the individual wiring paths that transmit signals, power supply voltages, etc. are also simply called "lines." A transmission line H refers to a set of one or more lines. The transmission line H includes various forms such as a flexible harness, a flexible substrate, a wire harness, etc. The transmission line H may be an integrated line of multiple lines, or individual lines may be bound together with a binder, tape, etc. Furthermore, when connectors are directly connected to each other, the terminals of the connectors become the transmission line H. In other words, even when there is no wire material such as a harness, it is included in the "transmission line H". That is, the transmission line H does not refer to a specific type or shape, but rather refers broadly to anything that forms electrical wiring between substrates, etc.

[0146] The power supply board 300 and the dispensing control board 29 are connected by a transmission line H1. The power supply board 300 and the inner frame LED relay board 400 are connected by a transmission line H3. These transmission lines H1 and H3 are formed by harnesses or the like arranged within the inner frame 2.

[0147] The power supply board 300 and the performance control board 30 are connected by a transmission line H2. The dispensing control board 29 and the main control board 20 are connected by a transmission line H4. The inner frame LED relay board 400 and the frame LED relay board 840 are connected by a transmission line H7. These transmission lines H2, H4, and H7 are formed by harnesses or the like that connect the inner frame 2 and the game board 3 across each other.

[0148] The main control board 20 and the performance control board 30 are connected by a transmission line H5. The performance control board 30 and the frame LED relay board 840 are connected by a transmission line H6. The performance control board 30 and the LED connection board 700 are connected by a transmission line H20. The LED connection board 700 and the rear left relay board 720 are connected by a transmission line H21. The rear left relay board 720 and the decorative board 740 are connected by a transmission line H22. The decorative substrate 740 and the relay substrate 760 are connected by a transmission line H23. The transmission line H23 may be a flexible cable for connection to the relay substrate 760 attached to the movable accessory. The relay board 760 and the LED board 780 are connected by a transmission line H24. The LED board 780 and the LED board 790 are connected by a transmission line H25. The LED connection board 700 and the under-board relay board 800 are connected by a transmission line H30. The under-board relay board 800 and the decorative board 820 are connected by a transmission line H31. These transmission lines H5, H6, H20, H21, H22, H23, H24, H25, H30, and H31 are formed by harnesses arranged within the game board 3.

[0149] The inner frame LED relay board 400 and the front frame LED connection board 500 are connected by a transmission line H8. This transmission line H8 is formed by a harness or the like that connects the inner frame 2 and the door 6 across the space between them.

[0150] The front frame LED connection board 500 and the relay board 550 are connected by a transmission line H9. The relay board 550 and the side unit upper right LED board 600 are connected by a transmission line H10. The side unit upper right LED board 600 and the side unit lower right LED board 620 are connected by a transmission line H11. The side unit upper right LED board 600 and the side unit upper LED board 630 are connected by a transmission line H12. The front frame LED connection board 500 and the button LED connection board 640 are connected by a transmission line H15. The button LED connection board 640 and the button LED board 660 are connected by a transmission line H16. These transmission lines H9, H10, H11, H12, H15, and H16 are formed by harnesses or the like arranged inside the door 6.

[0151] The power supply board 300 supplies power supply voltage to each part via transmission lines H1, H2, and H3. FIG. 12 shows the power supply inputs and outputs for the power supply board 300. The power supply board 300 is equipped with connectors CN1A to CN7A. The connectors CN5A, CN6A, and CN7A are connected to the transmission line ends of transmission lines H40, H41, and H42, which are not shown in FIG.

[0152] Hereinafter, the connectors CN1A to CN7A, as well as connectors appearing in other drawings, will be collectively referred to as "connectors CN." In this specification, the term "connector CN" refers to a connector terminal component provided on a substrate. The terminal portion for connector connection formed at the end of the transmission line H will be called the "transmission line end." The "connector CN" is connected to the "transmission line end." Alternatively, the "connector CN" may be directly connected to another connector CN of a corresponding shape.

[0153] A 24V AC power supply is supplied from the power plug 301 of the gaming machine 1 to the three-terminal connector CN5A via a transmission line H40 (AC-IN(A), AC-IN(B)). Also, an FG (frame ground) path (FG) is formed via the ground terminal 302, the transmission line H40, and the connector CN5A. The ground terminal 302 is connected to the outside of the gaming machine main body, for example.

[0154] A transmission line H41 is connected to the two-terminal connector CN6A, forming an FG path (FG-1) via ground terminals 303 and 304. The ground terminals 303 and 304 are connected to, for example, the gaming machine main body. A transmission line H42 is connected to the two-terminal connector CN7A, forming an FG path (FG-2) via ground terminals 305 and 306. The ground terminals 305 and 306 are connected to, for example, the gaming machine main body.

[0155] A transmission line H1-1 is connected to the 14-terminal connector CN1A. A transmission line H1-2 is also connected to the 3-terminal connector CN4A. These two transmission lines H1-1 and H1-2, which serve as harnesses, are shown as the transmission line H1 in Figure 11. A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the dispensing control board 29 via the transmission line H1-1, and a ground path (GND) is also formed. Two systems of 24V DC voltage (DC24VA, DC24VB) are supplied to the dispensing control board 29 via the transmission line H1-2, and an FG path (FG) is also formed.

[0156] A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the main control board 20 via the dispensing control board 29, and a ground path (GND) is also formed.

[0157] A transmission line H2 is connected to the 20-terminal connector CN2A. Transmission line H2 supplies 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) to the performance control board 30, and also forms a ground path (GND).

[0158] Based on the power supply via this transmission line H2, 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) are supplied from the performance control board 30 to the LED connection board 700, and are used as operating power sources for the LED connection board 700 and each downstream board (the left rear panel relay board 720, the bottom rear panel relay board 800, etc.). On the other hand, the frame LED relay board 840 is a board that simply has relay wiring and does not require a power supply voltage, and no power supply voltage is supplied from the performance control board 30.

[0159] For the purpose of explanation, the terms "upstream" and "downstream" are used, but in terms of data and control signals, the main control board 20 is the most upstream, followed by the performance control board 30, and the "downstream" direction is from the performance control board 30 toward the actual performance devices such as LEDs and motors. With regard to the power supply voltage, power supply board 300 is the most upstream, and is "downstream" toward the actual performance device.

[0160] The transmission line H3 is connected to the six-terminal connector CN3A. A 12V DC voltage (DC12VB) is supplied to the inner frame LED relay board 400 via the transmission line H3, and a ground path (GND) is also formed. In other words, the inner frame LED relay board 400 is a board that is controlled by the performance control board 30, but is configured to receive power supply voltage directly from the power supply board 300. The inner frame LED relay board 400 supplies power supply voltage to each board (such as the front frame LED connection board 500) provided on the door 6 downstream of the inner frame LED relay board 400.

[0161] [5.2 Inner frame LED relay board 400] Below, we will explain the circuit configuration of some of the boards shown in Figure 11. First, we will explain the inner frame LED relay board 400 using Figures 13 and 14. 13 and 14 show the circuit configuration provided on the inner frame LED relay board 400 separately.

[0162] The inner frame LED relay board 400 is mounted with the connectors CN1B, CN2B, and CN3B shown in FIG. 13 and the connector CN4B shown in FIG.

[0163] The connector CN1B is connected to the end of a transmission line H7 that connects to the frame LED relay board 840. Although details about the frame LED relay board 840 are omitted, as described above, it is simply a board with relay wiring. Therefore, the connector CN1B essentially forms wiring between the performance control board 30 via the transmission line H7, the frame LED relay board 840, and the transmission line H6.

[0164] This connector CN1B has 28 terminals, numbered from pin 1 to pin 28, as indicated by the numbers "1" to "28." For ease of explanation, the term "pin" of connector CN does not refer only to pin-shaped male terminals, but also includes both male and female terminals, as well as so-called planar contact patterns and corresponding terminals.

[0165] Pins 1, 3, 5, 7, 8, 17, and 18 are ground terminals. Pin 2 is assigned as the clock signal S_IN_CLK, pin 4 is assigned as the load signal S_IN_LOAD, and pin 6 is assigned as the serial data signal S_IN_DATA.

[0166] Pin 9 is assigned as the clear signal CLR_L, pin 10 is assigned as the clear signal CLR_M, pin 11 is assigned as the clock signal CLK_L, pin 12 is assigned as the clock signal CLK_M, pin 13 is assigned as the data signal DATA_L, pin 14 is assigned as the data signal DATA_M, pin 15 is assigned as the enable signal ENABLE_L, and pin 16 is assigned as the enable signal ENABLE_M. The 19th to 28th pins are assigned to the + and - terminals of the upper right, middle right, lower right, upper left, middle left, and lower speakers, respectively, of the speaker 46.

[0167] Here, the serial data signal S_IN_DATA is serial data received from the front frame LED connection board 500 and transmitted from the inner frame LED relay board 400 to the performance control board 30. The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied from the performance control board 30 to the inner frame LED relay board 400, and then sent to the front frame LED connection board 500. These are used for serial data transmission operations from the front frame LED connection board 500, which is downstream.

[0168] The clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M are signals supplied from the performance control board 30 and used to control the driving of the performance devices. For example, the data signals DATA_L and DATA_M are light-emitting drive signals or motor drive signals that indicate the gradation of the LED, and the clear signals CLR_L, CLR_M, etc., clock signals CLK_L, CLK_M, etc., enable signals ENABLE_L, ENABLE_M, etc. are signals for controlling the operation of the LED driver or motor driver. The "_L" at the end of the clock signals CLK_L, CLK_M, etc. indicates that the signal is primarily used to control the operation of an LED, and the "_M" indicates that the signal is primarily used to control the operation of a motor.

[0169] The connector CN2B is connected to the end of a transmission line H8 that connects to the front frame LED connection board 500. This connector CN2B has 30 terminals, numbered from pin 1 to pin 30, as indicated by the numbers "1" to "30".

[0170] Pins 1 and 3 are terminals for 5V DC voltage (DC5VB). The four pins from pin 27 to pin 30 are terminals for 12V DC voltage (DC12VB). Pins 5, 7, 8, 17, and 18 are ground terminals. Conductor points P1 and P2 on the housing of connector CN2B are connected to ground. This is to ensure the connector's mounting strength. Conductor points P1 and P2 are not connected to the ground terminal inside the connector. In all other connectors CN shown in the drawings, the conductor points P1 and P2 on the housing are not connected to the ground terminal inside the connector.

[0171] The second pin is assigned as a clock signal S_IN_CLK, the fourth pin as a load signal S_IN_LOAD, and the sixth pin as a serial data signal S_IN_DATA terminal. Pin 9 is assigned as the clear signal CLR_L, pin 10 is assigned as the clear signal CLR_M, pin 11 is assigned as the clock signal CLK_L, pin 12 is assigned as the clock signal CLK_M, pin 13 is assigned as the data signal DATA_L, pin 14 is assigned as the data signal DATA_M, pin 15 is assigned as the general-purpose output port, and pin 16 is assigned as the enable signal ENABLE_M. Pins 19 to 26 are assigned as the + and - terminals for the upper right speaker, center right speaker, lower right speaker, upper left speaker, and center left speaker, respectively, of the speaker 46, as shown in the figure.

[0172] Connector CN3B is a connector for connection to the lower speaker, which is one of speakers 46 not shown in Fig. 11. The first and second pins of this connector CN3B, numbered "1" and "2," are assigned to the + and - terminals of the lower speaker, and are connected to pins 27 and 28 of connector CN1B.

[0173] The connector CN4B in FIG. 14 is connected to the transmission line end of the transmission line H3 that connects to the power supply board 300, and is connected to the connector CN3A of the power supply board 300 shown in FIG. This connector CN4B has six terminals, numbered "1" to "6," from pin 1 to pin 6, and is assigned in the same manner as connector CN3A of power supply board 300. That is, pins 1, 2, and 3 are terminals to which 12V DC voltage (DC12VA) is supplied from power supply board 300. Pins 4, 5, and 6 are ground terminals.

[0174] In this case, inner frame LED relay board 400 is configured so that 12V DC voltage (DC12VA) from pins 1, 2, and 3 is input to voltage regulator 401 via fuse F1B, and 5V DC voltage (DC5VB) is obtained as the output of voltage regulator 401. Capacitors C3B, C4B, C5B, and C6B are connected in parallel between the input terminal of voltage regulator 401 and ground. Capacitor C7B and resistor R24B are connected in parallel between the output terminal of voltage regulator 401 and ground. That is, a 5V generating unit 410 is formed that generates a 5V DC voltage (DC5VB) from a 12V DC voltage (DC12VA).

[0175] The 5V DC voltage (DC5VB) generated in this way by the inner frame LED relay board 400 is supplied to the downstream board from the first and third pins of the connector CN2B in FIG. The 12V DC voltage (DC12VB) supplied to the downstream board via pins 27 to 30 of connector CN2B is a voltage supplied from power supply board 300 via pins 1, 2, and 3 of connector CN4B in Figure 14.

[0176] As shown in FIG. 13, an inner frame LED relay board 400 is provided with buffer circuits 402 and 403 using ICs. The buffer circuits 402 and 403 use an IC that functions as an inverter when the CONT terminal of the first pin is at L level and as a buffer when it is at H level. In this case, the IC functions as a buffer by applying an H level using a 5V DC voltage (DC5VB). In addition, a 5V DC voltage (DC5VB) is applied to the VCC terminal of pin 20 as the operating power supply.

[0177] The buffer circuits 402 and 403 are Schmitt trigger buffers with eight CMOS circuits, which buffer signals input from the second pin (A1 terminal) to the ninth pin (A8 terminal), i.e., perform signal compensation (restore degraded H / L signal waveforms), and output the signals from the eighteenth pin (Y1 terminal) to the eleventh pin (Y8 terminal), respectively. That is, a signal input to the A1 terminal is buffered and output from the Y1 terminal, a signal input to the A2 terminal is buffered and output from the Y2 terminal, and so on, and a signal input to the A8 terminal is buffered and output from the Y8 terminal. Buffering refers to signal compensation processing such as signal amplification and waveform shaping, but since it primarily targets pulse signals as digital data, it has a greater meaning of waveform shaping. Below, these processes will be referred to as "buffering" or "signal compensation."

[0178] The buffer circuit 402 performs signal compensation for the clock signal S_IN_CLK, the load signal S_IN_LOAD, and the serial data signal S_IN_DATA. The clock signal S_IN_CLK from the second pin of the connector CN1B is input to the A3 terminal of the buffer circuit 402, output from the Y3 terminal, and supplied to the second pin of the connector CN2B. The load signal S_IN_LOAD from the fourth pin of the connector CN1B is input to the A1 terminal of the buffer circuit 402, output from the Y1 terminal, and supplied to the fourth pin of the connector CN2B. The serial data signal S_IN_DATA input from the downstream side to the sixth pin of the connector CN2B is input to the A5 terminal of the buffer circuit 402, output from the Y5 terminal, and supplied to the sixth pin of the connector CN1B.

[0179] Furthermore, the buffer circuit 402 has its 3rd pin (A2 terminal), 5th pin (A4 terminal), 7th pin (A6 terminal), 8th pin (A7 terminal), 9th pin (A8 terminal), 10th pin (GND terminal), and 19th pin (G terminal) connected to ground, and its 11th pin (Y8 terminal), 12th pin (Y7 terminal), 13th pin (Y6 terminal), 15th pin (Y4 terminal), and 17th pin (Y2 terminal) left open.

[0180] The buffer circuit 403 performs signal compensation for the clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, the 15th pin for the enable signal ENABLE_L, and the 16th pin for the enable signal ENABLE_M. Each of these signals input from the 9th to 16th pins of connector CN1B is input to one of the A1 to A8 terminals of buffer circuit 402, output from the Y1 to Y8 terminals, and supplied to the 9th to 16th pins of connector CN2B. Furthermore, the 10th pin (GND terminal) and the 19th pin (G terminal) of the buffer circuit 403 are connected to the ground.

[0181] As described above, the inner frame LED relay board 400 has the following configuration. The clock signal S_IN_CLK and load signal S_IN_LOAD supplied from the performance control board 30 (frame LED relay board 840) to the connector CN1B are compensated by the buffer circuit 402 and sent downstream by the connector CN2B. The serial data signal S_IN_DATA supplied from the downstream front frame LED connection board 500 to the connector CN2B is compensated by the buffer circuit 402 and transmitted to the upstream side by the connector CN1B. The clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M supplied from the performance control board 30 (frame LED relay board 840) to connector CN1B are compensated by buffer circuit 403 and sent downstream via connector CN2B.

[0182] Relays the audio signal to the speaker and sends it directly to the downstream board or speaker unit. · Power supply voltage is not supplied from connector CN1B (transmission line H7) connected to the performance control board 30 side (frame LED relay board 840). · 12V DC voltage (DC12V) is received from the power supply board 300 via connector CN4B, and is converted into 12V DC voltage (DC12VB) that is supplied downstream via fuse F1B. A 5V DC voltage (DC5VB) is generated using a 12V DC voltage (DC12V) to be used on the inner frame LED relay board 400 and downstream side, and is used as the operating power source for the buffer circuits 402 and 403 and is also supplied to the downstream side.

[0183] In addition to the above, as shown in FIGS. 13 and 14, the inner frame LED relay board 400 is also connected with resistors R1B to R26B, resistors formed by chip resistors RA1B and RA2B, and capacitors C1B to C17B at required locations. For example, for the clock signal S_IN_CLK, load signal S_IN_LOAD, clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M, resistors R25B, R26B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, and R15B are inserted as damping resistors on the input side (connector CN1B side), and resistors R3B and R2B and chip resistors RA1B and RA2B are inserted as damping resistors on the output side (connector CN2B side). In this case, if the wiring distance between the connector and the damping resistor is LA, and the wiring distance between the damping resistor and the buffer circuits 402 and 403 is LB, then: LA <LB In other words, the damping resistor is arranged closer to the connector (CN1B or CN2B) than the buffer circuits 402 and 403. This improves the signal noise reduction performance.

[0184] [5.3 Front Frame LED Connection Board 500] The front frame LED connection board 500 will be described with reference to Figures 15, 16, 17, 18, 19, and 20. These figures show the circuit configurations provided on the front frame LED connection board 500 separately.

[0185] The front frame LED connection board 500 is equipped with the following connectors: connectors CN2C, CN5C, CN6C, and CN8C in FIG. 15, connectors CN1C and CN4C in FIG. 16, connector CN3C in FIG. 17, connectors CN7C and CN9C in FIG. 18, and connector CN10C in FIG. 20.

[0186] The connector CN2C in FIG. 15 is connected to the transmission line end of the transmission line H8 that connects to the connector CN2B of the inner frame LED relay board 400 in FIG. Therefore, this connector CN2C has a 30-terminal configuration, from pin 1 to pin 30, as indicated by the numbers "1" to "30," and the terminal assignments are the same as those of the above-mentioned connector CN2B. Conductor points P1 and P2 on the housing of connector CN2C are also connected to ground. This is for the sake of the connector's mounting strength, and conductor points P1 and P2 are not connected to ground terminals inside the connector. Although not mentioned again, conductor points P1 and P2 on the housings of connectors CN1C, CN3C, CN4C, CN7C, CN8C, CN9C, and CN10C, which will be described later, are also connected to ground for mounting strength.

[0187] Connector CN5C is a connector for connection to the center right speaker, which is one of speakers 46. The first and second pins of this connector CN3B, numbered "1" and "2," are assigned as the + and - terminals for the center right speaker, and are connected to pins 20 and 22 of connector CN2C.

[0188] Connector CN6C is a connector for connection to the left center speaker, which is one of speakers 46. The first and second pins of this connector CN6B, numbered "1" and "2," are assigned as the + and - terminals for the left center speaker, and are connected to the 24th and 26th pins of connector CN2C.

[0189] Connector CN8C is a connector for connecting to the upper right speaker and upper left speaker, which are one of speakers 46. The first and second pins of connector CN6B, numbered "1" and "2," are assigned to the positive and negative terminals of the upper right speaker, and are connected to the 19th and 21st pins of connector CN2C. The third and fourth pins, numbered "3" and "4," are assigned to the positive and negative terminals of the upper left speaker, and are connected to the 23rd and 25th pins of connector CN2C.

[0190] The connector CN1C in FIG. 16 is a connector to be connected to an LED board not shown in FIG. The connector CN4C is also connected to an LED board in the handle (not shown).

[0191] The connector CN1C has 13 terminals, numbered "1" to "13," from pin 1 to pin 13. Pins 1 and 6 are ground terminals, pin 2 is the terminal for the clock signal CLK, pin 3 is the terminal for 5V DC voltage (DC5V), pin 4 is the terminal for the data signal DATA, pin 5 is the terminal for the reset signal RESET, and pin 7 is the terminal for 12V DC voltage (DC12V).

[0192] Pins 8 to 13 are input terminals for the R, G, and B LED light emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) supplied from an LED driver provided on a downstream LED board (not shown) to which connector CN1C is connected. This LED light emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) is supplied as is to another downstream LED board in the handle (not shown) via pins 2 to 7 of connector CN4C.

[0193] That is, an LED board (not shown) and an LED board inside the steering wheel are connected downstream of the front frame LED connection board 500 by connectors CN1C and CN4C, and an LED driver is mounted on the LED board. The LED driver operates using the clock signal CLK, 5V DC voltage (DC5V), data signal DATA, reset signal RESET terminal, and 12V DC voltage (DC12V) from connector CN1C to drive the LEDs on the LED board and also generate LED light emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) for the LEDs on the LED board inside the steering wheel. The LED light emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) are supplied to the LEDs on the LED board inside the steering wheel via the front frame LED connection board 500.

[0194] In addition, since these are the paths for the LED light emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7), Zener diodes D8C to D15C are connected to the second to seventh pins of connector CN4C as protection circuits. A 12V DC voltage (DC12VB) is applied to the first pin of the connector CN4C, and power supply voltage is supplied to the LED board in the handle (not shown).

[0195] Such a configuration is used so that two LED boards are connected downstream of the front frame LED connection board 500 and an LED driver is provided on only one of them. That is, the front frame LED connection board 500 outputs a clock signal CLK, a 5V DC voltage (DC5V), a data signal DATA, a reset signal RESET, and a 12V DC voltage (DC12V) to operate the LED driver, and then returns the LED light emission drive current generated by the LED driver, relays it, and sends it to the other LED board.

[0196] In this case, only one LED driver is needed to drive the two downstream LED boards. In particular, when controlling light emission with a common LED drive control signal, it is only necessary to send the LED drive control signal to one of the LED boards, which helps to simplify the wiring configuration. In other words, there is no need to send the clock signal CLK, 5V DC voltage (DC5V), data signal DATA, reset signal RESET, and 12V DC voltage (DC12V) to both LED boards. In addition, by relaying the LED light-emitting drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7), there is no need for a harness to transmit this between the two downstream LED boards.

[0197] 17 is connected to the end of a transmission line H9 that connects to the downstream relay board 550. This connector CN3C has 22 terminals, numbered from pin 1 to pin 22, as indicated by the numbers "1" to "22."

[0198] The five pins, pin 1, pin 3, pin 11, pin 13, and pin 18, are ground terminals. The second pin is the terminal for 5V DC voltage (DC5VB). The three pins, pins 5, 7, and 9, are terminals for 12V DC voltage (DC12VB).

[0199] The fourth pin is assigned as the serial data signal S_IN_DATAx, the sixth pin as the load signal S_IN_LOAD, and the eighth pin as the clock signal S_IN_CLK.

[0200] The 10th pin is assigned as the enable signal ENABLE_L, the 12th pin is the clear signal CLR_P, the 14th pin is the reset signal RESET_P, the 15th pin is the clock signal CLK_M, the 16th pin is the data signal DATA_P, the 17th pin is the reset signal RESET_M, the 19th pin is the data signal DATA_M, the 20th pin is the general-purpose drive signal 1, the 21st pin is the enable signal ENABLE_M, and the 22nd pin is the general-purpose drive signal 2.

[0201] 18 is connected to a circuit board (not shown) for detecting the cross key 15a, the enter key 15b, and the volume and light intensity buttons (not shown). This connector CN7C has nine terminals (pins 1 to 9) indicated by "1" to "9", with the first pin being a ground terminal and sense signals SENS0 to SENS7, which are detection signals for operations of the cross key 15a, etc., being input to each of the second to ninth pins. The sense signals SENS0 to SENS7 from the second to ninth pins are pulled up by a 5V DC voltage (DC5VB) via chip resistors RA3C and RA4C.

[0202] The connector CN9C is connected to a touch sensor (not shown) provided on the firing operation handle 15. This connector CN9C has a two-terminal configuration indicated by "1" and "2", with the first pin receiving the sense signal SENS14 from the touch sensor and the second pin serving as a ground terminal. The sense signal SENS14 is pulled up by a 5V DC voltage (DC5VB) via a resistor R26C.

[0203] The connector CN10C in FIG. 20 is connected to the transmission line end of the transmission line H15 that connects to the button LED connection board 640 in FIG. This connector CN10C has 20 terminals, numbered "1" to "20", from pin 1 to pin 20.

[0204] The five pins, pin 2, pin 4, pin 12, pin 13, and pin 19, are ground terminals. Pin 8 is the terminal for 5V DC voltage (DC5VB). Pin 6 is the terminal for 12V DC voltage (DC12VB). Pins 5 and 7 are terminals for the 12V motor drive voltage (MOT12V).

[0205] The first pin is assigned as the motor drive signal MOTφ / 2, the third pin is assigned as the motor drive signal MOTφ / 1, the ninth pin is assigned as the motor drive signal MOTφ2, the tenth pin is assigned as the motor drive signal DCMOT3, and the eleventh pin is assigned as the motor drive signal MOTφ1.

[0206] The 14th pin is assigned as a terminal for the clear signal CLR_L, the 16th pin is assigned as a terminal for the clock signal CLK_L, and the 18th pin is assigned as a terminal for the data signal DATA_L. The 15th, 17th, and 20th pins are terminals to which sense signals SENS8, SENS9, and SENS11, which are detection signals from the downstream side, are input. The sense signals SENS8, SENS9, and SENS11 are pulled up by a 5V DC voltage (DC5VB) via a chip resistor RA5C.

[0207] The power supply voltage for this front frame LED connection board 500 will be described. The front frame LED connection board 500 is equipped with, as ICs, buffer circuits 501, 502, 503, 507, and 508, which are eight-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously described in FIG. 13, and buffer circuits 504, 512, and 513, which are triple buffer gates. The power supply voltage for these components is a 5V DC voltage (DC5VB) supplied from the first pin of the connector CN2C.

[0208] Parallel / serial (hereinafter referred to as "P / S") conversion circuits 505 and 506 shown in FIG. 18 are mounted as ICs, and the power supply voltage for these is also 5V DC voltage (DC5VB) supplied from the first pin of connector CN2C.

[0209] Furthermore, an S / P conversion circuit 509 (LED driver) shown in FIG. 19 is mounted as an IC, and the power supply voltage for this is a 12V DC voltage (DC12VB) supplied from pins 27 to 30 of connector CN2C.

[0210] Furthermore, motor drivers 510 and 511 shown in FIG. 19 are mounted as ICs, and these use a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) as power supply voltages. The 12V motor drive voltage (MOT12V) is used as a power supply voltage for driving the motor, and the 12V direct current voltage (DC12VS) is used as a power supply voltage for motor drivers such as motor drivers 510 and 511.

[0211] The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB). As shown in FIG. 15, a capacitor C11 is inserted between pins 27 to 30 of connector CN2C and ground, and the anode side of a Schottky barrier diode D18C is connected to the positive electrode of capacitor C11. A resistor R27C, capacitors C12C and C13C, and a chip varistor 515 are connected in parallel between the cathode side of the Schottky barrier diode D18C and ground. With this configuration, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage with overvoltage protection. That is, a power supply isolation / protection circuit 520 is formed to isolate the 12V motor drive voltage (MOT12V) from the 12V DC voltage (DC12VA).

[0212] The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a power supply separation / protection circuit 521 including a diode D19C, a resistor R34C, and a capacitor C21C shown in FIG.

[0213] The flow of various signals in the front frame LED connection board 500 will be described below. To the connector CN2C in Figure 15, clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, a general-purpose output port signal (general-purpose signal HANYOU), and an enable signal ENABLE_M are transmitted from the inner frame LED relay board 400. These signals are input to terminals A1 to A8 of buffer circuit 501 and are compensated for. The clear signals CLR_L and CLR_M supplied from the inner frame LED relay board 400 are shown as reset signals RESET_L and RESET_M in the front frame LED connection board 500.

[0214] The clock signal CLK_L, the data signal DATA_L, and the reset signal RESET_L are compensated by the buffer circuit 501 and then supplied to the buffer circuit 504 in Fig. 16 via the chip resistor RA1C. Then, after being buffered, they are output from the connector CN1C to an LED board (not shown).

[0215] 15 are supplied to the A5 terminal, A6 terminal, A7 terminal, and A8 terminal of the buffer circuit 502 in Fig. 17. The signal-compensated outputs from the Y5 terminal, Y6 terminal, Y7 terminal, and Y8 terminal of the buffer circuit 502 are output from the connector CN3C to the relay board 550 as the clock signal CLK_P, the enable signal ENABLE_L (from the general-purpose signal HANYOU), the data signal DATA_P, and the reset signal RESET_P.

[0216] That is, downstream of the relay board 550, signals for LED control and the like output from the upstream inner frame LED relay board 400 are compensated by the buffer circuits 501 and 502 and then transmitted.

[0217] The clock signal CLK_P is output from connector CN3C via a constant voltage / protection circuit consisting of Zener diode D5C and resistor R19C, the enable signal ENABLE_L via a constant voltage / protection circuit consisting of Zener diode D4C and resistor R15C, the data signal DATA_P via a constant voltage / protection circuit consisting of Zener diode D6C and resistor R20C, and the reset signal RESET_P via a constant voltage / protection circuit consisting of Zener diode D7C and resistor R21C.

[0218] Furthermore, the clock signal CLK_L, data signal DATA_L, and reset signal RESET_L that have been signal compensated by the buffer circuit 501 in Fig. 15 are supplied to the buffer circuit 512 in Fig. 20. After being amplified, they are output from the connector CN10C to the button LED connection board 640 as the clock signal CLK_L, data signal DATA_L, and clear signal CLR_L (reset signal RESET_L).

[0219] Therefore, downstream of the button LED connection board 640, signals for LED control, etc. output from the upstream inner frame LED relay board 400 are compensated by buffer circuits 501 and 512 and then transmitted.

[0220] The clock signal CLK_L, data signal DATA_L, and general-purpose signal HANYOU_L that have been signal compensated by the buffer circuit 501 in Fig. 15 are supplied to a serial / parallel (S / P) conversion circuit 509 in Fig. 19. This S / P conversion circuit 509 is configured using a chip that functions as an LED driver. The LED driver is a device that outputs a light-emitting drive current according to the clock signal CLK_L and the data signal DATA_L, but in this case, it is used primarily for serial / parallel conversion to drive the motor. In other words, the LED driver chip is used as part of the motor driving means.

[0221] The S / P conversion circuit 509, which is made up of an LED driver chip, has output terminals LEDR1, LEDG1, LEDB1... LEDR8, LEDG8, and LEDB8 for light emission drive current and can output drive current for 24 systems, but in this case, only seven terminals are used: output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3. As shown in the figure, the other output terminals are connected to ground. The outputs (currents 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, 23-R3) of the output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 are buffered by a buffer circuit 508 and then supplied to input terminals IN1, IN2, IN3, and IN4 of a motor driver 510 and input terminals IN1, IN3, and IN4 of a motor driver 511.

[0222] The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 are connected to a 5V DC voltage (DC5VB) via chip resistors RA6C and RA7C to pass currents 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, and 23-R3.

[0223] The motor driver 510 outputs motor drive signals MOT1-1, MOT1- / 1, MOT1-2, and MOT1- / 2 from output terminals OUT1, OUT2, OUT3, and OUT4 based on signals at input terminals IN1, IN2, IN3, and IN4. The motor driver 511 outputs motor drive signals MOT3-1, MOT3-3, and MOT3-4 from output terminals OUT1, OUT3, and OUT4 based on signals at input terminals IN1, IN3, and IN4.

[0224] The motor drive signals MOT1-1, MOT1- / 1, MOT1-2, MOT1- / 2, and MOT3-1 are supplied to the connector CN10 in Figure 20 and output to the button LED connection board 640 as motor drive signals MOTφ1, MOTφ / 1, MOTφ2, MOTφ / 2, and DCMOT3 as described above. The motor drive signals MOT3-3 and MOT3-4 are supplied to the connector CN3C in FIG. 17 and output to the relay board 550 as the above-mentioned general drive signals 1 and 2.

[0225] The above constitutes a circuit system within the front frame LED connection board 500 that uses the clock signal CLK_L-, the data signal DATA_L-, and the general-purpose signal HANYOU_L- to generate motor drive signals for the downstream button LED connection board 640 and subsequent boards.

[0226] The clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and clear signal CLR_M (reset signal RESET_M) input from connector CN2C in Fig. 15 are signal compensated by buffer circuit 501 and then supplied to the A1 terminal, A3 terminal, A5 terminal, and A7 terminal of buffer circuit 503 in Fig. 17 via chip resistor RA2C. The signal-compensated outputs from the Y1 terminal, Y3 terminal, Y5 terminal, and Y7 terminal of buffer circuit 503 are then output from connector CN3C to relay board 550 as clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and reset signal RESET_M.

[0227] Therefore, downstream of the relay board 550, the signal for motor control from the upstream inner frame LED relay board 400 is compensated by the buffer circuits 501 and 503 and then transmitted.

[0228] The clock signal CLK_M is output from connector CN3C via a constant voltage / protection circuit consisting of Zener diode D12C and resistor R22C, the enable signal ENABLE_M via a constant voltage / protection circuit consisting of Zener diode D16C and resistor R24C, the data signal DATA_M via a constant voltage / protection circuit consisting of Zener diode D14C and resistor R23C, and the reset signal RESET_M via a constant voltage / protection circuit consisting of Zener diode D17C and resistor R25C.

[0229] The clock signal S_IN_CLK and the load signal S_IN_LOAD input from the connector CN2C in Fig. 15 are supplied to the A3 terminal and A2 terminal of the buffer circuit 502 in Fig. 17. Then, the signal-compensated outputs from the Y3 terminal and Y2 terminal of the buffer circuit 502 are output from the connector CN3C to the relay board 550 as the clock signal S_IN_CLK and the load signal S_IN_LOAD. Therefore, downstream of the relay board 550 and beyond, signals for serial data transmission are compensated by the buffer circuits 501 and 502 before being transmitted.

[0230] The clock signal S_IN_CLK is output from the connector CN3C via a constant voltage / protection circuit made up of a Zener diode D3C and a resistor R11C, and the load signal S_IN_LOAD is output from the connector CN3C via a constant voltage / protection circuit made up of a Zener diode D2C and a resistor R9C.

[0231] 17 from the downstream relay board 550 is supplied to the A1 terminal of the buffer circuit 502. The signal-compensated output of the Y1 terminal of the buffer circuit 502 is input to the SI terminal (serial input terminal) of the P / S conversion circuit 505 in FIG.

[0232] The P / S conversion circuit 505 and the P / S conversion circuit 506 in the same figure are CMOS 8-bit shift registers, which have 8-bit parallel input / output, serial input, and serial output, and perform parallel-to-serial conversion of data. When the P / S CONT terminal is low, the eight terminals Q / D1 to Q / D8 become parallel outputs, and data from the SI terminal is stored in each register at the rising edge of the input waveform to the CK terminal and output to the Q / D1 to Q / D8 terminals. In addition, by setting the CLR / LOAD terminal to low, each register is reset asynchronously with the input to the CK terminal. When the P / S CONT terminal is high, the eight terminals Q / D1 to Q / D8 become parallel inputs, and when the CLR / LOAD terminal is low, the input data of terminals Q / D1 to Q / D8 is stored in each register asynchronously with the CK terminal input.

[0233] In this example, when a 5V DC voltage (DC5VB) is applied to the P / S CONT terminal of the P / S conversion circuits 505 and 506, the P / S CONT terminal is set to H, and the eight terminals Q / D1 to Q / D8 are set to parallel input. 15 are buffered by a buffer circuit 513 and then input to P / S conversion circuits 505 and 506. That is, the clock signal S_IN_CLK is input to the CK terminal, and the load signal S_IN_LOAD is input to the CLR / LOAD terminal.

[0234] At the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 505, sense signal SENS8 is input to the Q / D1 terminal, sense signal SENS9 to the Q / D2 terminal, sense signal SENS11 to the Q / D4 terminal, and sense signal SENS14 to the Q / D7 terminal. The Q / D3, Q / D5, Q / D6, and Q / D8 terminals are connected to ground, meaning that each input is "0" (L level). Sense signals SENS8, SENS9, and SENS11 are detection signals of a switch sensor that detects button operation and a sensor that detects the rotational position and origin position of a movable body inside the button, which are input to connector CN10C in Figure 20 from the downstream button LED connection board 640. The sense signal SENS14 is a detection signal of the touch sensor input from the connector CN9C in FIG.

[0235] The P / S conversion circuit 505 converts the input serial data signal S_IN_DATAx and sense signals SENS8, SENS9, SENS11, and SENS14 into serial data and outputs it from the Q8C terminal as the serial data signal SDT1. This serial data signal SDT1 is input to the SI terminal of the P / S conversion circuit 506.

[0236] At the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 506, sense signal SENS0 is input to the Q / D1 terminal, sense signal SENS1 to the Q / D2 terminal, sense signal SENS2 to the Q / D3 terminal, sense signal SENS3 to the Q / D4 terminal, sense signal SENS4 to the Q / D5 terminal, sense signal SENS5 to the Q / D6 terminal, sense signal SENS6 to the Q / D7 terminal, and sense signal SENS7 to the Q / D8 terminal. These sense signals SENS0 to SENS7 are detection signals of the cross key 15a and the like, which are input to the connector CN7C in FIG. The sense signals SENS0 to SENS7 from the connector CN7C are compensated by the buffer circuit 507 and then input to the above-mentioned terminals of the P / S conversion circuit 506.

[0237] As described above, the P / S conversion circuit 506 converts the serial data signal SDT1 from the P / S conversion circuit 505 and the sense signals SENS0 to SENS7, which are input to the SI terminal, into serial data and outputs it from the Q8 terminal as the serial data signal SDT2. This serial data signal SDT2 is input to the buffer circuit 513 via a filter made up of resistor R35C and capacitor C27C, and is buffered. This output is transmitted upstream from the connector CN2C in FIG. 15 as the serial data signal S_IN_DATA from the front frame LED connection board 500.

[0238] As described above, the front frame LED connection board 500 has the following configuration. Figure 21 summarizes the flow of the clock signals CLK_L, CLK_M, clear signals CLR_L, CLR_M (reset signals RESET_L, RESET_M), data signals DATA_L, DATA_M, general-purpose signal HANYOU, and enable signal ENABLE_M supplied from the upstream inner frame LED relay board 400 to the connector CN2C.

[0239] The clock signal CLK_L, the clear signal CLR_L (reset signal RESET_L), the data signal DATA_L, and the general-purpose signal HANYOU are transmitted downstream via buffer circuits 501 and 502 by connector CN3C as the clock signal CLK_P, the reset signal RESET_P, the data signal DATA_P, and the enable signal ENABLE_L. The clock signal CLK_L, the clear signal CLR_L (reset signal RESET_L), and the data signal DATA_L are transmitted downstream via a buffer circuit 504 by a connector CN1C as the clock signal CLK, the reset signal RESET, and the data signal DATA. The clock signal CLK_L, the clear signal CLR_L (reset signal RESET_L), and the data signal DATA_L are transmitted downstream as the clock signal CLK_L, the clear signal CLR_L, and the data signal DATA_L by the connector CN10C via a buffer circuit 512. The clock signal CLK_L, the data signal DATA_L, and the general-purpose signal HANYOU are supplied to an S / P conversion circuit 509 and used to generate a motor drive current.

[0240] The clock signal CLK_M, the clear signal CLR_M (reset signal RESET_M), the data signal DATA_M, and the enable signal ENABLE_M are transmitted downstream via buffer circuits 501 and 503 by the connector CN3C as the clock signal CLK_M, the reset signal RESET_M, the data signal DATA_M, and the enable signal ENABLE_M.

[0241] Motor drive signals MOTφ1, MOTφ / 1, MOTφ2, MOTφ / 2, and DCMOT3 are generated by an S / P conversion circuit 509, a buffer circuit 508, and motor drivers 510 and 511, which constitute the motor drive means, and are transmitted downstream from a connector CN10C.

[0242] FIG. 22 also shows a summary of the flows of the serial data signal S_IN_DATA, the clock signal S_IN_CLK, the load signal S_IN_LOAD, and the sense signals SENS0 to SENS7, SENS8, SENS9, SENS11, and SENS14.

[0243] The clock signal S_IN_CLK and the load signal S_IN_LOAD are transmitted downstream from the connector CN3C via a buffer circuit 502. The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to the P / S conversion circuits 505 and 506 via a buffer circuit 513 and are used for parallel / serial conversion processing.

[0244] The serial data signal S_IN_DATAx input from the downstream side to the connector CN3C is input to the P / S conversion circuit 505 via the buffer circuit 502, where it is combined with the sense signals SENS8, SENS9, SENS11, and SENS14 to form serial data, which is then input to the P / S conversion circuit 506 as the serial data signal SDT1. The sense signals SENS0 to SENS7 input from the downstream side to the connector CN7C are input to the P / S conversion circuit 506 via the buffer circuit 507. The P / S conversion circuit 506 combines the serial data signal SDT1 from the P / S conversion circuit 505 with the sense signals SENS0 to SENS7 to form serial data, which is then output as the serial data signal SDT2. This serial data signal SDT2 is transmitted upstream from the connector CN2C via the buffer circuit 513 as the serial data signal S_IN_DATA from the front frame LED connection board 500.

[0245] The front frame LED connection board 500 further has the following configuration. ·Relays the audio signal to the speaker and sends it to the speaker unit. Connector CN2C receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) as operating power. The 12V motor drive voltage (MOT12V) and 12V DC voltage (DC12VS) used to generate motor drive signals are separated from the 12V DC voltage (DC12VB). By separating the power supplies according to their use - 12V DC voltage (DC12VB) for the LED and LED driver, 12V motor drive voltage (MOT12V) for motor drive, and 12V DC voltage (DC12VS) for the motor driver - the adverse effects of noise are prevented. · 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are supplied to the downstream side as operating power supply voltage.

[0246] In addition to those mentioned above, as shown in Figures 15 to 20, electronic elements such as resistors R1C, R2C..., resistors such as chip resistors RA1C, RA2C..., capacitors C1C, C2C..., diodes (including Zener diodes and Schottky barrier diodes) D1C, D2C..., etc. are connected to the front frame LED connection board 500 at required locations. Resistors R8C, R10C, R12C, R13C, R14C, R16C, R17C, and R18C are inserted on the connector CN2C side in Figure 15 as damping resistors for signal lines such as the clear signals CLR_L and CLR_M, clock signals CLK_L and CLK_M, data signals DATA_L and DATA_M, general-purpose output port signal (general-purpose signal HANYOU), and enable signal ENABLE_M, and chip resistors RA1C and RA2C are also inserted. In other words, the waveform is shaped by inserting damping resistors near connector CN2C and before the signal branch. As shown in the figure, taps TP1C to TP14C are provided and used for connection to required locations. Although not shown, capacitors are appropriately placed between the DC 5V or DC 12V power supply line and the ground to reduce power supply noise, etc.

[0247] [5.4 Relay board 550] 23 shows the configuration of the relay board 550. The relay board 550 has connectors CN1D and CN2D mounted thereon.

[0248] The connector CN1D is connected to the end of a transmission line H9 that connects with the connector CN3C of the front frame LED connection board 500 in FIG. Therefore, this connector CN1D has 22 terminals, numbered "1" to "22," with pins 1 to 22, and the terminal assignments are the same as those of the above-mentioned connector CN3C. Conductor points P1 and P2 on the housing of connector CN1D are also connected to ground for mounting strength.

[0249] The connector CN2D is connected to the end of a transmission line H10 that connects the upper right LED board 600 of the downstream side unit. This connector CN2D has 20 terminals, numbered from pin 1 to pin 20, as indicated by the numbers "1" to "20."

[0250] The four pins, pins 3, 9, 11, and 16, are ground terminals. The first pin is the terminal for 5V DC voltage (DC5VB). The two pins, pins 5 and 7, are terminals for 12V DC voltage (DC12VB).

[0251] The second pin is assigned as the serial data signal S_IN_DATAx, the fourth pin as the load signal S_IN_LOAD, and the sixth pin as the clock signal S_IN_CLK.

[0252] The 8th pin is assigned as the enable signal ENABLE_L, the 10th pin is the clock signal CLK_P, the 12th pin is the reset signal RESET_P, the 13th pin is the clock signal CLK_M, the 14th pin is the data signal DATA_P, the 15th pin is the reset signal RESET_M, the 17th pin is the data signal DATA_M, the 18th pin is the general-purpose drive signal 1, the 19th pin is the enable signal ENABLE_M, and the 20th pin is the general-purpose drive signal 2.

[0253] In this relay board 550, the 12V DC voltage (DC12VB) assigned to the three terminals, pins 5, 7, and 9, of connector CN1D is aggregated to the two terminals, pins 5 and 7, on the connector CN2D side and transferred downstream. Additionally, connector CN1D has five ground terminals: pins 1, 3, 11, 13, and 18, while connector CN2D has four ground terminals: pins 3, 9, 11, and 16. This reduces the number of terminals on the downstream connector CN2D. Additionally, connectors CN1D and CN2D are different types of connectors. Connector CN2D has a higher rated current per pin, which allows the number of power supply terminals and ground terminals on connector CN2D to be reduced. In addition, the CN2D connector is easier to insert and remove than the CN1D connector, and has thicker terminals and a larger housing.

[0254] [5.5 Side unit upper right LED board 600] The side unit upper right LED board 600 will be described with reference to Figures 24, 25, 26, 27, 28, and 29. These figures show the circuit configurations provided on the side unit upper right LED board 600 separately.

[0255] The side unit upper right LED board 600 is equipped with connectors such as connector CN1E in FIG. 24, connector CN7E in FIG. 25, connectors CN2E and CN3E in FIG. 26, and connectors CN4E, CN5E and CN6E in FIG.

[0256] The connector CN1E in FIG. 24 is connected to the transmission line end of the transmission line H10 that connects with the connector CN2D of the relay board 550 in FIG. Therefore, this connector CN1E has 20 terminals, from the first pin to the twentieth pin, as indicated by the numbers "1" to "20", and the terminal assignment is the same as that of the above-mentioned connector CN2D.

[0257] The connector CN7E in Fig. 25 is connected to a sensor in the side unit device 101 shown in Fig. 10, and a sense signal SENS2X is input to the third pin. This sensor 101S is, for example, a sensor that detects a player's operation of the side unit device 101. The sense signal SENS2X of the sensor 101S is pulled up by a 5V DC voltage (DC5V) via a resistor R64E. A 12V DC voltage (DC12VB) is applied to the first pin as a power supply voltage on the sensor 101S side of the side unit device 101. The second pin is used as a ground terminal.

[0258] The connector CN2E in FIG. 26 is a six-terminal connector to which the transmission line end of the transmission line H12 that connects to the LED board 630 on the downstream side unit is connected. The first to sixth pins of this connector CN2E are assigned as a ground terminal, a clock signal CLK terminal, a data signal DATA terminal, a reset signal RESET terminal, a ground terminal, and a 12V DC voltage (DC12VB) terminal.

[0259] The connector CN3E is connected to the end of a transmission line H11 that connects the connector CN3E to the lower right LED board 620 of the downstream side unit. This connector CN3E has 16 terminals, numbered from pin 1 to pin 16, as indicated by the numbers "1" to "16."

[0260] The first pin is the terminal for 5V DC voltage (DC5VB). Pins 8 and 13 are ground terminals. Pin 15 is the terminal for the 12V motor drive voltage (MOT12V). A Zener diode D11E is connected between pin 15 and ground as a protection circuit.

[0261] The second pin is assigned as the clock signal CLK, the third pin is assigned as the sense signal SENS1X, the fourth pin is assigned as the data signal DATA, the fifth pin is assigned as the sense signal SENS_A, the sixth pin is assigned as the reset signal RESET, the seventh pin is assigned as the sense signal SENS_B, and the ninth pin is assigned as the sense signal SENS_C. As shown in FIG. 25, the sense signal SENS1X is pulled up by a 5V DC voltage (DC5V) via a resistor R13E. The sense signals SENS_A, SENS_B, and SENS_C are also pulled up by a 5V DC voltage (DC5V) via resistors R29E, R27E, and R21E, respectively.

[0262] Furthermore, the connector CN3E in FIG. 26 has the 10th pin assigned as the motor drive signal MOT1- / 2, the 12th pin assigned as the motor drive signal MOT1- / 1, the 14th pin assigned as the motor drive signal MOT1-2, and the 16th pin assigned as the motor drive signal MOT1-1. Zener diodes D10E, D12E, D13E, and D14E are connected between pins 10, 12, 14, and 16 and ground, respectively, as protection circuits.

[0263] The connector CN4E in Fig. 28 is connected to the side unit upper right movable motor 104 (see Fig. 10). The first pin of this connector CN4E is a terminal for a 12V motor drive voltage (MOT12V), and the second pin is a terminal for a vibration control signal L_VIB.

[0264] The connector CN5E is connected to the side unit upper right movable solenoid 105 (see FIG. 10). The first pin of this connector CN5E is a terminal for a 12V motor drive voltage (MOT12V), and the second pin is a terminal for a solenoid control signal L_SOL_01.

[0265] The connector CN6E is connected to the blower 106 (see FIG. 10) on the side unit. The first pin of this connector CN6E is a terminal for a 12V motor drive voltage (MOT12V), and the second pin is a terminal for the blower control signal L_BRO.

[0266] The conductor points P1 and P2 on the housings of the connectors CN2E, CN3E, CN4E, CN5E, CN6E, and CN7E are connected to ground for mounting strength.

[0267] The power supply voltage for this side unit upper right LED board 600 will be described. The side unit upper right LED board 600 is equipped with the following ICs: a buffer circuit 601 shown in Fig. 25, a buffer circuit 604 shown in Fig. 26, and a buffer circuit 607 shown in Fig. 28. These are eight-circuit Schmitt trigger buffers similar to the buffer circuit 402 previously described in Fig. 13. A 5V DC voltage (DC5V) is used as the power supply voltage for these. The 5V DC voltage (DC5V) is the voltage on the positive side of capacitor C1E via fuse F1E, for the 5V DC voltage (DC5VB) supplied from the first pin of connector CN1E in Figure 24.

[0268] 25 are mounted as ICs, and the power supply voltage for these is also 5V DC (DC5V). The P / S conversion circuits 602 and 603 are ICs similar to the P / S conversion circuit 505 in FIG.

[0269] Furthermore, an LED driver 605 shown in FIG. 27 and an S / P conversion circuit (LED driver) 606 shown in FIG. 28 are mounted as ICs, and the power supply voltage for these is a 12V DC voltage (DC12VB) supplied from the 5th and 7th pins of the connector CN1E. In this case, the 12V DC voltage (DC12VB) is taken out as a voltage on the positive side of the capacitor C2E via the fuse F2E from the fifth and seventh pins of the connector CN1E in FIG.

[0270] Furthermore, motor drivers 608 and 609 shown in FIG. 28 are mounted as ICs, and these use a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) as power supply voltages.

[0271] The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB). As shown in Fig. 29, the anode side of a Schottky barrier diode D8E is connected to the line of a 12V DC voltage (DC12VB). A resistor R23E, capacitors C10E and C11E, and a chip varistor 611 are connected in parallel between the cathode side of the Schottky barrier diode D8E and ground. With this configuration, the 12V motor drive voltage (MOT12V) is isolated as a power supply voltage with overvoltage protection. As shown in the figure, the 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a circuit consisting of a diode D7E, a resistor R17E, and a capacitor C8E.

[0272] The flow of various signals in the side unit upper right LED board 600 will be described below. The load signal S_IN_LOAD, clock signal S_IN_CLK, enable signal ENABLE_L (reset signal RESET_M), clock signal CLK_P, reset signal RESET_P, and data signal DATA_P are input to connector CN1E in Figure 24 from relay board 550, and these signals are supplied to buffer circuit 601 in Figure 25 via damping resistors R66E, R9E, R11E, and R12E, where they are compensated. In addition, the signal paths of these signals are provided with protection circuits, as shown in Figure 24, consisting of resistor R3E and Zener diode D2E, resistor R6E and Zener diode D3E, resistor R66E and Zener diode D15E, resistor R9E and Zener diode D6E, resistor R11E and Zener diode D5E, and resistor R12E and Zener diode D15E.

[0273] The clock signal CLK_P, data signal DATA_P, and reset signal RESET_P are compensated by buffer circuit 601, and then output as clock signal CLK_A, data signal DATA_A, and reset signal RESET_A, and input to buffer circuit 604 in Fig. 26. In this case, the clock signal CLK_A is input to terminals A1 and A5, the data signal DATA_A to terminals A2 and A6, and the reset signal RESET_A to terminals A3 and A7. The signals that have been buffered and output from the Y1, Y2, and Y3 terminals are then output as a clock signal CLK, a data signal DATA, and a reset signal RESET from the connector CN2E via damping resistors R18E, R19E, and R20E. Furthermore, the signals that have been buffered and output from the Y5, Y6, and Y7 terminals are output from the connector CN3E as a clock signal CLK, a data signal DATA, and a reset signal RESET via damping resistors R24E, R25E, and R26E.

[0274] 26 are each branched into two systems before being input to the buffer circuit 604, and are buffered separately. These are then output from connectors CN2E and CN3E to separate boards as the clock signal CLK, the data signal DATA, and the reset signal RESET, respectively. Therefore, the buffer circuit 604 performs buffering while branching into two systems, enabling appropriate buffering after each branch. Furthermore, the clock signal CLK, data signal DATA, and reset signal RESET output from connectors CN2E and CN3E in this way are originally the clock signal CLK_P, data signal DATA_P, and reset signal RESET_P input from connector CN1E in Fig. 24. As described above, these are buffered by buffer circuit 601 in Fig. 25, output as clock signal CLK_A, data signal DATA_A, and reset signal RESET_A, and then branched into two systems at buffer circuit 604 in Fig. 26. In other words, by buffering the signals before branching, attenuation in the transmission path up to that point is compensated for before branching. This ensures a stable signal supply when distributing a common signal to two boards.

[0275] The clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_A output from the buffer circuit 601 in FIG. 25 are also supplied to the LED driver 605 in FIG. The LED driver 605 outputs a light emission drive current according to the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_A. The LED driver 605 has output terminals LEDR1, LEDG1, LEDB1... LEDR8, LEDG8, LEDB8 for light emission drive current and can output drive current for 24 systems, but in this case, 14 terminals are used: output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, LEDG5. As shown in the figure, the other output terminals are connected to ground.

[0276] The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, and LEDG5 are connected to the 14 LED circuits formed as the light-emitting unit 612, respectively, and pass light-emitting drive currents (25-R1, 25-G1, 25-B1, 25-R5, 25-G5, and 25-B5). As shown in the figure, each LED circuit in the light-emitting unit 612 is composed of two or three LEDs (LED1, LED2, etc.) connected in series and a resistor. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0277] In this configuration, the clock signal CLK_P, data signal DATA_P, and reset signal RESET_P input from connector CN1E in Fig. 24 are buffered by buffer circuit 601 in Fig. 25 and then branched. The buffered clock signal CLK_A, data signal DATA_A, and reset signal RESET_A are supplied as one branch to LED driver 605 in Fig. 27. The other branch is supplied to buffer circuit 604 in Fig. 26, where it is further branched and buffered before being transmitted to downstream boards from connectors CN2E and CN3E. In this case, the signal for controlling light emission drive is buffered by the buffer circuit 601 and then branched for transmission to the LED driver and downstream board, thereby ensuring stable transmission and making the buffer circuit configuration more efficient.

[0278] 28. The clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_M output from the buffer circuit 601 in FIG. 25 are supplied to the S / P conversion circuit 606 in FIG. This S / P conversion circuit 606 is configured using a chip that serves as an LED driver. The LED driver is a device that outputs a light-emitting drive current according to a clock signal CLK_L and a data signal DATA_L, but in this case, it is used primarily for serial / parallel conversion to drive the motor. In other words, the LED driver chip is used as part of the motor drive means.

[0279] The S / P conversion circuit 606, which is composed of an LED driver chip, is a device that outputs a light-emitting drive current according to a clock signal CLK_A, a data signal DATA_A, and a reset signal RESET_M, and in this case, it functions primarily as a serial / parallel conversion circuit for driving a motor. The S / P conversion circuit 606 has output terminals LEDR1, LEDG1, LEDB1... LEDR8, LEDG8, and LEDB8 for the light-emitting drive current, and can output drive currents in 24 systems, but in this case, it uses seven terminals: LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3. As shown in the figure, the other output terminals are connected to ground. The outputs (currents 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, 30-G3) from output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are buffered by a buffer circuit 607 and then supplied to input terminals IN2, IN3, and IN4 of a motor driver 608 and input terminals IN1, IN2, IN3, and IN4 of a motor driver 609.

[0280] The output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are connected to a 5V DC voltage (DC5V) via resistors R60E, R61E, R62E, R56E, R57E, R58E, and R59E. This is to use the 5V DC voltage (DC5V) as a power source to flow currents 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, and 30-G3.

[0281] The motor driver 608 outputs a blower control signal L_BRO, a solenoid control signal L_SOL01, and a vibration control signal L_VIB from output terminals OUT2, OUT3, and OUT4 based on signals from input terminals IN2, IN3, and IN4. These blower control signal L_BRO, solenoid control signal L_SOL01, and vibration control signal L_VIB are supplied to connectors CN6E, CN5E, and CN4E, respectively.

[0282] The motor driver 609 outputs motor drive signals MOT1-1, MOT1-2, MOT1- / 1, and MOT1- / 2 from output terminals OUT1, OUT2, OUT3, and OUT4 based on signals from input terminals IN1, IN2, IN3, and IN4. These motor drive signals MOT1-1, MOT1-2, MOT1- / 1, and MOT1- / 2 are supplied to connector CN3E in FIG. Therefore, the circuit from the LED driver 605 to the motor driver 609 forms a circuit system within the side unit upper right LED board 600 that generates a motor drive signal for the side unit lower right LED board 620 on the downstream side.

[0283] The load signal S_IN_LOAD and clock signal S_IN_CLK input from connector CN1E in FIG. 24 are compensated by buffer circuit 601 in FIG. 25 via damping resistors R3E and R6E, and then input to the CLR / LOAD terminal and CK terminal of P / S conversion circuits 602 and 603, respectively, to control the parallel / serial conversion process. In the P / S conversion circuits 602 and 603, when a 5V DC voltage (DC5V) is applied to the P / S CONT terminal, the P / S CONT terminal is set to H, and the eight terminals Q / D1 to Q / D8 are set as parallel inputs.

[0284] At the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 603, sense signal SENS_C is input to the Q / D1 terminal, sense signal SENS_B to the Q / D2 terminal, sense signal SENS_A to the Q / D4 terminal, sense signal SENS1X to the Q / D4 terminal, and sense signal SENS2X to the Q / D5 terminal. The Q / D6, Q / D7, and Q / D8 terminals are connected to ground. The sense signals SENS_A, SENS_B, SENS_C, and SENS1X are input from a connector CN3E, and the sense signal SENS2X is input from a connector CN7E.

[0285] The P / S conversion circuit 603 converts the input sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X into serial data (serial data signal SDT3) and outputs it from the Q8C terminal. This serial data signal SDT3 is input to the SI terminal of the P / S conversion circuit 602.

[0286] Of the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 602, a 5V DC voltage (DC5V) is applied to the Q / D1 terminal, Q / D2 terminal, and Q / D8 terminal, and the others are connected to ground. The P / S conversion circuit 602 converts the serial data signal SDT3 from the P / S conversion circuit 603 input to the SI terminal and the logic (H / L) of the Q / D1 to Q / D8 terminals together into serial data (serial data signal SDT4) and outputs it from the Q8 terminal. This serial data signal SDT4 is input to the buffer circuit 601 and buffered. This output is transmitted upstream from the connector CN1E via the damping resistor R1E in FIG. 24 as the serial data signal S_IN_DATAx from the upper right LED board 600 of the side unit.

[0287] As described above, the side unit upper right LED board 600 has the following configuration. An enable signal ENABLE_L (reset signal RESET_M), a clock signal CLK_P, a reset signal RESET_P, and a data signal DATA_P are input and buffered by a buffer circuit 601. The buffered signals are then used to light an LED, generate a motor drive signal, or are transferred downstream.

[0288] The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to P / S conversion circuits 602 and 603 via a buffer circuit 601 and are used for parallel / serial conversion processing. The various sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X are all converted into serial data to generate the serial data signal S_IN_DATAx. This serial data signal S_IN_DATAx is then transmitted upstream. As mentioned above, this serial data signal S_IN_DATAx is further converted into serial data together with the sense signals SENS8, SENS9, SENS11, and SENS1 on the front frame LED connection board 500, and is then transmitted as the serial data signal S_IN_DATA to the performance control board 30 via the inner frame LED relay board 400.

[0289] Connector CN1E receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) as operating power. The 12V motor drive voltage (MOT12V) and 12V DC voltage (DC12VS) used to generate motor drive signals are separated from the 12V DC voltage (DC12VB). · 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are supplied to the downstream side as operating power supply voltages.

[0290] In addition to those mentioned above, as shown in FIGS. 24 to 29, electronic elements such as resistors R1E, ​​R2E, etc., capacitors C1E, C2E, etc., diodes (including Zener diodes) D1E, D2E, etc. are connected to required locations on the side unit upper right LED board 600. As shown in the figure, taps TP1E, TP2E, etc. are provided and used for connecting to required locations. Although not shown, a capacitor is appropriately placed between the DC 5V or DC 12V power supply line and the ground to reduce power supply noise, etc.

[0291] [5.6 Side unit bottom right LED board 620] The side unit lower right LED board 620 will be described with reference to Figures 30 and 31. These figures show the circuit configuration provided on the side unit lower right LED board 620 separately.

[0292] The side unit lower right LED board 620 is equipped with connectors such as connectors CN1F, CN3F, and CN4F in FIG. 30 and connector CN2F in FIG.

[0293] The connector CN3F in FIG. 30 is connected to the transmission line end of the transmission line H11 that connects the connector CN3F to the connector CN3E of the upper right LED board 600 of the side unit in FIG. Therefore, this connector CN3F has 16 terminals, from the 1st pin to the 16th pin, as indicated by the numbers "1" to "16", and the terminal assignment is the same as that of the above-mentioned connector CN3E.

[0294] The connector CN1F is connected to the side unit lower right movable motor 103 shown in FIG. A 12V motor drive voltage (MOT12V) is applied to pins 3 and 4. The motor drive signals MOT1- / 2, MOT1- / 1, MOT1-2, and MOT1-1 input from connector CN3F are output from pins 1, 2, 5, and 6.

[0295] The connector CN4F is connected to the side unit lower right movable object position detection switch 102 shown in FIG. Pin 1 is the 12V DC voltage (DC12VB) terminal, Pin 2 is the ground terminal, and Pin 3 is the input terminal for the sense signal SENS1X from the connected position detection switch.

[0296] The connector CN2F in Fig. 31 is connected to an LED board (not shown) arranged in the side unit 10. The first pin is a terminal for 12V DC voltage (DC12VB). The second to fifth pins are terminals for light emission drive signals.

[0297] The conductor points P1 and P2 on the housings of the connectors CN1F, CN2F, CN3F, and CN4F are connected to ground for mounting strength.

[0298] The power supply voltage for this side unit lower right LED board 620 will be described. Photocouplers PC1F, PC2F, and PC3F are mounted on the lower right LED board 620 of the side unit. The power supply voltage for these devices is a 5V DC voltage (DC5V), which is supplied from the first pin of the connector CN3F.

[0299] The side unit lower right LED board 620 is equipped with an LED driver 621 shown in FIG. 31 as an IC, and the power supply voltage for this is a 12V DC voltage (DC12VB) supplied from the 11th pin of the connector CN1E. Also, the 12V motor drive voltage (MOT12V) output from the connector CN1F in FIG. 30 is supplied from the 15th pin of the connector CN3F.

[0300] The flow of various signals in the side unit lower right LED board 620 will be described. A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN3F from the side unit upper right LED board 600, and these signals are supplied to the LED driver 621 in FIG. The LED driver 621 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

[0301] The LED driver 621 has output terminals LEDR1, LEDG1, LEDB1... LEDR8, LEDG8, and LEDB8 for light emission drive current and can output drive current for 24 systems. In this case, 12 terminals, namely output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4, are used to drive LED light emission. In addition, four terminals, namely output terminals LEDR7, LEDG7, LEDB7, and LEDR8, are used to drive LED light emission on an LED board (not shown) connected to connector CN2F. As shown, the other output terminals are connected to ground.

[0302] The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 ​​are connected to the 12 LED circuits formed as the light-emitting unit 622, respectively, and pass light-emitting drive currents (27-R1, 27-G1, 27-B1, 27-R4, 27-G4, and 27-B4). As shown in the figure, each LED circuit in the light-emitting unit 622 is composed of one or three LEDs connected in series and a resistor. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each. The output terminals LEDR7, LEDG7, LEDB7, and LEDR8 are connected to four systems of the light emission drive unit 623. The light emission drive unit 623 outputs four systems of light emission drive currents (27-R7, 27-G7, 27-B7, . . . 27-R8) from the connector CN2F.

[0303] Sense signals SENS_A, SENS_B, and SENS_C are obtained by photocouplers PC1F, PC2F, and PC3F in Fig. 30. These are sent to the upper right LED board 600 of the side unit from a connector CN3F. Furthermore, the sense signal SENS1X obtained from the connector CN4F is also sent from the connector CN3F to the upper right LED board 600 of the side unit. These sense signals SENS_A, SENS_B, SENS_C, and SENS1X are converted into serial data as described above.

[0304] In addition to those mentioned above, electronic elements such as resistors R1F, R2F, etc., capacitors C1F, C2F, etc. are connected to required locations on the side unit lower right LED board 620, as shown in FIGS. 30 and 31. As shown in the figure, taps TP1F, TP2F, etc. are provided and used for connecting to required locations.

[0305] [5.7 Side unit LED board 630] The LED substrate 630 on the side unit will be described with reference to FIG. The LED board 630 on the side unit is equipped with a connector CN1T. The connector CN1T is connected to the end of a transmission line H12 that connects the connector CN1T to the connector CN2E of the upper right LED board 600 of the side unit in FIG.

[0306] Therefore, this connector CN1T has six terminals, from the first pin to the sixth pin, as indicated by the numbers "1" to "6", and the terminal assignment is the same as that of the above-mentioned connector CN2E. The conductor points P1 and P2 on the housing of the connector CN1T are connected to the ground for mounting strength.

[0307] An LED driver 631 is mounted as an IC on this side unit LED board 630, and as the power supply voltage for this, a 12V DC voltage (DC12VB) supplied from the sixth pin of the connector CN1T is used.

[0308] The flow of various signals will be explained below. A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN1T from the side unit upper right LED board 600, and these signals are supplied to an LED driver 631. The LED driver 631 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

[0309] The LED driver 631 has output terminals LEDR1, LEDG1, LEDB1... LEDR8, LEDG8, LEDB8 for light emission drive current and can output drive current for 24 systems, but in this case, LED light emission drive is performed using nine terminals: LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3. As shown in the figure, the other output terminals are connected to ground.

[0310] The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3 are connected to the nine LED circuits formed as the light-emitting unit 632, respectively, and pass light-emitting drive currents (27-R1, 27-G1, 27-B1, 27-R3, 27-G3, and 27-B3). As shown in the figure, each LED circuit in the light-emitting unit 632 is composed of two LEDs connected in series and a resistor. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0311] In addition to the above, electronic elements such as resistors R1T, R2T, etc., capacitors C1T, C2T, etc. are connected to required locations on the side unit LED board 630, as shown in FIG. As shown in the figure, taps TP1T, TP2T, etc. are provided and used for connecting to required locations.

[0312] [5.8 Button LED connection board 640] The button LED connection board 640 will be described with reference to FIG. The button LED connection board 640 is equipped with connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G.

[0313] The connector CN1G is connected to the end of a transmission line H15 that connects with the connector CN10C of the front frame LED connection board 500 in FIG. Therefore, this connector CN1E has 20 terminals, from the first pin to the twentieth pin, as indicated by the numbers "1" to "20", and the terminal assignment is the same as that of the above-mentioned connector CN10C.

[0314] The connector CN2G is connected to the end of the transmission line H16 that connects to the button LED board 660 shown in FIG. A 12V DC voltage (DC12VB) is applied to the third and seventh pins, which serves as the power supply voltage for the button LED board 660. The first and sixth pins are used as ground terminals. The second, fourth, and fifth pins are terminals for the clock signal CLK, the data signal DATA, and the reset signal RESET, respectively.

[0315] The connector CN3G is connected to a motor (not shown). The motor drive signals MOTφ1, MOTφ / 1, MOTφ2, and MOTφ / 2 input from the connector CN1G are output from the sixth, second, fifth, and first pins of the connector CN3G. Also, a 12V motor drive voltage (MOT12V) input from connector CN1G is applied to the third and fourth pins as the illustrated 12V motor drive voltage (MOT12VA).

[0316] The connector CN4G is connected to a vibration device (not shown). A 12V motor drive voltage (MOT12VA) is applied to the first pin as the power supply voltage for the vibration device, and a motor drive signal DCMOT3 input from the connector CN1G is output to the second pin as the drive signal for the vibration device. A DC motor is used for the vibration device.

[0317] The connector CN5G is connected to the push button sensor in the effect button 13. Pin 1 is the 12V DC voltage (DC12VB) terminal, pin 2 is the ground terminal, and pin 3 is the input terminal for the sense signal SENS8 from the connected push button sensor.

[0318] The connector CN6G is connected to the rotation origin sensor. Pin 1 is the 12V DC voltage (DC12VB) terminal, and pin 3 is the ground terminal. Pin 2 is the input terminal for the sense signal SENS9 from the connected rotation origin sensor.

[0319] Connector CN8G is connected to the rotation effect light sensor. Pin 1 is the 12V DC voltage (DC12VB) terminal, pin 3 is the ground terminal, and pin 2 is the input terminal for the sense signal SENS11 from the connected rotation effect light sensor.

[0320] The conductor points P1 and P2 on the housing of each of the connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G are connected to ground for mounting strength.

[0321] A buffer circuit 641 is mounted on this button LED connection board 640. A 5V direct current voltage (DC5V) is used as the power supply voltage for this. The 5V direct current voltage (DC5V) is supplied from the 8th pin of the connector CN1G.

[0322] The flow of various signals in the button LED connection board 640 will be described. The clock signal CLK_L, clear signal CLR_L, and data signal DATA_L supplied from the upstream front frame LED connection board 500 to the connector CN1G are input to the buffer circuit 641 via chip resistor RA1G and buffered. They are then sent to the connector CN2G via chip resistor RA2G and transmitted to the downstream button LED board 660. A capacitor C1G is inserted between the 5V DC voltage (DC5V) of the buffer circuit 641 and the ground.

[0323] Although not shown, in the button LED connection board 640, a capacitor is appropriately placed between the DC 5V or DC 12V power supply line and the ground to reduce power supply noise, etc.

[0324] [5.9 Button LED Board 660] The button LED board 660 will be described with reference to Figures 34 and 35. These figures show the circuit configuration provided on the button LED board 660 separately.

[0325] The button LED board 660 is equipped with the connector CN1H shown in FIG. The connector CN1H is connected to the end of a transmission line H16 that connects to the connector CN2G of the button LED connection board 640 in FIG. Therefore, this connector CN1H has seven terminals, from the first pin to the seventh pin, as indicated by the numbers "1" to "7", and the terminal assignment is the same as that of the above-mentioned connector CN2G. In addition, the conductor points P1 and P2 on the housing of the connector CN1H are connected to ground for mounting strength.

[0326] This button LED board 660 is supplied with a 12V DC voltage (DC12VB) as a power supply voltage input to a connector CN1H. The button LED board 660 is equipped with an LED driver 661 of FIG. 34 and an LED driver 663 of FIG. 35 as ICs, and a 12V DC voltage (DC12VB) is used as the power supply voltage for these. The power supply voltage for the light emitting units 664 and 662 is also 12V DC voltage (DC12VB).

[0327] The flow of various signals in the button LED board 660 will be described. A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN1H from the side unit upper right LED board 600, and these signals are supplied to the LED driver 661 via the chip resistor RA1H in FIG. The LED driver 661 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

[0328] The LED driver 661 drives 24 systems of LEDs for light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR8, LEDG8, and LEDB8 for light emission drive current. That is, the output terminals LEDR1, LEDG1, LEDB1...LEDR8, LEDG8, LEDB8 are connected to the 24 LED circuits formed as the light-emitting unit 662, respectively, and light-emitting drive currents (19-R1, 19-G1, 19-B1...19-R8, 19-G8, 19-B8) flow through them. As shown in the figure, each LED circuit in the light-emitting unit 662 is composed of two or three LEDs connected in series and a resistor. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0329] The clock signal CLK, the data signal DATA, and the reset signal RESET are also supplied to the LED driver 663 in FIG. The LED driver 663 drives six systems of LED light emission using three terminals each of the light emission drive current output terminals LEDR1, LEDG1, LEDB1, . . . LEDR6, LEDG6, and LEDB6. That is, the output terminals LEDR1, LEDG1, LEDB1...LEDR6, LEDG6, LEDB6 are connected to six LED circuits formed as the light-emitting unit 664, respectively, and light-emitting drive currents (20-R1, 20-G1, 20-B1...20-R6, 20-G6, 20-B6) flow through them. As shown in the figure, each LED circuit in the light-emitting unit 664 is composed of two or three LEDs connected in series and a resistor. A Zener diode is connected in parallel to each LED. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0330] In addition to the components mentioned above, as shown in Figures 34 and 35, electronic elements such as resistors R1H, R2H..., capacitors C1H, C2H..., diodes (including Zener diodes) D1H, D2H... are connected to the required locations on the side unit lower right LED board 620. As shown in the figure, taps TP1H, TP2H, etc. are provided and used for connecting to required locations.

[0331] [5.10 LED connection board 700] Next, the board placed on the gaming board 3 side will be explained. First, the LED connection board 700 will be described with reference to Figures 36, 37, 38, 39, 40, and 41. These figures show the circuit configurations provided on the LED connection board 700 separately. As shown in FIG. 11, the LED connection board 700 is a board that is connected to the performance control board 30 on the game board 3.

[0332] The LED connection board 700 is equipped with the following connectors: connector CN1J in FIG. 36, connectors CN5J and CN6J in FIG. 37, connectors CN2J, CN3J, CN4J, and CN12J in FIG. 38, connector CN10J in FIG. 39, connectors CN7C and CN11J in FIG. 40, and connectors CN8J and CN9J in FIG. 41.

[0333] The connector CN1J in FIG. 36 is connected to the transmission line end of the transmission line H20 that connects to the performance control board 30 as shown in FIG. This connector CN1J has 40 terminals, numbered from pin 1 to pin 40, as indicated by the numbers "1" to "40".

[0334] Pins 1, 2, 8, 9, 10, 16, 18, 19, 20, 22, 29, 31, 32, 33, 34, 39, and 40 of connector CN1J are connected to ground. Pins 4 and 6 are terminals for 5V DC voltage (DC5VB). Pins 12, 14, 24, 26, 28, and 30 are terminals for 12V DC voltage (DC12VB). Pins 11, 17, 35, and 37 are unused.

[0335] The third pin is assigned as the clock signal P_S_IN_CLK, the fifth pin as the serial data signal P_S_IN_DATA, and the seventh pin as the load signal P_S_IN_LOAD. The serial data signal P_S_IN_DATA is serial data transmitted from the LED connection board 700 to the performance control board 30, and the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are signals supplied from the performance control board 30 for transmitting the serial data signal P_S_IN_DATA.

[0336] The 13th pin is assigned as a terminal for the clock signal P_S_OUT_CLK, and the 15th pin is assigned as a terminal for the serial data signal P_S_OUT_DATA. The serial data signal P_S_OUT_DATA is serial data transmitted from the performance control board 30 together with the clock signal P_S_OUT_CLK.

[0337] Pin 21 is assigned as the clear signal M_S_CLR (reset signal RESET_M), pin 23 is assigned as the clock signal M_S_OUT_CLK (clock signal CLK_M), pin 25 is assigned as the serial data signal M_S_OUT_DATA (serial data signal DATA_M), and pin 27 is assigned as the enable signal M_S_ENABLEP (latch signal LATCH_M). The serial data signal M_S_OUT_DATA is serial data transmitted from the performance control board 30 together with the clock signal M_S_OUT_CLK.

[0338] In addition, conductor points P1 and P2 on the housing of connector CN1J and connectors CN2J, CN3J, CN4J, CN5J, CN6J, CN7J, CN8J, CN9J, CN10J, CN11J, and CN12J described below are connected to ground for mounting strength.

[0339] The connector CN5J in Fig. 37 is connected to a motor of a movable object (not shown). A DC voltage of 18V (MOT18VA) is applied to the third and fourth pins as the power supply voltage for the motor. The first pin is assigned as the motor drive signal MOT6- / 2, the second pin as the motor drive signal MOT6- / 1, the fifth pin as the motor drive signal MOT6-2, and the sixth pin as the motor drive signal MOT6-1.

[0340] The connector CN6J in Fig. 37 is also connected to a motor for another movable object (not shown). A DC voltage of 18V (MOT18VA) is applied to the third and fourth pins as the power supply voltage for the motor. The first pin is assigned as the motor drive signal MOT7- / 2, the second pin is assigned as the motor drive signal MOT7- / 1, the fifth pin is assigned as the motor drive signal MOT7-2, and the sixth pin is assigned as the motor drive signal MOT7-1.

[0341] Connector CN2J in Figure 38 is connected to the position detection switch of the accessory. A 12V DC voltage (DC12VB) is applied to the first pin, which serves as the power supply voltage for the position detection switch. Pin 3 is used as the ground terminal. A sense signal SENSv0, which is a detection signal of the lower depth movable right position detection switch 121 (see FIG. 10), is input to the second pin of this connector CN2J. The sense signal SENSv0 is pulled up by a 5V DC voltage (DC5V) via a resistor R5J.

[0342] Connector CN4J is also connected to the position detection switch of the device, with the first pin being the terminal for 12V DC voltage (DC12VB) which serves as the power supply voltage for the position detection switch, and the third pin being the ground terminal. A sense signal SENSv1, which is a detection signal of the lower depth movable left position detection switch 125 (see FIG. 10), is input to the second pin of this connector CN4J. The sense signal SENSv1 is pulled up by a 5V DC voltage (DC5V) via a resistor R29J.

[0343] Connector CN12J is also connected to the position detection switch of the device, with the first pin being the terminal for 12V DC voltage (DC12VB) which serves as the power supply voltage for the position detection switch, and the third pin being the ground terminal. A sense signal SENSv9, which is a detection signal of the lower depth movable upper position detection switch 120 (see FIG. 10), is input to the second pin of this connector CN12J. The sense signal SENSv9 is pulled up by a 5V DC voltage (DC5V) via a resistor R31J.

[0344] The connector CN3J is connected to the power supply module board 904 in Figure 7. The first, second, and fourth pins are used as terminals for the 18V DC voltage Vout, the seventh, ninth, and tenth pins are used as terminals for the 35V DC voltage (DC35V), and the fifth, sixth, and eighth pins are used as terminals for the ground.

[0345] The connector CN10J in Fig. 39 is connected to a relay board (not shown). As the numbers "1" to "32" indicate, it has 32 terminals from the 1st pin to the 32nd pin. Pin 1 is the terminal to which 12V DC voltage (DC12VB) is applied via fuse F6J, pin 2 is the terminal to which 5V DC voltage (DC5V) is applied via fuse F9J, and pins 3, 4, and 5 are terminals to which 12V motor drive voltage (MOT12V) is applied. Pins 9, 13, 17, 21, 25, 27, 29, 30, 31, and 32 are connected to ground.

[0346] The 7th pin is assigned as the motor drive signal MOT1- / 2, the 8th pin is assigned as the motor drive signal MOT1- / 1, the 10th pin is assigned as the motor drive signal MOT1-2, and the 12th pin is assigned as the motor drive signal MOT1-1. The 14th pin is assigned as the motor drive signal MOT2- / 2, the 16th pin is assigned as the motor drive signal MOT2- / 1, the 18th pin is assigned as the motor drive signal MOT2-2, and the 20th pin is assigned as the motor drive signal MOT2-1. Pin 22 is assigned as the motor drive signal MOT3- / 2, pin 24 is assigned as the motor drive signal MOT3- / 1, pin 26 is assigned as the motor drive signal MOT3-2, and pin 28 is assigned as the motor drive signal MOT3-1.

[0347] Pin 7 is the terminal for the clock signal CLK_B, and pin 11 is the terminal for the data signal DATA_B. Pin 15 is the terminal for the sense signal SENSv2, pin 19 is the terminal for the sense signal SENSv3, and pin 23 is the terminal for the sense signal SENSv4. The sense signal SENSv2 is, for example, a detection signal of the upper movable object position detection switch 132 in FIG. 10, the sense signal SENSv3 is, for example, a detection signal of the upper movable object left position detection switch 130, and the sense signal SENSv4 is, for example, a detection signal of the left movable object position detection switch 134.

[0348] Connector CN7J in Figure 40 is connected to an LED board (not shown). Pin 1 is a terminal for 12V DC voltage (DC12VB). Pins 5 and 6 are terminals for 18V LED drive voltage (LED18V). Pins 4, 7, and 8 are connected to ground. The second pin is a terminal for the clock signal CLK_E, and the third pin is a terminal for the data signal DATA_E.

[0349] The connector CN11J is connected to the end of the transmission line H30 that connects to the under-panel relay board 800 shown in Fig. 11. As indicated by the numbers "1" to "16," it has a 16-terminal configuration from pin 1 to pin 16.

[0350] Pins 4 and 6 are terminals to which 12V DC voltage (DC12VB) is applied via fuse F10J, and pins 7 and 9 are terminals to which 12V motor drive voltage (MOT12V) is applied via fuse F11J. Pins 1, 15, and 16 are connected to ground.

[0351] The third pin is the terminal for the motor drive signal MOT4- / 2, the fifth pin is the terminal for the motor drive signal MOT4- / 1, the eleventh pin is the terminal for the motor drive signal MOT4-2, and the thirteenth pin is the terminal for the motor drive signal MOT4-1. The 14th pin is a terminal for a sense signal SENSv7, which is a detection signal from the lower front movable position detection switch 123 shown in FIG. The second pin, eighth pin, tenth pin, and twelfth pin are terminals for outputting light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 to the lower relay board 800 side.

[0352] The connector CN9J in Figure 41 is connected to an LED board (not shown). Pin 1 is a terminal for 12V DC voltage (DC12VB). Pin 10 is a terminal for 5V DC voltage (DC5V). Pins 4 and 9 are connected to ground. The second pin is a terminal for the clock signal CLK_D, and the third pin is a terminal for the data signal DATA_D.

[0353] Pins 8, 7, 6, and 5 are terminals for light-emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8. These light-emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are generated by an LED driver mounted on an LED board (not shown). A clock signal CLK_D and a data signal DATA_D from pins 2 and 3 of connector CN9J are supplied to an LED driver mounted on the LED board (not shown). Based on these signals, the LED driver generates light-emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8. These light-emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8 flow from connector CN11J (FIG. 40) through a lower-back relay board 800 to LEDs in a light-emitting section 821 (see FIG. 48) of a decorative board 820 (described later), causing the LEDs to emit light.

[0354] The 11th pin of the connector CN9J is a terminal for a sense signal SENSv8, which is, for example, a detection signal from the distribution position detection switch 122 in FIG.

[0355] The connector CN8J in Fig. 41 is connected to the transmission line end of the transmission line H21 that connects to the rear left relay board 720 shown in Fig. 11. As indicated by the numbers "1" to "24," it has a 24-terminal configuration from pin 1 to pin 24.

[0356] Pins 1 to 4 are terminals to which an 18V motor drive voltage (MOT18VB) is applied via fuse F12J, pins 5 and 9 are terminals to which a 12V DC voltage (DC12VB) is applied via fuse F7J, and pin 11 is a terminal to which a 5V DC voltage (DC5VB) is applied via fuse F8J. Pins 7, 13, 14, 19, and 20 are connected to ground.

[0357] The 15th pin is a terminal for the clock signal CLK_C, and the 17th pin is a terminal for the data signal DATA_C. Pins 6 and 8 are the terminals for the motor drive signal MOT5- / 2, pins 10 and 12 are the terminals for the motor drive signal MOT5- / 1, pins 16 and 18 are the terminals for the motor drive signal MOT5-2, and pins 22 and 24 are the terminals for the motor drive signal MOT5-1. In this case, the motor being driven is a high-torque motor and is driven by an 18V motor drive voltage (MOT18VB). Because of the high power consumption, the motor drive signals MOT5- / 2, MOT5- / 1, MOT5-2, and MOT5-1 each use two pins / lines. Pin 21 is a terminal for sense signal SENSv6, and pin 23 is a terminal for sense signal SENSv5. Sense signal SENSv6 is, for example, a detection signal from the lower-rear movable lower-left position detection switch 128 in FIG. 10, and sense signal SENSv5 is, for example, a detection signal from the lower-rear movable lower-right position detection switch 127.

[0358] The power supply voltage in this LED connection board 700 will be described. The LED connection board 700 is equipped with, as ICs, buffer circuits 703 and 704 in FIG. 36 which are Schmitt trigger buffers with eight circuits similar to the buffer circuit 402 previously described in FIG. 13, buffer circuit 705 in FIG. 39 which is a triple buffer gate, and buffer circuits 707 and 708 in FIG. 41. As the power supply voltage for these components, a 5V DC voltage (DC5V) based on a 5V DC voltage (DC5VB) from the connector CN1J is used, as shown in FIG.

[0359] Also mounted as ICs are P / S conversion circuits 701 and 702 shown in Figure 36, which are also powered by a 5V DC voltage (DC5V). The 5V DC voltage (DC5VB) is taken from the positive terminal of capacitor C4J via connector CN1J and fuse F1J. The P / S conversion circuits 701 and 702 are ICs similar to the P / S conversion circuit 505 shown in Figure 18.

[0360] The 12V DC voltage (DC12VB) output downstream from connectors CN2J, CN4J, CN7J, CN8J, CN10J, CN11J, and CN12J is taken from the positive terminal of capacitor C5J via connector CN1J and fuse F2J.

[0361] Furthermore, motor drivers 710 to 713 shown in FIG. 37 are mounted as ICs on the LED connection board 700, and a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) are used as power supply voltages for these. Furthermore, motor drivers 714, 715, and 716 are mounted, and the power supply voltages for these are an 18V motor drive voltage (MOT18VA) and a 12V DC voltage (DC12VS).

[0362] The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB) by the power supply separation / protection circuit 719. As shown in Fig. 36, the anode side of Schottky barrier diode D5J is connected to pins 12, 14, 24, 26, 28, and 30 of connector CN1J. Resistor R6J, capacitors C14J and C15J, and chip varistor 709 are connected in parallel between the cathode side of Schottky barrier diode D5J and ground. This configuration as power supply isolation / protection circuit 719 isolates the 12V motor drive voltage (MOT12V) as a power supply voltage with overvoltage protection.

[0363] The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using the circuit shown in FIG. 38, which is made up of a diode D1J, a resistor R1J, and a capacitor C3J.

[0364] The 18V motor drive voltage (MOT18VA), the 18V motor drive voltage (MOT18VB), and the 18V LED drive voltage (LED18V) are also separated from the 18V DC voltage Vout input from the connector CN3J as shown in FIG. The anode side of Schottky barrier diode D7J is connected via fuse F3J to pins 1, 2, and 4, to which the 18V DC voltage Vout is applied. Resistor R7J and capacitors C17J and C18J are connected in parallel between the cathode side of Schottky barrier diode D7J and ground. This configuration provides the 18V motor drive voltage (MOT18VA). Similarly, the anode of Schottky barrier diode D9J is connected via fuse F4J to pins 1, 2, and 4, to which 18V DC voltage Vout is applied. Resistor R8J and capacitors C20J and C21J are connected in parallel between the cathode of Schottky barrier diode D9J and ground. This configuration provides the 18V motor drive voltage (MOT18VB). Similarly, the anode of Schottky barrier diode D11J is connected via fuse F5J to pins 1, 2, and 4, to which 18V DC voltage Vout is applied. Resistor R9J and capacitors C23J and C24J are connected in parallel between the cathode of Schottky barrier diode D11J and ground. This configuration provides an 18V LED drive voltage (LED18V).

[0365] The flow of various signals in the LED connection board 700 will be described below. 36 receives a clock signal P_S_OUT_CLK and a serial data signal P_S_OUT_DATA from the performance control board 30. These signals are used for operation control downstream of the LED connection board 700.

[0366] The clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA are input to the A5 terminal and A7 terminal of the buffer circuit 703 as shown in FIG. 36 as the clock signal CLK_P and the serial data signal DATA_P, and are then compensated. The signals are then output from terminals Y5 and Y7 of buffer circuit 703, and input to buffer circuit 706 in Fig. 40 as shown by clock signal CLK_A and serial data signal DATA_A, and are then transmitted downstream from connector CN7J as shown by clock signal CLK_E and serial data signal DATA_E.

[0367] In addition, the clock signal CLK_A and serial data signal DATA_A output from the Y5 terminal and Y7 terminal of the buffer circuit 703 are also input to the buffer circuit 705 in Figure 39, where they are buffered, and then transmitted downstream from the connector CN10J as the clock signal CLK_B and serial data signal DATA_B. The clock signal CLK_A and serial data signal DATA_A are also input to the buffer circuit 707 in FIG. 41 and buffered, and then transmitted downstream from the connector CN9J as the clock signal CLK_D and serial data signal DATA_D. Furthermore, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 708 in FIG. 41 and buffered, and are then transmitted from the connector CN8J to the downstream rear left relay board 720 on the panel back as the clock signal CLK_C and the serial data signal DATA_C.

[0368] A clear signal M_S_CLR (reset signal RESET_M), a clock signal M_S_OUT_CLK (clock signal CLK_M), a serial data signal M_S_OUT_DATA (serial data signal DATA_M), and an enable signal M_S_ENABLEP (latch signal LATCH_M) are sent from the performance control board 30 to connector CN1J in Figure 36. These are used to control the motor drive. These signals are input to the A7, A1, A3, and A5 terminals of the buffer circuit 704 and compensated for, and then input to the motor drivers 710 to 716 in FIG. 37 via the chip resistor RA4J. That is, in each of the motor drivers 710 to 716, the reset signal RESET_M is input to the RESET terminal, the latch signal LATCH_M is input to the LATCH terminal, the clock signal CLK_M is input to the SCLK terminal, and the serial data signal DATA_M is input to the SDIN terminal.

[0369] Motor drivers 710 to 713 each generate a 12V motor drive signal in response to these inputs. That is, the motor driver 710 generates motor drive signals MOT1- / 2, MOT1- / 1, MOT1-2, and MOT1-1 to be output from the connector CN10J. The motor driver 711 generates motor drive signals MOT2- / 2, MOT2- / 1, MOT2-2, and MOT2-1 to be output from the connector CN10J. The motor driver 712 generates motor drive signals MOT3- / 1, MOT3-2, and MOT3-1 to be output from the connector CN10J. The motor driver 713 generates motor drive signals MOT4- / 2, MOT4- / 1, MOT4-2, and MOT4-1 to be output from the connector CN11J.

[0370] Similarly, motor drivers 714 to 716 generate 18V motor drive signals in response to inputs of a reset signal RESET_M, a latch signal LATCH_M, a clock signal CLK_M, and a serial data signal DATA_M. That is, the motor driver 714 generates motor drive signals MOT5- / 2, MOT5- / 1, MOT5-2, and MOT5-1 to be output from the connector CN8J. The motor driver 715 generates motor drive signals MOT6- / 2, MOT6- / 1, MOT6-2, and MOT6-1 to be output from the connector CN5J. The motor driver 716 generates motor drive signals MOT7- / 2, MOT7- / 1, MOT7-2, and MOT7-1 that are output from the connector CN6J.

[0371] A clock signal P_S_IN_CLK and a load signal P_S_IN_LOAD are transmitted from the performance control board 30 to the connector CN1J in FIG. The clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are input to the A3 and A2 terminals of the buffer circuit 703 and subjected to signal compensation. Then, the signals are input from the Y3 and Y2 terminals of the buffer circuit 703 to the CK and CLR / LOAD terminals of the P / S conversion circuits 701 and 702 via the chip resistor RA1J. A 5V DC voltage (DC5V) is applied to the P / S CONT terminal of the P / S conversion circuits 701 and 702, setting the P / S CONT terminal to H, and the eight terminals Q / D1 to Q / D8 are set to parallel inputs. The P / S conversion circuits 701 and 702 perform parallel-to-serial conversion in response to the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD.

[0372] A sense signal SENSv8 from the connector CN9J in Fig. 41 is input to the Q / D1 terminal of the P / S conversion circuit 701. As shown in Fig. 36, this sense signal SENSv8 is pulled up by a 5V DC voltage (DC5V) via a resistor R23J. 38. The Q / D2 terminal of the P / S conversion circuit 701 receives the sense signal SENSv9 from the connector CN12J in FIG. The inputs to terminals Q / D3 to Q / D7 are ground level "0" (L level), and terminal Q / D8 is 5V level "1" (H level). The P / S conversion circuit 702 converts the above parallel inputs into serial data (serial data signal SDT5) and outputs it from the Q8C terminal. This serial data signal SDT5 is input to the SI terminal of the P / S conversion circuit 702.

[0373] Sense signals SENSv0 to SENSv7 are input to eight terminals, Q / D1 terminal to Q / D8 terminal, of the P / S conversion circuit 702. The sense signal SENSv0 is input from the connector CN2J. The sense signal SENSv1 is input from the connector CN4J. The sense signals SENSv2 to SENSv4 are input from the connector CN10J. The sense signals SENSv5 and SENSv6 are input from the connector CN8J. The sense signals SENSv5 and SENSv7 are input from the connector CN11J. The sense signals SENSv2 to SENSv7 are pulled up by a 5V DC voltage (DC5V) via resistors R24J, R2J and chip resistor RA3J, respectively.

[0374] As described above, the P / S conversion circuit 702 converts the serial data signal SDT5 from the P / S conversion circuit 701 and the sense signals SENSv0 to SENSv7, which are input to the SI terminal, into serial data (serial data signal SDT6) and outputs it from the Q8C terminal. This serial data signal SDT6 is input to the A1 terminal of the buffer circuit 703 and buffered. The Y1 output is then supplied to the third pin of the connector CN1J via chip resistor RA1J and transmitted to the upstream performance control board 30 as the serial data signal P_S_IN_DATA from the LED connection board 700.

[0375] As described above, the LED connection board 700 has the following configuration. The sense signals SENSv0 to SENSv9 input from the downstream side are converted into serial data and transmitted as a serial data signal P_S_IN_DATA from the connector CN1J to the upstream side via a buffer circuit 703. The clock signal P_S_OUT_CLK and serial data signal P_S_OUT_DATA sent from the performance control board 30 are transferred downstream via the buffer circuit 703 and a buffer circuit (any of 705, 706, 707, 708).

[0376] The clear signal M_S_CLR (reset signal RESET_M), clock signal M_S_OUT_CLK (clock signal CLK_M), serial data signal M_S_OUT_DATA (serial data signal DATA_M), and enable signal M_S_ENABLEP (latch signal LATCH_M) sent from the performance control board 30 are supplied to motor drivers 710 to 716 via buffer circuit 704, and motor drive signals (MOT1- / 2, MOT1- / 1, MOT1-2, MOT1-1...MOT7- / 2, MOT7- / 1, MOT7-2, MOT7-1) are generated and sent downstream (to the motors).

[0377] Connector CN1J receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) as operating power. The CN3J connector receives 18V DC voltage Vout, which is used as the operating power supply for 18V systems (for high-brightness LEDs and high-torque motors). · 12V DC voltage (DC12VB), 5V DC voltage (DC5V), 12V motor drive voltage (MOT12V), 18V motor drive voltage (MOT18V), and 18V LED drive voltage (LED18V) are supplied to the downstream side as operating power supply voltages.

[0378] In addition to those mentioned above, as shown in Figures 36 to 41, electronic elements such as resistors R1J, R2J..., resistors such as chip resistors RA1J, RA2J..., capacitors C1J, C2J..., diodes (including Zener diodes and Schottky barrier diodes) D1J, D2J... are connected to required locations on the LED connection board 700. As shown in the figure, taps TP1J, TP2J, etc. are provided and used for connecting to required locations. Although not shown, a capacitor is appropriately placed between the DC 5V or DC 12V power supply line and the ground to reduce power supply noise, etc.

[0379] [5.11 Back left relay board 720] The configuration of the rear left relay board 720 is shown in Fig. 42. The rear left relay board 720 has connectors CN1K and CN2K mounted thereon.

[0380] The connector CN1K is connected to the transmission line end of the transmission line H21 that connects to the connector CN8J of the LED connection board 700 in FIG. Therefore, this connector CN1K has 24 terminals, from the 1st pin to the 24th pin, as indicated by the numbers "1" to "24", and the terminal assignment is the same as that of the above-mentioned connector CN8J.

[0381] The connector CN2K is connected to the end of the transmission line H22 that connects to the decorative board 740 on the downstream side. This connector CN1B has 22 terminals, numbered from pin 1 to pin 22, as indicated by the numbers "1" to "22."

[0382] Pins 4, 7, and 10 are ground terminals. Pin 6 is the terminal for 5V DC voltage (DC5V). Pins 8 and 9 are terminals for 12V DC voltage (DC12VB). Pins 11, 12, 13, and 14 are terminals for the 18V motor drive voltage (MOT18VB).

[0383] The fifth pin is a terminal for the clock signal CLK_C, and the third pin is a terminal for the data signal DATA_C. Pins 15 and 16 are the terminals for the motor drive signal MOT5- / 2, pins 17 and 18 are the terminals for the motor drive signal MOT5- / 1, pins 19 and 20 are the terminals for the motor drive signal MOT5-2, and pins 21 and 22 are the terminals for the motor drive signal MOT5-1. The second pin is a terminal for the sense signal SENSv6, and the first pin is a terminal for the sense signal SENSv5.

[0384] The conductor points P1 and P2 on the housings of the connectors CN1K and CN2K are connected to the ground for mounting strength.

[0385] In this rear-left relay board 720, the ground terminals of pins 7, 13, 14, 19, and 20 of connector CN1K are converted to three terminals of pins 4, 7, and 10 on the connector CN2K side, converting the connector from 24 terminals to 22 terminals. This reduces the number of terminals on the downstream connector CN2D.

[0386] [5.12 Decorative Substrate 740] The decorative substrate 740 will be described with reference to FIG. The decorative board 740 is mounted with connectors CN1L, CN2L, CN3L, CN4L, CN5L, and CN6L.

[0387] The connector CN1L is connected to the end of the transmission line H22 that connects with the connector CN2K of the rear left relay board 720 of FIG. Therefore, this connector CN1L has 22 terminals, from the 1st pin to the 22nd pin, as indicated by the numbers "1" to "22," and the terminal assignment is the same as that of the above-mentioned connector CN2K. The conductor points P1 and P2 on the housings of the connectors CN1K to CN6K are connected to the ground for mounting strength.

[0388] The connector CN2L is connected to a position detection switch for a movable object (not shown). Pin 1 is the 12V DC voltage (DC12VB) terminal, and pin 3 is the ground terminal. Pin 2 is the input terminal for the sense signal SENSv5 from the connected position detection switch.

[0389] The connector CN3L is connected to another position detection switch of a movable object (not shown). Pin 1 is the 12V DC voltage (DC12VB) terminal, and pin 3 is the ground terminal. Pin 2 is the input terminal for the sense signal SENSv6 from the connected position detection switch.

[0390] The connector CN4L is connected to the end of the transmission line H23 that connects to the relay board 760 shown in Fig. 11. As indicated by the numbers "1" to "14," the connector has a 14-terminal configuration from the 1st pin to the 14th pin.

[0391] Pins 1, 2, and 3 are terminals to which a 12V DC voltage (DC12VB) is applied, and pins 12, 13, and 14 are terminals to which a 5V DC voltage (DC5V) is applied. Pins 4, 5, 7, 8, 10, and 11 are connected to ground. The 6th pin is the terminal for the clock signal CLK_C, and the 9th pin is the terminal for the data signal DATA_C. A flexible cable (for example, a flexible flat cable) is connected to the connector CN4L as the transmission line H23, but since the rated current of a flexible cable is small, the number of power terminals and ground terminals is made greater than that of the connector CN1L.

[0392] The connector CN5L is connected to a motor of a movable object (not shown). The third and fourth pins are the terminals to which the 18V motor drive voltage (MOT18V) is applied. The first pin is the terminal for the motor drive signal MOT5- / 2, the second pin is the terminal for the motor drive signal MOT5- / 1, the fifth pin is the terminal for the motor drive signal MOT5-2, and the sixth pin is the terminal for the motor drive signal MOT5-1.

[0393] The connector CN6L is connected to an LED board of a movable object (not shown). Pins 1 and 2 are terminals to which 12V DC voltage (DC12VB) is applied. The 3rd pin to the 24th pin are the light emitting drive current terminals for 22 systems, namely, 09-R1, 09-G1, 09-B1, 09-R8, and 09-G8.

[0394] A triple buffer gate buffer circuit 741 is mounted on this decorative board 740. A 5V DC voltage (DC5V) is used as the power supply voltage for this. The 5V DC voltage (DC5V) is supplied from the sixth pin of the connector CN1L.

[0395] An LED driver 742 is also mounted, and a 12V DC voltage (DC12VB) is used as the power supply voltage for this. The 12V DC voltage (DC12VB) is supplied from pins 8 and 9 of the connector CN1L.

[0396] The 18V motor drive voltage (MOT18V) supplied downstream from the connector CN5L is obtained from pins 11 to 14 of the connector CN1L.

[0397] The flow of various signals in the decorative substrate 740 will be described. The clock signal CLK_C and data signal DATA_C supplied from the upstream rear left relay board 720 to the connector CN1L are input to the buffer circuit 741 and buffered. They are then sent to the connector CN4L and transmitted to the downstream relay board 760.

[0398] The clock signal CLK_C and the data signal DATA_C are also supplied to an LED driver 742 . The LED driver 742 drives 22 systems of LEDs for light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR7, LEDG7, LEDR8, and LEDG8 for light emission drive current. These output terminals LEDR1, LEDG1, LEDB1... LEDR7, LEDG7, LEDR8, LEDG8 are connected to the 3rd pin to the 24th pin of the connector CN6L, and are configured to pass light emission drive current (09-R1, 09-G1, 09-B1... 09-R6, 09-G6, 09-B6) to 22 systems of LED circuits on a movable LED board (not shown).

[0399] As described above, the decorative substrate 740 has the following configuration. The clock signal CLK_C and the data signal DATA_C transmitted from the upstream side are transferred to the downstream side via the buffer circuit 703. The clock signal CLK and the data signal DATA are also used by the LED driver 742. The LED driver 742 drives the light emitting sections of other LED boards to emit light.

[0400] Connector CN1L receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) as operating power. · 12V DC voltage (DC12VB) and 18V motor drive voltage (MOT18VB) are supplied to the downstream side as operating power supply voltage.

[0401] In addition to the above, electronic elements such as resistors R1L, R2L, etc., capacitors C1L, C2L, etc. are connected to the decorative board 740 at required locations as shown in FIG. As shown in the figure, taps TP1L and TP2L are provided and used for connection to required locations.

[0402] [5.13 Relay board 760] The configuration of the relay board 760 is shown in Fig. 44. The relay board 760 has connectors CN1M, CN2M, and CN3M mounted thereon.

[0403] The connector CN1M is connected to the end of the transmission line H23 that connects with the connector CN4L of the decorative board 740 in FIG. Therefore, this connector CN1M has a 14-terminal configuration from the 1st pin to the 14th pin, as indicated by the numbers "1" to "14," and the terminal assignment is the same as that of the above-mentioned connector CN4L.

[0404] The connector CN2M is connected to an LED board (not shown). The fourth and sixth pins are ground terminals. Pin 5 is the terminal for 5V DC voltage (DC5V). The first pin is the terminal for 12V DC voltage (DC12VB). The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

[0405] The connector CN3M is connected to the end of a transmission line H24 that connects to the downstream LED board 780. This connector CN1B has six terminals, numbered "1" to "6," from pin 1 to pin 6. The fourth and sixth pins are ground terminals. Pin 5 is the terminal for 5V DC voltage (DC5V). The first pin is the terminal for 12V DC voltage (DC12VB). The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

[0406] The conductor points P1 and P2 on the housings of the connectors CN1M, CN2M, and CN3M are connected to the ground for mounting strength.

[0407] This relay board 760 is equipped with a buffer circuit 761, which is a Schmitt trigger buffer with eight CMOS circuits, similar to the buffer circuit 402 in Fig. 13. A 5V DC voltage (DC5V) is used as the power supply voltage for this. The 5V DC voltage (DC5V) is supplied from pins 12, 13, and 14 of the connector CN1M.

[0408] The clock signal CLK_C and data signal DATA_C supplied from the upstream decorative board 740 to the connector CN1M are input to the A1 and A2 terminals of the buffer circuit 761, where they are compensated. They are then output from the Y1 and Y2 terminals and transmitted downstream as the clock signal CLK and data signal DATA by the connector CN2M. The clock signal CLK_C and the data signal DATA_C are also input to the A5 terminal and A6 terminal of the buffer circuit 761, where they are compensated. They are then output from the Y5 terminal and Y6 terminal, and transmitted to the downstream LED board 780 as the clock signal CLK and the data signal DATA by the connector CN3M.

[0409] Therefore, the decorative substrate 740 buffers the clock signal CLK_C and the data signal DATA_C before transmitting them to the two downstream LED substrates (the LED substrate 780 and an LED substrate not shown).

[0410] [5.14 LED board 780] The configuration of the LED board 780 is shown in Fig. 45. The LED board 780 is equipped with connectors CN1N and CN2N.

[0411] The connector CN1N is connected to the end of the transmission line H24 that connects with the connector CN3M of the relay board 760 in FIG. Therefore, this connector CN1N has six terminals, from the first pin to the sixth pin, as indicated by the numbers "1" to "6", and the terminal assignment is the same as that of the above-mentioned connector CN3M.

[0412] The connector CN2N is connected to the LED board 790. The first pin is the terminal for 12V DC voltage (DC12VB). The fourth pin is the ground terminal. The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

[0413] The conductor points P1 and P2 on the housings of the connectors CN1N and CN2N are connected to the ground for mounting strength.

[0414] A buffer circuit 781, which is a triple buffer gate, is mounted on the LED board 780. A 5V DC voltage (DC5V) is used as the power supply voltage for this. The 5V DC voltage (DC5V) is supplied from the 5th pin of the connector CN1N.

[0415] Also mounted is an LED driver 782, which is supplied with a 12V DC voltage (DC12VB) as its power supply voltage. The 12V DC voltage (DC12VB) is supplied from the first pin of the connector CN1N.

[0416] The flow of various signals on the LED board 780 will be described. The clock signal CLK and data signal DATA supplied from the upstream relay board 760 to the connector CN1N are input to the buffer circuit 781 and buffered. They are then sent to the connector CN2N and transmitted to the downstream LED board 790.

[0417] The clock signal CLK and the data signal DATA are also supplied to an LED driver 782 . The LED driver 782 drives 22 systems of LEDs for light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR7, LEDG7, LEDB7, and LEDR8 for light emission drive current. These output terminals LEDR1, LEDG1, LEDB1... LEDR7, LEDG7, LEDB7, and LEDR8 are connected to the 22 LED circuits formed as the light-emitting unit 783, respectively, and pass light-emitting drive currents (03-R1, 03-G1, 03-B1... 03-G7, 03-B7, and 03-R8). As shown in the figure, each LED circuit of the light-emitting unit 783 is composed of two or three LEDs (LED1, LED2, etc.) connected in series and a resistor. The LED circuits of each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0418] As described above, the LED substrate 780 has the following configuration. The clock signal CLK and the data signal DATA transmitted from the upstream side are transferred to the downstream side via a buffer circuit 781. The clock signal CLK and the data signal DATA are also used by the LED driver 782 to drive the light emitting unit 783 to emit light.

[0419] Connector CN1N receives 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) as operating power. · 12V DC voltage (DC12VB) is supplied to the downstream side as the operating power supply voltage.

[0420] In addition to the above, as shown in FIG. 45, electronic elements such as resistors R1N, R2N, etc., capacitors C1N, C2N, etc. are connected to the LED board 780 at required locations. As shown in the figure, taps TP1N and TP2N are provided and used for connection to required locations.

[0421] [5.15 LED board 790] The configuration of the LED board 790 is shown in Fig. 46. The LED board 790 is equipped with a connector CN1X.

[0422] The connector CN1X is connected to the end of a transmission line H25 that connects with the connector CN2N of the LED board 780 in FIG. Therefore, this connector CN1X has a four-terminal configuration from the first pin to the fourth pin, as indicated by the numbers "1" to "4," and the terminal assignment is the same as that of the above-mentioned connector CN2N.

[0423] The conductor points P1 and P2 on the housing of the connector CN1X are connected to the ground for mounting strength.

[0424] An LED driver 791 is mounted on the LED board 790. A 12V DC voltage (DC12VB) is used as the power supply voltage for the LED driver 791. The 12V DC voltage (DC12VB) is supplied from the first pin of the connector CN1X.

[0425] The flow of various signals on the LED board 790 will be described. The clock signal CLK and the data signal DATA supplied from the upstream LED board 780 to the connector CN1X are supplied to an LED driver 791. The LED driver 791 drives 16 systems of LEDs for light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR5, LEDG5, LEDB5, and LEDR6 for light emission drive current. These output terminals LEDR1, LEDG1, LEDB1... LEDR5, LEDG5, LEDB5, and LEDR6 are connected to the 16 LED circuits formed as the light-emitting unit 792, respectively, and pass light-emitting drive currents (02-R1, 02-G1, 02-B1... 02-G5, 02-B5, and 02-R6). As shown in the figure, each LED circuit in the light-emitting unit 792 is composed of two or three LEDs (LED1, LED2, etc.) connected in series and a resistor. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0426] The above LED substrate 790 has the following configuration. The LED driver 791 uses the clock signal CLK and the data signal DATA transmitted from upstream to drive the light emitting unit 792 to emit light.

[0427] Connector CN1X receives 12V DC voltage (DC12VB) and serves as the operating power source.

[0428] In addition to the above, electronic elements such as resistors R1X, R2X, etc., and capacitors C1X, C2X, etc. are connected to the LED board 790 at required locations as shown in Fig. 46. Also, taps TP1X and TP2X are provided as shown in the figure and are used for connection to required locations.

[0429] The LED board 790 is equipped with an LED driver 791 and a light-emitting unit 792, but does not have a buffer circuit. For this reason, only a 12V DC voltage (DC12VB) is supplied from the connector CN2N of the LED board 780 to the connector CN1X of the LED board 790, and a 5V DC voltage (DC5V) is not supplied. In other words, the 5V DC voltage (DC5V) is supplied to the LED board 780, which is equipped with a buffer circuit, based on the 5V DC voltage (DC5VB) from the performance control board 30 (see the fourth and sixth pins of the connector CN1J in Figure 36).

[0430] [5.16 Under-panel relay board 800] The configuration of the relay board 800 is shown in Fig. 47. The relay board 800 has connectors CN1Q, CN2Q, CN3Q, and CN4Q mounted thereon.

[0431] The connector CN1Q is connected to the transmission line end of the transmission line H30 that connects with the connector CN11J of the LED connection board 700 in FIG. Therefore, this connector CN1Q has 16 terminals, from the 1st pin to the 16th pin, as indicated by the numbers "1" to "16", and the terminal assignment is the same as that of the above-mentioned connector CN11J.

[0432] Connector CN2Q is connected to the moving object motor. The third and fourth pins are the terminals to which the 12V motor drive voltage (MOT12V) is applied. The first pin is the terminal for the motor drive signal MOT4- / 2, the second pin is the terminal for the motor drive signal MOT4- / 1, the fifth pin is the terminal for the motor drive signal MOT4-2, and the sixth pin is the terminal for the motor drive signal MOT4-1.

[0433] The connector CN3Q is connected to the end of the transmission line H31 that connects to the decorative board 820 on the downstream side. This connector CN3Q has a ten-terminal configuration, from pin 1 to pin 10, as indicated by the numbers "1" to "10". Pins 1 to 6 are terminals for 12V DC voltage (DC12VB). The 7th, 8th, 9th, and 10th pins are terminals for the light emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8. This connector CN3Q is connected to a flexible cable (e.g., a flexible flat cable) as the transmission line H31, and because its rated current is small, it has more power terminals than other connectors. For example, the number of terminals (6) for 12V DC voltage (DC12VB) on connector CN3Q is greater than the number of terminals (2) for 12V DC voltage (DC12VB) on connector CN1Q.

[0434] The connector CN4Q is connected to a position detection switch. Pin 1 is the 12V DC voltage (DC12VB) terminal, Pin 2 is the ground terminal, and Pin 3 is the input terminal for the sense signal SENSv7 from the connected position detection switch.

[0435] The conductor points P1 and P2 on the housings of the connectors CN1Q, CN2Q, CN3Q, and CN4Q are connected to ground for mounting strength.

[0436] In this lower panel relay board 800, signals and voltages supplied by connector CN1Q are distributed downstream by connectors CN2Q, CN3Q, and CN4Q. Connector CN1Q inputs 12V DC voltage (DC12VB) through two terminals, pins 4 and 6, but connector CN3Q transmits 12V DC voltage (DC12VB) downstream through six terminals, pins 1 to 6. As a result, the number of terminals downstream (total number of terminals on connectors CN2Q, CN3Q, and CN4Q) is greater than the number of terminals upstream (number of terminals on connector CN1Q).

[0437] [5.17 Decorative board 820] The decorative substrate 820 will be described with reference to FIG. The decorative substrate 820 is equipped with a connector CN1S. The connector CN1S is connected to the end of the transmission line H31 that connects with the connector CN3Q of the lower relay board 800 in FIG. Therefore, this connector CN1S has a ten-terminal configuration from the first pin to the tenth pin, as indicated by the numbers "1" to "10," and the terminal assignment is the same as that of the above-mentioned connector CN3Q.

[0438] The decorative substrate 820 is provided with a light-emitting unit 821 equipped with four LED circuits, each of which is driven to emit light by light-emitting drive currents 13-B7, 13-R8, 13-G8, and 13-B8 via a connector CN1S. A 12V DC voltage (DC12VB) is applied to the anode side of the LED of the light-emitting unit 821 via the connector CN1S. This decorative substrate 820 is placed inside a movable body (not shown) and serves as a substrate for emitting LED light from the movable body portion.

[0439] Here, the light-emitting unit 821 has nine LED chips, designated LED1, LED2, LED9, which are indicated by dashed lines. As can be seen from the diagram, each LED chip is a full-color LED chip that emits light of the respective colors R, G, and B. Note that "GA," "RA," and "BA" in the diagram represent the anode of the green LED, the anode of the red LED, and the anode of the blue LED within the full-color LED chip, respectively.

[0440] This decorative board 820 is designed to emit light in two colors, red and green, for presentation purposes. Instead of using single-color red and green LED chips, full-color LED chips are used. As shown in the figure, the series circuit of unused blue LEDs in the full-color LED chips has both the anode and cathode connected to a 12V DC voltage (DC12VB) line, preventing the flow of light-emitting drive current. For example, in a series circuit of LED1, LED2, and LED3, three blue LEDs are connected in series, and the anode and cathode of the series circuit are connected to a 12V DC voltage (DC12VB) line.

[0441] In this configuration, costs can be reduced by using one full-color LED chip instead of the two single-color LED chips that would normally be used, one red and one green. Furthermore, if a light-emitting drive current terminal were to be connected to each of the three R, G, and B terminals on the full-color LED chip, the number of terminals (pins) on the connector CN1S would increase, and the number of light-emitting drive current terminals used by the LED driver would also increase. For this reason, as described above, light-emitting drive current is not supplied to the unused blue LED. This simplifies the connector configuration, LED driver configuration, and wiring, and also reduces costs.

[0442] Furthermore, if the unused color terminal (BA) is left unconnected, there is a possibility that it may emit light unintentionally due to noise, etc., so the anode and cathode sides are connected to the 12V DC voltage (DC12VB) line to prevent unintentional emission of light.

[0443] The unused terminals of the full-color LED chip (the anode / cathode of the blue LED) may be left unconnected. If the substrate has a ground, the ground may be connected to both ends of the unused terminals of the full-color LED chip.

[0444] Also, in the decorative board 820 of Figure 48, resistors R1S, R3S, and R5S are connected to the green LED system of the full-color LED chip, and resistors R2S, R4S, and R6S are connected to the red LED system, but since no current flows through the unused blue LED terminal (BA), no resistor is connected to the blue LED system. This also simplifies the circuit and promotes cost reduction.

[0445] <6. Other examples of board connection configurations> [6.1 Connection status of each board] An alternative example to the connection configuration of FIG. 11 is shown in FIG. 49, the same blocks as those in Fig. 11 are given the same reference numerals and descriptions thereof will be omitted. The example in Fig. 49 is an example in which an LED connection board 1500 is used instead of the LED connection board 700 on the game board 3 side in Fig. 11.

[0446] The LED connection board 1500 is connected downstream of the performance control board 30 by a transmission line H50. The LED connection board 1500 performs various signal processing required for driving the light emission of performance means such as LEDs and motors on the game board 3 based on control signals from the performance control board 30.

[0447] 49 illustrates an LED substrate 1600 downstream of the LED connection substrate 1500. The LED substrate 1600 may be connected to the LED connection substrate 1500 via an intermediate substrate or another LED substrate (not shown), or may be connected directly to the LED connection substrate 1500. In this FIG. 49, the LED substrate 1600 is one of multiple substrates connected downstream of the LED connection substrate 1500. In the configuration of Figure 49, it is also possible that downstream of the LED connection board 1500, each board from the left underside relay board 720 to the LED board 790 shown in Figure 11, and each board of the lower underside relay board 800 and decorative board 820, etc., may be connected in parallel with the LED board 1600.

[0448] [6.2 LED connection board 1500] The LED connection board 1500 will be described with reference to Figures 50, 51, 52, 53, 54, 55, 56, and 57. These figures show the circuit configurations provided on the LED connection board 1500 separately.

[0449] The LED connection board 1500 is equipped with the following connectors: connectors CN1V, CN2V, and CN3V in FIG. 50, connectors CN4V to CN8V in FIG. 51, connectors CN9V to CN16V in FIG. 52 or 53, connectors CN17V to CN20V in FIG. 54, connectors CN21V to CN25V in FIG. 57, and connectors CN26V to CN28V in FIG. 56.

[0450] The connector CN1V in FIG. 50 is connected to the transmission line end of the transmission line H50 that connects to the performance control board 30 as shown in FIG. This connector CN1V has 40 terminals, numbered from pin 1 to pin 40, as indicated by the numbers "1" to "40".

[0451] Pins 1, 2, 8, 9, 10, 16, 18, 19, 20, 22, 29, 32, 33, 34, 39, and 40 of connector CN1V are connected to ground. Pins 4 and 6 are terminals for 5V DC voltage (DC5VB). Pins 12, 14, 24, 26, 28, and 30 are terminals for 12V DC voltage (DC12VB). Pins 36 and 38 are terminals for 35V DC voltage (DC35V). Pin 17 is unused.

[0452] The third pin is assigned as a terminal for transmitting a clock signal LSI_SCK to the LSI serving as the motor driver control unit 1530 in FIG. 55, the fifth pin is assigned as a terminal for transmitting an SPI bus slave selection signal LSI_SS to the LSI, the seventh pin is assigned as a terminal for transmitting a serial data signal LSI_MOSI to the LSI, the eleventh pin is assigned as a terminal for transmitting a hardware reset signal LSI_RESET to the LSI, and the thirty-fifth pin is assigned as a terminal for transmitting a serial data signal LSI_MISO output from the LSI. The clock signal LSI_SCK and the serial data signal LSI_MOSI are signals transmitted from the performance control board 30 for motor drive control. The serial data signal LSI_MISO is serial data transmitted from this LED connection board 1500 to the upstream performance control board 30.

[0453] The 13th pin is assigned as a terminal for the clock signal CLK_P, and the 15th pin is assigned as a terminal for the serial data signal DATA_P. Pin 31 is assigned as the terminal for the load signal S_IN_LOAD, which is used for P / S conversion.

[0454] A clock signal CLK_P and a serial data signal DATA_P pass through a buffer circuit 1501 and are then branched into the following four systems by a buffer circuit 1502. Clock signal CLK_A, serial data signal DATA_A Clock signal CLK_B, serial data signal DATA_B Clock signal CLK_C, serial data signal DATA_C Clock signal CLK_D, serial data signal DATA_D

[0455] The clock signal CLK_A and the serial data signal DATA_A are supplied to the LED drivers 1510 and 1511 in FIG. 52 as signals for controlling the performance. The clock signal CLK_B and the serial data signal DATA_B are supplied to the LED drivers 1520, 1521, and 1522 in FIGS. 53 and 54 as signals for controlling the performance.

[0456] The clock signal CLK_C and the serial data signal DATA_C are signals for performance control sent to the performance drive means on the downstream board, and are sent to the downstream board from the connector CN2V in FIG. The clock signal CLK_D and the serial data signal DATA_D are signals for performance control that are sent to the performance drive means on the downstream board, and are sent from the connector CN3V to the downstream board.

[0457] The 21st pin of the connector CN1V in FIG. 50 is assigned as a terminal for the reset signal RESET_M, the 23rd pin as a terminal for the clock signal CLK_M / S, the 25th pin as a terminal for the serial data signal DATA_M, and the 27th pin as a terminal for the latch signal LATCH_M. The reset signal RESET_M, clock signal CLK_M / S, serial data signal DATA_M, and latch signal LATCH_M are signals used in the motor driver 1505 in Fig. 51. The clock signal CLK_M / S is supplied to the motor driver 1505 as the clock signal CLK_M via the buffer circuit 1503 in Fig. 50.

[0458] The 37th pin of the connector CN1V is assigned as a terminal for the serial data signal S_IN_DATA. The serial data signal S_IN_DATA is serial data transmitted from this LED connection board 1500 to the performance control board 30. In order to output the serial data signal S_IN_DATA, the clock signal CLK_M / S is supplied to a P / S conversion circuit 1504 as a clock signal S_IN_CLK via a buffer circuit 1503.

[0459] Conductor points P1 and P2 on the housings of connector CN1V and each of the other connectors CN2V to CN28V are connected to ground for mounting strength.

[0460] The connector CN2V in FIG. 50 is a connector that is connected to the downstream board. Pins 4, 6, and 8 of connector CN2V are connected to ground. The first pin is the terminal for 12V DC voltage (DC12VB). The second pin is the terminal for 5V DC voltage (DC5VB). The third pin is used as a terminal for the clock signal CLK (CLK_C). The fifth pin is the terminal for the serial data signal DATA (DATA_C). The seventh pin is a terminal to which the sense signal +P0x from the downstream side is input. Pins 9, 10, 11, and 12 are terminals for the motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+.

[0461] The connector CN3V is also a connector that is connected to a downstream board, and is provided with terminals for a 12V DC voltage (DC12VB), a serial data signal DATA (DATA_D), a clock signal CLK (CLK_D), and a ground.

[0462] The connector CN4V in Fig. 51 is connected to a movable motor (not shown). A 12V DC voltage (MOT12V) is applied to the third pin, which serves as the power supply voltage for the motor. Terminals for motor drive signals MOT1- / 2, MOT1- / 1, MOT1- / 2, and MOT1-1 are also provided. Connectors CN6V, CN7V, and CN8V are connectors to which sense signals SENS0, SENS1, and SENS2 are input from various sensors, respectively.

[0463] The connectors CN9V to CN16V in Fig. 52 or 53 are connectors connected to downstream LED boards (not shown), and are provided with terminals for outputting light emission drive current to the corresponding LED boards. The connectors CN17V to CN20V in Fig. 54 are also connectors connected to downstream LED boards (not shown), and are provided with terminals for outputting light emission drive current to the corresponding LED boards.

[0464] Connectors CN21V to CN25V in FIG. 57 are connectors to which sense signals +P0y, +P0z, +P0u, +P1z, and +P1u are input from various sensors, respectively. Connectors CN26V to CN28V in FIG. 56 are connectors that are connected to downstream motors (not shown). Connector CN26V is provided with terminals for motor drive signals MOTuA+, MOTuB-, MOTuA-, and MOTuB+. The connector CN27V is provided with terminals for the motor drive signals MOTzB+, MOTzA-, MOTzB-, and MOTzA+. The connector CN28V is provided with terminals for the motor drive signals MOTyB+, MOTyA-, MOTyB-, and MOTyA+.

[0465] The power supply voltage in this LED connection board 1500 will be described. The LED connection board 1500 is equipped with, as ICs, buffer circuits 1501, 1502, and 1503 shown in Fig. 50, which are Schmitt trigger buffers with eight circuits similar to the buffer circuit 402 previously described in Fig. 13, and a buffer circuit 1540 shown in Fig. 57. Also, a P / S conversion circuit 1504 shown in Fig. 50 is equipped. The power supply voltage for these components is a 5V DC voltage (DC5V) based on a 5V DC voltage (DC5VB) from connector CN1V. The 5V DC voltage (DC5VB) is taken out from the positive electrode side of the capacitor C3V via the connector CN1V and the fuse F1J. The P / S conversion circuit 1504 is an IC similar to the P / S conversion circuit 505 in FIG.

[0466] Furthermore, the LED connection board 1500 is equipped with a motor driver 1505 shown in FIG. 51 as an IC, and a 12V motor drive voltage (MOT12V) and a 12V direct current voltage (DC12VS) are used as power supply voltages for this.

[0467] The 12V motor drive voltage (MOT12V) and 12V DC voltage (DC12VS) are separated from the 12V DC voltage (DC12VB) by power supply separation / protection circuits 1551 and 1552 shown in FIG.

[0468] The LED connection board 1500 is also equipped with a motor driver control unit 1530 shown in FIG. 55 as an IC, and uses a 5V motor drive voltage (DC 5V) as the power supply voltage for this.

[0469] Furthermore, the LED connection board 1500 is equipped with a stepping motor driver 1532 in Fig. 55 and motor drivers 1533, 1534, and 1535 in Fig. 56. The power supply voltages used for these are 35V motor drive voltages (MOT35Vx), (MOT35Vy), (MOT35Vz), and (MOT35Vu), 5V DC voltage (DC5V), voltage VCCx, voltage VCCy, voltage VCCz, and voltage VCCu.

[0470] The 35V motor drive voltages (MOT35Vx), (MOT35Vy), (MOT35Vz), and (MOT35Vu) are separated from the 35V direct current voltage (DC35V) by a power supply separation / protection circuit 1553 shown in FIG. The voltages VCCx, VCCy, VCCz, and VCCu are voltages obtained from terminal 34 (monitor terminal of the internal regulator) of the motor drivers 1532, 1533, 1534, and 1535, respectively.

[0471] Furthermore, LED connection board 1500 is equipped with LED drivers 1510, 1511, 1520, 1521, and 1522 shown in FIGS. 52, 53, and 54 as ICs, and uses a 12V DC voltage (DC12VB) as the power supply voltage for these.

[0472] The flow of various signals in the LED connection board 1500 will be described below. The clock signal LSI_SCK, serial data signal LSI_MOSI, slave selection signal LSI_SS, and hardware reset signal LSI_RESET are sent from the performance control board 30 to connector CN1V in Figure 50 for motor drive control.

[0473] These signals are compensated by the buffer circuit 1501 and then supplied to the motor driver control unit 1530 in FIG. 55 via the chip resistor RA1V or RA2V. A motor driver control unit 1530 controls motor drivers 1532, 1533, 1534, and 1535 based on a clock signal LSI_SCK and a serial data signal LSI_MOSI.

[0474] Specifically, the motor driver control unit 1530 outputs X-axis output pulses OUTx, DIRx, and P3x to the motor driver 1532. In response to this, the motor driver 1532 generates motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+ and supplies them to the connector CN2V in FIG.

[0475] Further, the motor driver control section 1530 outputs Y-axis output pulses OUTy, DIRy, and P3y to the motor driver 1533 in FIG. The connections between Figures 55 and 56 are indicated by "c2", "c3", and "c4". The motor driver 1533 generates motor drive signals MOTyB+, MOTyA-, MOTyB-, and MOTyA+ in response to the Y-axis output pulses OUTy, DIRy, and P3y, and supplies them to a connector CN28V. Furthermore, the motor driver control unit 1530 outputs Z-axis output pulses OUTz, DIRz, and P3z to the motor driver 1534. In response to this, the motor driver 1534 generates motor drive signals MOTzB+, MOTzA-, MOTzB-, and MOTzA+ and supplies them to the connector CN27V. Furthermore, the motor driver control unit 1530 outputs U-axis output pulses OUTu, DIRu, and P3u to the motor driver 1535. In response to this, the motor driver 1534 generates motor drive signals MOTuA+, MOTuB-, MOTuA-, and MOTuB+ and supplies them to the connector CN26V.

[0476] The connectors CN26V, CN27V, and CN28V are connected to a movable motor (not shown). Furthermore, the connector CN2V in FIG. 50 is connected to a downstream board, and the motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+ from the motor driver 1532 are supplied to a movable motor (not shown) via the downstream board. Therefore, the motor driver control unit 1530 in FIG. 55 has the function of driving these movable motors based on the clock signal LSI_SCK and the serial data signal LSI_MOSI.

[0477] Sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u from various sensors input from connector CN2V in Fig. 50 and connectors CN21V to CN25V in Fig. 57 are input to the motor driver control unit 1530 via a buffer circuit 1540. The sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u are signals that detect the position of each movable body. The connection between Figure 55 and Figure 57 is indicated by "c1". The motor driver control unit 1530 converts these sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u into serial data and outputs it as a serial data signal LSI_MISO. In other words, the motor driver control unit 1530 also functions as a P / S conversion circuit. The serial data signal LSI_MISO obtained by the motor driver control unit 1530 is compensated by the buffer circuit 1501 in FIG. 50 and then supplied to the connector CN1V.

[0478] Sense signals SENS0, SENS1, and SENS2 are input from connectors CN6V, CN7V, and CN8V in Fig. 51. These sense signals SENS0, SENS1, and SENS2 are also signals that detect the position of each movable body. These signals may also be signals from a motion sensor that detects the player's movements or a proximity sensor that detects the gaming ball. The input sense signals SENS0, SENS1, and SENS2 are input to the P / S conversion circuit 1504 in FIG. 50 and converted into a serial data signal S_IN_DATA. This serial data signal S_IN_DATA is compensated by a buffer circuit 1503 and then supplied to a connector CN1V. These serial data signals LSI_MISO and S_IN_DATA are transmitted to the performance control board 30 as serial data signals obtained by converting the detection signals of various sensors into serial data.

[0479] The clock signal CLK_P and serial data signal DATA_P input from the connector CN1V are compensated by the buffer circuit 1501 and then supplied to the buffer circuit 1502 via the chip resistor RA2V. As described above, the clock signal CLK_P and serial data signal DATA_P are compensated by the buffer circuit 1502 and then branched into four systems, two of which, the clock signal CLK_C and serial data signal DATA_C, and the clock signal CLK_D and serial data signal DATA_D, are transmitted to downstream boards from the connectors CN2V and CN3V, respectively.

[0480] The clock signal CLK_A and the serial data signal DATA_A from the buffer circuit 1502 are supplied to LED drivers 1510 and 1511 shown in FIG.

[0481] The LED driver 1511 drives 20 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1... LEDR6, LEDG6, LEDB6 and output terminals LEDR8, LEDG8 for light emission drive current based on a clock signal CLK_A and a serial data signal DATA_A.

[0482] Of these output terminals, output terminals LEDR1, LEDG1, LEDB1... LEDR3, LEDG3, LEDB3 are connected to pins 2 to 10 of connector CN10V, and are configured to pass light emission drive current (08-R1, 08-G1, 08-B1... 08-R3, 08-G3, 08-B3) to nine systems of LED circuits on an LED board (not shown). In addition, output terminals LEDR4, LEDG4, LEDB4... LEDR6, LEDG6, LEDB6 are connected to pins 2 to 10 of connector CN14V, and are configured to pass light emission drive current (08-R4, 08-G4, 08-B4... 08-R6, 08-G6, 08-B6) to nine systems of LED circuits on an LED board (not shown).

[0483] The first pins of the connectors CN10V and CN14V are used to supply a 5V DC voltage (DC5V) to the downstream LED board.

[0484] The LED driver 1510 drives 21 systems of LED light emission using light emission drive current output terminals LEDR1, LEDG1, LEDB1, . . . LEDR7, LEDG7, and LEDB7 based on a clock signal CLK_A and a serial data signal DATA_A.

[0485] Of these output terminals, output terminals LEDR1, LEDG1, LEDB1... LEDR4, LEDG4, LEDB4 ​​are connected to pins 2 to 13 of connector CN9V, and are configured to pass light emission drive current (07-R1, 07-G1, 07-B1... 07-R4, 07-G4, 07-B4) to 12 systems of LED circuits on an LED board (not shown). Furthermore, output terminals LEDR5, LEDG5, LEDB5... LEDR7, LEDG7, LEDB7 are connected to pins 2 to 10 of connector CN13V. Output terminals LEDR8 and LEDG8 of LED driver 1511 are connected to pins 11 and 12. This results in a configuration in which light emission drive currents (07-R5, 07-G5, 07-B5... 07-R7, 07-G7, 07-B7, and 08-R8 and 08-G8) flow to 11 systems of LED circuits on an LED board (not shown). The first pins of the connectors CN9V and CN13V are used to supply 12V DC voltage (DC12VB) to the downstream LED boards.

[0486] The clock signal CLK_B and the serial data signal DATA_B from the buffer circuit 1502 in FIG. 50 are supplied to LED drivers 1520, 1521, and 1522 in FIGS.

[0487] The LED driver 1520 drives 24 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR8, LEDG8, and LEDB8 for light emission drive current based on the clock signal CLK_B and the serial data signal DATA_B.

[0488] Of these output terminals, output terminals LEDR1, LEDG1, LEDB1... LEDR5, LEDG5, and LEDB5 are connected to any of pins 2 to 16 of connector CN12V, and are configured to pass light emission drive current (09-R1... 09-B5) to 15 systems of LED circuits on an LED board (not shown). In addition, output terminals LEDR6, LEDG6, LEDB6... LEDR8, LEDG8, LEDB8 are connected to pins 2 to 10 of connector CN16V, and are configured to pass light emission drive current (09-R6, 09-G6, 09-B6... 09-R8, 09-G8, 09-B8) to nine LED circuits on an LED board (not shown).

[0489] The first pin of each of the connectors CN12V and CN16V is used to supply 12V DC voltage (DC12VB) to the downstream LED board. A fuse F6V is connected to the first pin of the connector CN16V.

[0490] The LED driver 1521 drives 24 systems of LED light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR8, LEDG8, and LEDB8 for light emission drive current based on the clock signal CLK_B and the serial data signal DATA_B.

[0491] Of these output terminals, output terminals LEDR1, LEDG1, LEDB1... LEDR5, LEDG5, and LEDB5 are connected to any of pins 2 to 16 of connector CN11V, and are configured to pass light emission drive current (10-R1... 10-B5) to 15 systems of LED circuits on an LED board (not shown). In addition, output terminals LEDR6, LEDG6, LEDB6... LEDR8, LEDG8, LEDB8 are connected to pins 2 to 10 of connector CN15V, and are configured to pass light emission drive current (10-R6, 10-G6, 10-B6... 10-R8, 10-G8, 10-B8) to nine LED circuits on an LED board (not shown).

[0492] The first pin of each of the connectors CN11V and CN15V is used to supply 12V DC voltage (DC12VB) to the downstream LED board. A fuse F5V is connected to the first pin of the connector CN15V.

[0493] The LED driver 1522 in FIG. 54 drives 17 systems of LED light emission using output terminals LEDR1...LEDR4 and output terminals LEDR5...LEDR7 for light emission drive current based on the clock signal CLK_B and serial data signal DATA_B.

[0494] The output terminals LEDR1 to LEDR4 are connected to the second to eleventh pins of the connector CN17V, and configured to pass light emission drive currents (11-R1 to 11-R4) to ten LED circuits on an LED board (not shown). The output terminals LEDR5, LEDG5, and LEDB5 are connected to the second to fourth pins of the connector CN19V, and configured to pass light emission drive currents (11-R5, 11-G5, and 11-B5) to three systems of LED circuits on an LED board (not shown). The output terminals LEDR6, LEDG6, and LEDB6 are connected to the second to fourth pins of the connector CN20V, and configured to pass light emission drive currents (11-R6, 11-G6, and 11-B6) to three systems of LED circuits on an LED board (not shown). The output terminal LEDR7 is connected to the second pin of the connector CN18V, and is configured to pass a light emission drive current (11-R7) to one system of LED circuits on an LED board (not shown).

[0495] The first pins of the connectors CN17V, CN18V, CN19V, and CN20V are used to supply 12V DC voltage (DC12VB) to the downstream LED boards.

[0496] The reset signal RESET_M, clock signal CLK_M / S (clock signal CLK_M), serial data signal DATA_M, and latch signal LATCH_M input from connector CN1V in Figure 50 are signal compensated in buffer circuit 1503 and then supplied to motor driver 1505 in Figure 51 via chip resistor RA3V.

[0497] The motor driver 1505 generates motor drive signals MOT1- / 2, MOT1- / 1, MOT1- / 2, and MOT1-1 based on the clock signal CLK_M and the serial data signal DATA_M and supplies them to a connector CN4V. The connector CN4V is connected to a movable motor (not shown). Therefore, the motor driver 1505 drives the movable motor based on the clock signal CLK_M and the serial data signal DATA_M.

[0498] As described above, the LED connection board 1500 has the following configuration. The sense signals SENS0, SENS1, and SENS2 input from the downstream side are converted into serial data by a P / S conversion circuit 1504, and are transmitted as a serial data signal S_IN_DATA from the connector CN1V to the upstream side via a buffer circuit 1503. The sense signals +P0x, +P0y, +P0z, +P0u, +P1z, and +P1u input from the downstream side are supplied to the motor driver control unit 1530 via a buffer circuit 1540 and converted into serial data. This serial data signal LSI_MISO is transmitted to the upstream side from the connector CN1V via the buffer circuit 1501.

[0499] The clock signal CLK_P (CLK_C, CLK_D) and serial data signal DATA_P (DATA_C, DATA_D) transmitted from the performance control board 30 are transferred downstream via buffer circuits 1501 and 1502. · The clock signal CLK_P (CLK_A, CLK_B) and serial data signal DATA_P (DATA_A, DATA_B) transmitted from the performance control board 30 are supplied to the LED drivers 1510, 1511, 1520, 1521, and 1522 to drive the LEDs to emit light.

[0500] The clock signal LSI_SCK and serial data signal LSI_MOSI sent from the performance control board 30 are supplied to the motor driver control unit 1530 to drive the motor. The drive method is bipolar. The clock signal CLK_M and serial data signal DATA_M sent from the performance control board 30 are supplied to the motor driver 1505, which generates a motor drive signal and sends it to the downstream motor / board. The drive method is unipolar. The motor drive system is a mixture of bipolar and unipolar drive, but by using high-torque bipolar drive for large moving bodies and low-cost unipolar drive for small moving bodies, appropriate drive force and cost reduction are achieved.

[0501] Connector CN1V receives 12V DC voltage (DC12VB), 5V DC voltage (DC5VB), and 35V DC voltage (DC35V) as operating power. · 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) are supplied to the downstream side as operating power supply voltage.

[0502] 50 to 57, in addition to those mentioned above, electronic elements such as resistors R1V, R2V..., chip resistors RA1V, RA2V..., capacitors C1V, C2V..., diodes (including Zener diodes and Schottky barrier diodes) D1V, D2V..., fuses F1V, F2V..., transistors (FETs) Q1V, Q2V..., and oscillator X1V are connected to required locations on the LED connection board 1500. Also, as shown in the figures, taps TP1V, TP2V... are provided and used for connection to required locations. Some of the capacitors C1V, C2V, etc. are placed between the DC 5V or DC 12V power supply line and ground to reduce power supply noise, etc.

[0503] Incidentally, instead of receiving the 5V DC voltage (DC5VB) from the upstream board, the 5V DC voltage (DC5VB) may be generated based on, for example, a 12V DC voltage (DC12VB).

[0504] [6.3 LED board 1600] The configuration of the LED substrate 1600 shown in FIG. 49 is shown in FIG. The LED board 1600 is equipped with a connector CN1W.

[0505] The connector CN1W is connected to an end of a transmission line that connects the LED connection board 1500 with a connector on a downstream board (not shown).

[0506] This connector CN1W has seven terminals, numbered "1" to "7," from pin 1 to pin 7. The terminal assignments, starting from pin 1, are as follows: ground terminal, clock signal CLK terminal, ground terminal, 5V DC voltage (DC5V) terminal, serial data signal DATA terminal, reset signal RESET terminal, and 12V DC voltage (DC12VB) terminal.

[0507] The conductor points P1 and P2 on the housing of the connector CN1W are connected to the ground for mounting strength.

[0508] An LED driver 1601 is mounted on the LED board 1600. A 12V direct current voltage (DC12VB) is used as the power supply voltage for the LED driver 1601. The 12V direct current voltage (DC12VB) is supplied from the seventh pin of the connector CN1W.

[0509] The flow of various signals in the LED board 1600 will be described. The clock signal CLK, the data signal DATA, and the reset signal RESET supplied from the upstream board to the connector CN1W are supplied to the LED driver 1601. The LED driver 1601 drives 15 systems of LEDs for light emission using output terminals LEDR1, LEDG1, LEDB1, . . . LEDR5, LEDG5, and LEDB5 for light emission drive current. These output terminals LEDR1, LEDG1, LEDB1...LEDR5, LEDG5, LEDB5 are connected to 15 LED circuits formed as the light emitting unit 1602, respectively, and pass light emission drive currents (20-R1, 20-G1, 20-B1...20-R5, 20-G5, 20-B5). As shown in the figure, each LED circuit in the light-emitting unit 1602 is composed of two LEDs (LED1, LED2, etc.) connected in series and a resistor. The LED circuits in each system are connected in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0510] As mentioned above, the LED board 1600 It has the following configuration. An LED driver 1601 drives a light emitting unit 1602 to emit light based on a clock signal CLK and a data signal DATA transmitted from upstream.

[0511] Connector CN1W receives 12V DC voltage (DC12VB) and uses it as operating power.

[0512] In addition to the components mentioned above, the LED board 1600 is also connected to required locations with electronic elements such as resistors R1W, R2W, etc., capacitors C1W, C2W, etc., as shown in Fig. 58. Also, as shown in the figure, taps TP1W, TP2W, etc. are provided and used for connection to required locations.

[0513] <7. Description of noteworthy components> Below, we will explain in order the noteworthy configurations of the gaming machine 1 that have been explained so far.

[0514] [7.1 Relationship between connector terminals and terminals of performance driving means] First, the relationship between the connector terminals on the various boards and the terminals of the performance drive means will be explained. The performance driving means is a general term for the circuit parts that drive performance devices, such as the light emitting driving means and the motor driving means. Specifically, it is a general term for the circuit parts that function as LED drivers, motor drivers, driver control units that control these, and S / P conversion circuits for motor drive control. In particular, the "terminals" of the performance driving means refer to the terminals of chips that function as LED drivers, motor drivers, driver control units, S / P conversion circuits, etc., mounted as chip components (IC chips).

[0515] The gaming machine 1 of the embodiment has the following (Configuration A1-1). (Configuration A1-1) The gaming machine 1 is A first circuit board provided with a first connector for inputting a first performance driving means using a chip component and a clock and performance driving control data for the first performance driving means; A second circuit board provided with a second connector for inputting a clock and control data for driving the second performance drive means, the second performance drive means being a chip component; Equipped with In the first substrate, the first performance driving means and the first connector are arranged on the same surface of the substrate; The left-right relationship of the input terminals of the clock and the control data for driving the performance in the first performance driving means when viewed from the pattern wiring side to the chip side; The left-right relationship of the connector terminals of the clock and the performance drive control data in the first connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal; are identical, In the second substrate, the second performance driving means and the second connector are arranged on the same surface of the substrate, The left-right relationship of the connector terminals of the clock and the performance drive control data in the second connector when viewed from the connector terminal side toward the lead-out direction of the pattern wiring connected to each connector terminal is the same as that of the first connector, The left-right relationship of the input terminals for the clock and performance drive control data in the second performance drive means when viewed from the pattern wiring side to the chip side is the same as that of the first performance drive means.

[0516] FIG. 59 shows a schematic diagram of the configuration of the first and second substrates. The various configurations are shown in schematic form below, with each diagram mainly showing connectors and performance drive means as blocks, as well as "clock CK," "data DT," and "pattern wiring PTH." Specific examples of clock CK and data DT will be described below, but these refer to the clock and performance drive control data supplied to the performance drive means from a connector on the board. The same applies to the drawings that schematically show the configurations of (Configuration A1-2) to (Configuration A9-3) that will be described later.

[0517] The pattern wiring PTH refers to the pattern wiring for supplying the clock CK and data DT from the connector to the performance driving means. Note that there may be resistor elements or the like between the connector and the performance drive means, but in such cases, the configuration shown in the schematic diagram does not no longer apply. In other words, even if other elements are interposed between the connector and the performance drive means, it is sufficient that the illustrated configuration is met between the connector and the performance drive means. More precisely, as long as the left-right relationship of the clock CK and data DT wiring is not reversed in the elements interposed between the connector and the performance drive means, these can be ignored and it can be considered to fall under the following configuration. Also, an IC chip that functions as a buffer circuit connected to the signal path between the connector and the performance drive means can be considered part of the performance drive means, but there is also the idea of ​​excluding it from the performance drive means in a narrower sense. Even if the buffer circuit is not included in the performance drive means, if the buffer circuit is interposed between the connector and the performance drive means, as long as the configuration does not invert the left-right relationship of the wiring for the clock CK and data DT, it can be considered to fall under the following configuration, ignoring the buffer circuit. The above should be considered in the same way for (Configuration A1-2) to (Configuration A9-3) described later.

[0518] As shown in FIG. 59, the first board is equipped with a first connector and a first performance driving means. The first connector and the first performance driving means are arranged on the same surface of the first substrate. In the figure, the blocks of the first connector and the first performance driving means are shown with solid lines, which indicates that they are arranged on the illustrated surface. Furthermore, the "○" in the blocks that serve as connectors or performance driving means indicates a terminal.

[0519] The first connector inputs a clock CK and performance drive control data (data DT) for the first performance drive means. The clock CK and data DT are supplied to the first performance drive means by the pattern wiring PTH on the substrate. As described above, the connection is not limited to the case where only the pattern wiring PTH is used, but there are also cases where a resistive element or chip is interposed. Also, if necessary, some of the wiring may be formed on the other side of the substrate via a through hole. Although these are not mentioned in detail in each example, the same applies to the pattern wiring PTH in other configuration examples described below.

[0520] The second board is equipped with a second connector and a second performance driving means. The second connector and the second performance driving means are arranged on the same surface on the second substrate. The second connector inputs a clock CK and performance drive control data (data DT) for the second performance drive means. The clock CK and data DT are supplied to the second performance driving means by pattern wiring PTH on the substrate. The first performance driving means and the second performance driving means are shown by the same rectangle because the left-right relationship of the clock CK and data DT terminals is the same.

[0521] In this case, attention is focused on the directions DIR1, DIR2, DIR3, and DIR4 indicated by the arrows. The directions DIR1 and DIR3 are directions in which the pattern wiring PTH connected to each connector terminal of the clock CK and the data DT is led out from the connector terminal side. The directions DIR2 and DIR4 are directions from the pattern wiring PTH side to the chip (=the chip that is the performance drive means) side of the input terminals of the clock CK and data DT in the performance drive means.

[0522] The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR1, DIR2, DIR3, and DIR4 is shown in the lower part of FIG.

[0523] The left-right relationship when viewed from the directions DIR1 and DIR3 is as follows: "The left-right relationship of the clock CK and data DT connector terminals in the connector when viewed from the connector terminal side in the direction in which the pattern wiring PTH connected to each connector terminal is led out" is. In the example of FIG. 59, as shown, the clock CK terminal is on the left and the data DT terminal is on the right.

[0524] The left-right relationship when viewed in the directions DIR1 and DIR3 can also be expressed as in the following examples, and any one of them may be applicable. "The left-right relationship of the clock CK and data DT connector terminals when viewed from the connector side to the pattern wiring PTH side" "The left-right relationship of the clock CK and data DT connector terminals in the connector when viewed from the connector terminal side toward the connector side from which the pattern wiring PTH connected to each connector terminal is led out"

[0525] Also, the left-right relationship when viewed from the directions DIR2 and DIR4 is as follows: "The left-right relationship of the input terminals of the clock CK and the control data DT for driving the performance in the performance drive means when viewed from the pattern wiring PTH side to the chip (= the chip of the performance drive means) side" is. In the example of FIG. 59, as shown, the clock CK terminal is on the left and the data DT terminal is on the right.

[0526] The left-right relationship when viewed in the directions DIR2 and DIR4 can also be expressed as in the following examples, and any one of them may be applicable. "The left-right relationship of the clock CK and data DT input terminals in the performance drive means when viewed facing the chip side where the input terminals are located" "The left-right relationship of the clock CK and data DT input terminals in the performance drive means when viewed from the chip side along the introduction direction of the pattern wiring PTH connected to each input terminal"

[0527] In these directions, when the left-right relationship of the connector terminals and the left-right relationship of the terminals of the performance drive means are the same, this can be said to be a left-right relationship in which, even if the connector and the performance drive means are placed on the same surface of the board with their corresponding terminals facing each other and wiring is laid to connect each terminal over the shortest distance, no crossing of the wiring occurs.

[0528] In the example of FIG. 59, the left-right relationship between the clock CK terminal and the data DT terminal is the same when viewed in the directions DIR1, DIR2, DIR3, and DIR4.

[0529] The same left-right relationship may mean that the clock CK terminal is on the left and the data DT terminal is on the right, or that the clock CK terminal is on the right and the data DT terminal is on the left. This also applies to the configurations described below other than (Configuration A1-1).

[0530] The configuration shown in FIG. 59 corresponds to the above-mentioned (Configuration A1-1). The following (Specific Example 1) is assumed as an example corresponding to this (Configuration A1-1).

[0531] (Example 1) First board: LED board 780 (see FIG. 45) Second board: LED board 790 (see FIG. 46) Clock (CK) for the first performance driving means: clock signal CLK Control data (DT) for driving the first performance driving means: data signal DATA First performance driving means: LED driver 782 Clock input terminal in the first performance driving means: Terminal 2 (SCLK terminal) Input terminal of control data for driving the first performance driving means: Terminal 3 (SDATA terminal) First connector: Connector CN1N Clock connector pin of the 1st connector: 2nd pin Connector terminal for control data for driving the first connector: 3rd pin Second performance driving means: LED driver 791 Clock (CK) for the second performance driving means: clock signal CLK Control data (DT) for driving the second performance driving means: data signal DATA Clock input terminal for the second performance driving means: Terminal 2 (SCLK terminal) Input terminal of control data for driving the second performance driving means: Terminal 3 (SDATA terminal) Second connector: Connector CN1X Clock connector terminal of the second connector: 2nd pin Connector terminal for control data for driving the second connector: 3rd pin

[0532] In this (Specific Example 1), an LED substrate 780 corresponding to the first substrate is shown in FIGS. FIG. 60 shows the conductor pattern on the front surface layer of an LED substrate 780 having the circuit configuration described in FIG. 45, and FIG. 61 shows the conductor pattern on the back surface layer. The back surface layer in FIG. 61 is shown as a perspective view seen from the front surface layer side in FIG. 60, and is shown in a state in which the left and right are reversed. The identification numbers of the components printed on the board are omitted from Figures 60 and 61. The part shown as "XX+XX△△" actually displays the board control number.

[0533] The plurality of light emitting elements mounted on the LED substrate 780 are light emitting elements LED1 to LED12 as color LED chips and light emitting elements LED14 to LED22 as single color LED chips, as shown in a light emitting section 783 in FIG. "pLED1" to "pLED22" in FIG. 60 (surface layer) indicate positions (pads or lands as contact points, hereinafter collectively referred to as pads) on the LED substrate 780 where the light emitting elements LED1 to LED22 are respectively arranged. Furthermore, "p782" indicates the position (pad) where the LED driver 782 is placed, "pCN1N" and "pCN2N" indicate the positions (pads) where the connectors CN1N and CN2N are placed, and "p781" indicates the position (pad) where the buffer circuit 781 is placed.

[0534] For connector CN1N, the pad on the upper left side of the drawing is the first pin side. For connector CN2N, the pad on the left side of the drawing is the first pin side.

[0535] As shown in FIGS. 60 and 61, a ground pattern 784 is formed as a solid ground on the front and back layers, and pattern wiring for realizing the circuit configuration of FIG. 45 is also formed. The numerous small circular areas shown on the pattern represent through holes or vias. This includes through-hole vias (interlayer wiring) with copper foil. For the sake of explanation, these will also be collectively referred to as "through holes."

[0536] Also, a power supply pattern 785 for 12V DC voltage (DC12VB) is formed mainly on the back surface layer from the contact point (pad) of the first pin of connector CN1N via a through hole TH10 as shown in FIGS. The power supply pattern 785 on the back surface layer is connected to the SVCC terminal of the LED driver 782 by a through hole TH11, and also connected to the VLED terminal of the LED driver 631 via a through hole TH12.

[0537] In the case of the LED substrate 780, in order to supply a 5V DC voltage (DC5V) to the buffer circuit 781, a power supply pattern 786 is formed on the back surface layer from the contact (pad) of the 5th pin of the connector CN1N via a through hole TH15, and is connected to the buffer circuit 781 via a through hole TH16.

[0538] Here, the first to sixth pins of connector CN1N are shown enlarged in the lower left of Figure 60. Looking at the left and right direction in DIR1, the clock signal CLK terminal (second pin) is on the left, and the data signal DATA terminal (third pin) is on the right.

[0539] 60. The LED driver 782 placed at "p782" is placed in the direction (posture) shown in the enlarged view at the top left of FIG.

[0540] A plan view of the LED driver 782 placed at "p782" is shown in Fig. 62. The LED driver 782 is a square chip component. In this example, the chip component is substantially square, but it may of course be rectangular. Also, the corners of the square chip housing are chamfered as shown in the figure, so strictly speaking it is an octagon, but the chamfered parts should not be considered sides, but should be considered as a quadrilateral. "Square shape" means that it is approximately square, ignoring minor shapes such as the chamfered parts.

[0541] Under the above assumptions, the chip serving as the LED driver 782 is rectangular and has four sides. The sides are designated as sides sd1, sd2, sd3, and sd4. Sides sd1 and sd3 are opposite each other, and sides sd2 and sd4 are opposite each other. The terminals of the LED driver 631 shown in Figure 62 are provided on side sd1 with terminals 1 (VREF) to 12 (A1), on side sd2 with terminals 13 (A2) to 24 (LEDG3), on side sd3 with terminals 25 (LEDB3) to 36 (LEDR6), and on side sd4 with terminals 37 (LEDG6) to 48 (SVCC).

[0542] Terminal 1 (VREF) is the 5V reference voltage output terminal. Terminal 2 (SCLK) is the input terminal for the clock signal CLK. Terminal 3 (SDATA) is an input terminal for the data signal DATA. Terminal 4 (SDEN) is an enable signal input terminal. Terminal 5 (CTLSCT) is a serial bus communication setting terminal, and the reference voltage from terminal 1, that is, H level, is input to set the specified mode. Terminal 6 (OUTSCT) is an output mode control terminal for the LED drive current, and in this example is set to L level by being connected to ground, and is set to a predetermined mode, for example, constant current output. Terminal 7 (RESET) is the input terminal for the reset signal RESET. Terminal 8 (RT1) is a resistor connection terminal for setting the reference current. In this example, resistor R1T is connected. Terminals 9 and 31 (NC) are dummy terminals (no internal connection). Terminal 10 (SGND) is the ground terminal.

[0543] Terminals 11 to 15 (A0 to A4) are address terminals for setting a slave address. In this example, as shown in Fig. 75, A0, A1, and A2 are connected to ground, and A3 and A4 are connected to a reference voltage of 5V, so that the slave address of the LED driver 631 becomes "00011."

[0544] Terminals 16 to 45 (excluding terminals 30 and 31) are formed with terminals (LEDR1 to LEDB8) for LED light emission drive current and ground terminals (PGND1 to PGND4).

[0545] Terminals 46 and 47 are test terminals and are connected to ground. As mentioned above, terminal 48 (SVCC) is the operating power supply terminal, and terminal 30 (VLED) is the protection terminal for the LED drive output.

[0546] The same type of chip as shown in FIG. 62 can also be used for LED drivers mounted on other substrates, such as LED driver 631 on the LED substrate on the side unit and LED driver 791 on LED substrate 790.

[0547] If we apply the terminal arrangement in Figure 62 to Figure 60, the left-right relationship when viewed in direction DIR2 for the LED driver 782 is such that the terminal for the clock signal CLK (terminal No. 2 (SCLK terminal)) is on the left and the terminal for the data signal DATA (terminal No. 2 (SCLK terminal)) is on the right.

[0548] Between the connector CN1N and the LED driver 782, a clock pattern wiring 787 for the clock signal CLK is formed, and a signal pattern wiring 788 for the data signal DATA is formed.

[0549] Next, an LED substrate 790 corresponding to the second substrate in the above (Specific Example 1) is shown in Figures 63 and 64. Figure 63 shows the conductor pattern on the front surface layer of LED substrate 790 having the circuit configuration explained in Figure 46, and Figure 64 shows the conductor pattern on the back surface layer. The back surface layer in FIG. 64 is shown as a perspective view seen from the front surface layer side in FIG. 63, and is shown in a state in which the left and right are reversed. The identification numbers of the components printed on the board are omitted from Figures 63 and 64. The part shown as "X○+○○○" actually displays the board control number.

[0550] The plurality of light emitting elements mounted on the LED substrate 790 are light emitting elements LED1 to LED9 as color LED chips and light emitting elements LED10 to LED17 as single color LED chips, as shown in a light emitting section 792 in FIG. 63 (surface layer), "pLED1" to "pLED17" indicate positions (pads) where the light emitting elements LED1 to LED17 are respectively arranged on the LED substrate 790. Also, "p791" indicates the position (pad) where the LED driver 791 is arranged, and "pCN1X" indicates the position (pad) where the connector CN1X is arranged.

[0551] As shown in FIGS. 63 and 64, a ground pattern 794 is formed as a solid ground on the front and back layers, and pattern wiring and through holes for realizing the circuit configuration of FIG. 46 are also formed.

[0552] Here, the right side of Figure 63 shows an enlarged view of pins 1 to 4 of connector CN1X. Looking at the direction DIR3, the clock signal CLK terminal (pin 2) is on the left, and the data signal DATA terminal (pin 3) is on the right.

[0553] The LED driver 791 placed at "p791" is placed in the orientation (posture) shown in the enlarged view at the top right of Fig. 63. The terminal arrangement of the LED driver 791 is as shown in Fig. 62. Therefore, if we apply the terminal arrangement in Figure 62 to Figure 63, the left-right relationship when viewed in direction DIR4 for the LED driver 791 is that the terminal for the clock signal CLK (terminal No. 2 (SCLK terminal)) is on the left, and the terminal for the data signal DATA (terminal No. 3 (SDATA terminal)) is on the right.

[0554] Between the connector CN1X and the LED driver 791, a clock pattern wiring 795 for the clock signal CLK is formed, and a signal pattern wiring 796 for the data signal DATA is formed.

[0555] The LED substrates 780 and 790 described above have the following configuration. On the LED board 780, the connector CN1N and the LED driver 782 are arranged on the same surface of the board. On the LED board 790, the connector CN1X and the LED driver 791 are arranged on the same surface of the board. When viewed in the directions DIR1, DIR2, DIR3, and DIR4, the left-right relationship between the clock signal CLK terminal and the data signal DATA terminal is the same in all cases.

[0556] Therefore, this corresponds to the configuration shown in FIG. The configuration of FIG. 59 provides the following effects. The wiring for the clock CK between the first connector and the first performance drive means and the wiring for the performance drive control data DT can be extended in the same direction from the connector and can be continued to the performance drive means without crossing each other, which makes it possible to improve the efficiency of wiring on the first board and shorten the wiring length. This is advantageous when you want to perform wiring that does not go through other layers. Specifically, as shown in FIG. 60, clock pattern wiring 787 and signal pattern wiring 788 are formed without crossing each other, thereby realizing efficient wiring and shortening of wiring length.

[0557] Furthermore, the clock CK wiring and data DT wiring from the first connector can be led out in the same direction (from the same side of the connector housing). This means that one of the clock CK wiring and data DT wiring does not need to be routed around from the opposite side to adjust the left-right relationship. This also eliminates the need for wiring that routes around in the opposite direction from such a connector. This is effective in improving wiring efficiency and shortening wiring length.

[0558] This also eliminates the need for unnecessary wiring, shortening the wiring length and reducing noise contamination. Reducing noise contamination makes the performance more stable. In particular, the clock CK and data DT are signals that directly control the generation of the performance drive signal by the performance drive means at each point in time. Therefore, at least for this set of clock CK and data DT, the wiring is made more efficient and noise contamination is reduced, resulting in the effect of improving the stability of performance operations (LED lighting and the movement of movable objects by motors). Although other signal wiring such as a reset signal may be used between the connector and the performance drive means, the clock CK and data DT are signals that directly affect performance operation at all times and have the highest average frequency. Ensuring that the wiring for such clock CK and data DT does not cross each other and improving the efficiency of the wiring is effective in reducing the effects of noise and ensuring stable performance operation. The advantage of efficient wiring for the set of clock CK and data DT is the same for (Configuration A1-2) to (Configuration A9-3) described later.

[0559] The above effects can also be obtained on the second substrate. Furthermore, by adopting the same left-right terminal relationship on the second board as on the first board, it is possible to efficiently wire from the connector to the driver using multiple boards. Specifically, as shown in FIG. 60, clock pattern wiring 787 and signal pattern wiring 788 are formed without intersecting, and as shown in FIG. 63, clock pattern wiring 795 and signal pattern wiring 796 are formed without intersecting. This improves the wiring efficiency of multiple boards within the gaming machine 1, reduces noise interference, and improves design efficiency, promoting stable performance.

[0560] In addition, the left-right relationship of the pins assigned to the connector's clock CK and data DT is standardized across multiple boards, such as the first and second boards, making it easier to draw circuit diagrams and design wiring. This not only improves design efficiency, but is also useful for developing new gaming machines.

[0561] In addition, in the case of (Specific Example 1), the above effects are more easily achieved by adopting the configuration of Fig. 59 between the boards connected in series as the LED boards 780 and 790. Sharing the boards connected to each other is also suitable for circuit design and maintenance.

[0562] The gaming machine 1 of the embodiment has the following (Configuration A1-2) in addition to (Configuration A1-1). (Configuration A1-2) The gaming machine 1 is a third board provided with a third connector for inputting a clock and performance drive control data for the third performance drive means; The left-right relationship of each connector terminal for the clock and the control data for driving the performance in the third connector when viewed from the side of each connector terminal in the direction in which the pattern wiring connected to each connector terminal is derived is the same as that of the first connector.

[0563] The first, second, and third substrates in this (Configuration A1-2) are shown schematically in Figure 65. The first and second substrates are the same as those in Figure 59, but Figure 65 adds a third substrate.

[0564] The third board is equipped with a third connector. From the third connector, pattern wiring PTH for clock CK and data DT is led out.

[0565] In this figure, the third performance driving means is not shown on the third board, but it is one of the following. The third performance driving means is mounted on the same surface as the third connector on the third board. The third performance driving means is mounted on a different side of the third board from the third connector. The third performance driving means is mounted on another board downstream of the third board.

[0566] The direction DIR5 is the direction in which the pattern wiring PTH connected to each connector terminal of the clock CK and data DT of the third connector is led out from the connector terminal side of the clock CK and data DT. In this example, the clock CK terminal is on the left and the data DT terminal is on the right.

[0567] The left-right relationship between the clock CK terminal and the data DT terminal when viewed in the directions DIR1, DIR2, DIR3, DIR4, and DIR5 is shown at the bottom of Figure 65, and the left-right relationship between the clock CK terminal and the data DT terminal is the same for all.

[0568] As an example corresponding to (Configuration A1-2) as shown in FIG. 65, the first and second substrates are assumed to be the above (Specific Example 1), and the third substrate is assumed to be the following (Specific Example 2).

[0569] (Example 2) Third board: LED board 630 on the side unit (see Figure 32) Clock (CK) for the third performance driving means: clock signal CLK Control data (DT) for driving the third performance driving means: data signal DATA Third connector: Connector CN1T Third connector clock connector terminal: 2nd pin Connector terminal for control data for driving the third connector: 3rd pin

[0570] In this (Specific Example 2), the LED substrate 630 on the side unit, which corresponds to the third substrate, is shown in FIGS. FIG. 66 shows the conductor pattern on the front surface layer of the LED substrate 630 on the side unit, and FIG. 67 shows the conductor pattern on the back surface layer.

[0571] The back surface layer in Figure 67 is shown as a perspective view from the front surface layer side in Figure 66, and the conductor pattern and board control number are shown in a state that is reversed left to right from the state in which the back surface of the board is normally viewed. In Figures 66 and 67, the component identification numbers printed on the board are omitted. The part shown as "○○+xxx△" actually displays the board control number.

[0572] On the front surface layer in FIG. 66 and the back surface layer in FIG. 67, a ground pattern 633 as a solid ground and pattern wiring that realizes the circuit configuration in FIG. 32 are formed. "pLED1" to "pLED10" in FIG. 66 (surface layer) indicate the positions (pads) where the light emitting elements LED1 to LED10 in FIG. 32 are respectively arranged. "p631" in FIG. 67 (back surface layer) indicates the position (pad) where the LED driver 631 is arranged, and "pCN1T" indicates the position (pad) where the connector CN1T is arranged.

[0573] As for the pads for connector CN1T, as shown enlarged at the top of the figure, the pad on the right side of the drawing is for the first pin, and the pad on the left side is for the sixth pin. Therefore, in terms of the left-right relationship when viewed in the direction DIR5, the terminal (second pin) for the clock signal CLK of the connector CN1T is on the left, and the terminal (third pin) for the data s...

Claims

[Claim 1] A substrate on which a performance driving means is provided, The performance driving means A power supply input terminal to which a first power supply voltage is input, a plurality of address terminals to set slave addresses, and a power supply output terminal to output a reference voltage in the performance drive means which is a voltage value different from the first power supply voltage; The address terminal set to H level is connected to the power supply output terminal via a first pattern wiring on a surface of the substrate different from the mounting surface of the performance drive means, The address terminal set to the L level is connected to the solid ground of the mounting surface, The length of the second pattern wiring from the address terminal set to the L level to the solid ground is shorter than the length of the first pattern wiring. Gaming machine.

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