Semiconductor integrated circuits, substrate products, substrate product communication devices

Abstract

To provide a semiconductor integrated circuit which includes a bus driver which can reduce a sudden change in a waveform on an external bus.SOLUTION: A semiconductor integrated circuit comprises: a conductor which is configured to be connected to a bus; and an open drain type bus driver which is connected to the conductor. The bus driver includes a drive circuit which includes a driving transistor in a high breakdown voltage structure having a first threshold, a control line which is connected to a gate electrode of the driving transistor, and a pre-stage circuit which receives a signal output to the bus and connected to the control line. The pre-stage circuit includes a first detection circuit and a charging circuit. The first detection circuit is configured to detect whether or not the voltage on the control line crosses a first detection threshold and is connected to the control line to provide a first detection signal indicating a detection result. The charging circuit charges the control line with the current of the initial charging current value in response to the first signal from the input, and charges the control line with the current of the first current value smaller than the initial charging current value in response to the first detection signal from the first detection output.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit including a bus driver, a substrate product including the semiconductor integrated circuit, and a substrate product communication device including the substrate product. [Background technology]

[0002] Patent Document 1 discloses a high-speed driver circuit that drives a transmission line between a power supply voltage of 2.5V and a reference voltage of 0V. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-332968 Summary of the Invention [Problem to be solved by the invention]

[0004] In a certain technical field, for example, the technical field of semiconductor integrated circuits mounted on vehicles, a semiconductor integrated circuit or a circuit board mounting a semiconductor integrated circuit communicates with another circuit board or semiconductor integrated circuit via an external bus that operates under a power supply system with a voltage higher than 3.3 V, for example, a 12 V power supply system. For this communication, the semiconductor integrated circuit includes a transceiver for communication.

[0005] The bus for this communication has a wide range of voltage amplitudes. Therefore, the change of the rectangular voltage waveform due to the transition of the signal to be transmitted generates radiated noise. Therefore, the communication uses a slope waveform for the rising and falling transitions of the voltage amplitude of the external bus.

[0006] However, a closer examination of the slope waveforms of the rising and falling transitions reveals that the waveforms at the beginning of the transition from a high potential power supply level and / or at the end of the transition from a low potential power supply level exhibit larger time variations over a given time interval than the intermediate waveform variations during each of these transitions.

[0007] An object of the present invention is to provide a semiconductor integrated circuit including a bus driver capable of reducing abrupt changes in the waveform on an external bus, a board product including this semiconductor integrated circuit, and a board product communication device including the board product. [Means for solving the problem]

[0008] A semiconductor integrated circuit according to a first aspect of the present invention includes a conductor configured to be connected to a bus to be driven, and a bus driver connected to the conductor, wherein the bus driver includes a drive circuit including an open-drain drive transistor connected between a first reference potential line and the conductor and having a first threshold, a control line connected to a gate electrode of the drive transistor, and a front-end circuit connected to the control line, the front-end circuit having an input configured to receive a signal output to the bus, the front-end circuit including a first detection circuit configured to detect whether a voltage on the control line has crossed a first detection threshold, the first detection circuit having a first input connected to the control line and a first detection output providing a result of the detection, and a charging circuit that charges the control line with a current of an initial charging current value in response to a first signal from the input, and that charges the control line with a current of a first current value smaller than the initial charging current value in response to a first detection signal from the first detection output, and the drive transistor has a high-voltage structure.

[0009] A semiconductor integrated circuit according to a second aspect of the present invention is according to the first aspect, wherein the pre-stage circuit includes a second detection circuit configured to detect whether the voltage on the control line has crossed a second detection threshold, and has a second input connected to the control line and a second detection output providing a result of the detection, and the charging circuit charges the control line with a current of a second current value greater than the first current value in response to a second detection signal from the second detection output, and the first detection threshold is smaller than the second detection threshold.

[0010] A semiconductor integrated circuit according to a third aspect of the present invention is according to the second aspect, and each of the first detection circuit and the second detection circuit includes a first transistor having a gate electrode connected to the control line, a source electrode connected to the first reference potential line, and a drain electrode, and having the first threshold value, and a first load circuit connected to the drain electrode of the first transistor, and the first transistor has the high-voltage structure.

[0011] A fourth aspect of the present invention relates to the semiconductor integrated circuit of the third aspect, wherein the pre-stage circuit includes a constant current source circuit, and the constant current source circuit is configured to be connected to the charging circuit and enable the charging circuit to provide a constant current for the first current value and the initial charging current value, and the first load circuit includes a first switch that conducts in response to the first signal and a first constant current source connected to the drain electrode of the first transistor, and the first constant current source is connected to the constant current source circuit.

[0012] A semiconductor integrated circuit according to a fifth aspect of the present invention is according to the second, third or fourth aspect, wherein the pre-stage circuit further includes a discharge circuit, which discharges the control line with a current of an initial discharge current value in response to a second signal from the input that is different from the first signal, and discharges the control line with a current of a third current value smaller than the initial discharge current value in response to the second detection signal.

[0013] A sixth aspect of the present invention relates to a semiconductor integrated circuit according to any one of the first to fifth aspects, and includes a receiver having an input connected to the conductor and receiving a signal from the bus via the conductor; and a signal processing circuit configured to process the signal for a single-wire communication protocol of the bus, wherein the receiver provides the received signal to the signal processing circuit, and the signal processing circuit provides a signal to be output to the bus to the input of the previous stage circuit.

[0014] A semiconductor integrated circuit according to a seventh aspect of the present invention is according to any one of the first to sixth aspects, and the bus is connected to a second reference potential line different from the first reference potential line via a resistor.

[0015] A substrate product according to an eighth aspect of the present invention comprises a semiconductor chip including a semiconductor integrated circuit according to any one of the first to sixth aspects described above, a connector, and a circuit board carrying the semiconductor chip and the connector and having a conductor layer patterned to connect the semiconductor chip and the connector.

[0016] A board product communication device according to a ninth aspect of the present invention comprises a first board product according to the eighth aspect described above, a second board product according to the eighth aspect described above, and a single conductive line connecting the conductors of the first board product and the conductors of the second board product to each other via the connector of the first board product and the connector of the second board product.

[0017] A board product communication device according to a tenth aspect of the present invention is in accordance with the ninth aspect and further comprises a resistor mounted on the circuit board of at least one of the first board product and the second board product, the resistor being connected via the conductor layer between a second reference potential line different from the first reference potential line and the output of the bus driver.

[0018] A substrate product communication device according to an eleventh aspect of the present invention is one that conforms to the ninth aspect, wherein the semiconductor chip of at least one of the first substrate product and the second substrate product further includes a resistor connected via the conductor layer between a second reference potential line different from the first reference potential line and the output of the bus driver. [Effects of the Invention]

[0019] In a bus driver for a semiconductor integrated circuit according to a first aspect, a charging circuit is operable in response to a first signal from an input of a preceding circuit to charge a control line with a current of an initial charging current value, thereby raising the potential of the control line. A first detection circuit generates a first detection signal from a first detection output when it detects that the voltage on the control line is equal to or greater than a first detection threshold, which is greater than a first threshold. In response to the first detection signal, the charging circuit charges the control line with a current of a first current value less than the initial charging current value. Switching to charging with a current of the smaller first current value reduces the rate at which the potential of the control line rises. The slow rate at which the potential of the control line rises allows the drive transistor to change the potential of the bus more slowly. The gradual change in the bus potential reduces noise caused by bus transitions.

[0020] In a bus driver of a semiconductor integrated circuit according to a second aspect, the second detection circuit generates a second detection signal from a second detection output when it detects that the voltage on the control line is equal to or greater than a second detection threshold greater than the first detection threshold. The charging circuit charges the control line with a current having a second current value greater than the first current value in response to the second detection signal. Switching to charging with a current having a larger second current value controls the rate of change of the potential of the control line and increases the rate of rise. The high rate of rise of the control line potential allows the drive transistor to quickly change the bus potential. Switching the rate of rise of the bus potential allows the bus transition to be completed while avoiding noise generation.

[0021] According to the bus driver of the semiconductor integrated circuit of the third aspect, since both the drive transistor and the first transistor have a high-voltage structure, it becomes easy to adjust the first detection threshold of the first detection circuit to the conductive and non-conductive states of the drive transistor.

[0022] In the bus driver of the semiconductor integrated circuit according to the fourth aspect, the first load circuit including the constant current source facilitates setting of the first detection threshold and low current consumption.

[0023] In a fifth aspect of the semiconductor integrated circuit bus driver, the discharge circuit is operable in response to a second signal from the input of the preceding circuit, and discharges the control line with a current of an initial discharge current value to lower the potential of the control line. The second detection circuit generates a second detection signal from a second detection output when it detects that the voltage on the control line is equal to or less than a second detection threshold. In response to the second detection signal, the discharge circuit discharges the control line with a current of a third current value less than the initial discharge current value. Switching to discharging with a current of the third current value, which is smaller than the initial discharge current value, reduces the rate at which the potential of the control line drops. The slow rate at which the control line potential drops allows the drive transistor to gradually change the potential waveform as the bus approaches the potential of the high-potential line. The gradual change in bus potential reduces noise caused by bus transitions.

[0024] In the semiconductor integrated circuit according to the sixth aspect, the receiver and the bus driver are both connected to the conductor, so that the semiconductor integrated circuit can provide communication based on a single-wire communication protocol.

[0025] In the semiconductor integrated circuit according to the seventh aspect, the resistor functions as a pull-up resistor for the open-drain bus driver.

[0026] According to the eighth aspect of the present invention, a semiconductor chip including a semiconductor integrated circuit is mounted on a circuit board to provide a board product capable of communication via a high-voltage bus.

[0027] According to the board product communication device of the ninth aspect, a semiconductor chip including a semiconductor integrated circuit is mounted on a circuit board to provide a board product capable of communication via a high-voltage bus.

[0028] A board product communication device according to a tenth aspect provides a resistor provided on a circuit board.

[0029] According to an eleventh aspect of the present invention, a substrate product communication device is provided that includes a resistor integrated with a bus driver on a semiconductor chip. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor integrated circuit according to the present embodiment. [Figure 2] FIG. 2 is a diagram showing transition waveforms of a bus driven by a transceiver according to this embodiment and signal waveforms provided to the transceiver. Part (a) of FIG. 2 shows the waveform of a transmission signal from the signal processing circuit 35. Part (b) of FIG. 2 shows the waveform of a bus driven by the signal processing circuit shown in part (a) of FIG. 2. Part (c) of FIG. 2 shows the falling waveform (WF) shown in part (b) of FIG. 2. Part (d) of FIG. 2 shows the rising waveform (WR) shown in part (b) of FIG. 2. [Figure 3] FIG. 3 is a circuit diagram showing a specific example of a charging circuit for controlling the discharge of the control line. [Figure 4] FIG. 4 is a circuit diagram showing a specific example of a discharge circuit for controlling the discharge of the control line. [Figure 5] FIG. 5 is a diagram schematically illustrating the operation of a front-end circuit of a semiconductor integrated circuit according to an embodiment. Part (a) of FIG. 5 is a diagram illustrating the waveform of the detection output of a detection circuit. Part (b) of FIG. 5 is a diagram illustrating bus waveforms with and without the front-end circuit according to this embodiment. In part (b) of FIG. 5, the solid line illustrates the bus transition waveform of a bus driver using a front-end circuit, and the dashed line illustrates the bus transition waveform of a bus driver without the front-end circuit. Part (c) of FIG. 5 illustrates the potential waveform of a control line. Part (d) of FIG. 5 is a diagram illustrating an example of switching the charging current of a charging circuit. [Figure 6] FIG. 6 is a diagram schematically illustrating the operation of a front-end circuit of a semiconductor integrated circuit according to an embodiment. Part (a) of FIG. 6 is a diagram illustrating the waveform of the detection output of the detection circuit. Part (b) of FIG. 6 is a diagram illustrating the bus waveform with and without the front-end circuit according to this embodiment. In part (b) of FIG. 6, the solid line shows the bus transition waveform of a bus driver using a front-end circuit, and the dashed line shows the bus transition waveform of a bus driver without a front-end circuit. Part (c) of FIG. 6 shows the potential waveform of a control line. Part (d) of FIG. 6 is a diagram illustrating an example of switching the discharge current of a discharge circuit. [Figure 7] FIG. 7 is a circuit diagram showing a detection circuit according to this embodiment. [Figure 8] FIG. 8 is a circuit diagram showing circuits related to the detection circuit according to this embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing an example of a high-voltage structure of a driving transistor. [Figure 10] FIG. 10 is a diagram schematically showing a substrate product according to this embodiment. [Figure 11] FIG. 11 is a diagram schematically illustrating a board product communication system including a board product according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations will be omitted.

[0032] 1 is a diagram schematically illustrating a semiconductor integrated circuit according to this embodiment. The semiconductor integrated circuit 11 includes a conductor 13 configured to be connected to a bus 10 to be driven, and a bus driver 15 connected to the conductor 13. The bus driver 15 includes an open-drain drive circuit 17, a control line 19, and a pre-stage circuit 21. The conductor 13 is a member for electrically connecting the semiconductor integrated circuit 11 to the outside, and can be, for example, an electrode such as a pad electrode or a bump electrode.

[0033] The drive circuit 17 includes a drive transistor 23 having a first threshold voltage, but does not include a drive transistor directly connected to the high-voltage line VH. The drive transistor 23 has a gate electrode G connected to the control line 19, a source electrode S connected to the low-voltage line VL, and a drain electrode D connected between the low-voltage line VL and a conductor. The drive transistor 23 has a high-voltage structure, which is provided, for example, by a double-diffused lateral MOS transistor. The double-diffused lateral MOS transistor has a double-diffused drain structure and a thick gate insulating film that can withstand the high voltage (HHV) of the bus 10. To indicate a field-effect transistor with a high-voltage structure, FIG. 1 depicts the gate electrode as a rectangle and the drain electrode as a circle. In the following description, the gate electrode, drain electrode, and source electrode of the field-effect transistor are referred to by the symbols "G," "D," and "S," respectively. The low-voltage line VL and the high-voltage line VH provide their respective reference potentials. "HHV" indicates a potential level greater than the high-voltage line VH.

[0034] The semiconductor integrated circuit 11 may include a receiver 33 and a signal processing circuit 35. The receiver 33 receives a signal from the bus. The receiver 33 has an input 33a and an output 33b, and the input 33a receives a signal from the bus 10 via a conductor 13 connected to the conductor 13, and the output 33b provides a signal at the high potential line VH system level to the signal processing circuit 35. The receiver 33 includes a field effect transistor with a high breakdown voltage structure having a gate electrode connected to the conductor line from the input 33a.

[0035] FIG. 2 shows the transition waveforms of a bus driven by a transceiver according to this embodiment and the waveform of a signal provided to the transceiver. Part (a) of FIG. 2 shows the waveform of a transmission signal from the signal processing circuit 35. Part (b) of FIG. 2 shows the waveform of a bus driven by the bus driver 15 shown in part (a) of FIG. 2. Part (c) of FIG. 2 shows the falling waveform (WF) shown in part (b) of FIG. 2. Part (d) of FIG. 2 shows the rising waveform (WR) shown in part (b) of FIG. 2.

[0036] The signal processing circuit 35 is configured to process signals for a single-wire communication protocol (e.g., CXPI, LIN) of the bus 10, for example. CXPI is an abbreviation for Clock Extension Peripheral Interface, and LIN is an abbreviation for Local Interconnect Network. Specifically, the signal processing circuit 35 can process a received signal received from the bus 10 and generate a transmit signal SIG to be transmitted to the bus 10. The transmit signal SIG is provided to an input 21a of the pre-stage circuit 21. In the semiconductor integrated circuit 11, the bus driver 15 and the receiver 33 are both connected to the conductor 13, so that the semiconductor integrated circuit 11 includes a transceiver that can provide communication based on a single-wire communication protocol.

[0037] The bus 10 is connected to a high potential line HHV (a power supply system higher than the high potential line VH, for example, 12 volts) different from the high potential line VH via a resistor 37. In the semiconductor integrated circuit 11, the resistor 37 functions as a pull-up resistor for the open-drain bus driver 15. This pull-up resistor may be, for example, about 0.5 to 1.0 kilohms.

[0038] In addition to the drive transistor 23, the drive circuit 17 may include a capacitor 39 connected to the gate electrode G of the drive transistor 23. The capacitor 39 has a capacitance value greater than the gate capacitance of the drive transistor 23. The capacitance value of the capacitor 39 may be, for example, 10 picofarads.

[0039] The front end circuit 21 is connected to the control line 19 and has an input 21a configured to receive a signal SIG to be output to the bus 10. The front end circuit 21 includes one or more detection circuits 24, such as a first detection circuit 25 and a second detection circuit 29, and further includes a charging circuit 27 and a discharging circuit 28. The charging circuit 27 and the discharging circuit 28 are connected to the control line 19 and control the potential of the control line 19.

[0040] The sensing circuit 24 has an input 24a connected to the control line 19 and an output 24b that provides a signal for controlling the charging circuit 27 and the discharging circuit 28. Specifically, the first sensing circuit 25 is configured to sense whether the voltage on the control line 19 crosses a first sensing threshold DTH1. The first sensing circuit 25 has a first input 25a connected to the control line 19 and a first sensing output 25b that provides the result of the sensing. The second sensing circuit 29 is configured to sense whether the voltage on the control line 19 crosses a second sensing threshold DTH2. The second sensing circuit 29 has a second input 29a connected to the control line 19 and a second sensing output 29b that provides the result of the sensing.

[0041] The charging circuit 27 controls the change in the potential of the control line 19 in response to signals from the detection circuits 24, such as the first detection circuit 25 and the second detection circuit 29. Specifically, the charging circuit 27 charges the control line 19 with a current of an initial charging current value in response to a first signal SB1 (a value that activates the charging circuit 27 and deactivates the discharging circuit 28) from the input 21a, and changes the charging current in response to a first detection signal SD1 from the first detection output 25b to charge the control line 19. This changed charging current has a first current value that is smaller than the initial charging current value. The charging circuit 27 further changes the charging current in response to a second detection signal SD2 from the second detection output 29b to charge the control line 19. This further charging current has a second current value that is greater than the first current value.

[0042] FIG. 3 is a circuit diagram showing a specific example of a charging circuit for controlling the discharge of the control line 19. In FIG.

[0043] To control the potential of the control line 19, the charging circuit 27 includes transistors 27a, 27b, 27c, and 27d (for example, four) for multiple constant current sources, and transistors 27e, 27f, 27g, and 27h as switches. The charging circuit 27 also has a control input 27i that receives multiple control signals (CNTL1) for switching these switches (27e, 27f, 27g, and 27h), and a signal input 27k that receives a signal to be output to the bus 10. The transistors 27a, 27b, 27c, and 27d are each connected to a constant current source circuit 51, which generates a constant current using a current mirror circuit CM5. The transistors 27e, 27f, 27g, and 27h operate as switches for switching the constant current sources (27a, 27b, 27c, and 27d). The signal input 27k is connected to the gate electrode of the transistor 27j, and the control input 27i is connected to the gate electrodes G of the respective transistors 27e, 27f, 27g, 27h. The transistor 27j activates the charging circuit 27 in response to a first signal SB1 from the signal input 27k.

[0044] Transistors 27e, 27f, 27g, and 27h select at least one of the constant current source transistors 27a, 27b, 27c, and 27d (i.e., one or more current sources) to enable charging circuit 27 to generate the desired charging current.

[0045] Referring to FIG. 1 , the discharge circuit 28 controls the change in the potential of the control line 19 in response to signals from the detection circuits 24, e.g., the first detection circuit 25 and the second detection circuit 29. Specifically, the discharge circuit 28 discharges the control line 19 with a current of an initial discharge current value in response to a second signal SB2 from the input 21a (a value that activates the discharge circuit 28 and deactivates the charge circuit 27). The second signal SB2 has a value different from the first signal SB1. The discharge circuit 28 then continues discharging the control line 19 by changing the discharge current in response to a second detection signal SD2 from the second detection output 29b. This changed discharge current is a third current value that is smaller than the initial discharge current value. The discharge circuit 28 further changes the discharge current in response to a first detection signal SD1 from the first detection output 25b to discharge the control line 19. This further discharge current is a fourth current value that is greater than the third current value.

[0046] FIG. 4 is a circuit diagram showing a specific example of a discharge circuit for controlling the discharge of the control line 19. In FIG.

[0047] The discharge circuit 28 includes transistors 28a, 28b, 28c, and 28d (for example, four) for multiple constant current sources, and transistors 28e, 28f, 28g, and 28h as switches. The discharge circuit 28 also has a control input 28i that receives multiple control signals (CNTL2) that switch these switches (28e, 28f, 28g, and 28h), and a signal input 28k that receives a signal to be output to the bus 10. The transistors 28d, 28e, 28f, and 28h are each connected to a constant current source circuit 51 and generate a constant current using a current mirror circuit CM6. The transistors 28e, 28f, 28g, and 28h operate as switches that switch the constant current sources (28a, 28b, 28c, and 28d). The signal input 28k is connected to the gate electrode G of the transistor 28j, and the control input 28i is connected to the gate electrodes G of the respective transistors 28e, 28f, 28g, 28h. The transistor 28j activates the discharge circuit 28 in response to a second signal SB2 from the signal input 28k.

[0048] Transistors 28e, 28f, 28g, and 28h select at least one of the constant current source transistors 28a, 28b, 28c, and 28d (i.e., one or more current sources) to enable discharge circuit 28 to generate the desired discharge current.

[0049] 1, the pre-stage circuit 21 may further include a control circuit 30, which generates control signals (CNTL1, CNTL2) that cause the charging circuit 27 and the discharging circuit 28 to perform desired operations based on the detection signals (SD1, SD2, SD3) from the detection circuits (25, 29, 31), respectively. The control circuit 30 has a logic circuit that generates the control signals (CNTL1, CNTL2) based on the detection signals (SD1, SD2, SD3).

[0050] FIG. 5 is a diagram illustrating the operation of the front-end circuit 21 of the semiconductor integrated circuit 11 according to the embodiment. Part (a) of FIG. 5 illustrates waveforms from the detection outputs (25b, 29b, 31b) of the detection circuits (25, 29, 31). Part (b) of FIG. 5 illustrates bus waveforms with and without the front-end circuit 21 according to the embodiment. In part (b) of FIG. 5, the solid line and dashed line respectively represent the bus transition waveforms of the bus driver 15 using the front-end circuit 21 and the bus transition waveforms of the bus driver without the front-end circuit. Part (c) of FIG. 5 illustrates the potential waveform of the control line 19. Part (d) of FIG. 5 illustrates an example of switching the charging current of the charging circuit 27.

[0051] During a rising transition of the bus 10, the control line 19 is charged from the voltage of the low potential line VL (eg, ground potential).

[0052] According to the bus driver 15 of the semiconductor integrated circuit 11, the charging circuit 27 responds to the first signal SB1 from the input 21a of the pre-stage circuit 21 to generate an initial charging current value I 01(For example, the current of IC1 + IC2) charges the control line 19 to raise the potential of the control line 19. When the first detection circuit 25 detects that the voltage on the control line 19 is equal to or greater than the first detection threshold DTH1 greater than the first threshold value of the drive transistor 23, the first detection signal SD1 is generated from the first detection output 25b. The charging circuit 27 charges the control line 19 with a first current value I1 smaller than the initial charging current value I 01 (For example, the current of IC1 or IC1 + IC3 <IC1 + IC2). The switching to charging with the current of the smaller first current value I1 reduces the rising speed of the potential of the control line 19. The low rising speed of the potential of the control line 19 enables the drive transistor 23 to gently change the potential of the bus 10. This gentle change can reduce the noise caused by the bus transition.

[0053] In the semiconductor integrated circuit 11 according to the embodiment, the preceding stage circuit 21 further includes a second detection circuit 29. The second detection circuit 29 is configured to detect whether the voltage on the control line 19 has crossed the second detection threshold DTH2, and has a second input 29a connected to the control line 19 and a second detection output 29b that provides the result of the detection. The charging circuit 27 charges the control line 19 with a second current value I2 (for example, IC1 + IC3 + IC4) greater than the first current value I1 in response to the second detection signal SD2 from the second detection output 29b. The second detection threshold DTH2 is greater than the first detection threshold DTH1.

[0054] According to the bus driver 15, when the second detection circuit 29 detects that the voltage on the control line 19 is equal to or greater than the second detection threshold DTH2 greater than the first detection threshold DTH1, the second detection signal SD2 is generated from the second detection output 29b.

[0055] In the semiconductor integrated circuit 11, the charging circuit 27 charges the control line 19 with a second current value I2, which is greater than the first current value I1, in response to the second detection signal SD2. Switching to charging with the larger second current value I2 controls the rate of change in the potential of the control line 19 and increases the rate of rise in the potential of the control line 19. The high rate of rise in the potential of the control line 19 allows the drive transistor 23 to quickly change the potential of the bus. The rapid change in the bus potential allows the transition of the bus 10 to be completed while avoiding the generation of noise.

[0056] In the semiconductor integrated circuit 11 according to the embodiment, the pre-stage circuit 21 includes one or more third detection circuits 31. In one example, the semiconductor integrated circuit 11 includes a single third detection circuit 31, and the addition of the third detection circuit 31 makes it possible to increase the number of times the charging current of the control line 19 is switched.

[0057] Specifically, the third sense circuit 31 is configured to sense whether the voltage on the control line 19 crosses a third sense threshold DTH3, and has a third input 31a connected to the control line 19 and a third sense output 31b providing the result of the sensing. In this embodiment, the third sense threshold DTH3 is less than the second sense threshold DTH2 and greater than the first sense threshold DTH1. According to the bus driver 15, the third sense circuit 31 generates a third sense signal SD3 from the third sense output 31b when it senses that the voltage on the control line 19 is equal to or greater than the third sense threshold DTH3.

[0058] The pre-stage circuit 21 including the third detection circuit 31 changes the potential of the control line 19 as follows.

[0059] In response to the rise in the potential of the control line 19, the first detection circuit 25 generates a first detection signal SD1 from the first detection output 25b. In response to the first detection signal SD1, the charging circuit 27 increases the charging current to an initial charging current value I 01 The smaller first intermediate current value I 11 (e.g., IC1) to charge the control line 19. A smaller first intermediate current value I 11Switching to charging by the current reduces the rising speed of the potential of control line 19. The low rising speed of the potential of control line 19 enables the drive transistor 23 to gently change the potential of bus 10. This gentle change can reduce the noise caused by the bus transition.

[0060] In response to a further rise in the potential of control line 19, the third detection circuit 31 generates a third detection signal SD3 from the third detection output 31b. The charging circuit 27, in response to the third detection signal SD3, sets the charging current to a first intermediate current value I 11 (e.g., IC1) and charges control line 19 with a current of a second intermediate current value I 12 (e.g., IC1 + IC3 < IC1 + IC2). Switching to charging by the current of the slightly larger second intermediate current value I 12 increases the rising speed of the potential of control line 19. The increased rising speed enables the drive transistor 23 to speed up the change in the potential of bus 10 and shorten the time of the transition with a large voltage amplitude.

[0061] In response to a further rise in the potential of control line 19, the second detection circuit 29 provides a second detection signal SD2 from the second detection output 29b. The charging circuit 27, in response to the second detection signal SD2 from the second detection output 29b, charges control line 19 with a current of a second current value I2 (e.g., IC1 + IC3 + IC14) larger than the second intermediate current value I 11 . The change in the bus potential during this period is a monotonic rise, and the influence on noise generation due to the bus transition is small.

[0062] The use of the first intermediate current value I 11 and the second intermediate current value I 12 enables a further gentle transition of the bus potential. Initial charging current value I 01 : For example, IC1 + IC2, transistors 27e and 27f conduct. Transistors 27g and 27h do not conduct. <​​​ Transistors 27f, 27g, and 27h do not conduct. Second intermediate current value I 12 :For example, IC1+IC3, Transistors 27e and 27g are conductive. Transistors 27f and 27h do not conduct. Second current value I2: for example, IC1+IC3+IC14) Transistors 27e, 27g, and 27h are conductive. Transistor 27f does not conduct.

[0063] In this embodiment, by switching in the charging circuit 27, the charging current is set to an initial charging current value I 01 , the first intermediate current value I 11 , the second intermediate current value I 12 , and the second current value I2. For example, the charging current is changed from the initial charging current value I 01 , the second intermediate current value I 12 , the first intermediate current value I 11 , the first current value I1, and the second current value I2. 01 , the first intermediate current value I 11 , the second intermediate current value I 12 , and the second current value I2 is more effective in reducing noise.

[0064] The charging circuit 27 charges the control line 19 with a current (C1+C2) of the second current value I2, regardless of whether the third detection circuit 31 is present. Switching to charging with a current of the larger second current value I2 controls the rate of change of the potential of the control line 19 and increases the rate of rise. The high rate of rise of the potential of the control line 19 allows the drive transistor 23 to quickly change the potential of the bus 10. The rapid change in the potential of the bus 10 allows the transition of the signal waveform on the bus 10 to be completed while avoiding the generation of noise.

[0065] 1, the front-end circuit 21 may further include a discharge circuit 28. The discharge circuit 28 controls the change in the potential of the control line 19 using detection circuits, for example, a first detection circuit 25 and a second detection circuit 29.

[0066] FIG. 6 is a drawing schematically showing the operation of the pre-stage circuit 21 of the semiconductor integrated circuit 11 according to the embodiment. The part (a) of FIG. 6 shows the waveform of the detection output of the detection circuit. The part (b) of FIG. 6 shows the waveform of the bus in the presence or absence of the pre-stage circuit according to the present embodiment. In the part (b) of FIG. 6, the solid line indicates the transition waveform of the bus 10 of the bus driver 15 using the pre-stage circuit 21, and the broken line indicates the transition waveform of the bus of the bus driver without the pre-stage circuit 21. The part (c) of FIG. 6 shows the potential waveform of the control line 19. The part (d) of FIG. 6 shows an example of switching of the discharge current of the discharge circuit 28.

[0067] When there is a falling transition of the bus 10, the control line 19 discharges from the voltage of the high potential line VH. Since the first detection threshold value DTH1 is smaller than the second detection threshold value DTH2, the second detection circuit 29 first detects the falling transition, and then the first detection circuit 25 detects a further falling transition.

[0068] According to the bus driver 15 of the semiconductor integrated circuit 11, the discharge circuit 28 can operate in response to the second signal SB2 from the input 21a of the pre-stage circuit 21, and discharges the control line 19 with a current of an initial discharge current value I 02 (for example, ID1 + ID2), thereby lowering the potential of the control line 19.

[0069] Also, when the second detection circuit 29 detects that the voltage dropping on the control line 19 is equal to or smaller than the second detection threshold value DTH2, the second detection circuit 29 generates a second detection signal SD from the second detection output 31b. The discharge circuit 28 discharges the control line 19 with a current of a third current value I3 (ID1 or ID1 + ID3 < ID1 + ID2) smaller than the initial discharge current value I 02 (ID1 + ID2).

[0070] Then, when the first detection circuit 25 detects that the voltage drop on the control line 19 is equal to or less than the first detection threshold DTH1, it generates a first detection signal SD1 from the first detection output 25b. In response to the first detection signal SD1, the discharge circuit 28 discharges the control line 19 with a current of a fourth current value I4 (e.g., ID1+ID3+ID4) greater than the third current value I3. Switching the discharge current to the larger fourth current value I4 increases the rate at which the potential of the control line 19 falls. The larger rate at which the potential of the control line 19 falls changes the voltage change from a gradual one to a larger one as the bus 10 approaches the potential of the high-potential line HHV. Overall, the gradual change in the potential of the bus 10 can reduce noise caused by bus transitions.

[0071] During a falling transition of the bus 10, the second sense circuit 29 is configured to sense whether the voltage on the control line 19 crosses a second sense threshold DTH2. The discharge circuit 28 responds to a second sense signal SD2 from the second sense output 29b to discharge the control line 19 with a current of a fourth current value I4 (e.g., ID1+ID3+ID4) greater than the third current value I3.

[0072] According to the bus driver 15, the first detection circuit 25 generates a first detection signal SD1 from the first detection output 25b when it detects that the voltage on the control line 19 is equal to or greater than a first detection threshold DTH1 that is less than a second detection threshold DTH2.

[0073] In response to the first detection signal SD1, the discharge circuit 28 discharges the control line 19 with a fourth current value I4, which is greater than the third current value I3. Switching to discharging with the fourth current value I4 controls the rate of change of the potential of the control line 19 and increases the rate of fall of the control line 19. The greater rate of fall of the potential of the control line 19 allows the drive transistor 23 to quickly change the potential of the bus 10 after a gradual transition. The faster change in the bus potential allows the transition of the bus 10 to be completed while avoiding noise generation.

[0074] In the semiconductor integrated circuit 11 according to the embodiment, as already described, the front-end circuit 21 includes one or more third detection circuits 31 for the charging circuit 27, and in one embodiment, a single third detection circuit 31. The discharge circuit 28 uses the single third detection circuit 31 to control the discharge of the control line 19. The addition of the third detection circuit 31 makes it possible to increase the number of switching times of the discharge current of the control line 19.

[0075] Specifically, the third detection circuit 31 is configured to detect whether the voltage on the control line 19 has crossed the third detection threshold value DTH3, and has a third input 31a connected to the control line 19 and a third detection output 31b that provides the result of the detection. In this embodiment, the third detection threshold value DTH3 is smaller than the second detection threshold value DTH2 and larger than the first detection threshold value DTH1. According to this bus driver 15, when the third detection circuit 31 detects that the voltage on the control line 19 is equal to or greater than the third detection threshold value DTH3 (greater than the second detection threshold value DTH2), it generates a third detection signal SD3 from the third detection output 31b.

[0076] The front-end circuit 21 including the third detection circuit 31 changes the potential of the control line 19 as follows when discharging the control line 19.

[0077] In response to the potential drop of the control line 19, the second detection circuit 29 generates a second detection signal SD2 from the second detection output 29b. The discharge circuit 28 discharges the control line 19 with a current of a third intermediate current value I 02 smaller than the initial discharge current value I 31 ]](for example, ID1 + ID3 < IC1 + IC2). The switching to the discharge with the smaller third intermediate current value I 31 lowers the potential drop rate of the control line 19. The low potential drop rate of the control line 19 allows the drive transistor 23 to gently change the potential of the bus 10. This gentle change can reduce the noise caused by the bus transition.

[0078] ​In response to a further drop in the potential of the control line 19, the third detection circuit 31 generates a third detection signal SD3 from the third detection output 31b. In response to the third detection signal SD3, the discharge circuit 28 increases the discharge current to a third intermediate current value I 31 (For example, ID1+ID3) A fourth intermediate current value I 32 (e.g., IC1) to discharge the control line 19. A fourth intermediate current value I 32 Switching to discharging by the current reduces the rate at which the potential of the control line 19 falls. The reduction in the rate at which the potential falls causes the drive transistor 23 to change the potential of the bus 10 more slowly, and the curvature of the transition waveform when the potential of the bus 10 reaches the level of the high potential line HHV becomes gentler.

[0079] In response to a further drop in the potential of the control line 19, the first detection circuit 25 generates a first detection signal SD1 from the first detection output 25b. The discharge circuit 28 generates a second intermediate current value I 32 The control line 19 is further discharged by a current of a larger fourth current value I4 (e.g., ID1+ID3+ID4>ID1+ID3). The change in bus potential during this period makes the drive transistor 23 substantially non-conductive, and therefore has little effect on noise generation due to bus transition.

[0080] Third intermediate current value I 31 and the fourth intermediate current value I 32 The use of allows for a gradual transition of the bus potential. Initial discharge current value I 02 :For example, ID1+ID2, Transistors 28e and 28f are conductive. Transistors 28g and 28h do not conduct. Third intermediate current value I 31 :For example, ID1, Transistor 28e is conductive. Transistors 28f, 28g, and 28h do not conduct. 4th intermediate current value I 32 :For example, ID1+ID3, Transistors 28e and 28g are conductive. Transistors 28f and 28h do not conduct. Fourth current value I4: for example, ID1+ID3+ID4) Transistors 28e, 28g, and 28h are conductive. Transistor 28f does not conduct.

[0081] In this embodiment, the discharge current is switched in the discharge circuit 28 to an initial discharge current value I 02 , the third intermediate current value I 31 , the fourth intermediate current value I 32 , the fourth current value I4. For example, the charging current is changed in the order of the initial charging current value I 01 , the fourth intermediate current value I 32 , the third intermediate current value I 31 , the fourth current value I4. 02 , the third intermediate current value I 31 , the fourth intermediate current value I 32 , and the fourth current value I4 are useful for reducing noise.

[0082] The discharge circuit 28 discharges the control line 19 with a current of a fourth current value I4 (ID1+ID3+ID4), regardless of whether the third detection circuit 31 is present. Switching to a discharge with a current of a larger fourth current value I4 controls the rate of change of the potential of the control line 19 and increases the rate of fall. A large rate of fall of the potential of the control line 19 quickly turns the drive transistor 23 off, preventing the drive transistor 23 from affecting the change in the potential of the bus 10 and allowing the transition of the signal waveform on the bus 10 to be completed without generating noise.

[0083] In this embodiment, the charging circuit 27 and the discharging circuit 28 use common detection circuits (24, 29, 31). The discharging circuit 28 may use detection circuits having a different number and / or detection voltage from the charging circuit 27, and may receive the same technical benefits as the above embodiments.

[0084] FIG. 7 is a circuit diagram showing a detection circuit according to this embodiment. In FIG. 7, in order to indicate a high-voltage structure, the transistor symbol is drawn with a rectangular gate electrode and a circle for the drain electrode. A transistor symbol that does not have a rectangular gate electrode and a circle for the drain electrode indicates a transistor with a thinner gate insulating film than a transistor with a high-voltage structure (a transistor used in a power supply voltage (VH) system, for example, 3.3 volts). In this transistor as well, in the following description, the gate electrode, drain electrode, and source electrode of the field-effect transistor will be referred to by the symbols "G," "D," and "S," respectively.

[0085] In the following description, reference will be made to the first detection circuit 25, but the second detection circuit 29 and the third detection circuit 31 may also have circuitry similar to the first detection circuit 25. However, the detection circuits according to the present disclosure are not limited to the specific circuitry shown in FIG.

[0086] The first detection circuit 25 may include a first transistor 41 (e.g., n-type) having a gate electrode G, a source electrode S connected to a low potential line VL, and a drain electrode D, and a load circuit 43. The gate electrode G, source electrode S, and drain electrode D of the first transistor 41 are connected to a control line 19, the low potential line VL as a first reference potential line, and the load circuit 43, respectively. The load circuit 43 includes a switch (p-type transistor 45) that conducts in response to a first signal SB1 from the input 21a of the previous stage circuit 21, and a constant current source (second transistor 47) connected to the drain electrode D of the first transistor 41. The constant current source includes a second transistor 47 having a gate connected to a constant current source circuit 51, and the second transistor 47 forms a current mirror circuit CM3 with the constant current source circuit 51 to generate a constant current.

[0087] The load circuit 43, which includes a constant current source 47, facilitates setting the detection threshold DTH1 (as well as DTH2, DTH3) and low current consumption.

[0088] 7, the first transistor 41 can have the same first threshold as the drive transistor 23 and the same high-voltage structure as the drive transistor 23. In this bus driver 15, because both the drive transistor 23 and the first transistor 41 have a high-voltage structure, it is easy to adjust the first detection threshold DTH1 of the first detection circuit 25 to the first threshold related to the conduction and non-conduction of the drive transistor 23. Here, the first transistor 41 and the drive transistor 23 have the same first threshold. However, this does not mean that the threshold of the first transistor 41 and the threshold of the drive transistor 23 are strictly identical, and the threshold of the transistor 41 in the detection circuit will differ from the threshold of the drive transistor 23 in the drive circuit 17 due to manufacturing variations.

[0089] The difference between the detection thresholds (DTH1, DTH2, DTH3) is adjusted by the current value of the constant current source provided by the second transistor 47 and the size of the first transistor 41. For example, if the size (width) of the first transistor 41 is fixed, the detection threshold increases as the current value of the second transistor 47 increases. Specifically, in order to make the detection thresholds (DTH1, DTH2, DTH3) different from one another, the first transistors 41 in the multiple detection circuits (e.g., 25, 29, 31) can have different transistor sizes (at least one of the width and length of the gate electrode).

[0090] Furthermore, when the current value of the second transistor 47 as a constant current source is fixed, the detection threshold decreases as the size (width) of the first transistor 41 increases. Alternatively, when the size (width) of the first transistor 41 is fixed, the detection threshold increases as the current value of the constant current source (second transistor 47) increases. In order to make the detection thresholds (DTH1, DTH2, DTH3) different from one another in the multiple detection circuits (25, 29, 31), constant current sources (second transistors 47) that provide different current values ​​can be used, and / or first transistors 41 of different sizes can be used.

[0091] Furthermore, in order to make the detection thresholds (DTH1, DTH2, DTH3) different from one another, at least one of the size of the first transistor 41 and the current value of the second transistor 47 (constant current source) can be made different in the multiple detection circuits (for example, 25, 29, 31).

[0092] Detection circuit threshold design example First detection circuit 25 First detection threshold DTH1: Approximately the first threshold (eg, 0.7 volts). Second detection circuit 29 Second detection threshold DTH2: First threshold + First differential voltage (eg, 0.05 volts). Third detection circuit 31 Third detection threshold DTH3: First threshold + second differential voltage (e.g., 0.10 volts).

[0093] 8 is a circuit diagram showing the circuits related to the detection circuit according to this embodiment. As shown in FIG. 8, the constant current source circuit 51 is connected not only to the detection circuits (25, 29, 31) but also to the charging circuit 27 and the discharging circuit 28. These connections are made so as to receive a mirrored current from the constant current source circuit 51.

[0094] The constant current source circuit 51 includes a voltage source 53 and a current source transistor 55 (e.g., p-type) connected to the voltage source 53. The voltage source 53 may include, for example, a bandgap circuit. The current source transistor 55 receives a constant voltage signal from, for example, the bandgap circuit at its gate electrode G and receives a high potential line VH at its source electrode S to generate a constant current. A drain electrode D of the current source transistor 55 is connected to the drain electrode D and gate electrode G of a transistor 57a (e.g., n-type) that constitutes two current mirror circuits CM1 and CM2.

[0095] The gate electrode of transistor 57a is connected to the gate electrode G of transistor 57b to form a current mirror circuit CM1. The drain electrode D of transistor 57b is connected to the gate electrode G and drain electrode D of transistor 59b (e.g., p-type). In this embodiment, the gate electrode G of transistor 59b forms a current mirror circuit CM5 that provides constant currents to multiple current sources (IC1, IC12, IC3, IC4) of the charging circuit 27.

[0096] Also, the gate electrode G of transistor 57a (e.g., n-type) is connected to the gate electrode G of transistor 57c, and the drain electrode D of transistor 57c is connected to the gate electrode G and drain electrode D of transistor 59a (e.g., p-type) to form a current mirror circuit CM2. The gate electrode G of transistor 59a is connected to the gate electrode G of each second transistor 47 of the detection circuit (25, 29, 31) to form a current mirror circuit CM3 with the second transistor 47. This connection enables the second transistor 47 to operate as a current source.

[0097] Furthermore, the gate electrode G of transistor 59a is connected to the gate electrode G of transistor 59c (e.g., p-type) to form a further current mirror circuit CM4. The drain electrode D of transistor 59c is connected to the gate electrode G and drain electrode D of transistor 57d (e.g., n-type). In this embodiment, the gate electrode G of transistor 57d forms a current mirror circuit CM6 that provides constant currents to multiple current sources (ID1, ID12, ID3, ID4) of the discharge circuit 28. In the current mirror circuits CM1 to CM6, the mirrored currents are determined by the size ratio of the transistors in each of the current mirror circuits CM1 to CM6.

[0098] 9 is a cross-sectional view showing an example of a high-voltage structure of a drive transistor. The drive transistor and other transistors can be provided by using, for example, a manufacturing technique for complementary MOS transistors.

[0099] A double-diffused lateral MOS transistor 71 is formed in a first conductivity type (e.g., p-type) semiconductor region 72, e.g., a silicon region. Specifically, the transistor 71 includes a first conductivity type channel well 75a, a second conductivity type (e.g., n-type) drain well 75b, a second conductivity type high concentration source region 77a and a second conductivity type high concentration drain region 77b, a gate insulating film 79a, an isolation insulating layer 79b, and a gate electrode G.

[0100] The channel well 75a and the drain well 75b are provided in the semiconductor region 72. The heavily doped source region 77a and the heavily doped drain region 77b are provided in the channel well 75a and the drain well 75b, respectively, and have the second conductivity type (n-type). The gate electrode G is provided on the gate insulating film 79a and the isolation insulating layer 79b. The gate insulating film 79a may include, for example, silicon oxide, and the isolation insulating layer 79b may include, for example, silicon oxide. The gate electrode G extends on a boundary 79c between the gate insulating film 79a and the isolation insulating layer 79b. The isolation insulating layer 79b is thicker than the gate insulating film 79a.

[0101] The second conductor region 76 for the drain region (D) of the transistor 71 includes a drain well 75b and a high-concentration drain region 77b, and the first conductor region 74 for the source region (S) of the transistor 71 includes a high-concentration source region 77a. The channel well 75a is fed by a high-concentration well region 77c of the first conductivity type. The high-concentration source region 77a and the high-concentration well region 77c are connected to the low potential line VL by a source metal layer 78a. The high-concentration drain region 77b is connected to the conductor 13 by a drain metal layer 78b. The high-concentration source region 77a is separated from the drain well 75b by the channel well 75a and the semiconductor region 72. The channel well 75a is deeper than the high-concentration source region 77a and covers the bottom and side surfaces of the high-concentration source region 77a. The drain well 75b is deeper than the high-concentration drain region 77b and covers the bottom and side surfaces of the high-concentration drain region 77b. The gate electrode G and the isolation insulating layer 79b are covered with an interlayer insulating film 80a. The interlayer insulating film 80a, the source metal layer 78a, and the drain metal layer 78b are covered with a protective insulating film 80b.

[0102] FIG. 10 is a diagram schematically illustrating a board product according to this embodiment. The board product 60 includes a connector 61, a semiconductor chip 62 including a semiconductor integrated circuit 11, and a circuit board 63 on which the connector 61 and the semiconductor chip 62 are mounted. The circuit board 63 includes a conductor layer 63a patterned to connect the connector 61 and the semiconductor chip 62, and conductor layers 63b and 63c for a low-potential line VL and a high-potential line VH. The semiconductor chip 62 contains the semiconductor integrated circuit 11, which includes a conductor 13, a bus driver 15 (external), a pre-stage circuit 21, a receiver 33, and a signal processing circuit 35. The circuit board 63 may include a flexible or rigid base material. The connector 61 can be connected to an external bus.

[0103] A semiconductor chip 62 including a semiconductor integrated circuit 11 is mounted on a circuit board 63 to provide a board product 60 capable of two-way communication via a high-voltage external bus. In the semiconductor chip 62, the conductor 13 can be, for example, a metal pad or a bump electrode. In the semiconductor chip 62, the drive transistor 23 has a high-voltage structure.

[0104] 11 is a diagram schematically illustrating a board product communication device (board product communication system) including a board product according to this embodiment. The board product communication device 65 includes a plurality of board products 60a, 60b, 60c, and 60d and a single conductive wire 67 that connects the board products 60a, 60b, 60c, and 60d to one another via their respective connectors 61. Specifically, the single conductive wire 67 connects the conductors 13 in the board products 60a, 60b, 60c, and 60d to one another via their respective connectors 61, enabling bidirectional communication between them. The single conductive wire 67 can be included in a metal wire cable such as a wire harness.

[0105] According to a plurality of board products 60a, 60b, 60c, and 60d, a semiconductor chip 62 mounted on a circuit board 63 and including a semiconductor integrated circuit 11 provides a board product communication device 65 capable of communication via a high-voltage external bus.

[0106] Specifically, in the board product 60a, the resistor 37 is mounted on the circuit board 63 and connected to the semiconductor chip 62 via the conductive layer of the circuit board 63. The resistor 37 is connected between the high-potential line HHV on the circuit board 63 and the output (bus 10) of the bus driver 15. In the board product 60b, the resistor 37 is integrated in the semiconductor chip 62 and connected to the conductor 13 of the semiconductor integrated circuit 11. The resistor 37 is connected between the high-potential line HHV in the semiconductor integrated circuit 11 and the output of the bus driver 15. In the board products 60a and 60c, the resistor 37 is provided outside the semiconductor chip 62 and not on the circuit board 63.

[0107] As described above, according to this embodiment, there are provided a semiconductor integrated circuit 11 including a bus driver 15 capable of reducing abrupt changes in the waveform on an external bus, board products 60, 60a, 60b, 60c, and 60d including this semiconductor integrated circuit 11, and a board product communication device 65 including the board products 60, 60a, 60b, 60c, and 60d.

[0108] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0109] 10 bus, 11 semiconductor integrated circuit, 13 conductor, 15 bus driver, 17 drive circuit, 19 control line, 21 previous stage circuit, 21a input, 23 drive transistor, 24 detection circuit, 24a input, 24b output, 25 first detection circuit, 25a first input, 25b first detection output, 27 charging circuit, 27a, 27b, 27c, 27d, 27e, 27f, 27g, 27j transistor, 27i control input, 27k signal input output, 28···discharge circuit, 28a, 28b, 28c, 28d, 28e, 28f, 28g, 28j···transistor, 28i···control input, 28k···signal input, 29···second detection circuit, 29a···second input, 29b···second detection output, 30···control circuit, 31···third detection circuit, 31a···third input, 31b···third detection output, 33···receiver, 33a···input, 33b···output, 35··signal processing circuit, 37···resistor, 39···capacitor, 41···transistor, 4 3. Load circuit, 45. Transistor, 47. Transistor, 51. Constant current source circuit, 53. Voltage source, 55. Current source transistor, 57a, 57b, 57c, 57d, 59a, 59b, 59c. Transistor, 60, 60a, 60b, 60c. Substrate product, 61. Connector, 62. Semiconductor chip, 63. Circuit board, 63a, 63b, 63c. Conductor layer, 65. Substrate product communication device, 67. Conductive line, 71. Transistor, 72. Semiconductor region, 74. Conductor region, 75a···Channel well, 75b···Drain well, 76···Conductor region, 77a··Highly doped source region, 77b··Highly doped drain region, 77c··Highly doped well region, 78a···Drain metal layer, 78a···Source metal layer, 79a···Gate insulating film, 79b···Isolation insulating layer, 79c···Boundary, 80a···Interlayer insulating film, 80b···Protective insulating film, CM1, CM2, CM3, CM4, CM5, CM6··Current mirror circuit, DTH1, DTH2, DTH3··Detection threshold, I 01 Initial charging current value, I1 Current value, I 11 Intermediate current value, I 12Intermediate current value, I2 Current value, I 02 Initial discharge current value, I3 Current value, I 31 Intermediate current value, I 32 ···Intermediate current value, I4···Current value, D···Drain electrode, G···Gate electrode, S···Source electrode, SB1···First signal, SB2···Second signal, SD1, SD2, SD3···Detection signal, SIG···Signal, HHV···High potential line, VH···High potential line, VL···Low potential line.

Claims

1. A semiconductor integrated circuit, an electrical conductor configured to be connected to a bus to be driven; a bus driver connected to the electrical conductor; Including, The bus driver: a drive circuit including an open-drain drive transistor connected between a first reference potential line and the conductor and having a first threshold; a control line connected to a gate electrode of the driving transistor; a front end circuit connected to the control line, the front end circuit having an input configured to receive a signal to be output onto the bus; Including, The preceding circuit comprises: a first sense circuit configured to sense whether the voltage on the control line crosses a first sense threshold, the first sense circuit having a first input connected to the control line and a first sense output providing a result of the sensing; a charging circuit that charges the control line with a current of an initial charging current value in response to a first signal from the input, and that charges the control line with a current of a first current value smaller than the initial charging current value in response to a first detection signal from the first detection output; a constant current source circuit connected to the charging circuit and configured to enable the charging circuit to provide a constant current for the first current value and the initial charging current value; Including, the first detection circuit includes a current source connected to the constant current source circuit as a load circuit, and includes a transistor having a gate connected to the control line, a drain connected to the load circuit and the first detection output, and a source connected to a ground line; the driving transistor has a high voltage resistance structure; Semiconductor integrated circuit.

2. the front-stage circuit includes a second detection circuit; the second sense circuit is configured to sense whether the voltage on the control line crosses a second sense threshold, the second sense circuit having a second input connected to the control line and a second sense output providing a result of the sensing; the charging circuit charges the control line with a current of a second current value greater than the first current value in response to a second detection signal from the second detection output; the first detection threshold is less than the second detection threshold; 2. The semiconductor integrated circuit according to claim 1.

3. A semiconductor integrated circuit, an electrical conductor configured to be connected to a bus to be driven; a bus driver connected to the electrical conductor; Including, The bus driver: a drive circuit including an open-drain drive transistor connected between a first reference potential line and the conductor and having a first threshold; a control line connected to a gate electrode of the driving transistor; a front end circuit connected to the control line, the front end circuit having an input configured to receive a signal to be output onto the bus; Including, The preceding circuit comprises: a first sense circuit configured to sense whether the voltage on the control line crosses a first sense threshold, the first sense circuit having a first input connected to the control line and a first sense output providing a result of the sensing; a charging circuit that charges the control line with a current of an initial charging current value in response to a first signal from the input, and that charges the control line with a current of a first current value smaller than the initial charging current value in response to a first detection signal from the first detection output; Including, the driving transistor has a high voltage resistance structure, the front-stage circuit includes a second detection circuit; the second sense circuit is configured to sense whether the voltage on the control line crosses a second sense threshold, the second sense circuit having a second input connected to the control line and a second sense output providing a result of the sensing; the charging circuit charges the control line with a current of a second current value greater than the first current value in response to a second detection signal from the second detection output; the first detection threshold is less than the second detection threshold; each of the first detection circuit and the second detection circuit includes a first transistor having a gate electrode connected to the control line, a source electrode connected to the first reference potential line, and a drain electrode, the first transistor having the first threshold value; and a first load circuit connected to the drain electrode of the first transistor; the first transistor has the high-voltage structure; Semiconductor integrated circuit.

4. the preceding circuit includes a constant current source circuit, the constant current source circuit is configured to be connected to the charging circuit and enable the charging circuit to provide a constant current for the first current value and the initial charging current value; the first load circuit includes a first switch that is turned on in response to the first signal and a first constant current source connected to the drain electrode of the first transistor, the first constant current source being connected to the constant current source circuit; 4. A semiconductor integrated circuit according to claim 3.

5. the front-stage circuit further includes a discharge circuit; The discharge circuit discharges the control line with a current of an initial discharge current value in response to a second signal from the input that is different from the first signal, and increases the initial discharge current value in response to the second detection signal. and discharging the control line with a current having a third current value smaller than the first current value.

5. A semiconductor integrated circuit according to claim 2, claim 3, or claim 4.

6. a receiver having an input connected to the conductor for receiving a signal from the bus via the conductor; a signal processing circuit configured to process signals for a single-wire communication protocol of the bus; Including, the receiver provides a received signal to the signal processing circuit; the signal processing circuit provides a signal to be output to the bus to the input of the preceding circuit; 6. A semiconductor integrated circuit according to claim 1.

7. the bus is connected to a second reference potential line different from the first reference potential line via a resistor; 7. A semiconductor integrated circuit according to claim 1.

8. A semiconductor chip including the semiconductor integrated circuit according to any one of claims 1 to 6; A connector and a circuit board having the semiconductor chip and the connector mounted thereon and a conductor layer patterned to connect the semiconductor chip and the connector; Equipped with Substrate products.

9. A first substrate product according to claim 8; A second substrate product according to claim 8; a single conductive line connecting the conductor of the first substrate product and the conductor of the second substrate product to each other via the connector of the first substrate product and the connector of the second substrate product; Equipped with Board product communication device.

10. further comprising a resistor mounted on the circuit board of at least one of the first substrate product and the second substrate product; the resistor is connected between the conductor layer and a second reference potential line different from the first reference potential line.

10. The substrate product communication device according to claim 9.

11. the semiconductor chip of at least one of the first substrate product and the second substrate product further includes a resistor connected between the conductor layer and a second reference potential line different from the first reference potential line; 10. The substrate product communication device according to claim 9.

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