Data transmission device and data transmission system

Abstract

This technology relates to a data transmission device and a data transmission system that make it possible to achieve more efficient data transmission. A data transmission device according to this technology includes: a common terminal connected to a transmission line through which a first signal and a second signal are transmitted, the second signal being transmitted in a direction opposite the direction in which the first signal is transmitted and having a frequency band different from that of the first signal; a reception circuit that receives the first signal from the transmission line via the common terminal; and a transmission circuit that transmits the second signal via the common terminal. This technology may be applied to, for example, a data transmission system that transmits video data via an AC-coupled transmission line.

Description

[Technical Field]

[0001] The present technology relates to a data transmission device and a data transmission system, and more particularly to a data transmission device and a data transmission system that are capable of realizing more suitable data transmission. [Background technology]

[0002] There is a device that transmits signals using a pair of signal lines to transmit large amounts of data at high speed. For example, Patent Document 1 describes a data transmitting and receiving device that transmits data using a coaxial cable as a transmission path in addition to a differential cable. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 049524 Summary of the Invention [Problem to be solved by the invention]

[0004] With the recent increase in data volume, more suitable data transmission methods are required.

[0005] The present technology has been made in view of such circumstances, and makes it possible to realize more suitable data transmission. [Means for solving the problem]

[0006] A data transmission device according to a first aspect of the present technology includes a common terminal connected to a transmission path through which a first signal and a second signal having a different frequency band from the first signal and transmitted in a direction opposite to the first signal are transmitted, a receiving circuit that receives the first signal from the transmission path via the common terminal, and a transmitting circuit that transmits the second signal via the common terminal.

[0007] A data transmission system according to a second aspect of the present technology includes: a common terminal connected to a transmission path through which a first signal and a second signal having a different frequency band from the first signal and transmitted in a direction opposite to the first signal are transmitted; a data receiving device including: a downstream signal receiving circuit that receives the first signal from the transmission path via the common terminal; and an upstream signal transmitting circuit that transmits the second signal via the common terminal; and a data transmitting device including the downstream signal transmitting circuit that transmits the first signal and the upstream signal receiving circuit that receives the second signal from the transmission path.

[0008] In a first aspect of the present technology, a first signal and a second signal having a frequency band different from that of the first signal, which is transmitted in a direction opposite to that of the first signal, are received from a transmission path via a common terminal connected to the transmission path, and the second signal is transmitted via the common terminal.

[0009] In a second aspect of the present technology, a data receiving device includes a common terminal connected to a transmission path through which a first signal and a second signal, which is transmitted in a direction opposite to the first signal and has a different frequency band from the first signal, are transmitted, the data receiving device receives the first signal from the transmission path via the common terminal and transmits the second signal via the common terminal, and a data transmitting device transmits the first signal and receives the second signal from the transmission path. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an example configuration of a data transmission system according to an embodiment of the present technology. [Figure 2] 10 is a diagram illustrating a specific example of the circuit configuration of a downstream signal transmitting circuit and an upstream signal receiving circuit of a source device. FIG. [Figure 3] 1 is a diagram illustrating a specific example of the circuit configuration of an upstream signal transmitting circuit and a downstream signal receiving circuit of a conventional sink device. [Figure 4] 10 is a diagram illustrating a specific example of the circuit configuration of an upstream signal transmitting circuit and a downstream signal receiving circuit of a sink device according to the present technology. [Figure 5] 1A and 1B are diagrams illustrating examples of transmission bands of upstream and downstream signals. [Figure 6] 1 is a diagram showing the flow of upstream and downstream signals in a data transmission system according to the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present technology will be described in the following order. 1. Overview of the data transmission system 2. Circuit configuration example

[0012] <1. Data Transmission System Overview> FIG. 1 is a block diagram showing an example of the configuration of a data transmission system according to an embodiment of the present technology.

[0013] A data transmission system according to an embodiment of the present technology is a system that transmits differential signals, common-mode signals, etc. from a transmitting device (source device 1) to a receiving device (sink device 2) using a pair of signal lines. In the signal transmission using this pair of signal lines, high-speed data transfer is performed from the source device 1 to the sink device 2.

[0014] The data transmission system transmits and receives digital video and audio data using, for example, serial data transmission technology. As the digital video and audio data, moving images such as 24-bit gradation VGA (Video Graphics Array), WVGA (Wide VGA), SVGA (Super VGA), XGA (Elongated Graphics Array), WXGA (Wide XGA), SXGA (Super XGA), and UXGA (Ultra XGA) are transmitted based on, for example, the GVIF (registered trademark) standard.

[0015] As shown in Figure 1, the data transmission system is composed of a source device 1, a sink device 2, and a transmission path 3, which is the path of transmitted data. In the following explanation, the direction from source device 1 to sink device 2 is referred to as downstream, and the direction from the sink device to the source device is referred to as upstream. In the following explanation, downstream signals generally handle video signals and the like, and upstream signals handle low-speed signals such as control signals. A shielded pair cable, for example, is used as transmission path 3.

[0016] The source device 1 is made up of a downstream transmission processing unit 11, a downstream signal transmission circuit 12, an upstream signal reception circuit 13, and an upstream reception processing unit .

[0017] The downstream transmission processing unit 11 determines data to be transmitted from the source device 1 to the sink device 2, and supplies the determined data to the downstream signal transmission circuit 12. For example, when transmitting downstream data to the sink device 2, the downstream transmission processing unit 11 synchronizes the downstream data with a transmission clock TCLK, which is a clock for transmission, and supplies this synchronized downstream data to the downstream signal transmission circuit 12.

[0018] Furthermore, when a reference clock transmission command is supplied from the upstream reception processing unit 14, the downstream transmission processing unit 11 supplies a clock obtained by dividing the transmission clock TCLK by N to the downstream signal transmission circuit 12 as a reference clock.

[0019] The downstream signal transmission circuit 12 generates signals for serially transferring the signals supplied from the downstream transmission processing unit 11 over the transmission path 3. The downstream signal transmission circuit 12 generates, for example, a pair of signals (differential signals) having opposite phases to each other, and transmits them to the sink device 2 over the transmission path 3.

[0020] The upstream signal receiving circuit 13 includes an LPF (Low-Pass Filter) 21. The LPF 21 is a filter circuit that attenuates the signal output from the downstream signal transmitting circuit 12 and passes the signal transmitted from the sink device 2 via the transmission path 3.

[0021] In the data transmission system of the present technology, the downstream signal transmitted from source device 1 to sink device 2 and the upstream signal transmitted from sink device 2 to source device 1 have different frequency bands. Here, the downstream signal is transmitted as a high frequency, and the upstream signal is transmitted as a low frequency. Therefore, LPF 21 has the characteristic of separating the upstream signal from the downstream signal by frequency by passing the upstream signal and attenuating the downstream signal.

[0022] The upstream signal receiving circuit 13 supplies the signal that has passed through the LPF to an upstream receiving processing unit 14 .

[0023] The upstream reception processing unit 14 analyzes the signal supplied from the upstream signal receiving circuit 13 and outputs the analysis result. For example, when the signal supplied from the upstream signal receiving circuit 13 is upstream signal data (herein referred to as user data), the upstream reception processing unit 14 supplies the user data to a circuit (not shown) in the source device 1 that uses the user data. The upstream reception processing unit 14 supplies the upstream data clk to a circuit (not shown) in the source device 1 that uses the upstream data clk.

[0024] Furthermore, the upstream reception processing unit 14 supplies a reference clock transmission command to the downstream transmission processing unit 11 when the signal supplied by the upstream signal reception circuit 13 is a signal requesting a reference clock (reference clock request signal).

[0025] There is no particular limitation to the configuration of the upstream reception processing unit 14. For example, the upstream reception processing unit 14 is configured to have a function of comparing the signal supplied from the upstream signal receiving circuit 13 with a reference potential that is a predetermined potential, and detecting data by comparing the comparison result with a predetermined clock generated in the source device 1.

[0026] The sink device 2 is made up of an upstream transmission processing unit 41, an upstream signal transmission circuit 42, a downstream signal reception circuit 43, and a downstream reception processing unit 44.

[0027] The upstream transmission processing unit 41 determines data to be transmitted from the sink device 2 to the source device 1, and supplies the determined data to the upstream signal transmission circuit 42. For example, when a reference clock request transmission command is supplied from the downstream reception processing unit 44, the upstream transmission processing unit 41 supplies a reference clock request signal to the upstream signal transmission circuit 42.

[0028] Furthermore, when a reference clock request transmission command is not supplied and user data that is data to be transmitted is supplied, the upstream transmission processing unit 41 supplies the user data to the upstream signal transmission circuit 42. In this case, the upstream transmission processing unit 41 synchronizes the user data with an upstream transmission clock (upstream data clk), which is a clock for transmitting data in the upstream direction, and supplies this synchronized user data to the upstream signal transmission circuit 42.

[0029] The upstream signal transmitting circuit 42 generates a signal to transfer the signal supplied from the upstream transmission processing unit 41 over the transmission path 3. The upstream signal transmitting circuit 42 generates, for example, a differential signal and supplies it to the upstream signal receiving circuit 13 of the source device 1 via the transmission path 3.

[0030] The downstream signal receiving circuit 43 includes an HPF (High-Pass Filter) 51. The HPF 51 is a filter circuit that attenuates the signal output from the upstream signal transmitting circuit 42 and passes the signal transmitted from the source device 1 via the transmission path 3. As described above, in the data transmission system of the present technology, the downstream signal and the upstream signal have different frequency bands. Therefore, the HPF 51 has the characteristic of separating the upstream signal and the downstream signal by frequency by attenuating the upstream signal and passing the downstream signal.

[0031] The downstream signal receiving circuit 43 receives the signal that is supplied via the transmission path 3 and has passed through the HPF 51. That is, the downstream signal receiving circuit 43 receives the signal transmitted from the downstream signal transmitting circuit 12 of the source device 1, and supplies the signal to a downstream reception processing unit 44.

[0032] The downstream reception processing unit 44 analyzes the signal supplied from the downstream signal reception circuit 43 and outputs the analysis result. For example, when downstream data is transmitted, the downstream reception processing unit 44 supplies the downstream data and the transmission clock TCLK to a circuit (not shown) in the sink device 2 that uses the downstream data.

[0033] Furthermore, when reception of a reference clock is required, the downstream reception processing unit 44 supplies the upstream transmission processing unit 41 with a signal (reference clock request transmission command) for executing transmission of a reference clock request signal.

[0034] When the downstream reception processing unit 44 receives the reference clock, it synchronizes the clock (reference clock) used by the downstream reception processing unit 44 when detecting downstream data with the reference clock. The downstream reception processing unit 44 supplies the transmission clock TCLK to a circuit (not shown) in the sink device 2 that uses the transmission clock TCLK.

[0035] <2. Circuit configuration example> Circuit configuration example for source device 1 FIG. 2 is a diagram showing a specific example of the circuit configuration of the downstream signal transmitting circuit 12 and the upstream signal receiving circuit 13 of the source device 1. As shown in FIG.

[0036] The downstream signal transmission circuit 12 is, for example, a differential circuit. A resistive element R1 is provided in the subsequent stage of the downstream signal transmission circuit 12.

[0037] Since the upstream signal receiving circuit 13 also receives downstream signals, an LPF 21 is inserted in the preceding stage to attenuate the downstream signal components, thereby enabling the upstream signal receiving circuit 13 to receive only upstream signals.

[0038] Circuit configuration example for sink device 2 Before describing in detail the circuit configuration of sink device 2 of the present technology, the circuit configuration of a conventional sink device will be described below. Fig. 3 is a diagram showing a specific example of the circuit configuration of an upstream signal transmitting circuit 42A and a downstream signal receiving circuit 43A of the conventional sink device.

[0039] The upstream signal transmitting circuit 42A has a push-pull configuration, in which current flows in and out by switching switches 75 to 78 with respect to current sources 71 to 74. As the switches 75 to 78, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used.

[0040] The upstream signal transmitting circuit 42A is provided with a resistor element R11 for dividing the power supply voltage in order to determine the DC position when the current is cut off. These currents flow through the transmission line 3 to the resistor element R1 of the downstream signal transmitting circuit 12, causing a change in voltage.

[0041] A ferrite bead (FB) 201 is provided downstream of the upstream signal transmission circuit 42A. The FB 201 is an element that has high impedance at high frequencies and low impedance at low frequencies, and is inserted to reduce the effect of the load on the upstream signal transmission circuit 42A side.

[0042] The input of the downstream signal receiving circuit 43A is terminated by a resistive element R21. A capacitive element C11 is inserted before the resistive element R21, forming one HPF. Further ahead is a capacitive element C51 for cutting DC components, forming another HPF. These HPFs attenuate the upstream signal input to the downstream signal receiving circuit 43A.

[0043] FIG. 4 is a diagram showing a specific example of the circuit configuration of the upstream signal transmitting circuit 42 and the downstream signal receiving circuit 43 of the sink device 2 of the present technology.

[0044] In conventional sink devices, it was necessary to provide the FB 201 outside an integrated circuit (IC) in which the upstream signal transmission circuit 42A and the downstream signal reception circuit 43A were provided. Because the FB 201 was provided outside the IC, the output terminal of the upstream signal transmission circuit 42A and the input terminal of the downstream signal reception circuit 43A were provided as separate terminals on the IC. This increased the number of terminals on the IC. Furthermore, because components such as the FB 201 were provided outside the output terminal of the upstream signal transmission circuit 42A, a mounting area including the peripheral components was required.

[0045] To implement a component with the same specifications as FB201 within an IC, an inductor of several hundred nH would be required, and it would be impractical to provide such an inductor within the IC. Therefore, in the sink device 2 of the present technology, a resistive element R31 is provided within the IC instead of FB201, as shown in FIG. 4 . By implementing the components within the IC, the upstream signal transmitting circuit 42 and the downstream signal receiving circuit 43 are connected to the transmission path 3 via a common terminal 81 of the IC. That is, the upstream signal transmitting circuit 42 transmits an upstream signal via the common terminal 81, and the downstream signal receiving circuit 43 receives a downstream signal from the transmission path 3 via the common terminal 81. This allows the number of IC terminals to be reduced. Furthermore, by reducing the number of peripheral components, the mounting area can be reduced.

[0046] However, unlike FB201, the resistor element R31 cannot reduce impedance at low frequencies and increase impedance at high frequencies; rather, its impedance remains constant regardless of frequency. Therefore, the voltage amplitude at the upstream signal transmission circuit 42 terminal increases, reducing the performance of the MOS transistor that constitutes the current source. Therefore, the resistance value of the resistor element R31 cannot be increased. This makes it more difficult to achieve isolation between the downstream and upstream sides than with conventional designs. In other words, upstream signal components are more likely to interfere with the downstream signal.

[0047] Therefore, the sink device 2 of the present technology is provided with a circuit that generates an inverted phase signal from the replica circuit 62 of the main circuit 61 that generates the uplink signal, and adds the inverted phase signal to the downlink signal, thereby canceling the uplink signal component contained in the downlink signal. By providing such a circuit, the downlink signal receiving circuit 43 can output the downlink signal from which the uplink signal component has been removed to a subsequent stage.

[0048] First, a description will be given of a specific circuit configuration of the upstream signal transmission circuit 42. The upstream signal transmission circuit 42 is composed of a main circuit 61 and a replica circuit 62.

[0049] This circuit 61 has a circuit configuration similar to that of the upstream signal transmission circuit 42A described with reference to Fig. 3. For example, switches 75 and 78 are turned on when high and off when low. Switches 76 and 77 are turned on when low and off when high.

[0050] The replica circuit 62 is a replica circuit in which the output current of the main circuit 61 is reduced by a predetermined reduction ratio. A circuit in which the output current of the main circuit 61 is downscaled to, for example, 1 / 40 is used as the replica circuit 62. By using a circuit in which the output current is downscaled, it is possible to reduce the circuit area of ​​the replica circuit 62. It is also possible to use a circuit of the same size as the main circuit 61 as the replica circuit 62.

[0051] The replica circuit 62 has a push-pull configuration similar to the main circuit 61, in which current flows in and out by switching the switches 95 to 98 for the current sources 91 to 94. The output currents I11 / I12 of the current sources 91 to 94 are values ​​obtained by reducing the output currents I1 / I2 of the current sources 71 to 74 of the main circuit 61 by a reduction ratio of 1 / 40.

[0052] For example, MOSFETs are used as the switches 95 to 98. For example, the switches 95 and 98 are turned on when they are in a high state and turned off when they are in a low state. The switches 96 and 97 are turned on when they are in a low state and turned off when they are in a high state. The replica circuit 62 is provided with a resistor R12 corresponding to the resistor R11.

[0053] Next, a specific circuit configuration of the downstream signal receiving circuit 43 will be described. The input of the downstream signal receiving circuit 43 is connected to the output side of this circuit 61 via a resistive element R31. The input of the downstream signal receiving circuit 43 is terminated by a resistive element R41. A capacitive element C11 is inserted in the stage preceding this resistive element R41, which constitutes the HPF 51 on the main circuit 61 side. This HPF 51 attenuates the upstream signal from the main circuit 61 that is input to the downstream signal receiving circuit 43.

[0054] In the downstream signal receiving circuit 43A described with reference to Figure 3, the resistive element R21 is grounded to GND. In this configuration, an NMOS (Negative-channel MOS) cannot be provided at the input of the next-stage circuit, which is disadvantageous in assembling a high-frequency circuit. For this reason, the DC component is cut by an HPF formed by the capacitive element C51 in the subsequent stage, and a separate bias circuit based on VDD is provided.

[0055] Although a similar configuration is possible for the downstream signal receiving circuit 43 of this technology, the inclusion of two capacitive elements in series can increase the proportion of signals attenuated by parasitic capacitance. To avoid this, the resistive element R41 is grounded by an LDO (Low Dropout) circuit biased to VDD-V11. This allows a single capacitive element to generate bias for the next circuit stage.

[0056] A resistive element R51 is provided on the output side of the replica circuit 62. The output of the replica circuit 62 is terminated by the resistive element R52 and then terminated by the resistive element R61 via the capacitive element C21. The capacitive element C21 and the resistive element R61 form an HPF 52 on the replica circuit 62 side. This HPF 52 attenuates the output signal from the replica circuit 62 that is input to the downstream signal receiving circuit 43. The resistive element R61 is also grounded by an LOD circuit biased to VDD-V11.

[0057] The capacitance element C11 constituting the HPF 51 on the main circuit 61 side has a capacitance value that requires a considerable area when mounted on an IC. In the downstream signal receiving circuit 43, the capacitance value of the capacitance element C21 constituting the HPF 52 on the replica circuit 62 side is set to a value that is downscaled to 1 / 40, which is the reduction ratio of the output current of the replica circuit 62, thereby reducing the mounting area of ​​the capacitance element C11.

[0058] In the downstream signal receiving circuit 43, the resistance value of the resistive element R61 constituting the HPF 52 is adjusted to be 40 times the resistance value of the resistive element R41 constituting the HPF 51 in order to make the cutoff frequency HPF-fc of the HPF 52 the same as the cutoff frequency HPF-fc of the HPF 51 expressed by the following equation (1). The cutoff frequency HPF-fc of the HPF 52 is expressed by the following equation (2).

[0059]

number

number

[0060] Since the output current of the replica circuit 62 is adjusted to be 1 / 40 of the output current of the main circuit 61, the input voltage level of the HPF 52 on the replica circuit 62 side needs to be adjusted by the resistor elements R51 and R52 based on the input voltage level of the HPF 51 on the main circuit 61 side.

[0061] For example, the resistance values ​​of the resistor elements R51 and R52 are determined so that the voltage level of the input of the HPF 52 on the replica circuit 62 side, which is expressed by the following equation (3), is approximately the same as the voltage level of the input of the HPF 51 on the main circuit 61 side, which is expressed by the following equation (4). Note that in equations (3) and (4), IBC represents the output current of the main circuit 61.

[0062]

number

number

[0063] In the downstream signal receiving circuit 43 , the downstream signal including the upstream signal component that has passed through the HPF 51 and the reverse-phase signal of the output signal from the replica circuit 62 that has passed through the HPF 52 are supplied to the canceller circuit 101 .

[0064] The canceller circuit 101 adds the downstream signal and a signal having a reverse phase to the output signal from the replica circuit 62 .

[0065] Fig. 5 is a diagram showing an example of the transmission bands of the upstream signal and the downstream signal. The dashed lines in Fig. 5 indicate the filter characteristics of the HPF.

[0066] An example of the transmission bands of upstream and downstream signals in a conventional data transmission system is shown in A of Fig. 5. Conventionally, as shown in A of Fig. 5, the transmission band of the upstream signal is the frequency band of the attenuation band of the HPF provided in the downstream signal receiving circuit 43A, and the transmission band of the downstream signal is the frequency band of the pass band and transition band of the HPF.

[0067] Due to the recent trend toward higher pixel count images, the transmission bands of the upstream signal and the downstream signal are each becoming wider, as shown in B of Fig. 5. Furthermore, as described above, in the sink device 2 of the present technology, the resistive element R31 is provided between the upstream signal transmitting circuit 42 and the downstream signal receiving circuit 43 instead of the FB201, which makes it easier for the upstream signal component to interfere with the downstream signal.

[0068] 5, for example, the transition band frequency band of the HPF 51 provided in the downstream signal receiving circuit 43 is used as part of the transmission band of the upstream signal, and the upstream signal cannot be completely attenuated by the HPF 51. If only the HPF 51 is used to separate the upstream signal and the downstream signal, the upstream signal component that passes through the HPF 51 will become noise in the downstream signal receiving circuit 43, degrading the receiving sensitivity of the downstream signal receiving circuit 43.

[0069] FIG. 6 is a diagram showing the flow of upstream and downstream signals in the data transmission system of the present technology.

[0070] 6, the downstream signal from the downstream signal transmission circuit 12 passes through the HPF 51 and is supplied to the canceller circuit 101 of the downstream signal reception circuit 43. In addition, a part of the downstream signal passes through the LPF 21 and is supplied to the upstream signal reception circuit 13.

[0071] 6, the upstream signal from the main circuit 61 of the upstream signal transmission circuit 42 passes through the LPF 21 and is supplied to the upstream signal reception circuit 13. In addition, a part of the upstream signal passes through the HPF 51 and is supplied to the canceller circuit 101.

[0072] Furthermore, as indicated by the colored arrow in FIG. 6, a portion of the output signal from the replica circuit 62 of the upstream signal transmitting circuit 42 passes through the HPF 52, and a signal having an opposite phase to the output signal that has passed through the HPF 52 is supplied to the canceller circuit 101.

[0073] The canceller circuit 101 adds the signal that has passed through the HPF 51 to the reverse-phase signal of the signal that has passed through the HPF 52, thereby canceling the upstream signal component contained in the signal that has passed through the HPF 51 and reducing noise.

[0074] Furthermore, as described above, in the downstream signal receiving circuit 43, the resistive element R41 constituting the HPF 51 is grounded by the LDO circuit, so that the HPF 51 can be formed using a single-stage capacitive element, making it possible to suppress signal attenuation due to parasitic capacitance.

[0075] As described above, it is possible to reduce noise that occurs when transmitting high-frequency signals via the transmission path 3, which is an AC-coupled bidirectional transmission path using a pair of signal lines. Therefore, even when the frequency difference between the transmission bands of the upstream and downstream signals is small, it is possible to achieve high-speed communication using high-frequency signals, thereby achieving more suitable data transmission.

[0076] In this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all the components are contained in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0077] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0078] <Configuration combination example> The present technology can also be configured as follows.

[0079] (1) a common terminal connected to a transmission path through which a first signal and a second signal, which is transmitted in the opposite direction to the first signal and has a different frequency band from the first signal, are transmitted; a receiving circuit that receives the first signal from the transmission line via the common terminal; a transmitting circuit that transmits the second signal via the common terminal; A data transmission device comprising: (2) The receiving circuit includes a filter circuit that separates, by frequency, the first signal and the second signal transmitted via the common terminal. The data transmission device according to (1) above. (3) The filter circuit attenuates the second signal. The data transmission device according to (2) above. (4) The filter circuit is a first HPF configured by a first capacitance and a first resistance. The data transmission device according to (3) above. (5) The receiving circuit further includes a canceller circuit that adds the signal that has passed through the first HPF to a signal that is an inverse phase of the output signal from the replica circuit of the transmitting circuit. The data transmission device according to (4) above. (6) The transmission circuit includes the replica circuit. The data transmission device according to (5) above. (7) The replica circuit is a circuit in which the output current of the transmission circuit is reduced by a predetermined reduction ratio. The data transmission device according to (5) or (6). (8) the receiving circuit further includes a second HPF having the same cutoff frequency as the cutoff frequency of the first HPF; The canceller circuit adds the signal that has passed through the first HPF and the reverse-phase signal of the output signal from the replica circuit that has passed through the second HPF. The data transmission device according to (7) above. (9) The second HPF is composed of a second capacitor whose capacitance value is reduced by a reduction ratio of the output current of the replica circuit, and a second resistor whose resistance value is increased by a factor corresponding to the reduction ratio of the output current of the replica circuit. The data transmission device according to (8) above. (10) The receiving circuit further includes a resistor that adjusts a voltage level based on a voltage level of the output signal of the replica circuit that is input to the second HPF to a voltage level of the second signal that is transmitted from the transmitting circuit via the common terminal. The data transmission device according to (8) or (9). (11) The first resistor is grounded via an LDO circuit biased to a predetermined voltage. The data transmission device according to any one of (4) to (10). (12) The data transmitted through the transmission path is video data. The data transmission device according to any one of (1) to (11). (13) The device that receives the video data The data transmission device according to (12) above. (14) The video data is transmitted based on the GVIF (registered trademark) standard. The data transmission device according to (12) or (13) above. (15) a common terminal connected to a transmission path through which a first signal and a second signal, which is transmitted in the opposite direction to the first signal and has a different frequency band from the first signal, are transmitted; a downstream signal receiving circuit that receives the first signal from the transmission path via the common terminal; an upstream signal transmitting circuit that transmits the second signal via the common terminal; a data receiving device comprising: a downstream signal transmitting circuit that transmits the first signal; an upstream signal receiving circuit for receiving the second signal from the transmission line; a data transmission device comprising: A data transmission system comprising: [Explanation of symbols]

[0080] 1 source device, 2 sink device, 3 transmission path, 11 downstream transmission processing section, 12 downstream signal transmission circuit, 13 upstream signal reception circuit, 14 upstream reception processing section, 21 LPF, 41 upstream transmission processing section, 42 upstream signal transmission circuit, 43 downstream signal reception circuit, 44 downstream reception processing section, 51, 52 HPF, 61 main circuit, 62 replica circuit, 81 common terminal, 101 canceller circuit

Claims

1. a common terminal connected to a transmission path through which a first signal and a second signal having a different frequency band from that of the first signal are transmitted, the second signal being transmitted in a direction opposite to that of the first signal; a receiving circuit that receives the first signal from the transmission line via the common terminal; a transmitting circuit that transmits the second signal via the common terminal; Equipped with The receiving circuit a first HPF that separates, by frequency, the first signal and the second signal transmitted via the common terminal; a canceller circuit that adds the signal that has passed through the first HPF and an inverted phase signal of the output signal from the replica circuit of the transmission circuit; Equipped with The replica circuit is a circuit that outputs a current having a current value obtained by reducing the current value of the output current of the transmission circuit by a predetermined reduction ratio. Data transmission device.

2. The first HPF attenuates the second signal.

2. The data transmission device according to claim 1.

3. The first HPF is a filter circuit configured by a first capacitance and a first resistance.

3. The data transmission device according to claim 2.

4. The transmission circuit includes the replica circuit.

4. The data transmission device according to claim 3.

5. the receiving circuit further includes a second HPF having the same cutoff frequency as the first HPF; The canceller circuit adds the signal that has passed through the first HPF and the reverse-phase signal of the output signal from the replica circuit that has passed through the second HPF.

5. The data transmission device according to claim 3 or 4.

6. The second HPF is composed of a second capacitor having a capacitance value obtained by reducing the capacitance value of the first capacitor by the same reduction ratio as the reduction ratio of the output current of the replica circuit with respect to the output current of the transmission circuit, and a second resistor having a resistance value obtained by increasing the resistance value of the first resistor by a factor corresponding to the reduction ratio of the output current of the replica circuit with respect to the output current of the transmission circuit.

6. The data transmission device according to claim 5.

7. The receiving circuit further includes a resistor that adjusts a voltage level based on a voltage level of the output signal of the replica circuit that is input to the second HPF to a voltage level of the second signal that is transmitted from the transmitting circuit via the common terminal.

7. The data transmission device according to claim 5 or 6.

8. The first resistor is grounded via an LDO circuit biased to a predetermined voltage.

8. A data transmission device according to claim 3.

9. The data transmitted through the transmission path is video data.

9. A data transmission device according to claim 1.

10. The device that receives the video data 10. The data transmission device according to claim 9.

11. The video data is transmitted based on the GVIF (registered trademark) standard.

11. The data transmission device according to claim 9 or 10.

12. a common terminal connected to a transmission path through which a first signal and a second signal having a different frequency band from that of the first signal are transmitted, the second signal being transmitted in a direction opposite to that of the first signal; an upstream signal transmitting circuit that transmits the second signal via the common terminal; a downstream signal receiving circuit that receives the first signal from the transmission path via the common terminal, the downstream signal receiving circuit including: a first HPF that separates, by frequency, the first signal and the second signal transmitted via the common terminal; and a canceller circuit that adds a signal that has passed through the first HPF to an inverted phase signal of an output signal from a replica circuit of the upstream signal transmitting circuit, the replica circuit being a circuit that outputs a current having a current value obtained by reducing the current value of the output current of the upstream signal transmitting circuit by a predetermined reduction rate; a data receiving device comprising: a downstream signal transmitting circuit that transmits the first signal; an upstream signal receiving circuit for receiving the second signal from the transmission line; a data transmission device comprising: A data transmission system comprising:

Images