Photoelectric conversion device

Abstract

To provide a photoelectric conversion device capable of enhancing dynamic resolution.SOLUTION: A photoelectric conversion device includes a pixel array including a plurality of pixels which is arranged in a plurality of rows and respectively outputs signals corresponding to incident light through photoelectric conversion, a scanning circuit which performs scanning for sequentially outputting signals from the pixels row by row, and a processing circuit for processing the signals output from the pixels. The processing circuit corrects an optical signal based on the incident light on the basis of, a first reset signal and a second reset signal based on a reset state of the pixels. The scanning circuit outputs the optical signal and the first reset signal from the pixels by scanning performed in different periods.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device that samples the reset level of pixels multiple times. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-004727 Summary of the Invention [Problem to be solved by the invention]

[0004] In a photoelectric conversion device that samples the reset level multiple times as described in Patent Document 1, the time required to read one row becomes long, which can lead to a problem of reduced dynamic resolution.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a photoelectric conversion device that can improve dynamic resolution. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a pixel array including a plurality of pixels arranged in a plurality of rows, each pixel outputting a signal corresponding to incident light by photoelectric conversion; and a pixel detector for outputting signals sequentially from the pixels row by row. No. 1 scanning a second scan for sequentially outputting signals from the pixels row by row during a period different from that of the first scan; of A plurality of scans including the above scans are performed within one frame period in which a signal used to generate one frame is output. and a processing circuit that processes signals output from the pixels, wherein the processing circuit corrects the optical signal based on the incident light based on a first reset signal and a second reset signal that are based on the reset state of the pixels, and the scanning circuit The first By scanning Before The first reset signal is output from the pixel, and the scanning circuit The second outputting the optical signal and the second reset signal from the pixel by scanning; The aforementioned There is provided a photoelectric conversion device, wherein the first reset signal, the second reset signal, and the optical signal are output from the pixel within one frame period.

[0007] According to another aspect of the present invention, there is provided a pixel array including a plurality of pixels arranged in a plurality of rows, each pixel outputting a signal corresponding to incident light by photoelectric conversion; and a pixel detector for outputting signals sequentially from the pixels row by row. No. 1 scanning a second scan for sequentially outputting signals from the pixels row by row during a period different from that of the first scan; of A plurality of scans including the above scans are performed within one frame period in which a signal used to generate one frame is output. and a scanning circuit for performing the scanning. The aforementioned A first reset signal based on the reset state of the pixel is output from the pixel by the first scan, Record number By scanning the pixel twice, an optical signal based on the incident light is output from the pixel. ,before a second reset signal based on a reset state of the pixel is output from the pixel by the second scanning, and the optical signal is not output from the pixel during the first scanning; The aforementioned There is provided a photoelectric conversion device, wherein the first reset signal, the second reset signal, and the optical signal are output from the pixel within one frame period. According to another aspect of the present invention, there is provided a pixel array including a plurality of pixels each having a photoelectric conversion unit, arranged in a plurality of rows, each outputting a signal corresponding to incident light by photoelectric conversion; and a display device for displaying a signal from the pixels in a row by row. No. 1 scanning a second scan for outputting signals subsequent to the first scan, in which signals are output from the pixels row by row; of Multiple scans including and a processing circuit that processes signals output from the pixels, wherein the processing circuit corrects the optical signal based on the incident light based on a first reset signal and a second reset signal that are based on the reset state of the pixels, and the scanning circuit The first By scanning Before The first reset signal is output from the pixel, and the scanning circuit The second The optical signal and the second reset signal are output from the pixel by scanning, 1 run Inspection and the aforementioned No. 2There is provided a photoelectric conversion device characterized in that shutter scanning is performed during scanning to reset and release the photoelectric conversion unit. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a photoelectric conversion device capable of improving dynamic resolution. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic block diagram of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Figure 3] FIG. 3 is a timing chart showing a scanning method for the photoelectric conversion device according to the first embodiment. [Figure 4] 4 is a timing chart showing a method for reading out one row of the photoelectric conversion device according to the first embodiment. FIG. [Figure 5] 4 is a timing chart showing a method for reading out one row of the photoelectric conversion device according to the first embodiment. FIG. [Figure 6] FIG. 10 is a timing chart showing an outline of a scanning method of a photoelectric conversion device according to a modified example of the first embodiment. [Figure 7] FIG. 10 is a timing chart showing a method for reading out one row of the photoelectric conversion device according to the second embodiment. [Figure 8] FIG. 10 is a timing chart showing a method for reading out one row of the photoelectric conversion device according to the third embodiment. [Figure 9] FIG. 10 is a timing chart showing a method for reading out one row of the photoelectric conversion device according to the third embodiment. [Figure 10] FIG. 10 is a timing diagram illustrating the influence of a high-brightness subject. [Figure 11] 10 is a flowchart illustrating processing of a photoelectric conversion device according to a fourth embodiment. [Figure 12] FIG. 10 is a circuit diagram of a pixel according to a fifth embodiment. [Figure 13] FIG. 13 is a circuit diagram of a pixel according to a sixth embodiment. [Figure 14] FIG. 13 is a circuit diagram of a comparison circuit according to a seventh embodiment. [Figure 15] FIG. 13 is a schematic diagram showing the structure of a photoelectric conversion device according to an eighth embodiment. [Figure 16] FIG. 13 is a block diagram of a device according to a ninth embodiment. [Figure 17] FIG. 19 is a block diagram of a device according to a tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical or corresponding elements throughout the drawings are designated by common reference numerals, and their description may be omitted or simplified. In each of the following embodiments, an imaging device will be mainly described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an imaging device and may also be applied to other devices. Examples of other devices include a range finder and a photometric device. The range finder may be, for example, a focus detection device, a distance measurement device using TOF (Time-Of-Flight), etc. The photometric device may be a device that measures the amount of light incident on the device.

[0011] [First embodiment] 1 is a schematic block diagram of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 10, a vertical scanning circuit 11, reference signal generation circuits 14a and 14b, counters 18a and 18b, horizontal scanning circuits 19a and 19b, processing circuits 20a and 20b, frame memories 21a and 21b, output circuits 22a and 22b, and a control circuit 23. The various circuits constituting the photoelectric conversion device may be formed on one or more semiconductor substrates.

[0012] The pixel array 10 has a plurality of pixels 100 arranged in a plurality of rows and a plurality of columns, each of which outputs a signal corresponding to incident light through photoelectric conversion. Each of the plurality of pixels 100 has a photoelectric conversion unit that generates and accumulates signal charges based on the incident light. Microlenses and color filters may be arranged on the pixels 100.

[0013] The photoelectric conversion device also has a column circuit corresponding to each column of the pixel array 10. The column circuit has a current source 13a, a comparator 15a, a first memory 16a, and a second memory 17a. Alternatively, the column circuit has a current source 13b, a comparator 15b, a first memory 16b, and a second memory 17b.

[0014] The column signal lines 12a and 12b are provided for each column of pixels 100, and the pixels 100 in the same column output signals to the common column signal lines 12a and 12b. In this embodiment, the column signal lines 12a for odd-numbered columns and the column signal lines 12b for even-numbered columns may be connected to different circuits. That is, the pixels 100 in odd-numbered columns are read out by the circuit in the lower part of FIG. 1 via the column signal line 12a, and the pixels 100 in even-numbered columns are read out by the circuit in the upper part of FIG. 1 via the column signal line 12b. The number of column signal lines provided for each column of pixels 100 is not limited to one and may be multiple. Also, while FIG. 1 shows four column circuits, a greater number of column circuits are actually provided. Typically, the number of column circuits ranges from several hundred to several thousand.

[0015] 1, the reference numerals of the lower circuits that output signals from odd-numbered column signal lines 12a are suffixed with "a," and the reference numerals of the upper circuits that output signals from even-numbered column signal lines 12b are suffixed with "b." Because the configurations and functions of both circuits are similar, the following mainly describes only the elements that are suffixed with "a," and explanations of the elements that are suffixed with "b" may be omitted.

[0016] The control circuit 23 controls the vertical scanning circuit 11, the reference signal generating circuits 14a and 14b, the counters 18a and 18b, the horizontal scanning circuits 19a and 19b, the processing circuits 20a and 20b, the frame memories 21a and 21b, the output circuits 22a and 22b, and the first memories 16a and 16b. The control circuit 23 supplies control signals and the like that instruct the operation timing of each of these components.

[0017] The vertical scanning circuit 11 includes a shift register, a gate circuit, a buffer circuit, etc. The vertical scanning circuit 11 (scanning circuit) outputs control signals to the pixels 100 based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., and performs scanning to cause the pixels 100 to output signals sequentially row by row.

[0018] A column circuit including a current source 13a, a comparator 15a, a first memory 16a, and a second memory 17a processes signals output from the pixels 100 via the column signal lines 12a. Specifically, the column circuit amplifies the signals on the column signal lines 12a and performs AD (Analog to Digital) conversion. The current source 13a is connected to the column signal lines 12a and functions as a load circuit that supplies a drive current for signal output from the pixels 100. The comparator 15a compares a reference signal with the signal on the column signal line 12a. The first memory 16a and the second memory 17a hold count signals according to the comparison result by the comparator 15a.

[0019] The comparator 15a includes a differential amplifier circuit or the like and has an inverting input node, a non-inverting input node, and an output node. The inverting input node is connected to the column signal line 12a, and a reference signal RAMP is input to the non-inverting input node. The comparator 15a compares the reference signal RAMP with the signal from the pixel 100 and outputs a comparison signal representing the comparison result from the output node.

[0020] The reference signal generating circuit 14a generates a reference signal RAMP (ramp signal) whose voltage changes over time based on clock pulses output from the control circuit 23 or a clock generating circuit (not shown). The reference signal generating circuit 14a can be configured using various methods, such as a capacitive charging / discharging method, a DAC method, or a current steering method. The reference signal RAMP may be an up-slope signal in which the voltage increases over time, or a down-slope signal in which the voltage decreases over time. The reference signal RAMP may also include multiple slope waveforms with different voltage change rates per unit time.

[0021] The counter 18a counts clock pulses output from the control circuit 23 or a clock generation circuit (not shown) and counts up or down a count signal, which is a digital signal having a predetermined number of bits. The control circuit 23 or the clock generation circuit includes an oscillator circuit and supplies clock pulses to the counter 18a. The counter 18a starts counting clock pulses simultaneously with the start of a voltage change in the reference signal RAMP from the reference signal generation circuit 14a, and outputs the clock signal to the first memory 16a via a wiring.

[0022] The first memory 16a receives the comparison signal from the comparator 15a and the count value from the counter 18a. The first memory 16a latches the count signal when the comparison result is inverted. The count signal held in the first memory 16a represents a digital value obtained by analog-to-digital conversion of an analog signal. When a pulse of the control signal MTX is input from the control circuit 23 to the first memory 16a and the second memory 17a, the count value held in the first memory 16a is transferred to the second memory 17a. The second memory 17a can hold the count value transferred from the first memory 16a. The first memory 16a and the second memory 17a can each hold a count signal when the pixel 100 is reset and a count signal based on photoelectric conversion of the pixel 100.

[0023] The horizontal scanning circuit 19a includes a shift register, a gate circuit, a buffer circuit, etc. Based on the pulse of the control signal HTX supplied from the control circuit 23, the horizontal scanning circuit 19a sequentially outputs a control signal to the second memory 17a of the corresponding column via the wiring corresponding to each column. As a result, the count values ​​held in the second memory 17a are transferred sequentially for each column to the processing circuit 20a. The pulse of the control signal HTX is a signal that indicates the start timing of horizontal transfer of signals from the second memory 17a to the processing circuit 20a.

[0024] The processing circuit 20a includes a digital signal processor and a line memory, and has the function of performing processing such as digital correlated double sampling. The processing circuit 20a performs predetermined signal processing on the input count value and stores the result in the frame memory 21a. Specific details of the signal processing will be described later. The line memory in the processing circuit 20a is used to temporarily store signals for digital correlated double sampling. The signals held in the frame memory 21a are output to the outside of the photoelectric conversion device via the output circuit 22a in a format such as LVDS (Low Voltage Differential Signaling) under the control of the control circuit 23.

[0025] As described above, the first memory 16a and the second memory 17a have the function of holding the AD conversion results for one pixel. In contrast, the frame memory 21a has a data capacity that can collectively hold the AD conversion results of signals output from all of the pixels 100 in odd-numbered columns among the pixels 100 included in the pixel array 10. Furthermore, the frame memory 21b has a data capacity that can collectively hold the AD conversion results of signals output from all of the pixels 100 in even-numbered columns among the pixels 100 included in the pixel array 10. In other words, the combined data capacity of the frame memory 21a and the frame memory 21b is equivalent to one frame's worth of data. Furthermore, the frame memories 21a and 21b may have data capacities equivalent to multiple frames.

[0026] 1 illustrates an example in which a count signal is input from a common counter 18a to the plurality of first memories 16a, but this is not limiting. For example, a plurality of counters 18a may be provided corresponding to the plurality of first memories 16a, respectively. In this case, a common clock pulse is input to the plurality of counters 18a, and each of the plurality of counters 18a generates a count signal based on the common clock pulse.

[0027] FIG. 2 is a circuit diagram of a pixel 100 according to this embodiment. The pixel 100 may include a photoelectric conversion unit PD, a transfer transistor M1, a floating diffusion FD, a reset transistor M2, a source follower transistor M3, and a selection transistor M4. In the following description, unless otherwise specified, these transistors are assumed to be N-type MOS (Metal Oxide Semiconductor) transistors. A reference voltage (e.g., ground voltage GND) is supplied to the back gate nodes (not shown) of these transistors. The drain nodes of the reset transistor M2 and the source follower transistor M3 are connected to a power supply voltage Vdd. Note that P-type MOS transistors may be used instead of N-type MOS transistors. In this case, the voltage of a control signal applied to the gate node of the P-type MOS transistor is inverted relative to the voltage of the control signal applied to the gate node of the N-type MOS transistor.

[0028] The photoelectric conversion unit PD is, for example, a photodiode, which generates charges by photoelectric conversion of incident light and accumulates the generated charges. Note that instead of a photodiode, a configuration that generates a photoelectric effect, such as an organic photoelectric conversion film or a photogate, may be used. The photoelectric conversion unit PD is provided with a microlens, and light collected by the microlens is incident on the photoelectric conversion unit PD. The number of photoelectric conversion units PD included in one pixel 100 is not limited. For example, two, four, or more photoelectric conversion units PD may be provided so as to share one microlens. This makes it possible to obtain a ranging signal used for autofocusing using a phase difference detection method. Furthermore, dark current noise can be reduced by using an embedded photodiode as the photoelectric conversion unit PD.

[0029] The transfer transistor M1 is provided corresponding to the photoelectric conversion unit PD, and a control signal TX is applied to the gate node of the transfer transistor M1. When the control signal TX goes high, the charge generated by receiving light in the photoelectric conversion unit PD and accumulated therein is transferred to the floating diffusion FD via the transfer transistor M1.

[0030] A power supply voltage Vdd is applied to the drain node of the source follower transistor M3. The source potential of the source follower transistor M3 changes depending on the amount of charge transferred to the floating diffusion FD.

[0031] The selection transistor M4 is provided between the source follower transistor M3 and the column signal line 12a. The selection transistors M4 of multiple rows of pixels 100 in the same column are connected to a common column signal line 12a. The current source 13a and the source follower transistor M3 form a source follower. A control signal SEL is applied to the gate node of the selection transistor M4. When the control signal SEL goes high, the selection transistor M4 outputs a signal corresponding to the source potential of the source follower transistor M3 to the column signal line 12a.

[0032] The source node of the reset transistor M2 is connected to the floating diffusion FD, and the power supply voltage Vdd is applied to the drain node of the reset transistor M2. A control signal RES is applied to the gate node of the reset transistor M2. When the control signal RES goes high, the reset transistor M2 resets the potential of the floating diffusion FD.

[0033] FIG. 3 is a timing diagram illustrating a scanning method for a photoelectric conversion device according to this embodiment. FIG. 3 schematically illustrates the timing of the control signal VD, which initiates row-sequential readout of the pixel array 10, the scanning of the pixel array 10, the write scanning of the frame memory 21a, and the read scanning of the frame memory 21a. The horizontal direction in FIG. 3 represents the passage of time. The vertical direction of each of the "pixel array 10 scanning," "frame memory 21a write scanning," and "frame memory 21a read scanning" indicates the corresponding row of the pixel array 10. The diagonal lines representing each scan indicate the relationship between the row and the time at which the read, write, and other processes are performed in each scan. As shown in FIG. 3, each scan first processes the first row, then the second row, and so on, sequentially processing each row over time. This type of scanning is sometimes referred to as row-sequential scanning. The rising edge of the control signal VD pulse in FIG. 3 corresponds to the time at which the vertical scanning circuit 11 starts outputting the control signal for readout scanning and the start of readout of the first row of the pixel array 10.

[0034] At time t1, shutter scanning begins in the pixel array 10. As a result, shutter operations are performed sequentially in the pixel array 10, starting with the pixels 100 in the first row. The shutter operation is a process in which the transfer transistor M1 and reset transistor M2 are turned on in the pixels 100, thereby resetting the photoelectric conversion unit PD, and then the reset of the photoelectric conversion unit PD is released. After the reset of the photoelectric conversion unit PD is released, the photoelectric conversion unit PD starts generating and accumulating charges in response to incident light.

[0035] At time t2, the pulse of the control signal VD rises, starting a readout scan (first scan) of the reset signal in the pixel array 10. As a result, a reset signal (first reset signal) is output sequentially from the pixels 100 in the first row in the pixel array 10. The reset signal is an output signal in a state (reset state) in which the reset transistor M2 is on and the potential of the floating diffusion FD of the pixel 100 is reset. This reset signal is also called an N signal.

[0036] At time t2, in parallel with the readout scan, a write scan of the readout signal to the frame memory 21a begins. In this process, the reset signal read out from the pixel array 10 is AD converted. The processing circuit 20a halves the digital value of the AD-converted reset signal by bit-shifting it to the right. The reset signal thus halved is sometimes called an N / 2 signal. The N / 2 signal is written to the frame memory 21a.

[0037] At time t3, when the readout scanning of the pixel array 10 and the write scanning of the frame memory 21a are completed up to the last row, the readout scanning (second scanning) of the pixel array 10 and the write scanning of the frame memory 21a start again from the first row. In the scanning from time t3, a reset signal (second reset signal) and an optical signal are output sequentially from the pixels 100 in the pixel array 10, starting from the first row. The reset signal is the same as described above and is an output signal when the potential of the floating diffusion FD is reset. The optical signal is an output signal based on the potential of the floating diffusion FD after the charge accumulated in the photoelectric conversion unit PD is transferred to the floating diffusion FD as a result of the transfer transistor M1 being turned on. This optical signal is also called an S signal.

[0038] At time t3, in parallel with the readout scanning of the pixel array 10, a write scanning of the readout signals to the frame memory 21a begins. In this process, the reset signal and optical signal read out from the pixel array 10 are each AD converted. The processing circuit 20a halves the digital value of the AD-converted reset signal by bit-shifting it to the right. The reset signal thus halved is sometimes called an N / 2 signal. The processing circuit 20a also performs a process of subtracting the reset signal (N / 2 signal) halved from the optical signal (S signal). The signal obtained by this process is sometimes called an SN / 2 signal. The SN / 2 signal is written to the frame memory 21a.

[0039] At time t4, after the scanning performed from time t3 is completed, read scanning of the frame memory 21a begins. In the scanning performed from time t4, the N / 2 signal obtained by the scanning performed from time t2 and the SN / 2 signal obtained by the scanning performed from time t3 are read out row by row from the frame memory 21a, calculated, and output from the output circuit 22a. This calculation process may be a process of subtracting the N / 2 signal from the SN / 2 signal. This results in a signal indicating the result of subtracting two N / 2 signals from the S signal. This process corresponds to a process of subtracting the average of two N signals from the S signal. The average of the two N signals is sometimes called the Nave signal, and the signal obtained by subtracting the N / 2 signal from the SN / 2 signal is sometimes called the S-Nave signal.

[0040] From time t5 to time t8 and from time t9 to time t12, the same scanning as from time t1 to time t4 is performed. Although not shown in the figure, similar scanning can be repeated from time t12 onwards.

[0041] 4 and 5 are timing diagrams showing a method for reading out one row of the photoelectric conversion device according to this embodiment. Fig. 4 shows the processing for one row of readout scanning of N signals in the pixel array 10 and write scanning of N / 2 signals into the frame memory 21a, which starts at time t2. Fig. 5 shows the processing for one row of readout scanning of N signals and S signals in the pixel array 10 and write scanning of S / N / 2 signals into the frame memory 21a, which starts at time t3. Figs. 4 and 5 show the potential levels of the control signals TX, RES, MTX, and HTX, the potential of the reference signal RAMP, and the potential of the column signal line 12a.

[0042] First, referring to Figure 4, the operation of reading out N signals from the pixels 100 in one row and writing N / 2 signals to the frame memory 21a will be described. At time t20, the control signal RES goes high. Then, at time t21, the control signal RES goes low. These operations temporarily turn on the reset transistor M2, resetting the potential of the floating diffusion FD. In response, the potential of the column signal line 12a goes to the reset level.

[0043] At time t22, the potential of the reference signal RAMP output from the reference signal generating circuit 14a starts to change, and simultaneously, the count signal output from the counter 18a starts to change.

[0044] At time t23, when the magnitude relationship between the reference signal RAMP input to the comparator 15a and the potential of the column signal line 12a is inverted, the first memory 16a holds the count signal at that time. As a result, the first memory 16a acquires a digital signal corresponding to the time from time t22 to time t23. In this manner, AD conversion of the reset signal is performed. Thereafter, at time t24, the potential of the reference signal RAMP output from the reference signal generation circuit 14a is reset.

[0045] At time t25, the control signal MTX goes high. Then, at time t26, the control signal MTX goes low. In response to this pulse of the control signal MTX, the reset signal held in the first memory 16a is transferred to the second memory 17a.

[0046] At time t27, the control signal HTX goes high. Then, at time t28, the control signal HTX goes low. In response to this pulse of the control signal HTX, the horizontal scanning circuit 19a starts horizontal transfer, transferring the reset signal stored in the second memory 17a to the processing circuit 20a, column by column. As described above, the processing circuit 20a performs a right bit shift on the reset signal transferred from the second memory 17a, column by column, multiplying the value by 2 before transferring it to the frame memory 21a. In this way, an N / 2 signal is written to the frame memory 21a.

[0047] Next, the operation of reading out N and S signals from one row of pixels 100 and writing S / N / 2 signals to the frame memory 21a will be described with reference to Figure 5. From time t30 to time t38, the N signals are read out from the pixels 100 and the N / 2 signals are generated by operations similar to those from time t20 to time t28 in Figure 4. However, the generated N / 2 signals are not transferred to the frame memory 21a but are temporarily held in the line memory within the processing circuit 20a.

[0048] At time t39, the control signal TX goes high. Then, at time t40, the control signal TX goes low. These operations temporarily turn on the transfer transistor M1, transferring the charge accumulated in the photoelectric conversion unit PD to the floating diffusion FD, and the potential of the floating diffusion FD drops in accordance with the amount of transferred charge. As a result, the potential of the column signal line 12a reaches a level corresponding to the charge accumulated in the photoelectric conversion unit PD.

[0049] At time t41, the potential of the reference signal RAMP output from the reference signal generating circuit 14a starts to change, and simultaneously, the count signal output from the counter 18a starts to change.

[0050] At time t42, when the magnitude relationship between the reference signal RAMP input to the comparator 15a and the potential of the column signal line 12a is inverted, the first memory 16a holds the count signal at that time. As a result, the first memory 16a acquires a digital signal corresponding to the time from time t41 to time t42. In this manner, AD conversion of the optical signal is performed. Thereafter, at time t43, the potential of the reference signal RAMP output from the reference signal generation circuit 14a is reset.

[0051] At time t44, the control signal MTX goes high. Then, at time t45, the control signal MTX goes low. In response to this pulse of the control signal MTX, the optical signal held in the first memory 16a is transferred to the second memory 17a.

[0052] At time t46, the control signal HTX goes high. Thereafter, at time t47, the control signal HTX goes low. In response to this pulse of the control signal HTX, the horizontal scanning circuit 19a starts horizontal transfer, transferring the optical signals stored in the second memory 17a to the processing circuit 20a, column by column. As described above, the processing circuit 20a subtracts the N / 2 signal stored in the line memory within the processing circuit 20a from the optical signals transferred from the second memory 17a, column by column, and then transfers the resulting signals to the frame memory 21a. In this way, the S / N / 2 signal is written to the frame memory 21a.

[0053] As described above, in this embodiment, two row sequential scans are performed for one frame of image, or for one pulse of the control signal VD in FIG. 3. These two row sequential scans then obtain two reset signals and one optical signal used for correlated double sampling. In this way, two reset signals can be used for correlated double sampling, which further reduces noise compared to when only one reset signal is used for correlated double sampling.

[0054] Furthermore, in this embodiment, one reset signal is acquired by row sequential scanning separate from the row sequential scanning used to acquire the optical signal. This shortens the readout time for one row in the row sequential scanning used to acquire the optical signal, compared to acquiring two reset signals simultaneously using the same row sequential scanning used to acquire the optical signal, thereby improving dynamic resolution. Therefore, this embodiment provides a photoelectric conversion device capable of improving dynamic resolution. For example, when the photoelectric conversion device is an imaging device that captures an image, improving dynamic resolution can reduce subject blur.

[0055] Although not essential, in this embodiment, one reset signal is acquired by the same row sequential scanning as that used to acquire the optical signal, which allows one reset signal and the optical signal to be acquired at close times, thereby reducing the effects of low-frequency power supply noise, etc.

[0056] The above-described driving method of the photoelectric conversion device is an example and is not limited to this. A modified driving method will be described below with reference to FIG. 6. FIG. 6 is a timing chart showing a scanning method of a photoelectric conversion device according to a modified example of this embodiment. In the description of FIG. 6, parts common to FIG. 3 may be omitted or simplified.

[0057] 6, the shutter scanning from time t1 and the read scanning and write scanning of the reset signal from time t2 are the same as those in Fig. 3, and therefore their explanations are omitted. That is, N / 2 signals are written to the frame memory 21a in the same manner as in the driving method in Fig. 3.

[0058] At time t3a, when the readout scanning of the pixel array 10 and the write scanning of the frame memory 21a are completed up to the last row, readout scanning of the pixel array 10 starts again from row 1. In the readout scanning from time t3a, reset signals and optical signals are output sequentially from the pixels 100 in the first row in the pixel array 10, similar to the driving method of FIG.

[0059] Also, at time t3a, in parallel with the readout scanning of the pixel array 10, readout scanning of the frame memory 21a and write scanning of the calculated signal to the frame memory 21a begin. In this process, the reset signal and optical signal read out from the pixel array 10 are each AD converted. The processing circuit 20a performs a right bit shift on the digital value of the AD-converted reset signal to generate an N / 2 signal, and performs a process of subtracting the N / 2 signal from the optical signal (S signal). This generates an S-Nave signal. The processing circuit 20a then reads out the N / 2 signal acquired by the scanning from time t2 from the frame memory 21a and further performs a process of subtracting it from the S-Nave signal. This generates an S-Nave signal. The generated corrected S-Nave signal is written to the frame memory 21a.

[0060] At time t4a, readout scanning of the frame memory 21a starts. In the scanning from time t4a, the S-Nave signal is output from the output circuit 22a sequentially row by row from the frame memory 21a.

[0061] From time t5 to time t8a and from time t9 to time t12a, the same scanning as from time t1 to time t4a is performed. Although not shown in the figure, similar scanning can be repeated from time t12a onwards.

[0062] In the driving method of Fig. 3, the N / 2 signal and the SN / 2 signal are stored in the frame memory 21a at the same time, so the frame memory 21a requires a data capacity for two frames. In contrast, in the driving method of Fig. 6, the data capacity of the frame memory 21a is only required for one frame, so the data capacity of the frame memory 21a is reduced.

[0063] On the other hand, in the driving method of FIG. 6, reading from the frame memory 21a is added in the scanning from time t3a, so power consumption during operation increases compared to the driving method of FIG. 3. In addition, there is a possibility that interference noise may occur due to reading from the frame memory 21a. Therefore, the driving method of FIG. 3 is more suitable than the driving method of FIG. 6 in terms of power consumption and noise reduction. As described above, the driving method of FIG. 3 and the driving method of FIG. 6 have their advantages and disadvantages. They can be selected appropriately taking into account design requirements, etc.

[0064] The above-described method for calculating the S-Nave signal is one example. The N signal may be written directly to the frame memory 21a without being shifted to the right during row sequential scanning from time t2, and the Nave signal may be generated by averaging it with the N signal acquired during row sequential scanning from time t3 (or time t3a). In this case, the S-Nave signal can be acquired by subtracting the Nave signal from the S signal, similar to the driving method of FIG. 3 or 6.

[0065] [Second embodiment] A photoelectric conversion device according to a second embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first embodiment will be denoted by the same reference numerals, and detailed description may be omitted or simplified.

[0066] In the first embodiment, two reset signals are obtained by two sequential row scans, but in the photoelectric conversion device of this embodiment, four reset signals are obtained by two sequential row scans. The difference from the first embodiment is that the process of FIG. 4 is replaced by the process of FIG. 7, which will be described later. Other points are generally similar to those of the first embodiment, so a description thereof will be omitted.

[0067] Fig. 7 is a timing diagram showing a method for reading out one row of the photoelectric conversion device according to this embodiment. The operation from time t20 to time t28 shown in Fig. 7 is the same as the operation from time t20 to time t28 shown in Fig. 4. After time t28, the same operation is repeated two more times, and a total of three reset signals are read out.

[0068] In this embodiment, the processing circuit 20a performs a two-bit right shift on the reset signal transferred from the second memory 17a for each column, multiplying the value by 1 / 4. The reset signal converted to 1 / 4 in this manner is sometimes called an N / 4 signal. The processing circuit 20a then adds three N / 4 signals and transfers the result to the frame memory 21a. The signal obtained by adding the three N / 4 signals in this manner is sometimes called a 3N / 4 signal. To achieve this processing, the processing circuit 20a may include a line memory that temporarily stores the three N / 4 signals.

[0069] The processing at time t3 in FIG. 3 is generally the same as in the first embodiment, except that the amount of right bit shift for the reset signal is 2 bits. That is, the processing circuit 20a performs processing to subtract a reset signal (N / 4 signal) that has been converted to 1 / 4 from the optical signal (S signal). The signal obtained by this processing is sometimes called an SN / 4 signal. The SN / 4 signal is written to the frame memory 21a. In the scanning from time t4 in FIG. 3, the S-Nave signal is generated and output by subtracting the 3N / 4 signal from the SN / 4 signal.

[0070] In this embodiment, four reset signals and one optical signal used for correlated double sampling are acquired by two row-sequential scans. In this way, four reset signals can be used for correlated double sampling, which reduces noise more than in the first embodiment, in which only two reset signals are used. Therefore, this embodiment provides a photoelectric conversion device that can further reduce noise in addition to achieving the same effects as the first embodiment.

[0071] Note that the example of using two reset signals in the first embodiment and the example of using four reset signals in the second embodiment are merely illustrative. The number of reset signals may be any number, and can be changed as appropriate depending on the required noise level, etc. When the number of reset signals used in correlated double sampling is n, similar processing can be achieved by subtracting from the optical signal each of the reset signals multiplied by 1 / n. However, since division of digital values ​​can be easily performed by right bit shifting, it is desirable that n be a power of 2.

[0072] [Third embodiment] A photoelectric conversion device according to a third embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first or second embodiment will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0073] In the first embodiment, one reset signal is acquired by the first row sequential scanning, and one reset signal and one optical signal are acquired by the second row sequential scanning. In contrast, in the photoelectric conversion device of this embodiment, two reset signals (a first reset signal and a second reset signal) are acquired by the first row sequential scanning, and one optical signal is acquired by the second row sequential scanning. In this embodiment, the processes of FIGS. 4 and 5 of the first embodiment are replaced by the processes of FIGS. 8 and 9, respectively, which will be described later. Other points are generally similar to those of the first embodiment, and therefore description thereof will be omitted.

[0074] 8 and 9 are timing diagrams showing a method for reading out one row of the photoelectric conversion device according to this embodiment. The operation from time t20 to time t28 shown in Fig. 8 is the same as the operation from time t20 to time t28 shown in Fig. 4. After time t28, the same operation is repeated once more, and a total of two reset signals are read out.

[0075] The operations at times t30, t31, t39 to t47 shown in Fig. 9 are the same as the operations at the times indicated by the same reference numerals in Fig. 5. Furthermore, the operations at times t32 to t38 in Fig. 5 are omitted in Fig. 9. That is, in the operation in Fig. 9, the readout of the reset signal is omitted from the operation in Fig. 5, and only the optical signal is read out.

[0076] In the readout method of this embodiment, two reset signals are each bit-shifted to the right to generate two N / 2 signals, which are then subtracted from the S signal to obtain the S-Nave signal. Therefore, as in the first embodiment, correlated double sampling using two reset signals can be performed, reducing noise.

[0077] Also, in this embodiment, as in the first embodiment, the reset signal is acquired by row sequential scanning separate from the row sequential scanning used to acquire the optical signal. This allows the time required for row sequential scanning to acquire the optical signal to be shortened, improving dynamic resolution, compared to when two reset signals are acquired collectively by the same row sequential scanning used to acquire the optical signal. Therefore, as in the first embodiment, this embodiment also provides a photoelectric conversion device that can improve dynamic resolution.

[0078] 6, the N / 2 signal may be read from the frame memory 21a at time t3a and subtracted from the S signal. In this case, the data capacity of the frame memory 21a can be reduced, similarly to the modification of FIG.

[0079] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first to third embodiments will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0080] The photoelectric conversion device of this embodiment has a function of making a judgment based on a reset signal and changing the content of correction by correlated double sampling depending on the judgment result.Other points are generally the same as those of the first embodiment, so a description thereof will be omitted.

[0081] Before describing the configuration of this embodiment, the influence of a high-brightness subject, which is a premise of the photoelectric conversion device of this embodiment, will be described with reference to FIG. 10 . FIG. 10 is a timing diagram illustrating the influence of a high-brightness subject, and the operation timing of each control signal is the same as FIG. 4 . Here, assume that a high-brightness subject is present within the imaging range during the readout scan starting at time t2 in FIG. 6 of the first embodiment. In this case, as shown in FIG. 10 , after the control signal RES goes low at time t21 and the reset of the floating diffusion FD is released, the potential of the column signal line 12a may drop. This occurs because a large amount of charge generated in the photoelectric conversion unit PD due to strong incident light from the high-brightness subject overflows from the photoelectric conversion unit PD to the floating diffusion FD. In this case, the timing of time t23, when the magnitude relationship between the reference signal RAMP input to the comparator 15a and the potential of the column signal line 12a is reversed, is shifted, which may result in an error in the value of the reset signal after AD conversion. For this reason, if a high-brightness subject is present in the period from time t2 to time t3a, an error occurs in the reset signal due to the influence of the high-brightness subject, which can result in an effective decrease in time resolution.

[0082] Therefore, in this embodiment, the processing circuit 20a has a reset signal determination function. Fig. 11 is a flowchart explaining the processing of the photoelectric conversion device according to this embodiment. The reset signal determination processing in the processing circuit 20a will be explained with reference to Fig. 11. Note that the processing in Fig. 11 is performed in conjunction with read scanning from the frame memory 21a and write scanning to the frame memory 21a in the processing after time t3a in Fig. 6.

[0083] In step S11, the processing circuit 20a determines whether a determination signal based on the reset signal satisfies a predetermined determination condition. The determination signal may be, for example, the N / 2 signal stored in the frame memory 21a by scanning from time t2. The determination condition here may be, for example, based on whether the N / 2 signal read from the frame memory 21a exceeds a predetermined threshold. Alternatively, the determination condition may be, for example, based on whether a signal corresponding to the difference between the N / 2 signal read from the frame memory 21a and the N / 2 signal calculated from the reset signal read from the pixel 100 in scanning after time t3a exceeds a predetermined threshold.

[0084] If the predetermined determination condition is not met (NO in step S12), the process proceeds to step S13. This situation corresponds to the case where the high-brightness subject described above does not exist. If the predetermined determination condition is met (YES in step S12), the process proceeds to step S14. This situation corresponds to the case where the high-brightness subject described above exists.

[0085] In step S13, the processing circuit 20a subtracts two N / 2 signals from the S signal and outputs the S-Nave signal. This processing is similar to that described in the modified example of the first embodiment.

[0086] In step S14, the processing circuit 20a subtracts the reset signal read from the pixel 100 during scanning after time t3a from the S signal without right-bit shifting, thereby outputting the S-Nave signal. That is, the reset signal read during scanning from time t2 to time t3a is not used for correlated double sampling. Therefore, if a high-brightness subject is present during the period from time t2 to time t3a and an error occurs in the reset signal, the reset signal can be prevented from being used for correlated double sampling. Therefore, this embodiment provides a photoelectric conversion device that can suppress a decrease in effective temporal resolution due to a high-brightness subject.

[0087] [Fifth embodiment] A photoelectric conversion device according to the fifth embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first to fourth embodiments will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0088] The photoelectric conversion device of this embodiment is a modified example in which the configuration of the pixel 100 of the first embodiment is changed from that of Fig. 2. Other points are generally similar to those of the first embodiment, and therefore description thereof will be omitted.

[0089] FIG. 12 is a circuit diagram of a pixel 100 according to this embodiment. In addition to the configuration of the pixel 100 in FIG. 2, the pixel 100 further includes a capacitance switching transistor M5. The source node of the capacitance switching transistor M5 is connected to the floating diffusion FD, and the drain node of the capacitance switching transistor M5 is connected to the source node of the reset transistor M2. A control signal FDINC is applied to the gate node of the capacitance switching transistor M5. When the control signal FDINC goes high, the capacitance switching transistor M5 is turned on, and the parasitic capacitance of the floating diffusion FD increases. In this way, by changing the capacitance of the floating diffusion FD, the gain of the signal output from the pixel 100 can be changed. The capacitance can be switched using the control signal FDINC for each frame or during the readout period of one row. This embodiment provides a photoelectric conversion device capable of switching gain.

[0090] [Sixth embodiment] A photoelectric conversion device according to the sixth embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first to fifth embodiments will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0091] The photoelectric conversion device of this embodiment is a modified example in which the configuration of the pixel 100 of the first embodiment is changed from that of Fig. 2. Other points are generally similar to those of the first embodiment, and therefore description thereof will be omitted.

[0092] 13 is a circuit diagram of a pixel 100 according to this embodiment. The pixel 100 includes two photoelectric conversion units PDA and PDB and two transfer transistors M1A and M1B. The two photoelectric conversion units PDA and PDB are configured to receive light that has passed through different regions of the same microlens.

[0093] The transfer transistor M1A is provided corresponding to the photoelectric conversion unit PDA, and a control signal TXA is applied to the gate node of the transfer transistor M1A. When the control signal TXA goes high, the charge generated by receiving light in the photoelectric conversion unit PDA and accumulated therein is transferred to the floating diffusion FD via the transfer transistor M1A.

[0094] The transfer transistor M1B is provided corresponding to the photoelectric conversion unit PDB, and a control signal TXB is applied to the gate node of the transfer transistor M1B. When the control signal TXB becomes high level, the charge generated by receiving light in the photoelectric conversion unit PDB and accumulated therein is transferred to the floating diffusion FD via the transfer transistor M1B.

[0095] The pixel 100 of this embodiment can acquire a signal based on the charges accumulated in the photoelectric conversion unit PDA and a signal based on the charges accumulated in the photoelectric conversion unit PDB. These signals can be used as signals for distance measurement, such as focus detection using a phase difference detection method. This embodiment provides a photoelectric conversion device capable of acquiring signals for distance measurement.

[0096] Although modified examples of the configuration of the pixel 100 have been described in the fifth and sixth embodiments, the configuration of the pixel 100 is not particularly limited. For example, a single pixel 100 may be configured to have a plurality of selection transistors and a plurality of column signal lines. In this case, by controlling the plurality of selection transistors, it is possible to select a column signal line that outputs a signal from the pixel 100.

[0097] [Seventh embodiment] A photoelectric conversion device according to the seventh embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first to sixth embodiments will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0098] The photoelectric conversion device of this embodiment is a modified example in which the circuit configuration around the comparator 15a of the first embodiment in Fig. 2 is changed. Other points are generally the same as those of the first embodiment, so a description thereof will be omitted.

[0099] FIG. 14 is a circuit diagram of a comparator circuit according to this embodiment. As shown in FIG. 14, a comparator 15a according to this embodiment is a fully differential comparator having an inverting input node, a non-inverting input node, an inverting output node, and a non-inverting output node. Capacitors 50a and 51a and switches 52a and 53a are connected to the comparator 15a. The capacitor 50a is disposed between the column signal line 12a and the inverting input node. The capacitor 51a is disposed between a line through which the reference signal RAMP is transmitted and the non-inverting input node. The switch 52a is disposed between the inverting input node and the non-inverting output node. The switch 52a is disposed between the non-inverting input node and the inverting output node. By turning on the switches 52a and 53a, the offset level of the comparator circuit of FIG. 14 can be reset to a voltage corresponding to the difference between the potential of the column signal line 12a and the potential of the reference signal RAMP. This process is sometimes referred to as an auto-zero operation. According to this embodiment, a photoelectric conversion device capable of performing auto-zero operation in a comparator for AD conversion is provided.

[0100] [Eighth embodiment] A photoelectric conversion device according to the eighth embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first to seventh embodiments will be denoted by the same reference numerals, and detailed description thereof may be omitted or simplified.

[0101] The photoelectric conversion device of this embodiment is a modified example of the photoelectric conversion device of the first embodiment, configured using a plurality of substrates. Other points are generally similar to those of the first embodiment, and therefore description thereof will be omitted.

[0102] FIG. 15 is a schematic diagram showing the structure of a photoelectric conversion device according to this embodiment. The photoelectric conversion device according to this embodiment is composed of a pixel substrate 60 and a circuit substrate 61 stacked on top of each other. The pixel array 10 described in the first embodiment is arranged on the pixel substrate 60. At least a portion of the circuits other than the pixel array 10 described in the first embodiment is arranged on the circuit substrate 61. Note that all of the circuits other than the pixel array 10 described in the first embodiment may be arranged on the circuit substrate 61. According to this embodiment, a stacked photoelectric conversion device is provided.

[0103] The photoelectric conversion device may have a stacked structure of three or more layers. In the case of a three-layer structure, the pixel array 10 may be arranged on a first substrate, the processing circuit 20a may be arranged on a second substrate, and the frame memory 21a and the output circuit 22a may be arranged on a third substrate. The current source 13a, the comparator 15a, the first memory 16a, and the second memory 17a may be arranged on the second substrate.

[0104] [Ninth embodiment] The photoelectric conversion device in the above-described embodiment can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 16 shows a block diagram of a digital still camera as an example of such a device.

[0105] The device 7 shown in FIG. 16 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 70 (an example of a photoelectric conversion device). The device 7 also includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 70 is configured as in the above-described embodiment, and converts the optical image formed by the lens 702 into image data (image signals). The signal processing unit 708 performs various corrections, data compression, etc. on the imaging data output from the imaging device 70. The timing generation unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals may be input from outside the device. The device 7 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device 7 includes at least a photoelectric conversion device. The device 7 further includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (e.g., a robot arm) that operates in response to a signal from the photoelectric conversion device.

[0106] Each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and acquire information about the distance from the image capture device 70 to the subject.

[0107] [Tenth embodiment] 17(a) and 17(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. The device 8 includes an image capture device 80 (an example of a photoelectric conversion device) according to the above-described embodiment and a signal processing device (processing device) that processes signals from the image capture device 80. The device 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the image capture device 80, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the device 8. The device 8 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information includes information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0108] The device 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 8 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0109] In this embodiment, the device 8 captures images of the surroundings of the vehicle, for example, the front or rear. FIG. 17(b) shows the device when capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends an instruction to the device 8 or the imaging device 80 to perform an imaging operation. This configuration can further improve the accuracy of distance measurement.

[0110] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0111] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0112] In the above-described embodiment, the photoelectric conversion device includes the processing circuits 20 a, 20 b and the frame memories 21 a, 21 b. However, these may be arranged outside the photoelectric conversion device. In this case, the photoelectric conversion device outputs an optical signal and a plurality of reset signals to the outside, and digital correlated double sampling can be performed using these signals in a signal processing circuit outside the photoelectric conversion device.

[0113] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0114] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0115] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0116] 10 pixel array 11 Vertical scanning circuit 20a, 20b Processing circuit 100 pixels

Claims

1. a pixel array including a plurality of pixels arranged in a plurality of rows, each pixel outputting a signal corresponding to incident light through photoelectric conversion; a scanning circuit that performs a plurality of scans, including a first scan that causes the pixels to sequentially output signals row by row, and a second scan that causes the pixels to sequentially output signals row by row during a period different from the first scan, within one frame period during which signals used to generate one frame are output; a processing circuit for processing signals output from the pixels; and the processing circuit corrects the optical signal based on the incident light based on a first reset signal and a second reset signal based on a reset state of the pixel; the scanning circuit causes the pixel to output the first reset signal by the first scanning; the scanning circuit causes the pixel to output the optical signal and the second reset signal by the second scanning; The first reset signal, the second reset signal, and the optical signal are output from the pixel within the one frame period. A photoelectric conversion device characterized by:

2. further comprising a frame memory; The processing circuit reads out the first reset signal from the frame memory, corrects the optical signal, and stores the corrected optical signal in the frame memory.

2. The photoelectric conversion device according to claim 1.

3. The processing circuit changes the content of the correction of the optical signal depending on the result of the determination based on the first reset signal.

3. The photoelectric conversion device according to claim 1 or 2.

4. The processing circuit makes the determination by comparing a signal based on the difference between the first reset signal and the second reset signal with a threshold value.

4. The photoelectric conversion device according to claim 3.

5. The processing circuit makes the determination by comparing a signal based on the first reset signal with a threshold value.

4. The photoelectric conversion device according to claim 3.

6. The processing circuit determines whether or not to use both the first reset signal and the second reset signal in correcting the optical signal depending on the result of the determination.

6. The photoelectric conversion device according to claim 3, wherein the first and second electrodes are electrically connected to each other.

7. The processing circuit performs the correction by subtracting half the first reset signal and half the second reset signal from the optical signal.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. The processing circuit performs the correction by subtracting an average of the first reset signal and the second reset signal from the optical signal.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. The scanning circuit outputs a plurality of the first reset signals by performing a scan different from the first scan and the second scan.

7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

10. When the total number of the first reset signals and the second reset signals is n, The processing circuit performs the correction by subtracting 1 / n times the first reset signal and 1 / n times the second reset signal from the optical signal.

10. The photoelectric conversion device according to claim 9.

11. The processing circuit performs the correction by subtracting an average of the first reset signals and the second reset signals from the optical signal.

10. The photoelectric conversion device according to claim 9.

12. a pixel array including a plurality of pixels arranged in a plurality of rows, each pixel outputting a signal corresponding to incident light through photoelectric conversion; a scanning circuit that performs a plurality of scans, including a first scan that causes the pixels to sequentially output signals row by row, and a second scan that causes the pixels to sequentially output signals row by row during a period different from the first scan, within one frame period during which signals used to generate one frame are output; and The scanning circuit outputting a first reset signal based on a reset state of the pixel from the pixel by the first scanning; outputting an optical signal based on the incident light from the pixel by the second scanning; outputting a second reset signal based on a reset state of the pixel from the pixel by the second scanning; In the first scanning, the optical signal is not output from the pixel, The first reset signal, the second reset signal, and the optical signal are output from the pixel within the one frame period. A photoelectric conversion device characterized by:

13. a pixel array including a plurality of pixels each including a photoelectric conversion unit, arranged in a plurality of rows, each outputting a signal corresponding to incident light through photoelectric conversion; a scanning circuit that performs a plurality of scans, including a first scan that causes the pixels to sequentially output signals row by row, and a second scan that outputs signals subsequent to the first scan and causes the pixels to sequentially output signals row by row; a processing circuit for processing signals output from the pixels; and the processing circuit corrects the optical signal based on the incident light based on a first reset signal and a second reset signal based on a reset state of the pixel; the scanning circuit causes the pixel to output the first reset signal by the first scanning; the scanning circuit causes the pixel to output the optical signal and the second reset signal by the second scanning; Between the first scanning and the second scanning, shutter scanning is performed to reset and release the photoelectric conversion unit. A photoelectric conversion device characterized by:

14. The photoelectric conversion device according to any one of claims 1 to 13, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. The device characterized by:

15. The processing device processes the image signals generated by the plurality of photoelectric conversion units, and acquires distance information from the photoelectric conversion units to a subject.

15. The device of claim 14.

Images