Image forming device

Abstract

To use the same exposure head for a high-resolution image and a low resolution image without reducing the image quality.SOLUTION: In an exposure head for forming an image with a first resolution or an image with a second resolution lower than the first resolution corresponding to an array interval of a plurality of lower electrodes in the intersection direction, a circuit unit 602 includes an image data storage part 804 which is arranged on a silicon substrate together with the plurality of lower electrodes and converts the input image data to the image data according to the resolution.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention , painting It relates to an image forming apparatus. [Background technology]

[0002] Printers, which are electrophotographic image forming devices, commonly use an exposure head to expose a photosensitive drum to light to form a latent image. The exposure head is typically made of LEDs (light-emitting diodes) or organic electroluminescence (OLED). The exposure head consists of a row of light-emitting elements aligned along the length of the photosensitive drum and a rod lens array that focuses light from the row of light-emitting elements onto the photosensitive drum. LEDs and organic EL elements are known to have a surface-emitting configuration in which the light emitted from the light-emitting surface is directed in the same direction as the rod lens array. The length of the row of light-emitting elements is determined by the width of the image area on the photosensitive drum, and the spacing between the light-emitting elements is determined by the printer's resolution. For example, in a 1200 dpi printer, the pixel spacing is 21.16 μm, and therefore the spacing between the light-emitting elements also corresponds to 21.16 μm. Printers using such exposure heads use fewer parts than laser scanning printers, which scan a photosensitive drum with a laser beam deflected by a rotating polygon mirror, making it easier to make the device smaller and less expensive.

[0003] For example, in Patent Document 1, light-emitting elements aligned in the main scanning direction are arranged in a staggered pattern for each pixel. When the image resolution is low, only the even-numbered or odd-numbered light-emitting elements in the main scanning direction are turned on, and when the image resolution is high, all the light-emitting elements, both even and odd, are turned on. This allows light emission according to the image resolution. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-246703 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the number of light-emitting elements is changed according to the image resolution, as in the conventional example, the number of light-emitting elements must be reduced when the resolution is low, and the spacing between the emitting light-emitting elements must be adjusted to match the resolution. In this case, if the size of the spot formed by each light-emitting element on the photoconductor by emitting light is smaller than the pixel spacing of the image resolution, the spots formed by adjacent light-emitting elements will be far apart. This results in an image in which the dots are spaced apart in the main scanning direction, which can lead to issues such as degradation of image quality, such as the appearance of jagged edges on the image contours.

[0006] The present invention has been made under these circumstances, and has as its object to use the same exposure head for both high-resolution images and low-resolution images without degrading the image quality. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, the present invention has the following configuration.

[0008] (1) times A rotating photoreceptor, Each one The light that exposes the photosensitive member is emitted. A plurality of photosensitive members are arranged along the rotation axis of the photosensitive member. Illumination Department a light emitting chip having an exposure head having a substrate on which the light-emitting chips are provided; and a generation unit that generates image data for controlling light emission of the plurality of light-emitting units and outputs the image data to the exposure head; Equipped with the plurality of light-emitting units include a first light-emitting unit and a second light-emitting unit adjacent to the first light-emitting unit in the direction of the rotation axis, and the light-emitting chip further includes a first driving unit that drives the first light-emitting unit based on the image data, a second driving unit that drives the second light-emitting unit based on the image data, and a selector that transfers the same image data output by the generation unit to the first driving unit and the second driving unit. An image forming apparatus characterized by: [Effects of the Invention]

[0010] According to the present invention, the same exposure head can be used for both high resolution and low resolution images without degrading the image quality. [Brief explanation of the drawings]

[0011] [Figure 1]Schematic cross-sectional view showing the configuration of an image forming apparatus according to first and second embodiments. [Figure 2] FIG. 1 shows the configuration of an exposure head according to first and second embodiments. [Figure 3] FIG. 1 is a diagram showing the configuration of a printed circuit board according to a first embodiment; [Figure 4] 1 shows the structure of a silicon substrate in Examples 1 and 2. [Figure 5] Cross-sectional view of the light-emitting region of Example 1 and a configuration diagram of the light-emitting device [Figure 6] Block diagram of the image controller and printed circuit board of the first and second embodiments [Figure 7] Timing chart for explaining data transfer in the first embodiment [Figure 8] Circuit diagram in the light emitting device of Example 1 [Figure 9] 1 is a diagram showing waveforms of signals and shifts in image data according to the first embodiment; [Figure 10] FIG. 1 is an explanatory diagram of a pulse signal generating unit according to a first embodiment, showing waveforms of each signal. [Figure 11] Block diagram of the analog section and circuit diagram of the drive section of Examples 1 and 2 [Figure 12] FIG. 1 is a diagram illustrating a latent image on a photosensitive drum in the first embodiment. [Figure 13] FIG. 10 is a diagram showing the configuration of a printed circuit board according to a second embodiment; and FIG. 11 is a diagram showing the configuration of a silicon substrate. [Figure 14] Circuit diagram in the light emitting device of Example 2 [Figure 15] 10A and 10B are diagrams showing waveforms of signals and shifts of image data according to the second embodiment; [Figure 16] FIG. 10 is a diagram illustrating a latent image on a photosensitive drum in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. [Example]

[0013] [Configuration of image forming device] FIG. 1 is a schematic cross-sectional view showing the configuration of an electrophotographic image forming apparatus in Example 1. The image forming apparatus shown in FIG. 1 is a multifunction printer (MFP) equipped with a scanner function and a printer function. The image forming apparatus is composed of a scanner unit 100, an image creating unit 103, a fixing unit 104, a paper feed / transport unit 105, and a printer control unit (not shown) that controls these. The scanner unit 100 illuminates a document placed on a document table to optically read the document image, and converts the read image into an electrical signal to create image data.

[0014] The imaging unit 103 includes four image forming stations arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotational direction (counterclockwise) of an endless conveyor belt 111. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102, which is a photosensitive member that rotates in the direction of the arrow (clockwise), an exposure head 106, a charger 107, and a developing unit 108. The suffixes a, b, c, and d of the photosensitive drum 102, exposure head 106, charger 107, and developing unit 108 indicate that the configuration corresponds to the image forming station (black (K), yellow (Y), magenta (M), and cyan (C), respectively. In the following, the suffixes of the reference numerals will be omitted except when referring to a specific photosensitive drum, etc.

[0015] In the image forming unit 103, the photosensitive drum 102 is rotated and charged by a charger 107. An exposure head 106, which serves as an exposure means, causes a light-emitting device to emit light in accordance with image data, and the light generated by the light-emitting device is focused onto the photosensitive drum 102 (on the photosensitive member) by a rod lens array, forming an electrostatic latent image. A developing device 108, which serves as a development means, develops the electrostatic latent image formed on the photosensitive drum 102 with toner. The developed toner image is then transferred to a recording sheet on a conveyor belt 111 that conveys the recording sheet. This series of electrophotographic processes is performed at each image forming station. During image formation, after a predetermined time has elapsed since the start of image formation at the cyan (C) image forming station, image forming operations are performed sequentially at the magenta (M), yellow (Y), and black (K) image forming stations. This results in a full-color image being formed.

[0016] The image forming apparatus shown in FIG. 1 includes a paper feed / transport unit 105 having internal paper feed units 109a and 109b, a large-capacity external paper feed unit 109c, and a manual paper feed unit 109d as units for feeding recording paper. During image formation, recording paper is fed from a predetermined paper feed unit and transported to registration rollers 110. Registration rollers 110 transport the recording paper to a transport belt 111 at the timing when the toner image formed in the image forming unit 103 is transferred to the recording paper. Toner images formed on the photosensitive drums 102 of each image forming station are sequentially transferred onto the recording paper transported by the transport belt 111. The recording paper with the unfixed toner image transferred is transported to a fixing unit 104. Fixing unit 104 has a built-in heat source such as a halogen heater, and fixes the toner image on the recording paper to the recording paper by applying heat and pressure with two rollers. The recording paper on which the toner image has been fixed by the fixing unit 104 is discharged by a discharge roller 112 to the outside of the image forming apparatus.

[0017] An optical sensor 113, which serves as a detection unit, is disposed downstream of the black (K) image forming station in the recording paper transport direction, facing the transport belt 111. The optical sensor 113 detects the position of a test image formed on the transport belt 111 to derive the amount of color shift of the toner images between the image forming stations. The amount of color shift derived by the optical sensor 113 is notified to an image controller unit 700 (see FIG. 6), which will be described later, and the image position of each color is corrected so that a full-color toner image without color shift is transferred onto the recording paper. In addition, a printer control unit (not shown) executes image formation operations while controlling the scanner unit 100, image creation unit 103, fixing unit 104, paper feed / transport unit 105, etc., in accordance with instructions from an MFP control unit (not shown), which controls the entire multifunction peripheral (MFP).

[0018] Here, as an example of an electrophotographic image forming apparatus, an image forming apparatus that directly transfers a toner image formed on the photosensitive drum 102 of each image forming station onto recording paper on a conveyor belt 111 has been described. The present invention is not limited to printers that directly transfer a toner image on the photosensitive drum 102 onto recording paper. For example, the present invention can also be applied to an image forming apparatus that includes a primary transfer unit that transfers the toner image on the photosensitive drum 102 onto an intermediate transfer belt, and a secondary transfer unit that transfers the toner image on the intermediate transfer belt onto recording paper.

[0019] [Exposure head configuration] Next, the exposure head 106 that exposes the photosensitive drum 102 will be described with reference to Fig. 2. Fig. 2(a) is a perspective view showing the positional relationship between the exposure head 106 and the photosensitive drum 102, and Fig. 2(b) is a diagram illustrating the internal configuration of the exposure head 106 and how a light beam from the exposure head 106 is focused onto the photosensitive drum 102 by a rod lens array 203. As shown in Fig. 2(a), the exposure head 106 is attached to the image forming apparatus by an attachment member (not shown) at a position above the photosensitive drum 102, which rotates in the direction of the arrow, facing the photosensitive drum 102 (Fig. 1).

[0020] As shown in FIG. 2(b), the exposure head 106 is composed of a printed circuit board 202, a light-emitting device group 400 mounted on the printed circuit board 202, a rod lens array 203, and a housing 204. The rod lens array 203 and printed circuit board 202 are attached to the housing 204. As shown in FIG. 2, the rod lens array 203 is disposed between the light-emitting device group 400 and the photosensitive drum 102. The rod lens array 203 is disposed along the longitudinal direction of the printed circuit board 202 and focuses the light beams emitted by the light-emitting device group 400 onto the photosensitive drum 102. In the factory, the exposure head 106 is assembled and adjusted individually, and focus and light intensity adjustments are performed. Here, assembly adjustments are performed so that the distance between the photosensitive drum 102 and the rod lens array 203, and the distance between the rod lens array 203 and the light-emitting device group 400 are predetermined intervals. As a result, light from the light-emitting device group 400 is imaged on the photosensitive drum 102. Therefore, when adjusting the focus at the factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting device group 400 is a predetermined value. Also, when adjusting the light intensity at the factory, the lower electrode of the light emitting device 401 (described later) is driven, and a voltage (described later) applied to the light emitting device 401 is adjusted so that the light condensed on the photosensitive drum 102 via the rod lens array 203 has a predetermined light intensity.

[0021] [Configuration of light-emitting devices] 3A and 3B are diagrams illustrating a printed circuit board 202 and a light emitting device group 400 mounted on the printed circuit board 202. Fig. 3A is a schematic diagram showing the configuration of the surface of the printed circuit board 202 on which the light emitting device group 400 is mounted, and Fig. 3B is a schematic diagram showing the configuration of the surface (second surface) opposite to the surface (first surface) on which the light emitting device group 400 of the printed circuit board 202 is mounted.

[0022] As shown in FIG. 3A, the light-emitting device group 400 mounted on the printed circuit board 202, which is the second substrate, has a configuration in which 20 light-emitting devices 401-1 to 401-20, which are independent chips, are arranged in two staggered rows along the longitudinal direction of the printed circuit board 202. That is, on the printed circuit board 202 (second substrate), odd-numbered light-emitting devices 401-1... (401-2n+1: n ≥ 0) and even-numbered light-emitting devices 401-2... (401-2n: n ≥ 1) are arranged at different positions in the rotation direction of the photosensitive drum 102. The light-emitting devices 401-1 to 401-20 are sometimes collectively referred to as light-emitting devices 401. Note that in FIG. 3A, the up-down direction indicates the rotation direction of the photosensitive drum 102, which is a first direction, and the horizontal direction indicates the longitudinal direction, which is a second direction perpendicular to the first direction. The longitudinal direction is also a cross direction that intersects with the rotation direction of the photosensitive drum 102. Each light-emitting device 401 has a total of 748 lower electrodes (described later). In this embodiment, the lower electrodes are arranged at intervals of 21.16 μm (≒ 2.54 cm / 1200 dots). As a result, the arrangement distance from end to end of the 748 lower electrodes in one light-emitting device 401 is approximately 15.8 mm (≒ 21.16 μm × 748). The light-emitting device group 400 is composed of 20 light-emitting devices 401. The number of lower electrodes that can be exposed in the light-emitting device group 400 is 14,960 (= 748 electrodes × 20 chips), and the light-emitting device group 400 can expose an image width in the longitudinal direction of approximately 316 mm (≒ approximately 15.8 mm × 20 chips).

[0023] 3(b), a connector 305 is mounted on the surface of the printed circuit board 202 opposite to the surface on which the light emitting device group 400 is mounted. The connector 305 is a connector for connecting a control signal and a power supply line that controls the light emitting device group 400 from an image controller unit 700 (see FIG. 6), which will be described later, and the light emitting devices 401-1 to 401-20 are driven via the connector 305.

[0024] 3(c) is a diagram showing the boundary between chips of light emitting devices 401 arranged in two rows in the longitudinal direction, with the horizontal direction being the longitudinal direction of the light emitting device group 400 in FIG. 3(a), and multiple light emitting devices 401 are arranged. FIG. 3(c) shows the boundary between chips of light emitting devices 401 (the portion where the ends of chips overlap in the longitudinal direction (overlapping portion)). Even at the boundary between light emitting device 401-2n and light emitting device 401-2n+1, the longitudinal pitch of the lower electrodes 410 at the ends between different light emitting devices 401 (the distance (L) between the center points of two lower electrodes) is approximately 21.16 μm, which is the pitch for a resolution of 1200 dpi.

[0025] The light emitting devices 401 are arranged in two rows, one above the other, in the short direction, as follows: That is, the distance between the lower electrodes (shown by arrow S in the drawing) of the upper and lower light emitting devices 401, which will be described later, is approximately 105 μm (equivalent to five pixels at 1200 dpi). The distance between the light emitting points in the longitudinal direction of the exposure head 106 (shown by arrow L in the drawing) is approximately 21.16 μm (equivalent to one pixel at 1200 dpi). Note that, in the present invention, the distances S and L between the light emitting devices 401 do not have to be limited to the values ​​described above.

[0026] [Configuration of light-emitting device] FIG. 4 is a schematic diagram showing the internal configuration of a light-emitting device 401. As shown in FIG. 4, the longitudinal direction of the light-emitting device 401 is defined as the X direction, and the lateral direction is defined as the Y direction. The Y direction is the rotation direction of the photosensitive drum 102, or in other words, the movement direction of the photosensitive surface (photosensitive body surface) of the rotating photosensitive drum 102. The X direction is a direction substantially perpendicular to the Y direction, i.e., the rotation direction of the photosensitive drum 102. It is also a direction substantially parallel to the rotation axis direction of the photosensitive drum 102. Note that substantially perpendicular allows a tilt of approximately ±1° relative to an angle of 90°, and substantially parallel allows a tilt of approximately ±1° relative to an angle of 0°. That is, the longitudinal direction of the light-emitting device 401 may be tilted by approximately ±1° relative to the rotation axis direction of the photosensitive drum 102. The lateral direction of the light-emitting device 401 may also be tilted by approximately ±1° relative to the rotation direction of the photosensitive drum 102. Light emitting device 401 has wire bonding pads (hereinafter referred to as WB pads) 601-1, 601-2, 601-3, and 601-4 formed on a silicon substrate 402, which is a first substrate. The silicon substrate 402 has a built-in circuit section 602 (indicated by a broken line), which is a driving section. The circuit section 602 may be an analog driving circuit, a digital control circuit, or a configuration including both. Power supply to circuit section 602 and input / output of signals from outside light emitting device 401 are performed via WB pads 601.

[0027] The light-emitting device 401 of this embodiment includes a linear light-emitting region 604 extending along the rotation axis direction of the photosensitive drum 102. The light-emitting region 604 includes an anode, a cathode, and a light-emitting layer 450 (see FIG. 5 ), which will be described later, and is a region that emits light when a potential difference occurs between the anode and the cathode.

[0028] A silicon (Si) substrate can be suitably used as the silicon substrate 402. This is because it has the following advantages. Specifically, silicon substrates have well-developed process technologies for forming integrated circuits, and are already used as substrates for various integrated circuits, so they have the advantage of being able to form high-speed, highly functional circuits at high density. In addition, large-diameter wafers of silicon substrates are commercially available, so they have the advantage of being inexpensive.

[0029] In Example 1, circuit unit 602 is provided with a drive unit that drives light emitting region 604 and a data transfer and light emitting signal generation unit that generates a signal (hereinafter referred to as a light emitting signal) for causing light emitting region 604 to emit light, and circuit unit 602 is formed on silicon substrate 402. This forms a circuit that is capable of high-speed operation.

[0030] [Light-emitting area configuration] The light-emitting device 401 will be described in more detail using FIG. 5. The X direction in FIG. 5 indicates the longitudinal direction of the exposure head 106. The Z direction is the direction in which each layer of the layer structure described below overlaps (stacking direction). FIG. 5(a) is an enlarged view of a main part of the schematic diagram of the AA cross section in FIG. 4. FIG. 5(a) is a schematic diagram of lower electrodes 410-1 to 410-748 described below as viewed from the Y direction. As shown in FIGS. 5(a) and 5(c), the light-emitting device 401 includes a silicon substrate 402, lower electrodes 410-1 to 410-748, a light-emitting layer 450, and an upper electrode 460. The silicon substrate 402 is a drive substrate on which drive circuits including drive units corresponding to the lower electrodes 410-1 to 410-748 described below are formed during the manufacturing process.

[0031] As shown in Figures 5(a) and 5(c), lower electrodes 410-1 to 410-748 (cathodes) are multiple electrodes formed in layers (first electrode layers) on silicon substrate 402. Each of lower electrodes 410-1 to 410-748 is formed on multiple drive units built into silicon substrate 402 using Si integrated circuit processing technology in addition to the manufacturing process for silicon substrate 402. Lower electrodes 410-1 to 410-748 are preferably made of a metal with high reflectivity at the emission wavelength of light-emitting layer 450, which will be described later. Therefore, lower electrodes 410-1 to 410-748 preferably contain silver (Ag), aluminum (Al), or an alloy thereof, a silver-magnesium alloy, or the like.

[0032] As shown in Fig. 5, the lower electrodes 410-1 to 410-748 are electrodes provided corresponding to each pixel in the X direction. That is, the lower electrodes 410-1 to 410-748 are electrodes provided to form one pixel each. The lower electrodes 410-1 to 410-748 form a first electrode row. The lower electrodes 410-1 to 410-748 forming the first electrode row are aligned along the rotation axis of the photosensitive drum 102. Here, the lower electrodes 410-1 to 410-748 may be aligned at an angle of about ±1° with respect to the rotation axis of the photosensitive drum 102. They do not need to be aligned strictly parallel to the rotation axis of the photosensitive drum 102.

[0033] In this embodiment, the width W of the lower electrodes 410-1 to 410-748 in the X direction corresponds to the width of one pixel. The interval d is the distance between the lower electrodes in the X direction (arrangement interval). Because the lower electrodes 410-1 to 410-748 are formed on the silicon substrate 402 with the interval d between them, the multiple driving units formed on the silicon substrate 402 can individually control the voltages of the lower electrodes 410-1 to 410-748. The interval d is filled with an organic material of the light-emitting layer 450, and the lower electrodes are partitioned by the organic material.

[0034] In the light-emitting device 401 of this embodiment, the width W of the lower electrodes 410-1 to 410-748 is set to a nominal dimension of 20.90 μm, and the spacing d is set to a nominal dimension of 0.26 μm. In other words, the light-emitting device 401 of this embodiment has one lower electrode 410 every 21.16 μm in the X direction. Since 21.16 μm is the size of one pixel at 1200 dpi, the width of each lower electrode 410 in the X direction corresponds to one pixel, which corresponds to the output resolution of the image forming apparatus of this embodiment. The process rule for the light-emitting device 401 of this embodiment is highly accurate, at approximately 0.2 μm, and it is possible to form the width d with a resolution of 0.26 μm.

[0035] 5B, the width of the lower electrodes 410-1 to 410-748 in the Y direction, which is the rotation direction of the photosensitive drum 102, is also W. That is, the lower electrodes 410-1 to 410-748 in this embodiment are 20.90 μm square, and the area of ​​the lower electrode 410 is 436.81 μm 2 This means that the area of ​​one pixel is 447.7456 μm 2 The organic light-emitting material emits less light than an LED. By forming the lower electrodes 410 on the silicon substrate 402 in a square shape with a small distance between adjacent lower electrodes as described above, it is possible to ensure a light-emitting area sufficient to obtain a light intensity sufficient to change the potential of the photosensitive drum 102. It is desirable to ensure a lower electrode area of ​​at least 90% of the area occupied by one pixel. Therefore, for an image forming apparatus with an output resolution of 1200 dpi, it is desirable to form the lower electrode 410 with a side width of at least approximately 20.07 μm, and for an image forming apparatus with an output resolution of 2400 dpi, it is desirable to form the lower electrode 410 with a side width of at least approximately 10.04 μm.

[0036] On the other hand, the upper limit of the area occupied by the lower electrode 410 should be set based on the transmittance of the rod lens array 203 and the upper electrode 460 (described later). In this embodiment, however, the upper limit is set to 110% of the area occupied by one pixel. If the area is designed to be larger than 110% of the area occupied by one pixel, the size of the pixel formed when the highly sensitive photosensitive drum 102 is exposed may significantly exceed the resolution. Therefore, the upper limit of the area occupied by the lower electrode 410 is set to 110%. Therefore, for an image forming apparatus with an output resolution of 1200 dpi, it is desirable to form the lower electrode 410 with a side width of approximately 22.19 μm or less. For an image forming apparatus with an output resolution of 2400 dpi, it is desirable to form the lower electrode 410 with a side width of approximately 11.10 μm or less. In other words, the range of the area occupied by the lower electrode 410 with respect to the area occupied by one pixel is preferably 90% or more and 110% or less.

[0037] The shape of the lower electrode 410 is not limited to a square, and may be a polygon with more sides than a square, a circle, an ellipse, or the like, as long as it emits light of an exposure area size corresponding to the output resolution of the image forming device and the image quality of the output image produced by that light is at a level that satisfies the design specifications of the image forming device.

[0038] Next, the light-emitting layer 450 will be described. The light-emitting layer 450 is formed by being laminated on the silicon substrate 402 on which the lower electrodes 410-1 to 410-748 are formed. That is, the light-emitting layer 450 is laminated on the lower electrodes 410-1 to 410-748 in the portions where the lower electrodes 410-1 to 410-748 are formed. The light-emitting layer 450 is laminated on the silicon substrate 402 in the portions where the lower electrodes 410-1 to 410-748 are not formed. In this example, the light-emitting layer 450 in the light-emitting device 401 is formed so as to span all of the lower electrodes 410-1 to 410-748, but the embodiment is not limited to this. For example, the light-emitting layer 450 may be formed so as to be separately laminated on each lower electrode, similar to the lower electrodes 410-1 to 410-748, or the lower electrodes 410-1 to 410-748 may be divided into a plurality of groups, and one light-emitting layer may be laminated on each lower electrode belonging to each divided group.

[0039] For example, an organic material can be used for the light-emitting layer 450. The light-emitting layer 450, which is an organic EL film, is a laminated structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer. The light-emitting layer 450 may be made of an inorganic material other than an organic material.

[0040] An upper electrode 460 (anode) is laminated (second electrode layer) on the light-emitting layer 450. The upper electrode 460 is an electrode that can transmit (is transmissive to) light of the wavelength emitted by the light-emitting layer 450. For this reason, a material containing indium tin oxide (ITO) is used as a transparent electrode for the upper electrode 460 in this embodiment. An indium tin oxide electrode has a transmittance of 80% or more for light in the visible light range, making it suitable as an electrode for organic EL.

[0041] The upper electrode 460 is formed on the opposite side of the lower electrodes 410-1 to 410-748, with at least the light-emitting layer 450 sandwiched between them. That is, in the Z direction, the light-emitting layer 450 is disposed between the upper electrode 460 and the lower electrodes 410-1 to 410-748, and when the lower electrodes 410-1 to 410-748 are projected onto the upper electrode 460 in the Z direction, the area where the lower electrodes 410-1 to 410-748 are formed falls within the area where the upper electrode 460 is formed. Note that the transparent electrode does not need to be stacked over the entire light-emitting layer 450. However, in order to efficiently emit light generated in the light-emitting layer 450 to the outside of the light-emitting device 401, it is preferable that the area occupied by the upper electrode 460 is 100% or more, and more preferably 120% or more, of the area occupied by one pixel. The upper limit of the area occupied by the upper electrode 460 can be arbitrarily designed depending on the areas of the silicon substrate 402 and the light-emitting layer 450. Wiring may be provided in the upper electrode 460 except for the portion that transmits light.

[0042] The upper electrode 460 in this embodiment is an anode provided in common to the lower electrodes 410-1 to 410-748, but it may be provided individually for each of the lower electrodes 410-1 to 410-748, or one upper electrode may be provided for each of the lower electrodes.

[0043] The drive circuit controls the potential of each of the lower electrodes 410-1 to 410-748 based on image data to generate a potential difference between the upper electrode 460 and any one of the lower electrodes 410-1 to 410-748.

[0044] The light-emitting device 401 in this embodiment is a so-called top-emission type emission device. When a voltage is applied to the upper electrode 460, which is an anode, and the lower electrode 410, which is a cathode, a potential difference is generated between them. Electrons flow from the cathode into the light-emitting layer 450, and holes flow from the anode into the light-emitting layer 450. The electrons and holes then recombine in the light-emitting layer 450, causing the light-emitting layer 450 to emit light. When the light-emitting layer 450 emits light, light directed toward the upper electrode 460 passes through the upper electrode 460 and is emitted from the light-emitting device 401 in the direction of arrow A shown in FIG. 5 . Light directed from the light-emitting layer 450 toward the lower electrode 410 is reflected by the lower electrode 410 toward the upper electrode 460, and the reflected light also passes through the upper electrode 460 and is emitted from the light-emitting device 401. Although there is a time difference in the timing of emission from the upper electrode 460 between the light emitted from the light-emitting layer 450 directly toward the upper electrode 460 and the light reflected by each of the lower electrodes 410 and emitted from the upper electrode 460, the layer thickness of the light-emitting device 401 is extremely small, so the emission can be considered to be almost simultaneous.

[0045] By using a transparent electrode such as indium tin oxide as the upper electrode 460, the aperture ratio, which indicates the light transmittance of the electrode, can be made substantially equal to the transmittance of the upper electrode 460. In other words, since there is substantially no portion other than the upper electrode 460 that attenuates or blocks light, the light emitted from the light-emitting layer 450 is attenuated as little as possible or becomes emitted light without being blocked.

[0046] Furthermore, as described above, by forming the lower electrodes 410-1 to 410-748 using high-precision Si integrated circuit processing technology, the lower electrodes 410-1 to 410-748 can be arranged at high density. As a result, most of the area of ​​the light-emitting region 604 (here, the total area of ​​the lower electrodes 410-1 to 410-748 and the area of ​​the region between adjacent lower electrodes) can be allocated to the lower electrodes 410-1 to 410-748. In other words, the exposure head has a high utilization efficiency of the light-emitting region per unit area.

[0047] When light-emitting layer 450 is made of a moisture-sensitive light-emitting material such as an organic EL layer or an inorganic EL layer, it is desirable to seal light-emitting region 604 to prevent moisture from entering. For example, a sealing film is formed by forming a thin film, such as a single film or a laminated film, of silicon oxide, silicon nitride, or aluminum oxide. A method that excels in covering structures such as steps is preferred as a method for forming the sealing film, and for example, atomic layer deposition (ALD) can be used. The materials, configurations, and formation methods of the sealing film are merely examples, and are not limited to the above examples, and any suitable method may be selected as appropriate.

[0048] [Control Block] 6 shows a block diagram of the image controller unit 700 and the printed circuit board 202. Hereinafter, the chip select signal is referred to as cs_x, the line synchronization signal as lsync_x, the clock signal as clk, and the image data signal as data. The chip select signal cs_x is output corresponding to each light-emitting device 401. Specifically, the chip select signal cs_x_1 is output to the light-emitting device 401-1, and the chip select signal cs_x_2 is output to the light-emitting device 401-2. The chip select signal cs_s_20 is output to the light-emitting device 401-20. In the first embodiment, monochromatic processing will be described for the sake of simplicity, but it is assumed that similar processing is performed in parallel for four colors.

[0049] (Image controller) Image controller unit 700 receives image data generated by scanner unit 100 and transmits control signals for controlling printed circuit board 202. The image data input to image controller unit 700 may be data generated by scanner unit 100 as described above, or may be data transferred from a personal computer via a network device (not shown). The control signals include a chip select signal cs_x indicating the effective range of the image data, a clock signal clk, an image data signal data, a line synchronization signal lsync_x indicating the division of each line of image data, and a communication signal for communication with CPU 703. Each signal is transmitted to light-emitting device 401 in printed circuit board 202 via a chip select signal line 705, a clock signal line 706, an image data signal line 707, a line synchronization signal line 708, and a communication signal line 709. Chip select signal line 705 specifically refers to chip select signal lines 705-1 to 705-20. Image controller unit 700 processes image data and print timing. The image data generation unit 701 generates image data for print output by performing dithering processing on image data received from the scanner unit 100 or from outside the image forming apparatus at a resolution instructed by the CPU 703. In the first embodiment, for example, there is a low-resolution mode, which is a second mode in which dithering processing is performed at a second resolution of 600 dpi, and a high-resolution mode, which is a first mode in which dithering processing is performed at a resolution of 1200 dpi.

[0050] The synchronization signal generation unit 704 generates a line synchronization signal lsync_x, which is a second signal, and outputs it via a line synchronization signal line 708. The CPU 703 specifies the time interval of the signal period to the synchronization signal generation unit 704 as one line period for a predetermined rotation speed and resolution of the photosensitive drum 102. Here, one line period is a period in which the surface of the photosensitive drum 102 moves in the rotation direction by an amount corresponding to a pixel size corresponding to the resolution. In the rotation direction of the surface of the photosensitive drum 102, the CPU 703 specifies the time interval of the signal period to the synchronization signal generation unit 704 as one line period, which is a period in which the surface of the photosensitive drum 102 moves by an amount corresponding to a pixel size (approximately 42.32 μm) equivalent to 600 dpi in the low-resolution mode. For example, when printing is performed at a speed of 200 mm / s in the conveyance direction of the recording paper, the CPU 703 specifies the time interval to the synchronization signal generation unit 704 as one line period of 211.6 μs (two decimal places and below are omitted). In addition, in the high resolution mode, the CPU 703 specifies the time interval of the signal period to the synchronization signal generator 704, with one line period being the period of movement of a pixel size (approximately 21.16 μm) equivalent to 1200 dpi. For example, when printing is performed at a speed of 200 mm / s in the conveyance direction of the recording paper, the CPU 703 specifies the time interval as one line period of 105.8 μs (two decimal places and below omitted). The speed in the conveyance direction is calculated by the CPU 703 using a set value (fixed value) of the printing speed (image formation speed) set in a control unit (not shown) that controls the speed of the photosensitive drum 102. The printing speed is set, for example, depending on the type of recording paper.

[0051] The chip data conversion unit 702 divides one line of image data for each light emitting device 401 in synchronization with a line synchronization signal lsync_x generated by a synchronization signal generation unit 704. The chip data conversion unit 702 transmits the image data divided for each light emitting device 401 to the printed circuit board 202 together with a clock signal clk and a chip select signal cs_x. The clock signal clk is a signal that serves as a reference for control.

[0052] (printed circuit board) Next, the configuration of the printed circuit board 202 will be described. The head information storage unit 710 is a storage device that stores head information such as the light emission amount and mounting position information of each light-emitting device 401, and is connected to the CPU 703 via a communication signal line 709 that transmits communication signals. A clock signal line 706, an image data signal line 707, a line synchronization signal line 708, and a communication signal line 709 are connected to all of the light-emitting devices 401. The chip select signal line 705 has chip select signal lines 705-1 to 705-20 for each light-emitting device 401, and is connected to each of the light-emitting devices 401-1 to 401-20. Each light-emitting device 401 drives the lower electrode 410 based on the setting values ​​set by the chip select signal cs_x, clock signal clk, line synchronization signal lsync_x, image data signal data, and communication signal.

[0053] (Data transfer from the image controller to the printed circuit board) Here, data transfer from the image controller unit 700 to the light emitting device 401 mounted on the printed circuit board 202 will be described. FIG. 7 is a diagram showing the signals connected between the image controller unit 700 and the light emitting device 401 on the printed circuit board 202. In FIG. 7, (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the waveforms of the chip select signals cs_x_1 to cs_x_20, and (iv) shows the image data signals data (data0 to data19). The hatched portions of the image data signals data indicate invalid data as image data. Note that the chip select signals cs_x_1 and the like indicate chip select signals input to the light emitting device 401-1 and the like via the chip select signal line 705-1 and the like. Furthermore, image data for driving the lower electrode 410 in the nth light emitting device 401-n is represented as data(n-1). For example, the image data for driving the lower substrate in the first light emitting device 401-1 is data0. Therefore, data0 to data19 make up one line of image data. Furthermore, the image data signal data transfers one pixel's worth of image data in one cycle of the clock signal clk. The amount of image data for one line differs depending on the resolution mode. For example, in high resolution mode, one line is image data for 14,960 pixels, while in low resolution mode, one line is image data for half that, or 7,480 pixels.

[0054] 7 indicates the time required to transmit the image data signal "data" to the light-emitting devices 401-1, etc. In other words, in high-resolution mode, the time "ΔT0" is 748 (=14960 / 20) times one cycle of the clock signal "clk." On the other hand, in low-resolution mode, the time is 374 (=7480 / 20) times one cycle of the clock signal "clk." The chip select signals "cs_x_1" to "cs_x_20" input to the light-emitting devices 401-1 to 401-20 are sequentially enabled (asserted). This allows the image data "data0" to "data19" to correspond (synchronize) with the light-emitting devices 401-1 to 401-19. As mentioned above, the time "ΔT2," which is one cycle of the line synchronization signal "lsync_x," is 105.8 μs in high-resolution mode and 211.6 μs in low-resolution mode. One cycle of the clock signal clk is set to a cycle that becomes equal to the time ΔT2 when multiplied by an integer, but it is sufficient that the cycle is such that all image data data0 to data19 can be transferred to the light emitting device 401 within one cycle of the line synchronization signal lsync_x.

[0055] [Circuit configuration inside the light-emitting device] 8(a) shows a circuit block diagram within the light-emitting device 401. The circuit section 602 within the light-emitting device 401 has a digital section 800 and an analog section 806. The digital section 800 has the function of generating pulse signals for driving the lower electrodes 410-n in synchronization with a clock signal clk based on preset setting values ​​and various signals set by communication signals, and transmitting the pulse signals to the analog section 806 via a pulse signal line 1006. Here, the various signals refer to a chip select signal cs_x, an image data signal data, and a line synchronization signal lsync_x.

[0056] [Digital Department] The communication IF unit 801 controls the writing and reading of setting values ​​to and from the register unit 802 based on communication signals from the CPU 703. The register unit 802 stores setting values ​​(preset setting values) required for operation. These setting values ​​include exposure timing information used by the image data storage unit 804, width and phase information (delay information) of the pulse signal generated by the pulse signal generation unit 805, and setting information for the drive voltage set by the analog unit 806. Note that since the drive voltage can be derived from the resistance value between the lower electrode and the upper electrode and the range of this resistance value is known in advance, information on the drive current may be stored instead of setting information for the drive voltage. The image data storage unit 804 holds image data while the input chip select signal cs_x is valid and outputs the image data to the pulse signal generation unit 805 in synchronization with the line synchronization signal lsync_x. Details will be described later.

[0057] The pulse signal generating unit 805 generates a pulse signal based on the width information and phase information (delay information) of the pulse signal set in the register unit 802 in accordance with the image data input from the image data storage unit 804, and outputs the pulse signal to the analog unit 806. Details will be described later. The analog unit 806 generates a signal required to drive the lower electrode 410 based on the pulse signal generated in the digital unit 800. Details will be described later.

[0058] (Image data storage section) Next, the operation of the image data storage unit 804 will be described. The image data storage unit 804 of the first embodiment is built into the light-emitting device 401. As will be described later, the image data storage unit 804 functions as a converter that converts image data into image data appropriate for the resolution. FIG. 8B is a circuit diagram of the image data storage unit 804. While the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals in the following example, they may also be positive logic signals. Furthermore, the resolution mode signal connected to the register unit 802 via the resolution mode signal line 711 corresponds to a low-resolution mode (600 dpi) when it is "0" and a high-resolution mode (1200 dpi) when it is "1." The resolution mode signal is a register signal that is set in accordance with the operation of the image data generation unit 701. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk. The clock gate circuit 810 outputs the clock signal s_clk to the flip-flop circuit 811 only when the chip select signal cs_x is valid.

[0059] The flip-flop circuits 811 receive the image data signal DATA input to the image data storage unit 804 as their primary input. The same number of flip-flop circuits 811 (748 in the first embodiment) as the number of lower electrodes 410 arranged in the longitudinal direction of the light-emitting device 401 are connected in series. The entire flip-flop circuit 811 functions as a shift circuit. Specifically, the flip-flop circuit 811 is made up of flip-flop circuits 811-1, 811-2, ..., 811-748. Selectors 813-1, 813-2, ... are connected to the upstream stages of the data input terminals D of even-numbered flip-flop circuits 811, such as flip-flop circuits 811-2 and 811-4. The selectors 813-1, etc. are collectively referred to as selectors 813. The resolution mode signal line 711 is connected to the selector 813 as a select signal, and a resolution mode signal is input to the selector 813.

[0060] When the resolution mode signal is "1", the selector 813 outputs the output of the flip-flop circuit 811 connected in the preceding stage to the flip-flop circuit 811 connected in the succeeding stage of the selector 813. When the resolution mode signal is "0", the selector 813 outputs the input of the flip-flop circuit 811 connected in the preceding stage to the flip-flop circuit 811 connected in the succeeding stage of the selector 813. The selector 813-2 will be described in detail. When the resolution mode signal is "1", the selector 813-2 outputs the output (dly_data_002) of the flip-flop circuit 811-3 connected in the preceding stage of the selector 813-2 to the flip-flop circuit 811-4 connected in the succeeding stage of the selector 813-2. When the resolution mode signal is "0", the selector 813 outputs the input (dly_data_001) of the flip-flop circuit 811-3 in the stage preceding the selector 813-2 to the flip-flop circuit 811-4 in the stage following the selector 813-2.

[0061] The flip-flop circuit 811 operates in response to the clock signal s_clk sent from the clock gate circuit 810. The output of the flip-flop circuit 811 is output as image data dly_data_000 to dly_data_747 to the next adjacently connected flip-flop circuit 811 or to the selector 813 and the flip-flop circuit 812. The flip-flop circuits 811 and the flip-flop circuits 812 are provided in the longitudinal direction of the bottom electrodes 410 in the same number as the bottom electrodes 410 (748 in the first embodiment).

[0062] The flip-flop circuit 812 receives the output of the flip-flop circuit 811 as input and operates in accordance with the line synchronization signal lsync_x. The flip-flop circuit 812 is made up of flip-flop circuits 812-1, 812-2, ..., 812-748. The output of the flip-flop circuit 812 is output to pulse signal generating units 805-1 to 805-748 as image data buf_data_0_000 to buf_data_0_747. Note that one cycle of the line synchronization signal lsync_x is 105.8 μs (figures to two decimal places omitted) in high resolution mode.

[0063] (in high resolution mode) FIG. 9(a) is a timing chart showing the operation of the image data storage unit 804 in the longitudinal direction of the light-emitting device 401 in high-resolution mode, i.e., when the resolution mode signal is "1." In FIG. 9(a), (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the waveform of the chip select signal cs_x, and (iv) shows the image data signal data indicated by 000 to 747. Here, "747" indicates image data corresponding to, for example, the lower electrode 410-1, and "000" indicates image data corresponding to the lower electrode 410-748. The shaded portions of the image data signal data indicate invalid data. (v) indicates image data such as dly_data_000 that is the output of the flip-flop circuit 811, and (vi) indicates image data such as buf_data_0_000 that is the output of the flip-flop circuit 812.

[0064] During the period from time T0 to time T1 when the chip select signal cs_x is 0 (cs_x=0 (low level)), the image data is shifted through the serially connected flip-flop circuits 811 as follows. Time T0 is the time when cs_x=0 is captured by the rising edge of the clock signal clk. That is, the image data is shifted in the following order: data → dly_data_000 → dly_data_001 → ... → dly_data_747. In the high-resolution mode, the flip-flop circuit 811 operates as a shift register, and the input image data is sequentially transferred to the flip-flop circuits 811-1, 811-2, ... During the period when the chip select signal cs_x is low level (cs_x=0), the clock signals clk are input in the same number as the number of bottom electrodes 410 in the longitudinal direction of the light-emitting device 401, i.e., 748. In this manner, one line's worth of image data is held in dly_data_000 to dly_data_747.

[0065] After time T1, the chip select signal cs_x is 1 (cs_x=1 (high level)), so no shift operation is performed and the image data at time T1 is held. For example, the image data dly_data_000 held in the first flip-flop circuit 811 after time T1 is 747. When the line synchronization signal lsync_x becomes 0 (lsync_x=0 (low level)) at time T2, one line's worth of image data is simultaneously output to the pulse signal generation unit 805 as buf_data_0_000 to buf_data_0_747. Time T2 is the time when lsync_x=0 is captured by the rising edge of the clock signal clk. In other words, the image data dly_data_000 etc. held in the flip-flop circuit 811 is output to the pulse signal generation unit 805 via the flip-flop circuit 812 as image data buf_data_0_000 etc., and drives each lower electrode 410. Similar operations are repeated from time T2 onwards, and the image data output to the pulse signal generating units 805-1, 805-2, ... is updated sequentially for each line synchronization signal lsync_x. Note that the cycle of the line synchronization signal lsync_x is 105.8 μs in the high resolution mode, and the image data is updated at this cycle.

[0066] (in low resolution mode) Fig. 9(b) is a timing chart showing the operation of the light emitting device 401 in the longitudinal direction of the image data storage unit 804 in low resolution mode, i.e., when the resolution mode signal is "0." (i) to (vi) in Fig. 9(b) are graphs similar to (i) to (vi) in Fig. 9(a).

[0067] Between time T0 and time T1, when the chip select signal cs_x becomes 0 (cs_x=0 (low level)) at the rising edge of the clock signal clk, the image data signal 'data' is input to the flip-flop circuit 811 sequentially starting from 000. However, in low-resolution mode, selectors 813-1, ... are inserted before the even-numbered flip-flop circuits 811-2, 811-4, .... This selector 813 transfers the same image data as a set of image data dly_data_2n, dly_data_2n+1 (n≧0). Specifically, the same image data is input to dly_data_000 and dly_data_001, and the same data is input to dly_data_002 and dly_data_003, .... In this way, the image data signal 'data' is input to two adjacent flip-flop circuits 811, and the data amount is increased to twice the amount of data for each pixel before being transferred.

[0068] At time T2, when the line synchronization signal is captured as 0 (lsync_x=0 (low level)) on the rising edge of the clock signal clk, image data is transferred as follows: That is, the image data is transferred as follows: dly_data_000 → buf_data_0_000, dly_data_001 → buf_data_0_001, and so on. As a result, the image data buf_data_0_000, buf_data_0_001, etc. are output to the pulse signal generation units 805-1, 805-2, etc., to drive each lower electrode 410. Similar operations are repeated from time T2 onwards, and the image data output to the pulse signal generation units 805-1, 805-2, etc. is updated sequentially for each line synchronization signal lsync_x. Note that the cycle of the line synchronization signal lsync_x is 211.6 μs in the low resolution mode, and the image data is updated at this cycle.

[0069] By transferring image data in this manner, even if the number of lower electrodes 410 in the main scanning direction is equal to the number of pixels corresponding to the high-resolution mode, the low-resolution mode can also be supported. That is, in the low-resolution mode, image data is transferred so that two consecutive lower electrodes of the lower electrodes 410 are driven based on the same image data. This allows conversion of the resolution in the main scanning direction within the printed circuit board 202. In addition, in the sub-scanning direction, in the high-resolution mode, lines are formed at intervals of 1200 dpi, with the period of the line synchronization signal lsync_x. On the other hand, in the low-resolution mode, lines are formed at intervals of 600 dpi in the sub-scanning direction.

[0070] In the first embodiment, by transferring image data in this manner, the lower electrodes 410 have the same number of elements in the main scanning direction as in the high resolution mode, but in the low resolution mode, data is transferred so that two consecutive lower electrodes of the lower electrodes 410 are driven with the same data, thereby converting the resolution in the main scanning direction.

[0071] (Pulse signal generation unit) The pulse signal generating unit 805 will now be described. When the number of lower electrodes 410 is n, there are also n pulse signal generating units 805, the same number as the number of lower electrodes 410. In the first embodiment, pulse signal generating units 805-1 to 805-748 are provided for lower electrodes 410-1 to 410-748. The pulse signal generating units 805 provided for each lower electrode 410 have the same structure. Therefore, pulse signal generating unit 805-1 will be described here as an example.

[0072] 10(a) shows a block diagram of pulse signal generation unit 805-1. Pulse signal generation unit 805-1 has a pulse width selection unit 901, an addition unit 902, an output determination unit 903, and a counter unit 904. Pulse width selection unit 901 converts image data input from image data storage unit 804 into pulse width b in accordance with a pulse width table of pulse signals set by register unit 802. Table 1 shows an example of the pulse width table, which is a conversion table used when converting image data into pulse width b.

[0073] [Table 1] Table 1 shows image data in the first column and pulse width b of the pulse signal corresponding to the image data in the second column. For example, the image data is 4 bits ([3:0]) (0 to 15).

[0074] For example, when the input image data is 2, the pulse width selection unit 901 sets the pulse width b to 8 based on the pulse width Table of Table 1 set by the register unit 802 and outputs it to the output determination unit 903. However, the pulse width Table shown in Table 1 is only an example, and the bit width of the image data and pulse width may be different from the example in Table 1, and the value of pulse width b may also be set arbitrarily. The pulse width Table stored in the register unit 802 may be set individually for each lower electrode 410, or may be shared.

[0075] Due to process variations and the like, the light-emitting layers 450 corresponding to the lower electrodes 410 may have different light intensities even when the pulse signal has the same pulse width. The variations in the light intensities of the light-emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748 cause unevenness in the electrostatic latent image formed on the photosensitive drum 102, resulting in unevenness in the printed image. To eliminate this unevenness in the electrostatic latent image, a pulse width table is set for each of the lower electrodes 410-1 to 410-748 according to the measured light intensities, thereby changing the pulse width of the output pulse signal so that the electrostatic latent image is correct for the input image data. By setting the pulse width table for each of the lower electrodes 410-1 to 410-748 through the above control, it is possible to correct unevenness in the printed image caused by the variations in the light intensities of the light-emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748. The light intensity of the light emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748 is measured in a factory or by installing a light intensity measuring device (not shown) at a position opposite the exposure head 106.

[0076] The adder 902 adds a line delay signal common to all pulse signal generators 805 and a pixel delay signal that differs for each pulse signal generator 805. In this way, the adder 902 determines a delay time a of the pulse signal. The counter 904 counts the clock signal clk and resets the count for each period c of the line synchronization signal lxync_x (hereinafter referred to as the line synchronization signal period). The line synchronization signal period is shown as timings C-1 and C-2 in FIG. 10(b), which will be described later. The count is input to the output determination unit 903. In the first embodiment, the clock signal clk is counted up, but it may also be counted down. The counter 904 may be provided for each pulse signal generator 805 corresponding to each lower electrode 410, or may be shared.

[0077] The operation of the output determination unit 903 will be described with reference to Fig. 10(b). In Fig. 10(b), (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the count value that is the output of the counter unit 904, and (iv) shows the waveform of the pulse signal generated by the pulse signal generation unit 805.

[0078] The output determination unit 903 generates a pulse signal according to the count input from the counter unit 904, the delay time a output from the adder unit 902, and the pulse width b output from the pulse width selection unit 901. The output determination unit 903 sets the output pulse signal to a high level at the timing (timing A) when the count reaches a after the timing (timings C-1 and C-2) when the line synchronization signal lsync_x is at a low level at the rising edge of the clock signal clk. The output determination unit 903 then sets the output pulse signal to a low level at the timing (timing B) when the count reaches a+b after the time of pulse width b has elapsed at the rising edge of the clock signal clk. In this way, the output determination unit 903 generates a pulse signal. The pulse width table, line delay signal, and pixel delay signal are transmitted from the register unit 802, and their respective values ​​can be changed in units of clock cycles by rewriting the information in the register unit 802.

[0079] [Analog section] 11(a) shows a block diagram of the analog unit 806. In the first embodiment, for the sake of simplicity, the explanation will be given by illustrating only the driver units 1001-1 and 1001-2 that drive the two lower electrodes 410-1 and 410-2 in the lower electrodes 410-1 to 410-748. However, it is assumed that similar driver units 1001-3 to 1001-748 are formed corresponding to the lower electrodes 410-3 to 410-748. Furthermore, as described above, it is the light-emitting layer 450 in the regions corresponding to the lower electrodes 410-1 and 410-2 that actually emits light when the lower electrodes 410-1 and 410-2 are driven.

[0080] Pulse signal generating units 805-1 and 805-2 generate pulse signals that control the light emission (ON) timing of lower electrodes 410-1 and 410-2. Pulse signal generating units 805-1 and 805-2 input pulse signals to driving units 1001-1 and 1001-2 via pulse signal lines 1006-1 and 1006-2.

[0081] A digital-to-analog converter (hereinafter referred to as DAC) 1002 supplies an analog voltage that determines a drive current to the drivers 1001-1 and 1001-2 via a signal line 1003 based on data set in the register unit 802. A driver selection unit 1007 supplies a driver select signal that selects the drivers 1001-1 and 1001-2 to the drivers 1001-1 and 1001-2 via signal lines 1004 and 1005 based on the data set in the register unit 802. The driver select signal is generated so that only the signal connected to the selected driver 1001 is at a high level. For example, when the driver 1001-1 is selected, a high-level driver select signal is supplied only to the signal line 1004, and a low-level driver select signal is supplied to signal lines 1005 and the like connected to other drivers such as the driver 1001-2. In the first embodiment, the driver select signal is positive logic, but it may also be negative logic.

[0082] An analog voltage input via signal line 1003 is set for driver units 1001-1 and 1001-2 at the timing selected by driver unit selection unit 1007 (the timing when the driver unit select signal goes high). CPU 703 sequentially selects driver units 1001-1 and 1001-2 via register unit 802 and sets a voltage corresponding to the selected driver units 1001-1 and 1001-2. In this way, CPU 703 sets analog voltages for all driver units 1001 using a single DAC 1002. By the above-described operation, analog voltages and pulse signals that determine the drive current are input to driver units 1001-1 and 1001-2, and the drive current and light-emitting time of each of lower electrodes 410-1 and 410-2 are independently controlled by a drive circuit, which will be described below.

[0083] (Drive unit) 11(b) shows the circuit of driver 1001-1 that drives lower electrode 410-1. Drivers 1001-2 to 1001-748 for the other lower electrodes 410-2 to 410-748 are also driven by a similar circuit. MOS field effect transistor (hereinafter referred to as MOSFET) 1102 supplies a drive current to lower electrode 410-1 in accordance with the gate voltage value, and controls the current so that the drive current is turned off (light is turned off) when the gate voltage is at a low level.

[0084] A pulse signal line 1006-1 is connected to the gate terminal of the MOSFET 1104, and when the pulse signal is at a high level, the voltage charged in the capacitor 1106 is transferred to the MOSFET 1102. A driver unit select signal (transmitted via a signal line 1004) sent from the driver unit selection unit 1007 is connected to the gate terminal of the MOSFET 1107. When the received driver unit select signal is at a high level, the MOSFET 1107 turns on and charges the analog voltage (transmitted via a signal line 1003) output from the DAC 1002 to the capacitor 1106. In the first embodiment, the DAC 1002 sets an analog voltage in the capacitor 1106 before image formation, and keeps the MOSFET 1107 in an off state during the image formation period, thereby maintaining the voltage level.

[0085] Through this operation, MOSFET 1102 supplies a drive current to lower electrode 410 in accordance with the set analog voltage and pulse signal. If the input capacitance of lower electrode 410-1 is large and the response speed when turned off is slow, it is possible to speed up the turn-off speed by using MOSFET 1103. A signal obtained by logically inverting a pulse signal by inverter 1105 is input to the gate terminal of MOSFET 1103. When the pulse signal is at low level, the gate terminal of MOSFET 1103 becomes high level, and the charge stored in the input capacitance of lower electrode 410-1 is forcibly discharged.

[0086] [Latent image on the photosensitive drum] FIG. 12 is a schematic diagram showing a latent image formed on the photosensitive drum 102 using the operation in Example 1, and also shows the rotation direction of the photosensitive drum 102. The portions indicated by dashed lines in the figure indicate latent images corresponding to pixels formed by the lower electrode 410, the light-emitting layer 450, and the upper electrode 460 (hereinafter referred to as the lower electrode 410, etc.). Furthermore, one square in the direction perpendicular to the rotation direction indicates a latent image corresponding to a pixel formed by the lower electrodes 410-1, 410-2, ..., etc. FIG. 12(a) is a schematic diagram of a latent image formed on the photosensitive drum 102 in high-resolution mode. In high-resolution mode, a 1200 dpi latent image is formed in both the direction perpendicular to and parallel to the rotation direction of the photosensitive drum 102.

[0087] FIG. 12(b) is a schematic diagram of a latent image formed on the photosensitive drum 102 in low-resolution mode. In low-resolution mode, a latent image of 1200 dpi is formed in both the direction perpendicular to the rotation direction of the photosensitive drum 102 and the direction parallel to it. However, in the direction perpendicular to the rotation direction, an image based on the same image data is formed using every two pixels, in other words, two adjacent lower electrodes 410 (shown as "same data"). Therefore, the latent image has a resolution equivalent to 600 dpi. Furthermore, since the line synchronization signal lsync_x is output at a cycle equivalent to 600 dpi, 600 dpi pixels are also formed in the direction parallel to the rotation direction of the photosensitive drum 102.

[0088] As described above, by providing a circuit for converting resolution inside the light-emitting device 401, it is possible to handle both high-resolution and low-resolution images using the same exposure head. Furthermore, since the resolution is converted to the same resolution as the lower electrodes, etc. (in other words, the light-emitting points) of the light-emitting device 401 regardless of the input resolution, differences in the distance between the light-emitting points due to resolution do not occur, and a stable image can be formed. Note that in Example 1, the same image controller unit 700 is configured to be able to output both low-resolution and high-resolution images. However, with an exposure head configured as described above, it is possible to connect the same exposure head to an image controller unit that can only output low-resolution images or an image controller unit that can only output high-resolution images.

[0089] As described above, according to the first embodiment, the same exposure head can be used for both high-resolution images and low-resolution images without degrading the image quality. [Example]

[0090] Light-emitting devices using organic EL generally tend to have a relatively low emission brightness compared to laser diodes and the like. In particular, when one cycle of the line synchronization signal lsync_x becomes shorter, as in the high-resolution mode of Example 1, the exposure time for one pixel (or one line) becomes shorter, which may make it difficult to form a latent image on the photosensitive drum 102. Therefore, in Example 2, an example in which the lower electrodes 410 are arranged in two rows will be described. Note that the overall configuration of the image forming apparatus, the configuration of the exposure head, and the configuration of the substrate are the same as in Example 1, and the differences from Example 1 will be described below.

[0091] [Arrangement of multiple bottom electrodes in the light-emitting region (multiple light emission)] As shown in FIG. 13, the light emitting device 401 of Example 2 includes lower electrodes 420-1 to 420-748 in addition to lower electrodes 410-1 to 410-748. The lower electrodes 420-1 to 420-748 are multiple electrodes formed in layers (first electrode layers) on the silicon substrate 402, similar to the lower electrodes 410-1 to 410-748. The lower electrodes 420-1 to 420-748 form a second electrode row. The lower electrodes 420-1 to 420-748 forming the second electrode row are aligned along the rotation axis of the photosensitive drum 102. Here, these lower electrodes 420-1 to 420-748 may be aligned at an angle of about ±1° with respect to the rotation axis of the photosensitive drum 102. They do not need to be aligned strictly parallel to the rotation axis of the photosensitive drum 102.

[0092] That is, light emitting device 401 includes two-dimensionally arranged lower electrodes. The size, shape, and arrangement in the X direction of lower electrodes 420-1 to 420-748 are similar to those of lower electrodes 410-1 to 410-748, and therefore description thereof will be omitted.

[0093] The lower electrodes 420-1 to 420-748 (second electrode row) are arranged at a distance d from the lower electrodes 410-1 to 410-748 (first electrode row) in the Y direction. In the Y direction, the lower electrode 420-1 is arranged adjacent to the lower electrode 410-1, and similarly, the lower electrodes 420-2 to 420-748 are arranged adjacent to the lower electrodes 410-2 to 410-748, respectively. Here, the Y direction is substantially parallel to the rotation direction of the photosensitive drum 102. That is, the direction in which the first electrode row and the second electrode row are aligned may be inclined by approximately ±1° with respect to the rotation direction of the photosensitive drum 102. Note that, as in the second embodiment, it is not necessarily required to design the distance between the lower electrodes in the X direction and the Y direction to be equal, but it is desirable to design the distance between the lower electrodes in both directions to be equal in order to efficiently arrange the lower electrodes within a predetermined area. Furthermore, in Example 2, for ease of explanation, a light emitting device having two electrode rows is exemplified, but as shown in Fig. 13(c), the number of electrode rows may be any number of rows equal to or greater than three. For example, similarly to the above, lower electrodes 430-1 to 430-748 may be arranged adjacent to lower electrodes 420-1 to 420-748, respectively, and further lower electrodes 440-1 to 440-748 may be arranged adjacent to lower electrodes 430-1 to 430-748. For ease of explanation, the following description will be given taking light emitting device 401 having lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 as an example.

[0094] When the lower electrode 410-1 and the lower electrode 420-1 are driven simultaneously, the distance between the central positions exposed by driving the two electrodes on the photosensitive drum 102 is shifted by W+d in the rotation direction of the photosensitive drum 102. The image forming apparatus of this embodiment exposes an area corresponding to one pixel in the output resolution of the image forming apparatus by driving multiple lower electrodes (for example, the lower electrode 410-1 and the lower electrode 420-1) that are adjacent in the rotation direction of the photosensitive drum 102. Therefore, by providing a time difference between the timing of applying a voltage to the lower electrode 410-1 and the timing of applying a voltage to the lower electrode 420-1 in accordance with the rotation speed of the photosensitive drum 102, it is possible to expose an area corresponding to one pixel multiple times (multiple exposure).

[0095] The lower electrodes 410, 420 are arranged in a row at a predetermined interval in the X direction in the figure, for example, at a pitch of 21.16 μm when the resolution is 1200 dpi. The lower electrodes 410, 420 are also arranged at a pitch of 21.16 μm in the Y direction. In the case of Example 2, the width W is 20.9 μm, and the adjacent interval d is arranged at a pitch of 0.26 μm. The cross section of the lower electrodes 410, 420 is the same as in Example 1.

[0096] FIG. 13(b) is a diagram showing the boundary between chips of light emitting devices 401 arranged in two rows in the longitudinal direction, with the horizontal direction being the longitudinal direction of the light emitting device group 400 in FIG. 3(a), and multiple light emitting devices 401 arranged. FIG. 13(b) shows the boundary between chips of light emitting device 401 (the portion where the ends of chips overlap in the longitudinal direction (overlapping portion)). Light emitting device 401 has multiple lower electrodes 410. Even at the boundary between light emitting device 401-2n and light emitting device 401-2n+1, the longitudinal pitch of the lower electrodes 410 (the distance (L) between the center points of two lower electrodes) is approximately 21.16 μm, which is the pitch for a resolution of 1200 dpi.

[0097] The light emitting devices 401 are arranged in two rows, one above the other, in the short direction, as follows: That is, they are arranged so that the interval between the lower electrodes of the upper and lower light emitting devices 401 (indicated by arrow S in the figure) is approximately 105 μm (equivalent to five pixels at 1200 dpi). The interval between the lower electrodes 410 in the longitudinal direction of the exposure head 106 (indicated by arrow L in the figure) is approximately 21.16 μm (equivalent to one pixel at 1200 dpi). Note that in Example 2 as well, the intervals S and L between the light emitting devices 401 do not need to be limited to the values ​​described above.

[0098] FIG. 14(a) shows a circuit block diagram within light-emitting device 401. The circuit configuration is the same as in Example 1. However, because the number of lower electrodes 410 has increased to two columns, the number of pulse signal generation units 805 also doubles. Specifically, the pulse signal generation units corresponding to lower electrodes 410 are 805-1-1, 805-1-2, ... 805-1-748. The pulse signal generation units corresponding to lower electrodes 420 are 805-2-1, 805-2-2, ... 805-2-748. The pulse signal generation units 805-1-1, 805-2-1, etc. are connected to analog unit 806 via pulse signal lines 1006-1-1, 1006-2-1, etc.

[0099] (Image data storage section) Next, the operation of the image data storage unit 804 will be described. An example will be described in which the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals, but they may also be positive logic. The resolution mode signal connected to the register unit 802 via the resolution mode signal line 711 corresponds to low resolution mode (600 dpi) at "0" and high resolution mode (1200 dpi) at "1". The resolution mode signal is a register signal that is set in accordance with the operation of the image data generation unit 701. Figure 8(b) is a circuit configuration diagram of the image data storage unit 804. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk. The clock gate circuit 810 outputs the clock signal s_clk to the flip-flop circuit 811 only when the chip select signal cs_x is valid.

[0100] The flip-flop circuits 811 receive as their original input the image data signal data input to the image data storage unit 804. The same number of flip-flop circuits 811 (748 in the second embodiment) as the number of lower electrodes 410 provided in the longitudinal direction of the light emitting device 401 are connected in series. Selectors 813-1, 813-2, ... are connected to the stages preceding the data input terminals D of the even-numbered flip-flop circuits 811-2, 811-4, .... The resolution mode signal lines 711 are connected to the selectors 813-1, 813-2, ..., and a select signal is input thereto.

[0101] The flip-flop circuit 811 operates in response to the clock signal s_clk sent from the clock gate circuit 810. The output of the flip-flop circuit 811 is output as image data dly_data_000 to dly_data_747 to the next adjacently connected flip-flop circuit 811 or to the selector 813, flip-flop circuit 812, and selector 814. The flip-flop circuits 811 and flip-flop circuits 812 are provided in the longitudinal direction of the lower electrode 410 in the same number as the number of lower electrodes 410 (748 in the second embodiment). The entire flip-flop circuit 811 functions as a shift circuit.

[0102] The flip-flop circuit 812 receives the output of the flip-flop circuit 811 as input and operates in response to the line synchronization signal lsync_x. The output of the flip-flop circuit 812 is output as image data buf_data_0_000 to buf_data_0_747 to the pulse signal generating units 805 (805-2-1, 805-2-2, 805-2-3, etc.) and the selector 814. Each flip-flop circuit 812 functions as a memory circuit, and the flip-flop circuit 812 provided for one lower electrode 420 functions as a memory circuit group (or a second memory circuit group). The pulse signal generating units 805-2-1, 805-2-2, 805-2-3, etc. function as a first pulse signal generating unit group that generates a first pulse signal.

[0103] The output of the selector 814 is connected to a flip-flop circuit 815. Similar to the selector 813, the resolution mode signal line 711 is connected to the selector 814, and a select signal is input to it. When the resolution mode signal is "1", the selector 814 outputs the output of the flip-flop circuit 812 to the flip-flop circuit 815. When the resolution mode signal is "0", the selector 814 outputs the output of the flip-flop circuit 811 to the flip-flop circuit 815. The selector 814-2 will be described in detail. When the resolution mode signal is "1", the selector 814-2 outputs the output of the flip-flop circuit 812-2 (buf_data_0_001) to the flip-flop circuit 815-2. When the resolution mode signal is "0", the selector 814-2 outputs the output (dly_data_001) of the flip-flop circuit 811-2 to the flip-flop circuit 815-2.

[0104] The output of the selector 814 is input to a flip-flop circuit 815. The output of the flip-flop circuit 815 is output to pulse signal generating units 805 (805-1-1, 805-1-2, 805-1-3, etc.) as image data buf_data_1_000 to buf_data_1_747. Each flip-flop circuit 815 functions as a memory circuit, and the flip-flop circuit 815 provided for one lower electrode 410 functions as a memory circuit group (or a first memory circuit group). The pulse signal generating units 805-1-1, 805-1-2, 805-1-3, etc. function as a second pulse signal generating unit group that generates a second pulse signal.

[0105] (in high resolution mode) Fig. 15(a) is a timing chart of the image data storage unit 804 in high resolution mode, i.e., when the resolution mode signal is "1." (i) to (v) in Fig. 15(a) are graphs similar to (i) to (v) in Fig. 9(a). (vi) in Fig. 15(a) shows image data buf_data_0_000 and the like that is the output of the flip-flop circuit 812, and (vii) shows image data buf_data_1_000 and the like that is the output of the flip-flop circuit 815.

[0106] During the period from time T0 to time T1 when the chip select signal cs_x is 0 (cs_x=0 (low level)), the image data is shifted through the serially connected flip-flop circuits 811 as follows: Time T1 is the time when cs_x=0 is captured by the rising edge of the clock signal clk. That is, the image data is shifted in the following order: data → dly_data_000 → dly_data_001 → ... → dly_data_747. During the period when the chip select signal cs_x is low level (cs_x=0), the clock signal clk is input in the same number as the number of bottom electrodes in the longitudinal direction of the light emitting device 401, i.e., 748. In this way, one line's worth of image data is held in dly_data_000 to dly_data_747.

[0107] After time T1, the chip select signal cs_x is 1 (cs_x=1 (high level)), so no shift operation is performed and the image data at time T1 is held. For example, the image data dly_data_000 held in the first flip-flop circuit 811 after time T1 is 747. When the line synchronization signal lsync_x becomes 0 (lsync_x=0 (low level)) at time T2, one line's worth of image data is simultaneously output to the pulse signal generation unit 805 as buf_data_0_000 to buf_data_0_747. Time T2 is the time when lsync_x=0 is captured by the rising edge of the clock signal clk. In other words, the image data dly_data_000 etc. held in the flip-flop circuit 811 is output to the pulse signal generation units 805-2-1, 805-2-2 etc. as image data buf_data_0_000 etc. via the flip-flop circuit 812.

[0108] Furthermore, by the time the next line synchronization signal lsync_x is asserted, the next line of image data 748 to 1495 is transferred via the image data signal line 707. At time T3, one line of data is transferred all at once, in the order of buf_data_0_000 → buf_data_1_000, buf_data_0_001 → buf_data_1_001, .... That is, the image data buf_data_0_000 etc. held in the flip-flop circuit 812 is output to the pulse signal generation units 805-1-1, 805-1-2 etc. as image data buf_data_1_000 etc. via the flip-flop circuit 815. In this way, two lines of image data are output to the pulse signal generation unit 805.

[0109] (in low resolution mode) FIG. 15(b) is a timing chart of the image data storage unit 804 in low-resolution mode, i.e., when the resolution mode signal is "0." Graphs (i) to (vii) in FIG. 15(b) are similar to graphs (i) to (vii) in FIG. 15(a). Between time T0 and time T1, when the chip select signal is captured as 0 (cs_x=0 (low level)) by the rising edge of the clock signal clk, the image data is shifted as follows through the series-connected flip-flop circuits 811. Here, the image data signals are input sequentially starting with "data," but a selector 813 is inserted before each even-numbered flip-flop circuit 811. In low-resolution mode, the selector 813 transfers the same data as the image data signals "dly_data_2n" and "dly_data_2n+1" (n≧0) as a set. Specifically, the same image data is input to dly_data_000 and dly_data_001, the same image data is input to dly_data_002 and dly_data_003, etc. In this way, the image data signal data is increased to twice the data amount of each pixel and transferred.

[0110] At time T2, the line synchronization signal lsync_x is captured as 0 (lsync_x=0 (low level)) by the rising edge of the clock signal clk. In the low resolution mode, the selector 814 located before the flip-flop circuit 815 selects image data so that buf_data_0_n and buf_data_1_n become the same image data, as follows. Specifically, dly_data_000 becomes buf_data_0_000 and buf_data_1_000, and dly_data_001 becomes buf_data_0_001 and buf_data_1_001. Therefore, one line of image data is transferred all at once so that it is copied as two lines of image data, and is output to the pulse signal generation unit 805 as two lines of data.

[0111] [Latent image on the photosensitive drum] FIG. 16 is a schematic diagram showing a latent image formed on the photosensitive drum 102 using the operation of the second embodiment, and also shows the rotation direction of the photosensitive drum 102. The portions indicated by dashed lines in the figure indicate latent images corresponding to pixels formed by the lower electrodes 410 and 420. Furthermore, one square in the direction perpendicular to the rotation direction indicates a latent image corresponding to a pixel formed by the lower electrodes 410-1 and 420-1, the lower electrodes 410-2 and 420-2, and so on. FIG. 16(a) is a schematic diagram of a latent image formed on the photosensitive drum 102 in high-resolution mode. In high-resolution mode, a latent image of 1200 dpi, which is the same resolution as the lower electrodes 410 and 420, is formed in the direction perpendicular to the rotation direction of the photosensitive drum 102. A latent image of 1200 dpi is also formed in the direction parallel to the rotation direction of the photosensitive drum 102. Furthermore, since the lower electrodes 410 and 420 expose the same pixel on the photosensitive drum 102 with the same image data at different times, a latent image for each pixel is formed by two exposures.

[0112] 16(b) is a schematic diagram of a latent image formed on the photosensitive drum 102 in the low-resolution mode. In the low-resolution mode, a latent image of 1200 dpi is formed in both the direction perpendicular to the rotation direction of the photosensitive drum 102 and the direction parallel to the rotation direction of the photosensitive drum 102. However, in the direction perpendicular to the rotation direction of the photosensitive drum 102, an image based on the same image data is formed using every two pixels, in other words, two adjacent lower electrodes, so the latent image has a resolution equivalent to 600 dpi. Furthermore, since an image based on the same image data is formed in the direction parallel to the rotation direction of the photosensitive drum 102, although an image is formed at 1200 dpi, a latent image having a substantial resolution equivalent to 600 dpi is formed.

[0113] As described above, in Example 2, the exposure head has a light-emitting device 401 in which lower electrodes each having multiple rows (two rows in Example 2) are arranged in a two-dimensional manner. Even in this case, by providing a circuit for converting the resolution inside the light-emitting device 401, it is possible to perform multiple exposures even in a case where the light-emitting time per pixel is short, such as in high-resolution mode. Furthermore, even in low-resolution mode, resolution conversion is performed to convert the resolution to the same as the light-emitting point of the light-emitting device 401 regardless of the input resolution, so that there is no difference in the distance between the light-emitting points due to the resolution. In this way, the present invention can be applied to a silicon substrate 402 on which at least one row of lower electrodes is arranged.

[0114] As described above, according to the second embodiment, the same exposure head can be used for both high-resolution images and low-resolution images without degrading the image quality. [Explanation of symbols]

[0115] 202 Printed Circuit Board 401 Light-emitting device 402 Silicon substrate 410 Lower electrode 450 luminous layer 460 Upper electrode 602 Circuit section 604 Light-emitting area 804 Image data storage unit

Claims

1. A rotating photoreceptor; a light-emitting chip having a plurality of light-emitting portions arranged along the rotation axis direction of the photosensitive member, each of which emits light to expose the photosensitive member; an exposure head having a substrate on which the light-emitting chip is provided; a generation unit that generates image data for controlling light emission of the plurality of light-emitting units and outputs the image data to the exposure head; Equipped with the plurality of light-emitting units include a first light-emitting unit and a second light-emitting unit adjacent to the first light-emitting unit in the rotation axis direction, The light-emitting chip further includes a first driving unit that drives the first light-emitting unit based on the image data, a second driving unit that drives the second light-emitting unit based on the image data, and a selector that transfers the same image data output by the generation unit to the first driving unit and the second driving unit. An image forming apparatus characterized by:

2. An image forming device as described in claim 1, characterized in that it operates in a first mode in which a latent image is formed at a first resolution, and a second mode in which a latent image is formed at a second resolution lower than the first resolution.

3. An image forming apparatus as described in Claim 2, characterized in that when the image forming apparatus operates in the second mode, the selector transfers the same image data output by the generation unit to the first drive unit and the second drive unit.

4. An image forming device as described in Claim 3, characterized in that the selector does not transfer the same image data to the first drive unit and the second drive unit when the image forming device operates in the first mode.

5. the first resolution is twice the resolution of the second resolution; 5. The image forming apparatus according to claim 4.

6. The plurality of light-emitting elements are arranged in the direction of the rotation axis at intervals corresponding to the first resolution.

3. The image forming apparatus according to claim 2, wherein the image forming apparatus is a recording medium.

7. The light emitting chip further comprises a silicon substrate; the first driving unit and the second driving unit are built into the silicon substrate; 2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

8. The image forming device described in Claim 2, characterized in that the multiple light-emitting sections include a first electrode layer including multiple lower electrodes arranged along the rotation axis direction, the multiple lower electrodes arranged at intervals corresponding to the first resolution, a second electrode layer including upper electrodes provided corresponding to the multiple lower electrodes and transmitting light, and a light-emitting layer provided between the first electrode layer and the second electrode layer in a vertical direction perpendicular to the surface of the light-emitting chip, the light-emitting layer emitting light when a voltage is applied to the multiple lower electrodes.

9. the second electrode layer is formed in common with all of the plurality of electrodes; 9. The image forming apparatus according to claim 8,

10. The plurality of light-emitting units are organic electroluminescent (EL) units.

2. The image forming apparatus according to claim 1, wherein the image forming apparatus is a recording medium.

Images