GOA circuit and display panel

Abstract

In the GOA circuit and display panel provided in the embodiment of the present application, the GOA circuit includes a GOA unit that is arranged in a multi-stage cascade connection, and other than the GOA unit of the starting stage, the GOA unit includes a first output control module, a second output control module, a first output module and a second output module, where the first output module is used to output a first current stage scanning signal, and the second output module is used to output a second current stage scanning signal. In the GOA circuit, the space occupied by GOA with respect to the bezel can be reduced.

Description

[Technical Field]

[0001] The present application relates to the technical field of displays, and in particular to GOA circuits and display panels. [Background technology]

[0002] Gate Driver On Array (GOA) is a driving method that uses conventional thin film transistor liquid crystal display array processes to fabricate gate row scanning driving signal circuits on the array substrate, thereby realizing gate scanning by row.

[0003] The conventional GOA circuit uses low-temperature polycrystalline oxide display technology, which combines low-temperature polysilicon thin-film transistors and oxide thin-film transistors, allowing the display panel to combine high driving performance and low power consumption. However, low-temperature polycrystalline oxide display technology requires more cascaded GOA units to output forward and reverse scan signals, resulting in a wider bezel for the display panel.

[0004] As the visual requirement for narrower bezels for displays increases, how to reduce the space occupied by the GOA circuitry relative to the bezel so as to enable narrower bezel or bezel-less designs for display panels has become an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of the present application aim to provide a GOA circuit and a display panel to reduce the space occupied by the GOA circuit relative to the bezel.

[0006] In one aspect, an embodiment of the present application provides a GOA circuit, including a multi-stage cascaded GOA unit, the GOA unit including a first output control module, a second output control module, a first output module, and a second output module, the first output control module is electrically connected to a previous stage scan signal input terminal and a first node, and is used to control the potential of the first node, the second output control module is electrically connected to the previous stage scan signal input terminal and a second node, and is used to control the potential of the second node, the first output module is electrically connected to the first node, the second node, and a first current stage scan signal output terminal, and is used to output a first current stage scan signal, the second output module is electrically connected to the first node and a second current stage scan signal output terminal, and is used to output a second current stage scan signal, wherein the first current stage scan signal and the second current stage scan signal have opposite phases.

[0007] In another aspect, the present application provides a display panel, comprising: a display area; and the above-mentioned GOA circuit integrated at an edge of the display area, wherein the GOA unit comprises a multi-stage cascaded GOA unit, the GOA unit comprising: a first output control module, a second output control module, a first output module, and a second output module, wherein the first output control module is electrically connected to a previous stage scan signal input terminal and a first node, and is used to control the potential of the first node; the second output control module is electrically connected to the previous stage scan signal input terminal and a second node, and is used to control the potential of the second node; the first output module is electrically connected to the first node, the second node, and a first current stage scan signal output terminal, and is used to output a first current stage scan signal; and the second output module is electrically connected to the first node and a second current stage scan signal output terminal, and is used to output a second current stage scan signal, wherein the first current stage scan signal and the second current stage scan signal have opposite phases. [Effects of the Invention]

[0008] In the GOA circuit and display panel provided in the embodiments of the present application, the GOA circuit includes GOA units arranged in a multi-stage cascade connection, and in addition to a starting-stage GOA unit, the GOA unit includes a first output control module, a second output control module, a first output module, and a second output module, where the first output module is used to output the first current-stage scanning signal, and the second output module is used to output the second current-stage scanning signal. In the GOA circuit, by providing the first output module and the second output module, the GOA circuit can output forward and backward scanning signals with only one GOA unit, thereby reducing the space occupied by the GOA relative to the bezel and further helping to realize a narrower bezel or bezel-less design. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram of the GOA circuit structure provided in the examples of the present application. [Figure 2] FIG. 1 is a structural schematic diagram of a first embodiment of a GOA unit in a GOA circuit provided in an embodiment of the present application; [Figure 3] FIG. 1 is a circuit schematic diagram of a first embodiment of a GOA unit in a GOA circuit provided in an example of the present application. [Figure 4] FIG. 10 is a circuit schematic diagram of a second embodiment of the GOA unit in the GOA circuit provided in the examples of the present application. [Figure 5] FIG. 10 is a circuit schematic diagram of a third embodiment of the GOA unit in the GOA circuit provided in the examples of the present application. [Figure 6] FIG. 4 is a signal sequence diagram of the GOA unit in the GOA circuit provided in FIG. 3. [Figure 7] 4 is a schematic diagram of the simulation results of the GOA circuit provided in FIG. 3. [Figure 8] 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0010] The following describes the technical solutions in the embodiments of the present application in combination with the drawings in the embodiments of the present application. The described embodiments are only for interpreting and explaining the idea of ​​the present application, and should not be considered as limiting the protection scope of the present application.

[0011] The transistors used in all embodiments of the present application may be thin film transistors, field effect transistors, or other components with similar characteristics. Since the source and drain of the transistors used herein are symmetrical, the terms "source" and "drain" are interchangeable. In the embodiments of the present application, to distinguish between the two electrodes of the transistor other than the gate, one of the source and drain is referred to as the first electrode, and the other is referred to as the second electrode. Based on the configuration in the drawings, the intermediate input terminal of the switch transistor is defined as the gate, the signal input terminal as the first electrode, and the input terminal as the second electrode. Furthermore, the transistors used in the embodiments of the present application are P-type or N-type transistors. Here, a P-type transistor is conductive when its gate is at a low potential and is cut off when its gate is at a high potential, while an N-type transistor is conductive when its gate is at a high potential and is cut off when its gate is at a low potential.

[0012] Please refer to Figure 1, which is a structural schematic diagram of the GOA circuit provided in the embodiment of the present application. As shown in Figure 1, the GOA circuit provided in the embodiment of the present application includes multi-stage cascaded GOA units. Figure 1 takes as an example the cascaded N-1th stage GOA unit GOA(n-1), Nth stage GOA unit GOA(n) and N+1th stage GOA unit GOA(n+1).

[0013] The GOA unit GOA(n-1) of the N-1th stage, the GOA unit GOA(n) of the Nth stage, and the GOA unit GOA(n+1) of the N+1th stage are respectively connected to the scanning lines G(n-1), G(n), and G(n+1). Here, the GOA unit GOA(n) of the Nth stage receives the first current stage scanning signal PSCAN(n-1) output from the GOA unit GOA(n-1) of the N-1th stage. Accordingly, the GOA unit GOA(n+1) of the N+1th stage receives the first current stage scanning signal PSCAN(n) output from the GOA unit GOA(n). The same applies below, and at the same time, the GOA unit GOA(n-1) of the N-1th stage transmits the second current stage scan signal NSCAN(n-1) to the scan line G(n-1) connected to the GOA unit GOA(n-1) of the N-1th stage, the GOA unit GOA(n) of the Nth stage transmits the second current stage scan signal NSCAN(n) to the scan line G(n) connected to the GOA unit GOA(n) of the Nth stage, the GOA unit GOA(n+1) of the N+1th stage transmits the second current stage scan signal NSCAN(n+1) to the scan line G(n+1) connected to the GOA unit GOA(n+1) of the N+1th stage, and so on.

[0014] In addition, in the embodiment of the present application, the first current stage scanning signal may be NSCAN(n), and the first current stage scanning signal NSCAN(n) is output to the GOA unit of the subsequent stage. In this case, the second current stage scanning signal is PSCAN(n), and the second current stage scanning signal PSCAN(n) is transmitted to the scanning line G(n) connected to the GOA unit GOA(n) of the Nth stage.

[0015] Here, in response to the start signal STV, the first stage GOA unit GOA(1) transmits a second current stage scan signal NSCAN(1) to the first scan line G(1) connected to the first stage GOA unit GOA(1), and transmits a first current stage scan signal PSCAN(1) to the second stage GOA unit GOA(2). Note that the Nth stage GOA unit (N is a natural number greater than 1) transmits a second current stage scan signal NSCAN(n) to the Nth scan line G(n), and transmits a first current stage scan signal PSCAN(n) to the N+1th stage GOA unit GOA(n+1).

[0016] The scan driving control signal includes a first clock signal CK and a second clock signal XCK, and the first clock signal CK and the second clock signal XCK may be an inverse pair of clock signals, that is, when the first clock signal CK is at a high potential, the second clock signal XCK is at a low potential, or when the first clock signal CK is at a low potential, the second clock signal XCK is at a high potential.

[0017] When the Nth stage GOA unit is operating, the second current stage scanning signal NSCAN(n) output from the Nth stage GOA unit GOA(n) is at a high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode in each pixel through a data signal; the first current stage scanning signal PSCAN(n) is used to control the operation of the N+1th stage GOA unit; when the N+1th stage GOA unit is operating, the second current stage scanning signal NSCAN(n+1) output from the N+1th stage GOA unit GOA(n+1) is at a high potential, and the second current stage scanning signal NSCAN(n) output from the Nth stage GOA unit GOA(n) is at a low potential.

[0018] 2, which is a structural schematic diagram of a first embodiment of a GOA unit in a GOA circuit provided in an embodiment of the present application. As shown in FIG. 2, the GOA unit is a non-starting stage GOA unit, and includes a first output control module 101, a second output control module 102, a first output module 103, and a second output module 104.

[0019] Specifically, the first output control module 101 is electrically connected to the previous stage scanning signal input terminal PSCAN(n-1) / NSCAN(n-1) and the first node Q, and the first output control module 101 is used to control the potential of the first node Q.

[0020] Specifically, the second output control module 102 is electrically connected to the previous stage scanning signal input terminal PSCAN(n-1) / NSCAN(n-1) and the second node P, and the second output control module 102 is used to control the potential of the second node P.

[0021] Specifically, the first output module 103 is electrically connected to the first node Q, the second node P, and the first current stage scan signal output terminal PSCAN(n-1) / NSCAN(n-1), and the first output module 103 is used to output the first current stage scan signal PSCAN(n-1) / NSCAN(n-1).

[0022] Specifically, the second output module 104 is electrically connected to the first node Q and the second current stage scan signal output terminal NSCAN(n-1) / PSCAN(n-1), and the second output module 104 is used to output the second current stage scan signal NSCAN(n-1) / PSCAN(n-1).

[0023] Here, the phases of the first current stage scan signal PSCAN(n-1) / NSCAN(n-1) and the second current stage scan signal NSCAN(n-1) / PSCAN(n-1) are opposite, that is, when the first current stage scan signal is PSCAN(n-1), the second current stage scan signal is NSCAN(n-1), or when the first current stage scan signal is NSCAN(n-1), the second current stage scan signal is PSCAN(n-1).

[0024] In the GOA circuit provided in the present application, by providing a first output module 103 and a second output module 104 which respectively output scanning signals of opposite phases, the GOA circuit can output forward and backward scanning signals with only one GOA unit, which reduces the space occupied by the GOA relative to the bezel and helps to realize a narrower bezel or a bezel-less design.

[0025] In this embodiment, the second output module 104 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 is electrically connected to the first node Q, the first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the second current stage scan signal output terminal NSCAN(n), where the gate of the second transistor T2 is electrically connected to the first output module 103, the first electrode of the second transistor T2 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1. For details, please refer to the embodiments corresponding to Figures 3 and 4 below.

[0026] Please refer to Figure 3, which is a circuit diagram of a first embodiment of the GOA unit in the GOA circuit provided in the embodiment of the present application. As shown in Figures 2 and 3, the second output module 104 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 is electrically connected to a first node Q, the first electrode of the first transistor T1 is electrically connected to a reference high level signal input terminal VGH, and the second electrode of the first transistor T1 is electrically connected to a second current stage scan signal output terminal NSCAN(n).

[0027] The gate of the second transistor T2 is electrically connected to the first node Q, the first electrode of the second transistor T2 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1.

[0028] Specifically, the first output control module 101 includes a third transistor T3, the gate of which is electrically connected to the first clock signal input terminal CK, the first electrode of which is electrically connected to the previous stage scanning signal input terminal PSCAN(n-1), and the second electrode of which is electrically connected to the first node Q.

[0029] Specifically, the second output control module 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1, wherein the gate of the fourth transistor T4 is electrically connected to the third node S, the first electrode of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK, and the second electrode of the fourth transistor T4 is electrically connected to the second node P.

[0030] A gate of the fifth transistor T5 is electrically connected to the second clock signal input terminal XCK, a first electrode of the fifth transistor T5 is electrically connected to the third node S, and a second electrode of the fifth transistor T5 is electrically connected to the reference low level signal input terminal VGL.

[0031] The gate of the sixth transistor T6 is electrically connected to the previous stage scanning signal input terminal PSCAN(n-1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the third node S.

[0032] The gate of the seventh transistor T7 is electrically connected to the first node Q, the first electrode of the seventh transistor T7 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the second node P.

[0033] One end of the first capacitor C1 is electrically connected to the first clock signal input terminal CK, and the other end of the first capacitor C1 is electrically connected to the third node S.

[0034] Specifically, the first output module 103 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2 and a third capacitor C3, a gate of the eighth transistor T8 is electrically connected to the reference high level signal input terminal VGH, a first electrode of the eighth transistor T8 is electrically connected to the first node Q, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N.

[0035] The gate of the ninth transistor T9 is electrically connected to the fourth node N, the first electrode of the ninth transistor T9 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the first current stage scan signal output terminal PSCAN(n), where the first current stage scan signal output terminal PSCAN(n) is electrically connected to the next stage scan signal input terminal.

[0036] The gate of the tenth transistor T10 is electrically connected to the second node P, the first electrode of the tenth transistor T10 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the tenth transistor T10 is electrically connected to the first current stage scan signal output terminal PSCAN(n).

[0037] One end of the second capacitor C2 is electrically connected to the fourth node N, the other end of the second capacitor C2 is electrically connected to the first current stage scan signal output terminal PSCAN(n), one end of the third capacitor C3 is electrically connected to the second node P, and the other end of the third capacitor C3 is electrically connected to the reference low level signal input terminal VGL.

[0038] Specifically, the first output module 103 further includes an eleventh transistor T11, the gate of which is electrically connected to the fourth node N, the first electrode of which is electrically connected to the second electrode of the ninth transistor T9, and the second electrode of which is electrically connected to the first current stage scan signal output terminal PSCAN(n).

[0039] Here, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are all N-type transistors, and the first transistor T1 is a P-type transistor.

[0040] The previous stage scan signal input terminal PSCAN(n-1) receives the previous stage scan signal, the first current stage scan signal output terminal PSCAN(n) outputs the first current stage scan signal PSCAN(n), the second current stage scan signal output terminal NSCAN(n) outputs the second current stage scan signal NSCAN(n), the first clock signal input terminal CK receives the first clock signal CK, the second clock signal input terminal XCK receives the second clock signal XCK, the reference high level signal input terminal VGH receives the reference high level signal VGH, and the reference low level signal input terminal VGL receives the reference low level signal VGL.

[0041] Specifically, refer to Figure 4, which is a structural schematic diagram of a second embodiment of the GOA unit in the GOA circuit provided in the embodiment of the present application. As shown in Figures 2 and 4, the second output module 104 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 is electrically connected to the first node Q, the first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, the second electrode of the first transistor T1 is electrically connected to the second current stage scanning signal output terminal PSCAN(n), the gate of the second transistor T2 is electrically connected to the second node P, the first electrode of the second transistor T2 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1.

[0042] Specifically, the first output control module 101 includes a third transistor T3, the gate of which is electrically connected to the first clock signal input terminal CK, the first electrode of which is electrically connected to the previous stage scanning signal input terminal NSCAN(n-1), and the second electrode of which is electrically connected to the first node Q.

[0043] Specifically, the second output control module 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1, wherein the gate of the fourth transistor T4 is electrically connected to the third node S, the first electrode of the fourth transistor T4 is electrically connected to the first clock signal input terminal CK, and the second electrode of the fourth transistor T4 is electrically connected to the second node P.

[0044] A gate of the fifth transistor T5 is electrically connected to the second clock signal input terminal XCK, a first electrode of the fifth transistor T5 is electrically connected to the third node S, and a second electrode of the fifth transistor T5 is electrically connected to the reference low level signal input terminal VGL.

[0045] The gate of the sixth transistor T6 is electrically connected to the previous stage scanning signal input terminal NSCAN(n-1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the third node S.

[0046] The gate of the seventh transistor T7 is electrically connected to the first node Q, the first electrode of the seventh transistor T7 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the second node P.

[0047] One end of the first capacitor C1 is electrically connected to the first clock signal input terminal CK, and the other end of the first capacitor C1 is electrically connected to the third node S.

[0048] Specifically, the first output module 103 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2 and a third capacitor C3, a gate of the eighth transistor T8 is electrically connected to the reference high level signal input terminal VGH, a first electrode of the eighth transistor T8 is electrically connected to the first node Q, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N.

[0049] The gate of the ninth transistor T9 is electrically connected to the fourth node N, the first electrode of the ninth transistor T9 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the first current stage scanning signal output terminal NSCAN(n), where the first current stage scanning signal output terminal NSCAN(n) is electrically connected to the next stage scanning signal input terminal.

[0050] The gate of the tenth transistor T10 is electrically connected to the second node P, the first electrode of the tenth transistor T10 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the tenth transistor T10 is electrically connected to the first current stage scan signal output terminal NSCAN(n).

[0051] One end of the second capacitor C2 is electrically connected to the fourth node N, the other end of the second capacitor C2 is electrically connected to the first current stage scan signal output terminal NSCAN(n), one end of the third capacitor C3 is electrically connected to the second node P, and the other end of the third capacitor C3 is electrically connected to the reference low level signal input terminal VGL.

[0052] Here, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are N-type transistors, and the first transistor T1, the second transistor T2, and the seventh transistor T7 are P-type transistors.

[0053] The previous stage scan signal input terminal NSCAN(n-1) receives the previous stage scan signal NSCAN(n-1), the first current stage scan signal output terminal NSCAN(n) outputs the first current stage scan signal NSCAN(n), the second current stage scan signal output terminal PSCAN(n) outputs the second current stage scan signal, the first clock signal input terminal CK receives the first clock signal CK, the second clock signal input terminal XCK receives the second clock signal XCK, the reference high level signal input terminal VGH receives the reference high level signal VGH, and the reference low level signal input terminal VGL receives the reference low level signal VGL.

[0054] Specifically, refer to Figure 5, which is a structural schematic diagram of a third embodiment of the GOA unit in the GOA circuit provided in the embodiments of the present application. As shown in Figures 2 and 5, the second output module 104 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 is electrically connected to a first node Q, the first electrode of the first transistor T1 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the first transistor T1 is electrically connected to the second current stage scan signal output terminal PSCAN(n).

[0055] Specifically, the gate of the second transistor T2 is electrically connected to the first node Q, the first electrode of the second transistor T2 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1.

[0056] Specifically, the first output control module 101 includes a third transistor T3, the gate of which is electrically connected to the first clock signal input terminal CK, the first electrode of which is electrically connected to the previous stage scanning signal input terminal NSCAN(n-1), and the second electrode of which is electrically connected to the first node Q.

[0057] Specifically, the second output control module 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1, wherein the gate of the fourth transistor T4 is electrically connected to the third node S, the first electrode of the fourth transistor T4 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the second node P.

[0058] A gate of the fifth transistor T5 is electrically connected to the second clock signal input terminal XCK, a first electrode of the fifth transistor T5 is electrically connected to the third node S, and a second electrode of the fifth transistor T5 is electrically connected to the reference low level signal input terminal VGL.

[0059] The gate of the sixth transistor T6 is electrically connected to the previous stage scanning signal input terminal NSCAN(n-1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the third node S.

[0060] The gate of the seventh transistor T7 is electrically connected to the first node Q, the first electrode of the seventh transistor T7 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the seventh transistor T7 is electrically connected to the second node P.

[0061] One end of the first capacitor C1 is electrically connected to the reference low level signal input terminal VGL, and the other end of the first capacitor C1 is electrically connected to the third node S.

[0062] Specifically, the first output module 103 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second capacitor C2 and a third capacitor C3, a gate of the eighth transistor T8 is electrically connected to the reference low level signal input terminal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node Q, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N.

[0063] The gate of the ninth transistor T9 is electrically connected to the fourth node N, the first electrode of the ninth transistor T9 is electrically connected to the second clock signal input terminal XCK, and the second electrode of the ninth transistor T9 is electrically connected to the first current stage scan signal output terminal NSCAN(n).

[0064] The gate of the tenth transistor T10 is electrically connected to the second node P, the first electrode of the tenth transistor T10 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the tenth transistor T10 is electrically connected to the first current stage scan signal output terminal NSCAN(n).

[0065] One end of the second capacitor C2 is electrically connected to the fourth node N, and the other end of the second capacitor C2 is electrically connected to the first current stage scan signal output terminal NSCAN(n).

[0066] One end of the third capacitor C3 is electrically connected to the second node P, and the other end of the third capacitor C3 is electrically connected to the reference high level signal input terminal VGH.

[0067] Here, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all P-type transistors, and the second transistor T2 is an N-type transistor.

[0068] The previous stage scan signal input terminal NSCAN(n-1) receives the previous stage scan signal NSCAN(n-1), the first current stage scan signal output terminal NSCAN(n) outputs the first current stage scan signal NSCAN(n), the second current stage scan signal output terminal PSCAN(n) outputs the second current stage scan signal, the first clock signal input terminal CK receives the first clock signal CK, the second clock signal input terminal XCK receives the second clock signal XCK, the reference high level signal input terminal VGH receives the reference high level signal VGH, and the reference low level signal input terminal VGL receives the reference low level signal VGL.

[0069] Please refer to FIG. 6, which is a signal sequence diagram of the GOA unit in the GOA circuit shown in FIG. 3. FIG. 6 shows a GOA circuit with one set of clock control signals within one frame time period, using a high-frequency signal with a duty cycle of 50 / 50. In an actual display panel, clock signals with different duty cycles can be set to drive the GOA circuit as needed, and multiple sets of high-frequency clock signals can be designed according to the load of the display panel. Specifically, the start signal STV is input to the first output control module 101 of the first-stage GOA unit and the first output module 103 of the last-stage GOA unit, and is used to charge the first node Q.

[0070] Specifically, the start signal STV of the GOA circuit is used to start the first stage GOA circuit, while the start signal STV of the N+1th stage GOA circuit is generated from the first current stage scanning signal PSCAN(n) output from the first output module 103 of the Nth stage GOA circuit, thus gradually starting the GOA driving circuit and realizing row scanning driving.

[0071] Specifically, the first clock signal CK and the second clock signal XCK are a pair of high-frequency clock signals with the same high and low potentials but opposite phases. The pulse width, cycle and high and low potentials of the clock signals are mainly determined according to the design requirements of the waveform of the scanning signal of the display panel. Therefore, in actual application of the display panel, the signal does not necessarily have a duty ratio of 50 / 50 as shown in the figure. In addition, depending on the design requirements of the panel, different numbers of clock signals may be used to withstand different design loads.

[0072] Here, in the first output stage t1, the first clock signal CK is written to a high potential, and the third transistor T3 is turned on; at this time, the first node Q is written to a low potential of the start signal STV, and the first transistor T1 is turned on, and the second output module 104 outputs the second current stage scan signal NSCAN(n).

[0073] In the second output stage t2, the first clock signal CK is written to a high potential, and the third transistor T3 is turned on. At this time, the first node Q is written to the high potential of the start signal STV, charging the first node Q, and the first transistor T1 is turned off. Due to the high potential of the reference high level signal VGH, the eighth transistor T8 is turned on, and the high potential of the first node Q is transmitted to the second node N. The ninth transistor T9 and the eleventh transistor T11 are turned on, and the first output module 103 outputs the first current stage scan signal PSCAN(n).

[0074] Please refer to Figure 7, which is a schematic diagram of the simulation results of the GOA circuit provided in Figure 3. As shown in Figure 7, the potentials of the first current stage scan signal PSCAN(n), the second current stage scan signal NSCAN(n), and the previous stage scan signal PSCAN(n-1) (or start signal STV) change. In the GOA circuit provided in the present application, forward and backward scan signals can be output using only one GOA unit, reducing the space occupied by the GOA relative to the bezel, enabling a narrower bezel or bezel-less design of the display panel, preventing noise output during times when scan signals are not being output, and ensuring driving stability.

[0075] Please refer to Fig. 8, which is a structural schematic diagram of a display panel provided in an embodiment of the present application. As shown in Fig. 8, the present application further provides a display panel, which includes a display area 100 and the above-mentioned GOA circuit 10 integrated at the edge of the display area, where the GOA circuit 10 has the same structure and principle as the above-mentioned GOA circuit 10, and therefore will not be described here.

[0076] In the GOA circuit and display panel provided in the embodiments of the present application, the GOA circuit is provided with a first output module 103 and a second output module 104, so that the GOA circuit can output forward and backward scanning signals using only one GOA unit, thereby reducing the space occupied by the GOA relative to the bezel and enabling the display panel to have a narrower bezel or bezel-less design.

[0077] The above has provided a detailed description of the GOA circuit and display panel provided in the embodiments of the present application. Although the present specification has described the principles and embodiments of the present application using specific examples, the description of the above examples is merely intended to facilitate understanding of the method and gist of the present application. Furthermore, those skilled in the art may make modifications to the specific embodiments and application scope based on the concept of the present application, and therefore the contents of this specification should not be construed as limiting the present application.

Claims

1. The GOA unit includes a multi-stage cascaded GOA unit, the GOA unit including a first output control module, a second output control module, a first output module and a second output module; The first output control module is electrically connected to a previous stage scanning signal input terminal and a first node, and is used to control the potential of the first node; the second output control module is electrically connected to the previous stage scanning signal input terminal and a second node, and is used to control the potential of the second node; the first output module is electrically connected to the first node, the second node and a first current stage scanning signal output terminal, and is used to output a first current stage scanning signal; the second output module is electrically connected to the first node and a second current stage scanning signal output terminal, and is used to output a second current stage scanning signal; wherein the first current stage scanning signal and the second current stage scanning signal have opposite phases; the second output control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor, a gate of the fourth transistor is electrically connected to a third node, a first electrode of the fourth transistor is electrically connected to a first clock signal input terminal, and a second electrode of the fourth transistor is electrically connected to the second node; a gate of the fifth transistor electrically connected to a second clock signal input terminal, a first electrode of the fifth transistor electrically connected to the third node, and a second electrode of the fifth transistor electrically connected to a reference low level signal input terminal; a gate of the sixth transistor electrically connected to the previous stage scanning signal input terminal, a first electrode of the sixth transistor electrically connected to the reference low level signal input terminal, and a second electrode of the sixth transistor electrically connected to the third node; a gate of the seventh transistor electrically connected to the first node, a first electrode of the seventh transistor electrically connected to the reference low level signal input terminal, and a second electrode of the seventh transistor electrically connected to the second node; A GOA circuit, wherein one end of the first capacitor is electrically connected to the first clock signal input terminal, and the other end of the first capacitor is electrically connected to the third node.

2. the second output module includes a first transistor and a second transistor, a gate of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to a reference high level signal input terminal, and a second electrode of the first transistor is electrically connected to the second current stage scanning signal output terminal; 2. The GOA circuit as claimed in claim 1, wherein the gate of said second transistor is electrically connected to said first output module, and the first electrode of said second transistor is electrically connected to a reference low-level signal input terminal, and the second electrode of said second transistor is electrically connected to the second electrode of said first transistor.

3. The GOA circuit according to claim 2 , wherein the gate of the second transistor is electrically connected to the first node.

4. 4. The GOA circuit according to claim 3, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

5. The GOA circuit according to claim 2 , wherein the gate of the second transistor is electrically connected to the second node.

6. 6. The GOA circuit according to claim 5, wherein the first transistor and the second transistor are both P-type transistors.

7. 2. The GOA circuit of claim 1, wherein said first output control module comprises a third transistor, and the gate of said third transistor is electrically connected to a first clock signal input terminal, and the first electrode of said third transistor is electrically connected to said previous stage scanning signal input terminal, and the second electrode of said third transistor is electrically connected to said first node.

8. the first output module includes an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor, wherein a gate of the eighth transistor is electrically connected to a reference high-level signal input terminal, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to a fourth node; a gate of the ninth transistor electrically connected to the fourth node, a first electrode of the ninth transistor electrically connected to the reference high level signal input terminal, and a second electrode of the ninth transistor electrically connected to the first current stage scanning signal output terminal, wherein the first current stage scanning signal output terminal is electrically connected to the next stage scanning signal input terminal; a gate of the tenth transistor electrically connected to the second node, a first electrode of the tenth transistor electrically connected to a reference low level signal input terminal, and a second electrode of the tenth transistor electrically connected to the first current stage scanning signal output terminal; one end of the second capacitor is electrically connected to the fourth node, and the other end of the second capacitor is electrically connected to the first current stage scan signal output terminal; 2. The GOA circuit according to claim 1, wherein one end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the reference low-level signal input terminal.

9. 9. The GOA circuit of claim 8, wherein the first output module further comprises an eleventh transistor, wherein the gate of the eleventh transistor is electrically connected to the fourth node, the first electrode of the eleventh transistor is electrically connected to the second electrode of the ninth transistor, and the second electrode of the eleventh transistor is electrically connected to the first current stage scanning signal output terminal.

10. A multi-stage cascaded GOA unit is provided, the GOA unit including a first output control module, a second output control module, a first output module, and a second output module; The first output control module is electrically connected to a previous stage scanning signal input terminal and a first node, and is used to control the potential of the first node; the second output control module is electrically connected to the previous stage scanning signal input terminal and a second node, and is used to control the potential of the second node; the first output module is electrically connected to the first node, the second node and a first current stage scanning signal output terminal, and is used to output a first current stage scanning signal; the second output module is electrically connected to the first node and a second current stage scanning signal output terminal, and is used to output a second current stage scanning signal; wherein the first current stage scanning signal and the second current stage scanning signal have opposite phases; the second output module includes a first transistor and a second transistor, a gate of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to a reference high level signal input terminal, and a second electrode of the first transistor is electrically connected to the second current stage scanning signal output terminal; a gate of the second transistor electrically connected to the first output module, a first electrode of the second transistor electrically connected to a reference low-level signal input terminal, and a second electrode of the second transistor electrically connected to the second electrode of the first transistor; a gate of the second transistor electrically connected to the first node; the first transistor is a P-type transistor and the second transistor is an N-type transistor; the first output control module includes a third transistor, the gate of the third transistor is electrically connected to a first clock signal input terminal, the first electrode of the third transistor is electrically connected to the previous stage scanning signal input terminal, and the second electrode of the third transistor is electrically connected to the first node; The second output control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor, wherein a gate of the fourth transistor is electrically connected to a third node, a first electrode of the fourth transistor is electrically connected to a reference low-level signal input terminal, a second electrode of the fourth transistor is electrically connected to the second node, a gate of the fifth transistor is electrically connected to a second clock signal input terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to the reference low-level signal input terminal, and the sixth transistor a gate of the sixth transistor electrically connected to the previous stage scanning signal input terminal, a first electrode of the sixth transistor electrically connected to the reference low level signal input terminal, a second electrode of the sixth transistor electrically connected to the third node, a gate of the seventh transistor electrically connected to the first node, a first electrode of the seventh transistor electrically connected to the reference high level signal input terminal, and a second electrode of the seventh transistor electrically connected to the second node; one end of the first capacitor electrically connected to the reference low level signal input terminal, and the other end of the first capacitor electrically connected to the third node; The first output module includes an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor, wherein the gate of the eighth transistor is electrically connected to a reference low level signal input terminal, a first electrode of the eighth transistor is electrically connected to the first node, a second electrode of the eighth transistor is electrically connected to a fourth node, a gate of the ninth transistor is electrically connected to the fourth node, a first electrode of the ninth transistor is electrically connected to the second clock signal input terminal, and a second electrode of the ninth transistor is electrically connected to the first current stage scanning signal output terminal. GOA circuit, wherein the gate of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the reference high level signal input terminal, the second electrode of the tenth transistor is electrically connected to the first current stage scanning signal output terminal, one end of the second capacitor is electrically connected to the fourth node, the other end of the second capacitor is electrically connected to the first current stage scanning signal output terminal, one end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the reference high level signal input terminal.

11. A display area; A display panel, comprising: a GOA circuit according to any one of claims 1 to 10, which is integrated at the edge of the display area.

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