Packet processing device and packet processing method

Abstract

To improve performance of a parallel processing of a packet process of a plurality of communication entities.SOLUTION: A plurality of packet processing units execute a plurality of packet processes in parallel. Each of a plurality of storage units stores information associated with any of communication entity among a plurality of communication entities. A switching unit switches the plurality of storage units. A control unit assigns a packet processing of a specific communication entity among the plurality of communication entities to a specific packet processing unit among a plurality of packet processing units. Then, the control unit allows the specific packet processing unit to access to the information associated with the specific communication entity among the information stored by each of the plurality of storage units by controlling the switching unit.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to packet processing technology. [Background technology]

[0002] NFV (Network Function Virtualization) is a technology that implements network functions that were previously implemented using dedicated equipment using software on general-purpose servers. NFV uses server virtualization technology to accommodate multiple virtual network functions (VNFs) on a single physical server.

[0003] Fig. 1 shows an example of the configuration of a conventional NFV system. The NFV system in Fig. 1 includes a physical server 101, which includes VNFs 111-1 to 111-3, a hypervisor 112, and a network interface controller (NIC) 121. The VNFs 111-i (i = 1 to 3) and the hypervisor 112 are implemented by software.

[0004] The VNF 111-i is, for example, a virtual machine (VM) and operates on the hypervisor 112. The VNF 111-1 operates, for example, as a load balancer, the VNF 111-2 operates, for example, as a firewall, and the VNF 111-3 operates, for example, as a router. The NIC 121 is hardware and includes IFs (interfaces) 122-1 and 122-2.

[0005] Dashed line 131 represents the traffic of packets that the physical server 101 receives from an external communication network via IF 122-1. Dashed line 132 represents the traffic of service chaining realized by VNFs 111-1 to 111-3. Dashed line 133 represents the traffic of packets that the physical server 101 transmits to an external communication network via IF 122-2.

[0006] The hypervisor 112 includes a virtual switch 113. The virtual switch 113 relays communications between the VNF 111-i and an external communication network and communications among the VNFs 111-1 to 111-3. The hypervisor 112 may include a virtual router instead of the virtual switch 113.

[0007] In relation to NFV, a network load balancing device is known that enables a packet distribution control method to be changed for each of multiple VMs while maintaining high throughput of VNFs, thereby achieving high functionality and high throughput for the entire system (see, for example, Patent Document 1).A communication system is also known that improves communication efficiency by changing the communication path depending on the packet destination (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2020-10190 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-187430 Summary of the Invention [Problem to be solved by the invention]

[0009] In NFV, due to service chaining and other factors, communication within physical servers will increase significantly compared to conventional virtualized environments, making packet relay performance in virtual switches or virtual routers important.

[0010] However, in a software implementation such as that shown in Figure 1, a large amount of CPU (Central Processing Unit) resources are allocated to the packet relay process itself, reducing the CPU resources available for applications. In this case, it is effective to offload the relay process of the virtual switch or virtual router to an FPGA (Field Programmable Gate Array) or smart NIC.

[0011] In this case, the efficiency of packet processing can be improved by providing multiple circuits that operate in parallel within the smart NIC. However, if there is an imbalance in the number of VMs that each circuit is responsible for, the parallel processing performance may not be fully utilized, and the efficiency of packet processing may decrease.

[0012] This problem occurs not only when VM packet processing is performed in a smart NIC, but also when packet processing for various communication entities is performed in various packet processing devices.

[0013] In one aspect, the present invention aims to improve the performance of parallel processing in packet processing for multiple communication entities. [Means for solving the problem]

[0014] In one example, the packet processing device includes a plurality of packet processing units, a plurality of storage units, a switch unit, and a control unit.

[0015] The plurality of packet processing units executes a plurality of packet processes in parallel. Each of the plurality of storage units stores information associated with one of the plurality of communication entities. The switch unit switches between the plurality of storage units.

[0016] The control unit assigns packet processing for a specific one of the plurality of communication entities to a specific one of the plurality of packet processing units, and controls the switch unit to cause the specific packet processing unit to access information associated with the specific communication entity from information stored in each of the plurality of storage units. [Effects of the Invention]

[0017] According to one aspect, it is possible to improve the performance of parallel processing in packet processing for a plurality of communication entities. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a configuration diagram of a conventional NFV system. [Figure 2] FIG. 1 is a configuration diagram of an NFV system according to an embodiment. [Figure 3] FIG. 2 is a diagram illustrating information stored in a memory. [Figure 4] FIG. 1 is a diagram illustrating the configuration of a DMA read unit. [Figure 5] FIG. 1 is a diagram illustrating the configuration of a DMA write unit. [Figure 6] FIG. 10 is a diagram showing a first data transfer sequence. [Figure 7] This is a block diagram of the DMA read section, which includes three circuits. [Figure 8] FIG. 10 is a diagram showing a second data transfer sequence. [Figure 9] This is a block diagram of a DMA read unit that includes two circuits. [Figure 10] FIG. 10 is a diagram illustrating the throughput of a read request. [Figure 11] FIG. 10 is a configuration diagram of a packet processing device of a comparative example. [Figure 12] FIG. 2 is a functional configuration diagram of a packet processing device according to an embodiment. [Figure 13] 10 is a flowchart of packet processing. [Figure 14] FIG. 2 is a configuration diagram of a first packet processing device. [Figure 15] FIG. 10 is a diagram illustrating the configuration of a first packet processing device when N=4 and M=2. [Figure 16] FIG. 10 illustrates a first operation of the packet processing device. [Figure 17] FIG. 10 illustrates a second operation of the packet processing device. [Figure 18] FIG. 10 illustrates a third operation of the packet processing device. [Figure 19] FIG. 1 illustrates a first operation of the circuit. [Figure 20] FIG. 10 illustrates a second operation of the circuit. [Figure 21] FIG. 10 illustrates a fourth operation of the packet processing device. [Figure 22] FIG. 10 is a diagram illustrating a first priority control. [Figure 23] FIG. 10 is a diagram illustrating a first operation of a selector. [Figure 24] FIG. 10 is a diagram illustrating a second priority control. [Figure 25] FIG. 10 is a diagram illustrating a second operation of the selector. [Figure 26] 10 is a flowchart of a control process. [Figure 27] FIG. 10 is a diagram illustrating the correspondence between the maximum throughput value and the number of parallel processes. [Figure 28] FIG. 10 is a configuration diagram of a second packet processing device. [Figure 29] FIG. 10 is a diagram illustrating switching of a crossbar switch. [Figure 30] FIG. 10 is a diagram illustrating an update of a conversion table. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0020] Fig. 2 shows an example of the configuration of an NFV system according to an embodiment. The NFV system in Fig. 2 includes a physical server 201. The physical server 201 is an information processing device (computer) and includes a CPU 211, a memory 212, and a NIC 213. The CPU 211, the memory 212, and the NIC 213 are hardware components.

[0021] The CPU 211 runs VM0 to VM3 by executing programs using the memory 212. VMi (i=0 to 3) operates as, for example, a load balancer, a firewall, or a router. The number of VMs operating within the physical server 201 is not limited to four, and may be one to three, or five or more.

[0022] The NIC 213 includes a DMA read unit 221, a DMA write unit 222, a NIC control unit 223, a NIC switch unit 224, and an IF 225. These components are hardware.

[0023] The NIC 213 is, for example, a smart NIC, and uses a direct memory access (DMA) function to relay communications between VMi and an external communications network and communications among VM0 to VM3.

[0024] The DMA read unit 221 uses the DMA function to read outgoing data from the memory 212, generates a packet including the outgoing data, and outputs it to the NIC switch unit 224. The DMA write unit 222 extracts the outgoing data from the packet output from the NIC switch unit 224, and uses the DMA function to write the outgoing data to the memory 212 as received data. The NIC control unit 223 controls the operations of the DMA read unit 221 and the DMA write unit 222.

[0025] The NIC switch unit 224 relays packets output from the DMA read unit 221 or the IF 225 and outputs them to the DMA write unit 222 or the IF 225. The IF 225 receives packets from an external communication network and outputs the received packets to the NIC switch unit 224. The IF 225 also transmits packets output from the NIC switch unit 224 to the external communication network.

[0026] Fig. 3 shows an example of information stored in the memory 212 of Fig. 2. The transmission area 302 includes transmission data DATA0 to DATA2, and the transmission job table 301 includes identification information, virtual addresses, and sizes of each piece of transmission data included in the transmission area 302.

[0027] The identification information of DATA0 is ID0, the virtual address is VA0, and the size is SIZE0. The identification information of DATA1 is ID1, the virtual address is VA1, and the size is SIZE1. The identification information of DATA2 is ID2, the virtual address is VA2, and the size is SIZE2.

[0028] The receiving area 304 includes received data DATA0 to DATA2, and the received job table 303 includes identification information, virtual addresses, and sizes of each piece of received data included in the receiving area 304.

[0029] Fig. 4 shows an example of the configuration of the DMA read unit 221 in Fig. 2. The DMA read unit 221 in Fig. 4 includes a FIFO (First-In First-Out) circuit 411, a conversion circuit 412, a generation circuit 413, a FIFO circuit 414, registers 415-0 to 415-3, and registers 416-0 to 416-3. These components are hardware.

[0030] Register 415-i stores an address translation table for VMi, and register 416-i stores statistical information for VMi. The address translation table includes the correspondence between the virtual address and the physical address of each piece of data in memory 212. The statistical information includes logs such as the number of packets sent and the size of the transferred data.

[0031] When a source VMi transmits a packet to another VMi within the physical server 201 or to an external communication network, the CPU 211 stores the transmission data of the source VMi in the transmission area 302 in the memory 212. Then, the CPU 211 stores the identification information, virtual address, and size of the transmission data in the transmission job table 301.

[0032] The DMA read unit 221 checks whether a valid entry exists in the transmission job table 301, and if a valid entry exists, reads out the information of that entry and stores it in the FIFO circuit 411. Information ViJk (i=0 to 2, k=0 to 2) in the FIFO circuit 411 represents job k of VMi, and includes the identification information, virtual address, and size read out from the transmission job table 301.

[0033] The conversion circuit 412 sequentially reads ViJk from the FIFO circuit 411 from the beginning, and converts the virtual address included in ViJk into a physical address using the address conversion table for VMi in the register 415-i. Then, the conversion circuit 412 outputs the identification information, physical address, and size to the generation circuit 413.

[0034] The generation circuit 413 generates a read request using the physical address and size output from the conversion circuit 412, and issues it to the memory 212. Then, the generation circuit 413 stores additional information such as identification information of VMi and identification information of the transmission data in the FIFO circuit 414. For example, the number i is used as the identification information of VMi.

[0035] The memory 212 retrieves the transmission data indicated by the read request from the transmission area 302 and transfers it as read data to the DMA read unit 221. The DMA read unit 221 adds additional information to the transferred read data to generate a packet, and outputs it to the NIC switch unit 224. Then, the DMA read unit 221 updates the statistical information of VMi in the register 416-i.

[0036] Fig. 5 shows an example configuration of the DMA write unit 222 in Fig. 2. The DMA write unit 222 in Fig. 5 includes FIFO circuits 511-0 to 511-3, a conversion circuit 512, a generation circuit 513, registers 514-0 to 514-3, registers 515-0 to 515-3, a selector 516, and a selector 517. These components are hardware.

[0037] The register 514-i stores an address translation table for VMi, and the register 515-i stores statistical information for VMi, including logs of the number of received packets, transfer data size, and the like.

[0038] When the destination VM i receives a packet from another VM i in the physical server 201 or from an external communication network, the CPU 211 stores the identification information, virtual address, and size of the received data in the received job table 303 in the memory 212.

[0039] A FIFO circuit 511-i is provided for each VMi. The DMA write unit 222 checks whether a valid entry exists in the received job table 303. If a valid entry exists, the DMA write unit 222 reads the information of that entry and stores it in the FIFO circuit 511-i of the corresponding VMi via the selector 516.

[0040] When a packet is output from the NIC switch unit 224, the conversion circuit 512 reads the ViJk in the FIFO circuit 511-i of the corresponding VMi sequentially from the beginning via the selector 517. Then, the conversion circuit 512 converts the virtual address included in the ViJk into a physical address using the address conversion table for VMi in the register 514-i, and outputs the identification information, the physical address, and the size to the generation circuit 513.

[0041] When a packet corresponding to ViJk is output from the NIC switch unit 224, the generation circuit 513 generates a write request using the transmission data included in the packet and the physical address and size output from the conversion circuit 512, and issues the write request to the memory 212. The write request includes the transmission data as write data. The generation circuit 513 then updates the statistical information of VMi in the register 515-i.

[0042] The memory 212 writes the write data included in the write request as received data in the receiving area 304. Then, the CPU 211 acquires the received data written in the receiving area 304.

[0043] In the NIC 213 of FIG. 2, the throughput varies depending on the size of the read data transferred from the memory 212 to the DMA read unit 221, so the throughput may not reach the maximum value.

[0044] 6 shows an example of a first data transfer sequence when the DMA read unit 221 of FIG. 4 is used. FIG. 6(a) shows an example of a data transfer sequence that achieves maximum throughput. FIFO output represents the job output period in the FIFO circuit 411. In this example, a job is output from the FIFO circuit 411 to the conversion circuit 412 once every three cycles. Therefore, a job containing virtual address VA1 is output three cycles after a job containing virtual address VA0.

[0045] Address conversion represents the address conversion period in the conversion circuit 412. In this example, one address conversion takes three cycles. Therefore, VA0 is converted to physical address PA0 in the three cycle period after the job including VA0 is output, and VA1 is converted to physical address PA1 in the three cycle period after the job including VA1 is output.

[0046] The read requests represent the read request issuing period in the generation circuit 413. The read request Req0 including PA0 is issued in the cycle following the address translation of VA0, and the read request Req1 including PA1 is issued in the cycle following the address translation of VA1.

[0047] The read reply represents the period of time during which read data is received by the DMA read unit 221. In this example, one read reply takes four cycles. Therefore, immediately after reception of read data DT0 for Req0 is completed, reception of read data DT1 for Req1 begins.

[0048] In this case, since the time required for one read reply is longer than the time required for one read request to be issued, the data transfer throughput for transferring read data from memory 212 to DMA read unit 221 is 100%, thereby achieving maximum throughput.

[0049] Figure 6(b) shows an example of a data transfer sequence with low throughput. The periods for FIFO output, address translation, and read requests are the same as those in Figure 6(a). In this example, one read reply takes only one cycle. Therefore, after receiving DT0 for Req0, two cycles pass before receiving DT1 for Req1 begins.

[0050] In this case, the time required for one read reply is shorter than the time required for one read request to be issued, so the data transfer throughput for transferring read data from memory 212 to DMA read unit 221 is 33%, and therefore the maximum throughput cannot be achieved.

[0051] In order to improve the throughput in the data transfer of FIG. 6(b), it is effective to provide a plurality of circuits that operate in parallel within the DMA read unit 221.

[0052] 7 shows an example of the configuration of the DMA read unit 221, which includes three circuits. The DMA read unit 221 in FIG.

[0053] 4, the FIFO circuit 411, the conversion circuit 412, the generation circuit 413, and the FIFO circuit 414, and the circuits 701-1 to 701-3 operate in parallel. The selector 702 sequentially selects the read requests output from the circuits 701-j and issues them to the memory 212.

[0054] Fig. 8 shows an example of a second data transfer sequence when using the DMA read unit 221 of Fig. 7. FIFO output j represents the job output period in the FIFO circuit 411 in the circuit 701-j.

[0055] In this example, in circuit 701-1, a job containing virtual address VA1 is output three cycles after the job containing virtual address VA0. In circuit 701-2, a job containing virtual address VA2 is output in the cycle following the job containing VA0, and a job containing virtual address VA3 is output in the cycle following the job containing VA1.

[0056] In the circuit 701-3, a job including virtual address VA4 is output in the cycle following the job including VA2, and a job including virtual address VA5 is output in the cycle following the job including VA3.

[0057] Address conversion j represents the address conversion period in the conversion circuit 412 in circuit 701-j. In this example, in circuit 701-1, VA0 is converted to physical address PA0 during a period of three cycles after a job including VA0 is output, and VA1 is converted to physical address PA1 during a period of three cycles after a job including VA1 is output.

[0058] In circuit 701-2, VA2 is converted to physical address PA2 during the three cycle period after a job including VA2 is output, and VA3 is converted to physical address PA3 during the three cycle period after a job including VA3 is output. In circuit 701-3, VA4 is converted to physical address PA4 during the three cycle period after a job including VA4 is output, and VA5 is converted to physical address PA5 during the three cycle period after a job including VA5 is output.

[0059] The read requests represent a read request issuance period in the selector 702. In this example, the read requests are issued consecutively in the order of read request Req0, read request Req2, read request Req4, read request Req1, read request Req3, and read request Req5. Req0 includes PA0, Req2 includes PA2, and Req4 includes PA4. Req1 includes PA1, Req3 includes PA3, and Req5 includes PA5.

[0060] Req0 is issued in the cycle following the address translation of VA0, Req2 is issued in the cycle following the address translation of VA2, Req4 is issued in the cycle following the address translation of VA4, Req1 is issued in the cycle following the address translation of VA1, Req3 is issued in the cycle following the address translation of VA3, and Req5 is issued in the cycle following the address translation of VA5.

[0061] The read reply indicates a period during which the circuits 701-1 to 701-3 receive read data. In this example, the read data is received consecutively in the order of read data DT0, read data DT2, read data DT4, read data DT1, read data DT3, and read data DT5.

[0062] In this case, the time required for one read reply is the same as the time required for one read request to be issued, so the data transfer throughput for transferring read data from memory 212 to DMA read unit 221 is 100%. Therefore, the maximum throughput is obtained, as in the case of FIG. 6(a).

[0063] 9 shows an example of the configuration of the DMA read unit 221 including two circuits. The DMA read unit 221 in FIG.

[0064] 4, the FIFO circuit 411, the conversion circuit 412, the generation circuit 413, and the FIFO circuit 414, and the circuits 901-1 and 901-2 operate in parallel. The selector 902 sequentially selects the read requests output from the circuits 901-j and issues them to the memory 212.

[0065] 2, when VM0 to VM3 are running in the physical server 201, the VMs that each circuit 901-j is responsible for are fixed, and therefore the circuit 901-j to which packet processing is assigned for each VMi is fixed. For example, packet processing for VM0 and VM1 is assigned to the circuit 901-1, and packet processing for VM2 and VM3 is assigned to the circuit 901-2.

[0066] In this case, the circuit 901-1 performs address conversion by referring to the address conversion table for VM0 in the register 415-0 and the address conversion table for VM1 in the register 415-1. Then, the circuit 901-1 updates the statistical information for VM0 in the register 416-0 and the statistical information for VM1 in the register 416-1.

[0067] On the other hand, the circuit 901-2 performs address conversion by referring to the address conversion table for VM2 in the register 415-2 and the address conversion table for VM3 in the register 415-3. Then, the circuit 901-2 updates the statistical information for VM2 in the register 416-2 and the statistical information for VM3 in the register 416-3.

[0068] However, the number of VMs running in the physical server 201 dynamically increases or decreases during operation of the physical server 201. Because the CPU 211 does not recognize the circuit configuration of the DMA read unit 221, it is difficult to select a circuit 901-j that is responsible for each VM so that the circuits 901-1 and 901-2 are used efficiently.

[0069] Even if it were possible to select a circuit 901-j to handle a newly added VM by controlling the identification information of that VM, if a VM that has completed processing is deleted, the packet processing of the circuit 901-j that was handling that VM will simply be reduced.

[0070] Fig. 10 shows an example of the throughput of a read request in the DMA read unit 221 of Fig. 9. In this example, the maximum value of the throughput of a read request output from each circuit 901-j is 80% of the maximum value of the throughput of a read request output from the selector 902.

[0071] First, when only VM0 of VM0 to VM3 is operating and the circuit 901-1 is in charge of VM0, the throughput in the circuit 901-1 is 80% and the throughput in the circuit 901-2 is 0%. In this case, the throughput in the selector 902 is 80%.

[0072] Next, when VM2 is added, the circuit 901-1 is responsible for VM0, and the circuit 901-2 is responsible for VM2, the throughput in the circuit 901-1 is 80% and the throughput in the circuit 901-2 is 80%. In this case, the throughput in the selector 902 is 100%, and the maximum throughput is obtained.

[0073] Next, when VM1 is added, the circuit 901-1 is responsible for VM0 and VM1, and the circuit 901-2 is responsible for VM2, the throughput in the circuit 901-1 is 80% and the throughput in the circuit 901-2 is 80%. In this case, the throughput in the selector 902 is 100%, and the maximum throughput is obtained.

[0074] Next, when VM2 is deleted and the circuit 901-1 is in charge of VM0 and VM1, the throughput in the circuit 901-1 is 80% and the throughput in the circuit 901-2 is 0%. In this case, the throughput in the selector 902 is 80%, and the maximum throughput cannot be obtained.

[0075] In this way, even if multiple circuits are provided within the DMA read unit 221, if there is a bias in the number of VMs handled by each circuit, some circuits may not operate, and maximum throughput may not be achieved.

[0076] Fig. 11 shows an example of the configuration of a packet processing device of a comparative example. The packet processing device of Fig. 11 includes a NIC processing unit 1101 and a NIC control unit 1102. The NIC processing unit 1101 corresponds to the DMA read unit 221 or the DMA write unit 222 of Fig. 2, and the NIC control unit 1102 corresponds to the NIC control unit 223 of Fig. 2.

[0077] The NIC processing unit 1101 includes a register 1111, a selector 1112, a circuit 1113-1, a circuit 1113-2, a priority control unit 1114, a selector 1115, registers a0 to a3, registers b0 to b3, and registers c0 to c3. These components are hardware.

[0078] The NIC control unit 1102 includes a register 1121. The register 1121 is a 4-bit register, and bit i (i=0 to 3) indicates the state of VMi. A logical value "1" indicates that VMi is in an active state, and a logical value "0" indicates that VMi is in an inactive state. The active state is a state in which VMi is operating, and the inactive state is a state in which VMi is stopped. The register 1121 is updated by the CPU 211 and referenced by the circuit 1113-j (j=1, 2).

[0079] Register ai stores setting information related to VMi. The setting information is set by the CPU 211. When the NIC processing unit 1101 is the DMA read unit 221, register ai corresponds to register 415-i. When the NIC processing unit 1101 is the DMA write unit 222, register ai corresponds to register 514-i. Register ai is updated by the CPU 211 and is referenced by the CPU 211 or circuit 1113-j.

[0080] Register bi stores information about packets of VMi. When the NIC processing unit 1101 is the DMA read unit 221, register bi corresponds to register 416-i. When the NIC processing unit 1101 is the DMA write unit 222, register bi corresponds to register 515-i. Register bi is updated by circuit 1113-j and referenced by the CPU 211.

[0081] Register ci stores control information for a job of VMi. The control information for a job may be a control counter that indicates information in either FIFO circuit 411 or FIFO circuit 511-i. Register ci is updated by circuit 1113-j and referenced by circuit 1113-j.

[0082] In this example, register a0, register a1, register b0, register b1, register c0, and register c1 are assigned to circuit 1113-1, while register a2, register a3, register b2, register b3, register c2, and register c3 are assigned to circuit 1113-2.

[0083] The register 1111 stores a destination table. The destination table includes a correspondence between VMi and a circuit 1113-j. In this example, VM0 and VM1 are associated with the circuit 1113-1, and VM2 and VM3 are associated with the circuit 1113-2.

[0084] 4. The circuit 1113-j refers to the register 1121 in the NIC control unit 1102 and performs packet processing for the VMi it is responsible for among the VMi in the active state. At this time, the circuit 1113-j performs packet processing using the control information in the register ci.

[0085] The circuit 1113-j performs address conversion by referring to the address conversion table of VMi in the register ai, generates a read request, and outputs it to the selector 1115. The selector 1115 selects the read requests output from each circuit 1113-j in order according to the instructions of the priority control unit 1114, and issues them to the memory 212.

[0086] The selector 1112 receives the read data transferred from the memory 212 in response to the read request. Then, the selector 1112 selects, as a destination, the circuit 1113-j associated with VMi indicated by the read data from among the circuits 1113-1 and 1113-2 in accordance with the destination table in the register 1111, and outputs the read data to the selected destination.

[0087] The circuit 1113-j generates a packet using the read data output from the selector 1112, and outputs it to the NIC switch unit 224. Then, the circuit 1113-j updates the statistical information of VMi in the register bi.

[0088] 5, the FIFO circuit 511-i, the conversion circuit 512, the generation circuit 513, the selector 516, and the selector 517. The circuit 1113-j refers to the register 1121 in the NIC control unit 1102 and performs packet processing for the VMi it is responsible for among the VMi in the active state. At this time, the circuit 1113-j performs packet processing using the control information in the register ci.

[0089] The selector 1112 receives a packet output from the NIC switch unit 224. Then, the selector 1112 selects the circuit 1113-j associated with VMi as the destination from among the circuits 1113-1 and 1113-2 in accordance with the destination table in the register 1111, and outputs the packet to the selected destination.

[0090] The circuit 1113 - j performs address translation by referring to the address translation table of VM i in the register ai, generates a write request using the packet output from the selector 1112 , and outputs it to the selector 1115 .

[0091] The selector 1115 selects the write requests output from each circuit 1113-j in order according to the instructions of the priority control unit 1114, and issues them to the memory 212. Then, the circuit 1113-j updates the statistical information of VMi in the register bi.

[0092] 11, the registers ai, bi, and ci assigned to each circuit 1113-j are fixed, and therefore the circuit 1113-j to which packet processing is assigned for each VMi is fixed. Therefore, as in the case of the DMA read unit 221 in Fig. 9, if there is a bias in the number of VMi handled by each circuit 1113-j, maximum throughput may not be obtained.

[0093] 12 shows an example of the functional configuration of a packet processing device according to an embodiment. Packet processing device 1201 in FIG. 12 includes packet processing units 1211-1 to 1211-M (M is an integer of 2 or more), storage units 1212-1 to 1212-N (N is an integer of 2 or more), a switch unit 1213, and a control unit 1214.

[0094] Packet processing units 1211-1 to 1211-M execute multiple packet processes in parallel. Each storage unit 1212-i (i=1 to N) stores information associated with one of N communication entities. Switch unit 1213 switches between storage units 1212-1 to 1212-N.

[0095] Fig. 13 is a flowchart showing an example of packet processing performed by the packet processing device 1201 of Fig. 12. First, the control unit 1214 assigns packet processing of a specific one of the N communication entities to a specific packet processing unit 1211-j (j=1 to M) among the packet processing units 1211-1 to 1211-M (step 1301).

[0096] Then, the control unit 1214 controls the switch unit 1213 to cause a specific packet processing unit 1211-j to access information stored in each memory unit 1212-i that is associated with a specific communication entity (step 1302).

[0097] According to the packet processing device 1201 of FIG. 12, it is possible to improve the performance of parallel processing in packet processing for a plurality of communication entities.

[0098] Fig. 14 shows an example of the configuration of a first packet processing device corresponding to the specific example of packet processing device 1201 in Fig. 12. The packet processing device in Fig. 14 includes a NIC processing unit 1401 and a NIC control unit 1402. The NIC processing unit 1401 corresponds to the DMA read unit 221 or the DMA write unit 222 in Fig. 2, and the NIC control unit 1402 corresponds to the NIC control unit 223 in Fig. 2. In this example, N VMs, VM0 to VMN-1, are running in physical server 201.

[0099] The NIC processing unit 1401 includes a register 1411, a selector 1412, crossbar switches 1413-1 to 1413-3, circuits 1414-1 to 1414-M, a priority control unit 1415, and a selector 1416. The NIC processing unit 1401 further includes registers a0 to aN-1, registers b0 to bN-1, and registers c0 to cN-1. These components are hardware.

[0100] The circuit 1414-j (j=1 to M) corresponds to the packet processing unit 1211-j in Fig. 12, and the registers ai, bi, and ci (i=0 to N-1) correspond to the storage unit 1212-(i+1) in Fig. 12. The crossbar switches 1413-1 to 1413-3 correspond to the switch unit 1213 in Fig. 12.

[0101] The NIC control unit 1402 includes a register 1421, a register 1422, and a control unit 1423. These components are hardware. The control unit 1423 is a logic circuit such as an FPGA or an ASIC (Application Specific Integrated Circuit). The control unit 1423 corresponds to the control unit 1214 in FIG. 12.

[0102] Register 1421 and register 1422 are N-bit registers, and bit i indicates the state of VMi. VMi corresponds to a communication subject. A logical value "1" indicates that VMi is in an active state, and a logical value "0" indicates that VMi is in an inactive state.

[0103] The register 1421 is updated by the CPU 211 and referenced by the control unit 1423. The register 1422 is updated by the control unit 1423 and referenced by the control unit 1423 or the circuit 1414-j. The control unit 1423 controls the operation of the NIC processing unit 1401 while referring to the register 1421.

[0104] Register 1421 is an example of a first state storage unit, and the bit values ​​stored in register 1421 are an example of first state information indicating the state of each of the multiple communication entities. Register 1422 is an example of a second state storage unit, and the bit values ​​stored in register 1422 are an example of second state information indicating the state of each of the multiple communication entities.

[0105] Register ai stores setting information related to VMi. The setting information is set by the CPU 211. When the NIC processing unit 1401 is the DMA read unit 221, register ai corresponds to register 415-i. When the NIC processing unit 1401 is the DMA write unit 222, register ai corresponds to register 514-i. Register ai is updated by the CPU 211 and is referenced by the CPU 211 or circuit 1414-j.

[0106] Register bi stores information about packets of VMi. When the NIC processing unit 1401 is the DMA read unit 221, register bi corresponds to register 416-i. When the NIC processing unit 1401 is the DMA write unit 222, register bi corresponds to register 515-i. Register bi is updated by circuit 1414-j and referenced by the CPU 211.

[0107] Register ci stores control information for a job of VMi. The control information for a job may be a control counter that indicates information in either FIFO circuit 411 or FIFO circuit 511-i. Register ci is updated by circuit 1414-j and referenced by circuit 1414-j.

[0108] The register 1411 stores a destination table, which includes the correspondence between VMi and the circuit 1414-j.

[0109] The crossbar switch 1413-1 switches the connections between the circuits 1414-1 to 1414-M and the registers a0 to aN-1. The crossbar switch 1413-2 switches the connections between the circuits 1414-1 to 1414-M and the registers b0 to bN-1. The crossbar switch 1413-3 switches the connections between the circuits 1414-1 to 1414-M and the registers c0 to cN-1.

[0110] When assigning a specific VMi to a circuit 1414-j, the control unit 1423 selects an allocation target circuit 1414-j that will handle the VMi, and assigns packet processing for the specific VMi to the selected circuit 1414-j. The specific VMi corresponds to a specific communication entity, and the allocation target circuit 1414-j corresponds to a specific packet processing unit 1211-j.

[0111] As the circuit 1414-j to be allocated, for example, a circuit 1414-j to which no packet processing for any VMi is allocated, or a circuit 1414-j to which packet processing for a smaller number of VMi is allocated than other circuits 1414-j, is selected. This makes it possible to prevent a further increase in the load on the circuit 1414-j to which packet processing for a large number of VMi is allocated.

[0112] Next, the control unit 1423 outputs update information indicating that the specific VMi is associated with the circuit 1414-j to be allocated to the register 1411. The register 1411 adds information associating the specific VMi with the circuit 1414-j to be allocated to the destination table in accordance with the update information.

[0113] Then, the control unit 1423 controls the crossbar switch 1413-1 so that the register ai that stores the information of a specific VMi is connected to the circuit 1414-j that is the allocation target.

[0114] Furthermore, the control unit 1423 controls the crossbar switch 1413-2 so that a register bi that stores information about a specific VMi is connected to the circuit 1414-j to be assigned. Furthermore, the control unit 1423 controls the crossbar switch 1413-3 so that a register ci that stores information about a specific VMi is connected to the circuit 1414-j to be assigned.

[0115] This allows the circuit 1414-j to be allocated to access the information of the particular VMi stored in the registers ai, bi, and ci.

[0116] 4. When the NIC processing unit 1401 is the DMA read unit 221, the circuit 1414-j includes the FIFO circuit 411, the conversion circuit 412, the generation circuit 413, and the FIFO circuit 414. The circuit 1414-j performs packet processing to transmit packets whose source is VMi.

[0117] The circuit 1414-j performs packet processing for the VMi it is responsible for among the VMi in the active state, by referring to the register 1422 in the NIC control unit 1402. At this time, the circuit 1414-j performs packet processing using control information in the register ci connected via the crossbar switch 1413-3.

[0118] The circuit 1414-j refers to the address translation table of VMi in the register ai connected via the crossbar switch 1413-1, performs address translation, generates a read request, and outputs it to the selector 1416. The selector 1416 selects a read request output from any of the circuits 1414-j in accordance with an instruction from the priority control unit 1415, and issues the read request to the memory 212.

[0119] The selector 1412 receives the read data transferred from the memory 212 in response to the read request. Then, the selector 1412 selects, as a destination, one of the circuits 1414-1 to 1414-M, the circuit 1414-j associated with the VMi indicated by the read data, in accordance with the destination table in the register 1411, and outputs the read data to the selected destination.

[0120] The circuit 1414-j generates a packet using the read data output from the selector 1412 and outputs it to the NIC switch unit 224. Then, the circuit 1414-j updates the statistical information of VMi in the register bi connected via the crossbar switch 1413-2.

[0121] 5, the FIFO circuit 511-i, the conversion circuit 512, the generation circuit 513, the selector 516, and the selector 517. The circuit 1414-j performs packet processing to receive packets destined for VMi.

[0122] The circuit 1414-j performs packet processing for the VMi it is responsible for among the VMi in the active state, by referring to the register 1422 in the NIC control unit 1402. At this time, the circuit 1414-j performs packet processing using control information in the register ci connected via the crossbar switch 1413-3.

[0123] The selector 1412 receives a packet output from the NIC switch unit 224. Then, the selector 1412 selects, as a destination, one of the circuits 1414-1 to 1414-M, the circuit 1414-j associated with the VMi indicated by the packet, in accordance with the destination table in the register 1411, and outputs the packet to the selected destination.

[0124] The circuit 1414-j performs address translation by referring to the address translation table of VMi in the register ai connected via the crossbar switch 1413-1. Then, the circuit 1414-j generates a write request using the packet output from the selector 1412 and outputs it to the selector 1416.

[0125] The selector 1416 selects a write request output from one of the circuits 1414-j in accordance with an instruction from the priority control unit 1415, and issues it to the memory 212. Then, the circuit 1414-j updates the statistical information of VMi in the register bi connected via the crossbar switch 1413-2.

[0126] Fig. 15 shows a configuration example of the first packet processing device when N = 4 and M = 2. NIC processing unit 1401 in Fig. 15 includes a register 1411, a selector 1412, crossbar switches 1413-1 to 1413-3, circuits 1414-1 and 1414-2, a priority control unit 1415, and a selector 1416. NIC processing unit 1401 further includes register a0 to register a3, register b0 to register b3, and register c0 to register c3.

[0127] The registers 1421 and 1422 in the NIC control unit 1402 are 4-bit registers. The operations of the NIC processing unit 1401 and the NIC control unit 1402 in FIG.

[0128] Fig. 16 shows a first operation example of the packet processing device of Fig. 15. In state S1, register a0 and register a1 are connected to circuit 1414-1, and register a2 and register a3 are connected to circuit 1414-2.

[0129] VM0 to VM3 are in an inactive state, and the bit values ​​of the registers 1421 and 1422 are "0."

[0130] In state S2, VM0 changes from the inactive state to the active state, and bit 0 of register 1421 changes from "0" to "1." Therefore, control unit 1423 inhibits access from CPU 211 to registers a0 to a3, and allocates packet processing for VM0 to circuit 1414-1.

[0131] In state S3, the control unit 1423 instructs the crossbar switch 1413-1 to connect the register a0 to the circuit 1414-1. In accordance with the instruction from the control unit 1423, the crossbar switch 1413-1 maintains the connection between the register a0 and the circuit 1414-1.

[0132] In state S4, the control unit 1423 copies the bit values ​​of the register 1421 to the register 1422 and releases the restriction on access to the registers a0 to a3. As a result, the circuit 1414-1 starts packet processing for VM0 by referring to the register 1422 and accesses the register a0.

[0133] During a period 1601, accesses from the CPU 211 to the registers a0 to a3 are suspended, and the suspended accesses are executed after the access suspension is released. By suspending accesses to the registers a0 to a3 when an instruction is given to the crossbar switch 1413-1, each circuit 1414-j is prevented from referring to an incorrect address translation table.

[0134] Fig. 17 shows a second operation example of the packet processing device of Fig. 15. In state S11, register a0 and register a1 are connected to circuit 1414-1, and register a2 and register a3 are connected to circuit 1414-2.

[0135] VM0 is in the active state, and VM1 to VM3 are in the inactive state. Therefore, bit 0 of register 1421 and register 1422 is "1", and bits 1 to 3 are "0". Circuit 1414-1 refers to register 1422 and performs packet processing for VM0.

[0136] In state S12, VM1 changes from the inactive state to the active state, and bit 1 of register 1421 changes from “0” to “1.” Therefore, control unit 1423 inhibits access from CPU 211 to registers a0 to a3, and assigns packet processing of VM1 to circuit 1414-2, which is not in charge of any VMi.

[0137] In state S13, the control unit 1423 instructs the crossbar switch 1413-1 to connect the register a1 to the circuit 1414-2. In accordance with the instruction from the control unit 1423, the crossbar switch 1413-1 changes the connection destination of the register a1 to the circuit 1414-2.

[0138] In state S14, the control unit 1423 copies the bit values ​​of the register 1421 to the register 1422 and releases the restriction on access to the registers a0 to a3, whereby the circuit 1414-2 starts packet processing for VM1 by referring to the register 1422 and accesses the register a1.

[0139] During a period 1701, accesses from the CPU 211 to the registers a0 to a3 are suspended, and after the access restriction is lifted, the suspended accesses are executed.

[0140] According to the operation of Figure 17, by assigning packet processing of VM1 that has changed to the active state to circuit 1414-2 that is not handled by any VMi, the number of VMi handled by circuit 1414-1 and circuit 1414-2 can be leveled.

[0141] Fig. 18 shows a third operation example of the packet processing device of Fig. 15. In state S21, register a0 and register a1 are connected to circuit 1414-1, and register a2 and register a3 are connected to circuit 1414-2.

[0142] VM0 to VM2 are in the active state, and VM3 is in the inactive state. Therefore, bits 0 to 2 of register 1421 and register 1422 are "1", and bit 3 is "0". VM1 is an example of a first communication subject, and VM2 is an example of a second communication subject.

[0143] The circuit 1414-1 processes packets for VM0 and VM1 by referring to the register 1422. The circuit 1414-2 processes packets for VM2 by referring to the register 1422.

[0144] In state S22, the processing of VM2 ends, and the processing of packets by circuit 1414-2 for VM2 stops.

[0145] In state S23, VM2 changes from the active state to the inactive state, and bit 2 of register 1421 changes from "1" to "0." In this case, circuit 1414-1 is responsible for two VMs, while circuit 1414-2 is no longer responsible for any VMs, resulting in a bias in the number of VMs handled by circuit 1414-1 and circuit 1414-2. Therefore, control unit 1423 inhibits access from CPU 211 to registers a0 to a3, and changes the responsibility of VM1 from circuit 1414-1 to circuit 1414-2.

[0146] In state S24, circuit 1414-1 stops processing packets for VM1.

[0147] In state S25, the control unit 1423 instructs the crossbar switch 1413-1 to connect the register a1 to the circuit 1414-2. In accordance with the instruction from the control unit 1423, the crossbar switch 1413-1 changes the connection destination of the register a1 to the circuit 1414-2.

[0148] In state S26, the control unit 1423 copies the bit values ​​of the register 1421 to the register 1422 and releases the restriction on access to the registers a0 to a3, whereby the circuit 1414-2 starts packet processing for VM1 by referring to the register 1422 and accesses the register a1.

[0149] According to the operation of FIG. 18, the imbalance in the number of VMi's handled by the circuit 1414-1 and the circuit 1414-2 can be eliminated, and the number of VMi's handled by each circuit 1414-j can be leveled.

[0150] Fig. 19 shows a first operation example of the circuit 1414-1 in state S24 of Fig. 18. In the operation example of Fig. 19, the NIC processing unit 1401 corresponds to the DMA read unit 221, and the circuit 1414-1 performs transmission processing of packets whose source is the VM it is responsible for.

[0151] In state S31, the circuit 1414-1 generates a read request Req0 for VM0 and generates a packet with VM0 as the source using the read data transferred from the memory 212. The circuit 1414-1 also generates a read request Req1 for VM1 and generates a packet with VM1 as the source using the read data transferred from the memory 212.

[0152] In state S32, the circuit 1414-1 stops generating the read request Req1 for VM1.

[0153] In state S33, the circuit 1414-1 finishes receiving the read data transferred in response to the read request Req1 from VM 1. This causes the packet processing of VM 1 to stop.

[0154] Thereafter, in state S26 of FIG. 18, when the bit value of register 1421 is copied to register 1422, circuit 1414-2 starts the transmission process of a packet whose source is VM1.

[0155] Fig. 20 shows a second operation example of the circuit 1414-1 in state S24 of Fig. 18. In the operation example of Fig. 20, the NIC processing unit 1401 corresponds to the DMA write unit 222, and the circuit 1414-1 performs reception processing of packets whose destination is the VM it is responsible for.

[0156] In state S41, the circuit 1414-1 receives a packet addressed to VM0 and generates a write request for VM0, and receives a packet addressed to VM1 and generates a write request for VM1. G0a and G0b are write requests for VM0, and G1a, G1b, and G1c are write requests for VM1.

[0157] In state S42, the circuit 1414-1 outputs G0a to the selector 1416 and stops receiving packets addressed to VM1. The circuit 1414-2 receives packets addressed to VM1, generates a write request G1d for VM1, and suspends the output of G1d. This stops packet processing for VM1.

[0158] In state S43, the circuit 1414-1 outputs G1b, G0b, and G1c to the selector 1416, receives a packet addressed to VM0, and generates a write request for VM0. G0d and G0e are newly generated write requests for VM0. The circuit 1414-2 receives a packet addressed to VM1 and generates a write request for VM1. G1e and G1f are newly generated write requests for VM1.

[0159] Thereafter, in state S26 of FIG. 18, when the bit value of register 1421 is copied to register 1422, circuit 1414-2 starts outputting G1d, G1e, and G1f.

[0160] In the operation examples of FIGS. 16 to 20, the control method for the crossbar switch 1413-1 has been described, but the crossbar switches 1413-2 and 1413-3 are also controlled in the same manner as the crossbar switch 1413-1.

[0161] 14 and 15, registers ai, bi, and ci are dynamically allocated to each circuit 1414-j, so that the circuit 1414-j to which packet processing is assigned can be changed for each VMi. Therefore, the number of VMi handled by each circuit 1414-j can be leveled, improving the performance of parallel processing.

[0162] 18, it is assumed that the maximum throughput of the read or write requests output from each circuit 1414-j is 80%. In this case, in state S23, by changing the responsibility of VM1 from circuit 1414-1 to circuit 1414-2, the throughput of the selector 1416 increases from 80% to 100%.

[0163] Next, the reason for providing two registers in the NIC control unit 1402 to control the NIC processing unit 1401 will be explained.

[0164] Fig. 21 shows a fourth operation example of the packet processing device of Fig. 15. In the operation example of Fig. 21, only register 1421 is provided in NIC control unit 1402, and register 1422 is not provided. Therefore, circuit 1414-1 and circuit 1414-2 refer to register 1421 and perform packet processing for VMi in charge.

[0165] In state S51, packet processing for VM0 and VM1 is assigned to circuit 1414-1, and packet processing for VM2 and VM3 is assigned to circuit 1414-2. Registers a0 and a1 are connected to circuit 1414-1, and registers a2 and a3 are connected to circuit 1414-2.

[0166] VM0 is in the active state, and VM1 to VM3 are in the inactive state. Therefore, bit 0 of register 1421 is “1”, and bits 1 to 3 are “0”. Circuit 1414-1 refers to register 1421 and processes packets for VM0.

[0167] In state S52, VM1 changes from the inactive state to the active state, and bit 1 of register 1421 changes from "0" to "1." Therefore, control unit 1423 inhibits access from CPU 211 to registers a0 to a3, and assigns packet processing for VM1 to circuit 1414-2, which is not in charge of any VM. However, circuit 1414-1 detects that bit 1 of register 1421 has changed from "0" to "1," and starts packet processing for VM1.

[0168] In state S53, the control unit 1423 instructs the crossbar switch 1413-1 to connect the register a1 to the circuit 1414-2. In accordance with the instruction from the control unit 1423, the crossbar switch 1413-1 changes the connection destination of the register a1 to the circuit 1414-2.

[0169] Then, the control unit 1423 releases the inhibition of access to registers a0 to a3. The circuit 1414-2 starts packet processing for VM1 by referring to the register 1421, and accesses register a1. In this case, the same packet processing for VM1 is performed by both the circuit 1414-1 and the circuit 1414-2, and the order of the two packet processing for VM1 may be reversed.

[0170] 17, in state S12, bit 1 of register 1422 remains at "0," so that circuit 1414-1 does not start packet processing for VM1. Therefore, malfunction of circuit 1414-1 before switching of crossbar switch 1413-1 is prevented, and packet processing for VM1 can be performed in the correct order.

[0171] 14 determines a selection probability at which a request output from each circuit 1414-j is selected. Then, based on the determined selection probability, a selector 1416 selects one of the requests output from each of the circuits 1414-1 to 1414-M, and outputs the selected request to the memory 212.

[0172] When the NIC processing unit 1401 is the DMA read unit 221, the request output from the circuit 1414-j is a read request. When the NIC processing unit 1401 is the DMA write unit 222, the request output from the circuit 1414-j is a write request. The priority control unit 1415 is an example of a determination unit, and the selector 1416 is an example of a selection unit.

[0173] Fig. 22 shows an example of the first priority control performed by the priority control unit 1415 when M = 4. The priority control unit 1415 in Fig. 22 monitors the request j output from each circuit 1414-j, and when the request j is detected, determines that the circuit 1414-j is operating.

[0174] Then, the priority control unit 1415 determines the selection probability of each circuit 1414-j to be 1 / CN using the number CN of operating circuits 1414-j, and outputs a selection signal to the selector 1416 in accordance with the determined selection probability. The selector 1416 selects a request indicated by the selection signal from requests 1 to 4, and outputs the request to the memory 212.

[0175] For example, when CN=4, the selection probability of each circuit 1414-j is determined to be 25%. In this case, the priority control unit 1415 outputs to the selector 1416 a selection signal for selecting requests 1 to 4 in a round-robin manner.

[0176] Fig. 23 shows a first example of the operation of the selector 1416 based on the priority control of Fig. 22. In this example, the maximum throughput of requests output from each circuit 1414-j is 80% of the maximum throughput of requests output from the selector 1416.

[0177] When circuits 1414-1 to 1414-3 are operating, circuit 1414-1 is responsible for VM0 and VM1, circuit 1414-2 is responsible for VM2 and VM3, and circuit 1414-3 is responsible for VM4 and VM5, then CN=3. In this case, the selection probability of each of circuits 1414-1 to 1414-3 is 33%, the selection probability of circuit 1414-4 is 0%, and the selection probability of each of requests from VM0 to VM5 is 16.5%. Also, the output throughput of selector 1416 is 100%.

[0178] Next, when the processing of VM5 ends and the packet processing of VM5 by circuit 1414-3 stops, a bias occurs in the number of VMi handled by circuits 1414-1 to 1414-3. In this case, even if the handling is not changed, the output throughput of selector 1416 remains 100%, but the selection probability of VM4's request increases to 33%, while the selection probability of each of VM0 to VM3 is 16.5%. Therefore, a difference occurs in throughput between VM0 to VM3 and VM4.

[0179] On the other hand, if the VM3 is changed from the circuit 1414-2 to the circuit 1414-4 in order to equalize the number of VMi handled by each circuit 1414-j, the packet processing of VM3 is temporarily stopped due to the change in the handling. While the packet processing is stopped, the selection probability of the request of VM3 becomes 0%.

[0180] In order to prevent packet processing from being stopped due to such a change in responsibility, it is desirable that the control unit 1423 not change the responsibility as long as the output throughput of the selector 1416 is 100%, even if the number of VMi handled by each circuit 1414-j is uneven.

[0181] Fig. 24 shows an example of the second priority control performed by the priority control unit 1415 when M = 4. The priority control unit 1415 in Fig. 24 monitors VNj and requests j output from each circuit 1414-j. VNj represents the number of VMi handled by the circuit 1414-j.

[0182] The priority control unit 1415 determines the selection probability of each circuit 1414-j based on VNj output from each circuit 1414-j. The priority control unit 1415 determines the selection probability of the circuit 1414-j as the ratio of VNj to the sum of VN1 to VN4, for example, and outputs a selection signal to the selector 1416 in accordance with the determined selection probability. The selector 1416 selects a request indicated by the selection signal from requests 1 to 4 and outputs the selected request to the memory 212.

[0183] Fig. 25 shows a second example of operation of the selector 1416 based on the priority control of Fig. 24. In this example, the maximum throughput of requests output from each circuit 1414-j is 80% of the maximum throughput of requests output from the selector 1416.

[0184] If circuit 1414-1 is responsible for VM0 and VM1, circuit 1414-2 is responsible for VM2 and VM3, circuit 1414-3 is responsible for VM4 and VM5, and circuit 1414-4 is not responsible for any VMi, then VN1=VN2=VN3=2 and VN4=0.

[0185] In this case, the total number of VN1 to VN4 is 6, the selection probability of each of circuits 1414-1 to 1414-3 is 33%, the selection probability of circuit 1414-4 is 0%, and the selection probability of each of requests from VM0 to VM5 is 16.5%. Also, the output throughput of selector 1416 is 100%.

[0186] Next, when the processing of VM5 ends and the packet processing of VM5 by circuit 1414-3 stops, a bias occurs in the number of VMi handled by circuits 1414-1 to 1414-3. However, since the output throughput of selector 1416 can be maintained at 100% even without changing the handling, no change in the handling is made. Therefore, VN1=VN2=2, VN3=1, and VN4=0.

[0187] In this case, the total number of VN1 to VN4 is 5, the selection probability of each of the circuits 1414-1 and 1414-2 is 40%, the selection probability of the circuit 1414-3 is 20%, and the selection probability of the circuit 1414-4 is 0%. Also, the throughput of the output of the selector 1416 is 100%. Since the selection probability of each of the requests of VM0 to VM4 is 20%, there is no difference in throughput among VM0 to VM4.

[0188] Next, when the processing of VM3 is completed and the packet processing of VM3 by the circuit 1414-2 is stopped, VN1=2, VN2=VN3=1, and VN4=0.

[0189] In this case, the total number of VN1 to VN4 is 4, the selection probability of circuit 1414-1 is 50%, the selection probability of each of circuits 1414-2 and 1414-3 is 25%, and the selection probability of circuit 1414-4 is 0%. Also, the throughput of the output of selector 1416 is 100%. Since the selection probability of each of the requests of VM0, VM1, VM2, and VM4 is 25%, there is no difference in throughput among VM0, VM1, VM2, and VM4.

[0190] 24, when the processing of any VMi is completed and the number of active VMi decreases, it is possible to prevent the suspension of packet processing due to the change of responsibility. Also, by changing the selection probability according to the number of VMi handled by each circuit 1414-j, it is possible to equalize the throughput of requests from each VMi.

[0191] Fig. 26 is a flowchart showing an example of control processing performed by the packet processing device of Fig. 14. The control processing of Fig. 26 is performed when the control unit 1423 of the NIC control unit 1402 detects a change in the bit value of the register 1421. Hereinafter, a change in the bit value from "0" to "1" may be referred to as ON, and a change in the bit value from "1" to "0" may be referred to as OFF.

[0192] First, the control unit 1423 checks whether the bit value of the register 1421 has changed (step 2601). If the change in the bit value includes ON (step 2601, YES), the control unit 1423 sets the control variable p to 0 (step 2602) and checks whether the bit p has changed from "0" to "1" (step 2603).

[0193] If bit p changes from "0" to "1" (step 2603, YES), the control unit 1423 assigns packet processing of VMp to the circuit 1414-j that is responsible for the fewest number of VMi (step 2604). Then, the control unit 1423 outputs update information to the register 1411, indicating that VMp is associated with the circuit 1414-j to which packet processing has been assigned.

[0194] Furthermore, the control unit 1423 controls the crossbar switches 1413-1 to 1413-3 so that the registers ap, bp, and cp that store information on VMp are connected to the circuit 1414-j to be allocated.

[0195] Next, the control unit 1423 increments p by 1 (step 2605) and compares p with N-1 (step 2606). If p is equal to or less than N-1 (step 2606, NO), the control unit 1423 repeats the processes from step 2603 onwards. If bit p has not changed from "0" to "1" (step 2603, NO), the control unit 1423 performs the processes from step 2605 onwards.

[0196] If p is greater than N-1 (step 2606, YES), the control unit 1423 copies the bit value of the register 1421 to the register 1422. Then, the priority control unit 1415 of the NIC processing unit 1401 performs priority control for the request (step 2607). In step 2607, the priority control unit 1415 determines, for example, the ratio of VNj to the total sum of M VNj (j=1 to M) as the selection probability of the circuit 1414-j, and outputs a selection signal to the selector 1416 in accordance with the determined selection probability.

[0197] If the only change in bit value is OFF (step 2601, NO), the control unit 1423 compares the number of operating circuits with the number of parallel circuits (step 2608). The number of operating circuits represents the number of circuits 1414-j that operate when packet processing of VMi corresponding to OFF is stopped, and the number of parallel circuits represents the number of circuits 1414-j that can make the output throughput of the selector 1416 100%.

[0198] 27 shows an example of the correspondence between the maximum throughput of requests output from each circuit 1414-j and the number of parallel processes. When the maximum throughput is 100%, the number of parallel processes is 1, and when the maximum throughput is 99% to 50%, the number of parallel processes is 2. When the maximum throughput is 34% to 49%, the number of parallel processes is 3, and when the maximum throughput is 25% to 33%, the number of parallel processes is 4. When the maximum throughput is 20% to 24%, the number of parallel processes is 5.

[0199] For example, in the example of operation in FIG. 25, the maximum throughput of requests output from each circuit 1414-j is 80%, so 2 is used as the number of parallel processes in step 2608.

[0200] If the number of operating circuits is less than the number of parallel circuits (step 2608, NO), the control unit 1423 checks whether there is a circuit 1414-j that handles multiple VMi when packet processing of VMi corresponding to OFF is stopped (step 2609).

[0201] If there is a circuit 1414-j that is in charge of multiple VMi (step 2609, YES), the control unit 1423 changes the circuit in charge (step 2610).

[0202] In step 2610, the control unit 1423 selects one of the multiple VMs managed by the same circuit 1414-j as VMq, and assigns packet processing of VMq to the circuit 1414-j that is managed by the fewest VMs. Then, the control unit 1423 outputs update information indicating that VMq is associated with the circuit 1414-j to which packet processing is assigned, to the register 1411.

[0203] Furthermore, the control unit 1423 controls the crossbar switches 1413-1 to 1413-3 so that the register aq, register bq, and register cq that store information on VMq are connected to the circuit 1414-j to be allocated. Then, the control unit 1423 copies the bit value of the register 1421 to the register 1422, and the priority control unit 1415 performs the process of step 2607.

[0204] If the number of operating circuits is equal to or greater than the number of parallel circuits (step 2608, YES), or if there is no circuit 1414-j that is in charge of multiple VMi (step 2609, NO), the control unit 1423 copies the bit value of the register 1421 to the register 1422. Then, the priority control unit 1415 performs the process of step 2607.

[0205] If the change in bit value includes both ON and OFF (step 2601, YES), in step 2604, only the packet processing assignment associated with ON is performed, and the handling change associated with OFF is not performed.

[0206] 14, if the number N of VMi or the number of bits of registers ai, bi, and ci increases, the amount of hardware in crossbar switches 1413-1 to 1413-3 increases, making implementation difficult. In this case, the increase in the amount of hardware can be suppressed by changing the configuration of NIC processor 1401 to a configuration in which the information stored in registers ai, bi, and ci is swapped.

[0207] Fig. 28 shows an example of the configuration of a second packet processing device corresponding to the specific example of packet processing device 1201 in Fig. 12. The packet processing device in Fig. 28 includes a NIC processing unit 2801 and a NIC control unit 2802. The NIC processing unit 2801 corresponds to the DMA read unit 221 or the DMA write unit 222 in Fig. 2, and the NIC control unit 2802 corresponds to the NIC control unit 223 in Fig. 2. In this example, four VMs, VM0 to VM3, are running in physical server 201.

[0208] The NIC processing unit 2801 includes a register 1411, a selector 1412, a circuit 1414-1, a circuit 1414-2, a priority control unit 1415, a selector 1416, a conversion unit 2811, a conversion unit 2812, a conversion unit 2813, and a crossbar switch 2814. The NIC processing unit 2801 further includes registers a0 to aN-1, registers b0 to bN-1, and registers c0 to cN-1. These components are hardware.

[0209] The circuit 1414-j (j=1, 2) corresponds to the packet processing unit 1211-j in Fig. 12, and the register ai, register bi, and register ci (i=0 to 3) correspond to the storage unit 1212-(i+1) in Fig. 12. The crossbar switch 2814 corresponds to the switch unit 1213 in Fig. 12.

[0210] The NIC control unit 2802 includes a register 1421, a register 1422, and a control unit 2821. These components are hardware. The control unit 2821 is a logic circuit such as an FPGA or ASIC. The control unit 2821 corresponds to the control unit 1214 in FIG. 12.

[0211] The register 1421 is updated by the CPU 211 and referenced by the control unit 2821. The register 1422 is updated by the control unit 2821 and referenced by the control unit 2821 or the circuit 1414-j. The control unit 2821 controls the operation of the NIC processing unit 2801 while referring to the register 1421.

[0212] Register a0, register a1, register b0, register b1, register c0, and register c1 are connected to circuit 1414-1, and register a2, register a3, register b2, register b3, register c2, and register c3 are connected to circuit 1414-2.

[0213] Each of the registers ai, bi, and ci is also connected to an input path and an output path. The arrow on the left side of each register represents the input path, and the arrow on the right side represents the output path. The other ends of the input path and the output path are connected to the crossbar switch 2814. Hereinafter, each of the registers ai, bi, and ci may be referred to as a register Ri.

[0214] Depending on the position of register Ri, other registers Ri may exist on the input path or output path. For example, registers b0 and c0 exist on the output path of register a0. Register a0 exists on the input path of register b0, and register c0 exists on the output path. Registers a0 and b0 exist on the input path of register c0.

[0215] The crossbar switch 2814 switches the connections between the registers c0 to c3 and the registers a0 to a3, thereby switching the connections between the output path and input path of each register Ri.

[0216] A loop of registers Ri is formed by connecting the output path and input path of each register Ri via a crossbar switch 2814. The loop logic of register Ri may be user logic specified by a user or test logic of a scan circuit. The bit width of the output path and input path is one bit or multiple bits.

[0217] The information of VMi stored in each register Ri may be transferred to another register Ri via the output path of that register Ri, the crossbar switch 2814, and the input path of another register Ri. Therefore, a register Ri does not necessarily store the information of VMi indicated by its number i.

[0218] The register 1411 stores a destination table. The destination table includes a correspondence between VMi and a circuit 1414-j. In this example, VM0 and VM1 are associated with the circuit 1414-1, and VM2 and VM3 are associated with the circuit 1414-2. However, the VMi assigned to each circuit 1414-j is variable, and the circuit 1414-1 may be assigned to VM2, and the circuit 1414-2 may be assigned to VM1.

[0219] When the conversion unit 2811 receives an access request for information of any VMi from the CPU 211, it converts the number i of VMi included in the access request into the number i of the register Ri that actually stores the information of VMi, using a conversion table. This makes it possible to conceal from the CPU 211 the movement of information of VMi between registers Ri.

[0220] When the NIC processor 2801 is the DMA read unit 221 and receives read data for any VMi from the memory 212, the converter 2812 converts the number i of VMi indicated by the read data using a conversion table. The number i of VMi indicated by the read data is converted to the number i of the register Ri that actually stores the information for that VMi. This allows the selector 1412 to output the read data to the circuit 1414-j connected to the register Ri that contains the information for VMi indicated by the received read data.

[0221] When the NIC processor 2801 is the DMA writer 222 and receives a packet for any VMi from the NIC switch unit 224, the converter 2812 converts the number i of VMi indicated by the packet using a conversion table. The number i of VMi indicated by the packet is converted to the number i of the register Ri that actually stores the information of that VMi. This allows the selector 1412 to output the packet to the circuit 1414-j connected to the register Ri that contains the information of VMi indicated by the received packet.

[0222] When the NIC processing unit 2801 is the DMA read unit 221 and a read request is output from the selector 1416, the conversion unit 2813 converts the number i of VMi indicated by the read request in the opposite manner to that of the conversion unit 2812. When the NIC processing unit 2801 is the DMA write unit 222 and a write request is output from the selector 1416, the conversion unit 2813 converts the number i of VMi indicated by the write request in the opposite manner to that of the conversion unit 2812.

[0223] The operations of the register 1411, the selector 1412, the circuit 1414-1, the circuit 1414-2, the priority control unit 1415, and the selector 1416 are the same as those of the NIC processing unit 1401 in Fig. 14. However, when referring to the register 1422, the circuits 1414-1 and 1414-2 convert the number i of the bit i in the same way as the conversion unit 2811, and determine which VMi is in the active state.

[0224] When the control unit 2821 assigns a specific VMi to one of the circuits 1414-j, it selects the circuit 1414-j to be assigned to handle the VMi, and assigns packet processing for the specific VMi to the selected circuit 1414-j.

[0225] The circuit 1414-j to be allocated is selected, for example, as a circuit 1414-j to which no packet processing of any VMi is allocated, or as a circuit 1414-j to which packet processing of a smaller number of VMi is allocated than other circuits 1414-j.

[0226] Next, the control unit 2821 controls the crossbar switch 2814 so that the output path of the register Ri that stores the information of the specific VMi is connected to the input path of the register Ri connected to the circuit 1414-j to be assigned. Then, the control unit 2821 moves the information of the specific VMi to the register Ri connected to the circuit 1414-j to be assigned.

[0227] This allows the allocation target circuit 1414-j to access the information of a specific VMi. In addition, by linking the registers ai, bi, and ci to the crossbar switch 2814, it is possible to suppress an increase in the amount of hardware required for the crossbar switch 2814.

[0228] The register Ri connected to the circuit 1414-j to be allocated is an example of a specific storage unit.

[0229] Next, the control unit 2821 outputs update information for updating the conversion table in accordance with the movement of information on the specific VMi to the conversion units 2811, 2812, and 2813. The conversion units 2811, 2812, and 2813 update the conversion table in accordance with the update information.

[0230] As an example, it is assumed that VM0 is in the active state and VM1 to VM3 are in the inactive state, similar to state S11 in FIG.

[0231] In this case, register a0, register b0, and register c0 store information for VM0, and register a1, register b1, and register c1 store information for VM1. Register a2, register b2, and register c2 store information for VM2, and register a3, register b3, and register c3 store information for VM3. Circuit 1414-1 processes packets for VM0 while accessing register a0, register b0, and register c0.

[0232] Next, when VM1 changes from the inactive state to the active state, the control unit 2821 inhibits access to the registers ai, bi, and ci from the CPU 211. Then, the control unit 2821 assigns the packet processing of VM1 to the circuit 1414-2 that is not in charge of any VMi.

[0233] Then, the control unit 2821 instructs the crossbar switch 2814 to move the information in register a1, register b1, and register c1 to register a2, register b2, and register c2, respectively. In accordance with the instruction from the control unit 2821, the crossbar switch 2814 switches the connections between register c1 and register c2 and register a1 and register a2.

[0234] 29 shows an example of such switching of the crossbar switch 2814. The crossbar switch 2814 connects the output path of register c1 to the input path of register a2, and connects the output path of register c2 to the input path of register a1, in accordance with instructions from the control unit 2821. As a result, the output path of register a1 is connected to the input path of register a2, and the output path of register a2 is connected to the input path of register a1.

[0235] Next, the crossbar switch 2814 moves the information in register a1, register b1, register c1, register a2, register b2, and register c2 along the loop formed by the switching, thereby swapping the information in register a1 and register a2, swapping the information in register b1 and register b2, and swapping the information in register c1 and register c2.

[0236] After the information exchange, the register a1, register b1, and register c1 store the information of VM2, and the register a2, register b2, and register c2 store the information of VM1.

[0237] Conversion unit 2811 includes conversion table 2901, conversion unit 2812 includes conversion table 2902, and conversion unit 2813 includes conversion table 2903. Conversion table 2901 in Fig. 29 indicates that the number i (i = 0 to 3) of VMi is converted to the same number i. Conversion tables 2902 and 2903 are similar to conversion table 2901.

[0238] When the transfer of information from register a1, register b1, register c1, register a2, register b2, and register c2 is complete, control unit 2821 outputs update information to conversion units 2811, 2812, and 2813. The update information indicates that the number "1" of VM1 and the number "2" of VM2 contained in the conversion table are to be swapped. Conversion units 2811, 2812, and 2813 update conversion tables 2901, 2902, and 2903 in accordance with the update information.

[0239] Fig. 30 shows an example of such a conversion table update. Conversion table 2901 in Fig. 30 shows that the number "1" of VM1 is converted to the number "2" of VM2, and the number "2" of VM2 is converted to the number "1" of VM1. Conversion tables 2902 and 2903 are similar to conversion table 2901.

[0240] Next, the control unit 2821 copies the bit value of the register 1421 to the register 1422, and releases the inhibition of access to the registers ai, bi, and ci.

[0241] The circuit 1414-2 converts the number "1" of bit 1 of register 1422 to the number "2" of VM2 in the same manner as in the conversion table 2901, and determines that VM2 is in the active state. Then, the circuit 1414-2 starts packet processing for VM2 and accesses register a2, register b2, and register c2. This actually starts packet processing for VM1.

[0242] By moving information in this way and assigning packet processing for VM1 that has changed to the active state to circuit 1414-2, which is not in charge of any VMi, the number of VMi handled by circuit 1414-1 and circuit 1414-2 can be leveled.

[0243] Next, it is assumed that VM0 to VM2 are in the active state and VM3 is in the inactive state, similar to state S22 in FIG.

[0244] In this case, registers a0, b0, and c0 store information for VM0, registers a1, b1, and c1 store information for VM1, registers a2, b2, and c2 store information for VM2, and registers a3, b3, and c3 store information for VM3.

[0245] The circuit 1414-1 processes packets for VM0 by accessing registers a0, b0, and c0, and processes packets for VM1 by accessing registers a1, b1, and c1. The circuit 1414-2 processes packets for VM2 by accessing registers a2, b2, and c2.

[0246] Next, when VM2 changes from the active state to the inactive state, the control unit 2821 inhibits access to the registers ai, bi, and ci from the CPU 211. Then, the control unit 2821 shifts the responsibility for VM1 from the circuit 1414-1 to the circuit 1414-2, and the circuit 1414-1 stops packet processing for VM1.

[0247] Next, the control unit 2821 instructs the crossbar switch 2814 to move the information in register a1, register b1, and register c1 to register a2, register b2, and register c2, respectively. In accordance with the instruction of the control unit 2821, the crossbar switch 2814 switches the connections between register c1 and register c2 and register a1 and register a2, as shown in FIG.

[0248] Next, the crossbar switch 2814 moves the information in register a1, register b1, register c1, register a2, register b2, and register c2 along the loop formed by the switching, thereby swapping the information in register a1 and register a2, swapping the information in register b1 and register b2, and swapping the information in register c1 and register c2.

[0249] Next, control unit 2821 outputs the update information to conversion unit 2811, conversion unit 2812, and conversion unit 2813. In accordance with the update information, conversion unit 2811, conversion unit 2812, and conversion unit 2813 update conversion table 2901, conversion table 2902, and conversion table 2903, as shown in FIG.

[0250] Next, the control unit 2821 copies the bit value of the register 1421 to the register 1422, and releases the inhibition of access to the registers ai, bi, and ci.

[0251] The circuit 1414-2 converts the number "1" of bit 1 of register 1422 to the number "2" of VM2 in the same manner as in the conversion table 2901, and determines that VM2 is in the active state. Then, the circuit 1414-2 starts packet processing for VM2 and accesses register a2, register b2, and register c2. This actually starts packet processing for VM1.

[0252] By changing the assignment in this way, it is possible to eliminate the imbalance in the number of VMi assigned to the circuit 1414-1 and the circuit 1414-2, and to equalize the number of VMi assigned to each circuit 1414-j.

[0253] 28, since information about VMi is dynamically assigned to each circuit 1414-j, it is possible to change the circuit 1414-j to which packet processing is assigned for each VMi. Therefore, it is possible to level out the number of VMi handled by each circuit 1414-j, and similarly to the packet processing devices of FIGS. 14 and 15, the performance of parallel processing is improved.

[0254] 28 includes three or more circuits 1414-j, the circuit 1414-j to which packet processing is assigned can be changed for each VMi in the same manner. The number of operating VMi is not limited to one to four, but may be five or more.

[0255] The control processing performed by the packet processing device in Fig. 28 is the same as that in Fig. 26. However, in steps 2604 and 2610, the control unit 2821 outputs update information to the conversion units 2811, 2812, and 2813 instead of outputting update information to the register 1411. Also, the control unit 2821 controls the crossbar switch 2814 instead of controlling the crossbar switches 1413-1 to 1413-3.

[0256] The configurations of the NFV systems in Figures 1 and 2 are merely examples, and some of the components may be omitted or changed depending on the use or conditions of the NFV system. The configurations of the DMA read unit 221 in Figures 4, 7, and 9 and the DMA write unit 222 in Figure 5 are merely examples, and some of the components may be omitted or changed depending on the use or conditions of the NFV system. The configurations of the packet processing devices in Figures 11, 12, 14, 15, and 28 are merely examples, and some of the components may be omitted or changed depending on the use or conditions of the NFV system.

[0257] The flowcharts of FIG. 13 and FIG. 26 are merely examples, and some of the processes may be omitted or changed depending on the configuration or conditions of the packet processing device.

[0258] The information shown in Figure 3 is merely an example, and the information stored in memory 212 changes depending on the VMi that is operating. The data transfer sequences shown in Figures 6 and 8 are merely an example, and the data transfer sequence changes depending on the VMi that is operating. The read request throughput shown in Figure 10 is merely an example, and the read request throughput changes depending on the VMi that is operating.

[0259] 16 to 21, 29, and 30 are merely examples, and the operation of the packet processing device changes depending on the state of each VMi. The priority control shown in Figures 22 to 25 is merely an example, and the priority control changes depending on the configuration of the priority control unit 1415. The correspondence relationship between the maximum throughput value and the number of parallel processes shown in Figure 27 is merely an example, and the number of parallel processes may be determined by another method.

[0260] Although the disclosed embodiments and their advantages have been described in detail, those skilled in the art may make various modifications, additions, and omissions without departing from the scope of the invention as clearly set forth in the claims.

[0261] The following notes are further provided regarding the embodiment described with reference to FIGS. (Appendix 1) a plurality of packet processing units that execute a plurality of packet processes in parallel; a plurality of storage units each storing information associated with one of a plurality of communication entities; a switch unit for switching between the plurality of storage units; a control unit that assigns packet processing for a specific communication entity among the plurality of communication entities to a specific packet processing unit among the plurality of packet processing units, and controls the switch unit to cause the specific packet processing unit to access information associated with the specific communication entity among information stored in each of the plurality of storage units; A packet processing device comprising: (Appendix 2) The packet processing device according to claim 1, characterized in that the control unit selects, from among the plurality of packet processing units, a packet processing unit that is not assigned packet processing for any communication entity, or a packet processing unit that is assigned packet processing for a smaller number of communication entities than the other packet processing units, as the specific packet processing unit. (Appendix 3) the switch unit switches connections between each of the plurality of packet processing units and each of the plurality of storage units; The packet processing device according to claim 1 or 2, characterized in that the control unit controls the switch unit so that a specific memory unit among the plurality of memory units that stores information associated with the specific communication entity is connected to the specific packet processing unit. (Appendix 4) a first state storage unit that stores first state information indicating the state of each of the plurality of communication entities; a second state storage unit that stores second state information indicating the state of each of the plurality of communication entities; Furthermore, the first status information indicates that the specific communication entity is in an inactive state; when the specific communication entity changes from the inactive state to the active state in the first state information, the control unit assigns packet processing of the specific communication entity to the specific packet processor, controls the switch unit so that the specific storage unit and the specific packet processor are connected, and copies the first state information to the second state information; The packet processing device described in Appendix 3, characterized in that after the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the specific communication entity based on the second state information and accesses the specific memory unit. (Appendix 5) a first state storage unit that stores first state information indicating the state of each of the plurality of communication entities; a second state storage unit that stores second state information indicating the state of each of the plurality of communication entities; Furthermore, the specific communication entity is a first communication entity, packet processing of the first communication entity is assigned to a packet processing unit other than the specific packet processing unit among the plurality of packet processing units, packet processing of a second communication entity among the plurality of communication entities is assigned to the specific packet processing unit; the first state information indicates that the first communication entity and the second communication entity are in an active state; when the second communication entity changes from the active state to the inactive state in the first state information, the control unit assigns packet processing of the first communication entity to the specific packet processing unit instead of packet processing of the second communication entity, controls the switch unit so that the specific storage unit and the specific packet processing unit are connected, and copies the first state information to the second state information; The packet processing device described in Appendix 3, characterized in that after the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the first communication entity based on the second state information and accesses the specific memory unit. (Appendix 6) each of the plurality of storage units is connected to one of the plurality of packet processing units, and is also connected to an input path and an output path; the switch unit switches a connection between the input path connected to each of the plurality of storage units and the output path connected to each of the plurality of storage units; The packet processing device according to claim 1 or 2, characterized in that the control unit controls the switch unit so that the output path of a memory unit that stores information associated with the specific communication entity is connected to the input path of a specific memory unit connected to the specific packet processing unit, and moves the information associated with the specific communication entity to the specific memory unit. (Appendix 7) a first state storage unit that stores first state information indicating the state of each of the plurality of communication entities; a second state storage unit that stores second state information indicating the state of each of the plurality of communication entities; Furthermore, the first status information indicates that the specific communication entity is in an inactive state; when the specific communication entity changes from the inactive state to the active state in the first state information, the control unit allocates packet processing of the specific communication entity to the specific packet processor, controls the switch unit so that the output path of the storage unit that stores the information associated with the specific communication entity is connected to the input path of the specific storage unit connected to the specific packet processor, moves the information associated with the specific communication entity to the specific storage unit, and copies the first state information to the second state information; The packet processing device described in Appendix 6, characterized in that after the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the specific communication entity based on the second state information and accesses the specific memory unit. (Appendix 8) a first state storage unit that stores first state information indicating the state of each of the plurality of communication entities; a second state storage unit that stores second state information indicating the state of each of the plurality of communication entities; Furthermore, the specific communication entity is a first communication entity, packet processing of the first communication entity is assigned to a packet processing unit other than the specific packet processing unit among the plurality of packet processing units, packet processing of a second communication entity among the plurality of communication entities is assigned to the specific packet processing unit; the first state information indicates that the first communication entity and the second communication entity are in an active state; when the second communication entity changes from the active state to the inactive state in the first state information, the control unit allocates packet processing of the first communication entity to the specific packet processing unit instead of packet processing of the second communication entity, controls the switch unit so that the output side path of the storage unit that stores information associated with the specific communication entity is connected to the input side path of the specific storage unit connected to the specific packet processing unit, moves the information associated with the specific communication entity to the specific storage unit, and copies the first state information to the second state information; The packet processing device described in Appendix 6, characterized in that after the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the first communication entity based on the second state information and accesses the specific memory unit. (Appendix 9) a determination unit that determines a selection probability of selecting a request output from each of the plurality of packet processing units based on the number of communication entities corresponding to packet processing assigned to each of the plurality of packet processing units; a selection unit that selects and outputs any one of the requests output from each of the plurality of packet processing units based on the selection probability; 9. The packet processing device according to any one of claims 1 to 8, further comprising: (Appendix 10) each of the plurality of communication entities is a virtual machine; the specific communication entity is a specific virtual machine, A packet processing device described in any one of Supplementary Notes 1 to 9, characterized in that the packet processing of the specific communication entity is processing of sending packets whose source is the specific virtual machine, or processing of receiving packets whose destination is the specific virtual machine. (Appendix 11) a first step of assigning packet processing of a specific communication entity among a plurality of communication entities to a specific packet processing unit among a plurality of packet processing units that execute a plurality of packet processes in parallel; a second step of controlling a switch unit that switches between a plurality of storage units that each store information associated with one of the plurality of communication entities, thereby causing the specific packet processing unit to access information associated with the specific communication entity among the information stored in each of the plurality of storage units; A packet processing method comprising: (Appendix 12) The packet processing method according to claim 11, characterized in that the first step includes a step of selecting, from among the plurality of packet processing units, a packet processing unit that is not assigned packet processing for any communication entity, or a packet processing unit that is assigned packet processing for a smaller number of communication entities than the other packet processing units, as the specific packet processing unit. (Appendix 13) the switch unit switches connections between each of the plurality of packet processing units and each of the plurality of storage units; The packet processing method according to claim 11 or 12, characterized in that the second step includes a step of controlling the switch unit so that a specific memory unit among the plurality of memory units that stores information associated with the specific communication entity is connected to the specific packet processing unit. (Appendix 14) the first step includes a step of allocating packet processing of the specific communication entity to the specific packet processor when the specific communication entity changes from an inactive state to an active state in first state information indicating the states of the respective communication entities; The second step comprises: copying the first state information to second state information after the specific storage unit and the specific packet processing unit are connected; After the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the specific communication entity based on the second state information and accesses the specific storage unit; 14. The packet processing method of claim 13, further comprising: (Appendix 15) the first step includes a step of allocating packet processing of the first communication entity to the specific packet processing unit instead of packet processing of the second communication entity when the specific communication entity is a first communication entity, packet processing of the first communication entity is assigned to a packet processing unit other than the specific packet processing unit among the plurality of packet processing units, packet processing of a second communication entity among the plurality of communication entities is assigned to the specific packet processing unit, and first state information indicating the states of the respective plurality of communication entities indicates that the first communication entity and the second communication entity are in an active state, and when the second communication entity changes from the active state to an inactive state, The second step comprises: copying the first state information to the second state information after the specific storage unit and the specific packet processing unit are connected; After the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the first communication entity based on the second state information and accesses the specific storage unit; 14. The packet processing method of claim 13, further comprising: (Appendix 16) each of the plurality of storage units is connected to one of the plurality of packet processing units, and is also connected to an input path and an output path; the switch unit switches a connection between the input path connected to each of the plurality of storage units and the output path connected to each of the plurality of storage units; The second step comprises: a step of controlling the switch unit so that the output path of a storage unit that stores information associated with the specific communication entity is connected to the input path of a specific storage unit connected to the specific packet processing unit; a step of moving information associated with the specific communication entity to the specific storage unit; 13. The packet processing method according to claim 11 or 12, comprising: (Appendix 17) the first step includes a step of allocating packet processing of the specific communication entity to the specific packet processor when the specific communication entity changes from an inactive state to an active state in first state information indicating the states of the respective communication entities; The second step comprises: a step of connecting the output path of a storage unit that stores information associated with the specific communication entity and the input path of the specific storage unit, and copying the first status information to the second status information after the information associated with the specific communication entity has been moved to the specific storage unit; After the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the specific communication entity based on the second state information and accesses the specific storage unit; 17. The packet processing method of claim 16, further comprising: (Appendix 18) the first step includes a step of allocating packet processing of the first communication entity to the specific packet processing unit instead of packet processing of the second communication entity when the specific communication entity is a first communication entity, packet processing of the first communication entity is assigned to a packet processing unit other than the specific packet processing unit among the plurality of packet processing units, packet processing of a second communication entity among the plurality of communication entities is assigned to the specific packet processing unit, and first state information indicating the states of the respective plurality of communication entities indicates that the first communication entity and the second communication entity are in an active state, and when the second communication entity changes from the active state to an inactive state, The second step comprises: a step of connecting the output path of a storage unit that stores information associated with the specific communication entity and the input path of the specific storage unit, and copying the first status information to the second status information after the information associated with the specific communication entity has been moved to the specific storage unit; After the first state information is copied to the second state information, the specific packet processing unit starts packet processing of the first communication entity based on the second state information and accesses the specific storage unit; 17. The packet processing method of claim 16, further comprising: (Appendix 19) determining a selection probability of selecting a request output from each of the plurality of packet processing units based on the number of communication entities corresponding to packet processing assigned to each of the plurality of packet processing units; selecting and outputting any one of the requests output from each of the plurality of packet processing units based on the selection probability; 19. The packet processing method according to any one of appendices 11 to 18, further comprising: (Appendix 20) each of the plurality of communication entities is a virtual machine; the specific communication entity is a specific virtual machine, A packet processing method described in any one of Appendices 11 to 19, characterized in that the packet processing of the specific communication entity is a process of sending a packet whose source is the specific virtual machine, or a process of receiving a packet whose destination is the specific virtual machine. [Explanation of symbols]

[0262] 101, 201 physical servers 111-1~111-3 VNF 112 Hypervisor 113 Virtual Switch 121NIC 122-1, 122-2, 225 IF 131~133 dashed line 211 CPU 212 memory 221 DMA lead section 222 DMA write section 223, 1102, 1402, 2802 NIC control unit 224 NIC switch section 301 Send Job Table 302 Transmission Area 303 Received Jobs Table 304 Receiving Area 411, 414, 511-0 to 511-3 FIFO circuit 412, 512 conversion circuit 413, 513 generation circuit 415-0 to 415-3, 416-0 to 416-3, 514-0 to 514-3, 515-0 to 515-3, 1111, 1121, 1411, 1421, 1422 registers 701-1~701-3, 901-1, 901-2, 1113-1, 1113-2, 1414-1~1414-M circuit 702, 902, 1112, 1115, 1412, 1416 selector 1101, 1401, 2801 NIC processing unit 1114, 1415 Priority control section 1201 Packet Processing Device 1211-1 to 1211-M Packet processing unit 1212-1~1212-N Storage section 1213 Switch section 1214, 1423, 2821 Control section 1413-1 to 1413-3, 2814 crossbar switches 1601, 1701 period 2811~2813 Conversion unit 2901~2903 Conversion Table a0~aN-1, b0~bN-1, c0~cN-1 registers

Claims

1. a plurality of packet processing units that execute a plurality of packet processes in parallel; a plurality of storage units each storing information associated with one of a plurality of communication entities; a switch unit that switches connections between each of the plurality of packet processing units and each of the plurality of storage units; a control unit that assigns packet processing for a specific communication entity among the multiple communication entities to a specific packet processing unit among the multiple packet processing units, and controls the switch unit so that a specific storage unit among the multiple storage units that stores information associated with the specific communication entity is connected to the specific packet processing unit, thereby causing the specific packet processing unit to access information associated with the specific communication entity among information stored in each of the multiple storage units; Equipped with A packet processing device characterized in that the information associated with any of the communication entities is configuration information regarding any of the communication entities, information regarding packets of any of the communication entities, or control information regarding jobs of any of the communication entities.

2. The packet processing device according to claim 1, characterized in that the control unit selects, from among the plurality of packet processing units, a packet processing unit that is not assigned packet processing for any communication entity, or a packet processing unit that is assigned packet processing for a smaller number of communication entities than the other packet processing units, as the specific packet processing unit.

3. a first state storage unit configured to store first state information indicating the state of each of the plurality of communication entities; a second state storage unit configured to store second state information indicating the state of each of the plurality of communication entities; Furthermore, the first status information indicates that the specific communication entity is in an inactive state; when the specific communication entity changes from the inactive state to the active state in the first state information, the control unit assigns packet processing of the specific communication entity to the specific packet processing unit, controls the switch unit so that the specific storage unit and the specific packet processing unit are connected, and copies the first state information to the second state information; 3. The packet processing device according to claim 1, wherein the specific packet processing unit starts packet processing of the specific communication entity based on the second status information after the first status information is copied to the second status information, and accesses the specific memory unit.

4. a first state storage unit configured to store first state information indicating the state of each of the plurality of communication entities; a second state storage unit configured to store second state information indicating the state of each of the plurality of communication entities; Furthermore, the specific communication entity is a first communication entity, packet processing of the first communication entity is assigned to a packet processing unit other than the specific packet processing unit among the plurality of packet processing units, packet processing of a second communication entity among the plurality of communication entities is assigned to the specific packet processing unit; the first state information indicates that the first communication entity and the second communication entity are in an active state; when the second communication entity changes from the active state to the inactive state in the first state information, the control unit assigns packet processing of the first communication entity to the specific packet processing unit instead of packet processing of the second communication entity, controls the switch unit so that the specific storage unit and the specific packet processing unit are connected, and copies the first state information to the second state information; 3. The packet processing device according to claim 1, wherein the specific packet processing unit starts packet processing of the first communication entity based on the second status information after the first status information is copied to the second status information, and accesses the specific memory unit.

5. A plurality of packet processing units that execute a plurality of packet processes in parallel; a plurality of storage units each storing information associated with one of a plurality of communication entities; a switch unit for switching between the plurality of storage units; a control unit that assigns packet processing for a specific communication entity among the plurality of communication entities to a specific packet processing unit among the plurality of packet processing units, and controls the switch unit to cause the specific packet processing unit to access information associated with the specific communication entity among information stored in each of the plurality of storage units; Equipped with each of the plurality of storage units is connected to one of the plurality of packet processing units, and is also connected to an input path and an output path; the switch unit switches a connection between the input path connected to each of the plurality of storage units and the output path connected to each of the plurality of storage units; the control unit controls the switch unit so that the output path of a storage unit that stores information associated with the specific communication entity is connected to the input path of a specific storage unit connected to the specific packet processing unit, and moves the information associated with the specific communication entity to the specific storage unit; A packet processing device characterized in that the information associated with any of the communication entities is configuration information regarding any of the communication entities, information regarding packets of any of the communication entities, or control information regarding jobs of any of the communication entities.

6. A packet processing device as described in Claim 5, characterized in that the control unit selects as the specific packet processing unit, from among the plurality of packet processing units, a packet processing unit that is not assigned packet processing for any communication entity, or a packet processing unit that is assigned packet processing for a smaller number of communication entities than the other packet processing units.

7. a first state storage unit configured to store first state information indicating the state of each of the plurality of communication entities; a second state storage unit configured to store second state information indicating the state of each of the plurality of communication entities; Furthermore, the first status information indicates that the specific communication entity is in an inactive state; when the specific communication entity changes from the inactive state to the active state in the first state information, the control unit allocates packet processing of the specific communication entity to the specific packet processor, controls the switch unit so that the output path of the storage unit that stores information associated with the specific communication entity is connected to the input path of the specific storage unit connected to the specific packet processor, moves the information associated with the specific communication entity to the specific storage unit, and copies the first state information to the second state information; 7. The packet processing device according to claim 5, wherein the specific packet processing unit starts packet processing of the specific communication entity based on the second status information after the first status information is copied to the second status information, and accesses the specific memory unit.

8. a first state storage unit configured to store first state information indicating the state of each of the plurality of communication entities; a second state storage unit configured to store second state information indicating the state of each of the plurality of communication entities; Furthermore, the specific communication entity is a first communication entity, packet processing of the first communication entity is assigned to a packet processing unit other than the specific packet processing unit among the plurality of packet processing units, packet processing of a second communication entity among the plurality of communication entities is assigned to the specific packet processing unit; the first state information indicates that the first communication entity and the second communication entity are in an active state; when the second communication entity changes from the active state to the inactive state in the first state information, the control unit allocates packet processing of the first communication entity to the specific packet processing unit instead of packet processing of the second communication entity, controls the switch unit so that the output side path of the storage unit that stores information associated with the specific communication entity is connected to the input side path of the specific storage unit connected to the specific packet processing unit, moves the information associated with the specific communication entity to the specific storage unit, and copies the first state information to the second state information; 7. A packet processing device according to claim 5, wherein the specific packet processing unit starts packet processing of the first communication entity based on the second status information after the first status information is copied to the second status information, and accesses the specific memory unit.

9. a determination unit that determines a selection probability of selecting a request output from each of the plurality of packet processing units based on the number of communication entities corresponding to packet processing assigned to each of the plurality of packet processing units; a selection unit that selects and outputs any one of the requests output from each of the plurality of packet processing units based on the selection probability; Furthermore, 9. The packet processing device according to claim 1, wherein the request output from each of the plurality of packet processing units is a read request or a write request to a memory.

10. The setting information relating to any one of the communication entities is an address translation table of any one of the communication entities, 10. The packet processing device according to claim 1, wherein the information relating to packets of any one of the communication entities is statistical information of packets of any one of the communication entities.

11. assigning packet processing of a specific communication entity among the plurality of communication entities to a specific packet processing unit among the plurality of packet processing units that executes a plurality of packet processes in parallel; controlling a switch unit that switches connections between each of the plurality of packet processing units and each of the plurality of storage units so that a specific storage unit that stores information associated with the specific communication entity among a plurality of storage units that each store information associated with one of the plurality of communication entities is connected to the specific packet processing unit, thereby causing the specific packet processing unit to access information associated with the specific communication entity among the information stored in each of the plurality of storage units; A packet processing method characterized in that the information associated with any of the communication entities is configuration information regarding any of the communication entities, information regarding packets of any of the communication entities, or control information regarding jobs of any of the communication entities.

12. A first step of assigning packet processing of a specific communication entity among a plurality of communication entities to a specific packet processing entity among a plurality of packet processing entities that executes a plurality of packet processing in parallel; a second step of controlling a switch unit that switches between a plurality of storage units that respectively store information associated with any one of the plurality of communication entities, thereby causing the specific packet processing unit to access information associated with the specific communication entity among the information stored in each of the plurality of storage units; Equipped with each of the plurality of storage units is connected to one of the plurality of packet processing units, and is also connected to an input path and an output path; the switch unit switches a connection between the input path connected to each of the plurality of storage units and the output path connected to each of the plurality of storage units; The second step comprises: controlling the switch unit so that the output path of a storage unit that stores information associated with the specific communication entity is connected to the input path of a specific storage unit connected to the specific packet processing unit; a step of moving information associated with the specific communication entity to the specific storage unit; Including, A packet processing method characterized in that the information associated with any of the communication entities is configuration information regarding any of the communication entities, information regarding packets of any of the communication entities, or control information regarding jobs of any of the communication entities.

13. The setting information relating to any one of the communication entities is an address translation table of any one of the communication entities, 13. The packet processing method according to claim 11, wherein the information about the packets of any one of the communication entities is statistical information about the packets of any one of the communication entities.

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