Display panel and manufacturing method thereof, display device

Abstract

To provide a display panel, a method for manufacturing the same, and a display device.SOLUTION: A display panel includes reset signal line patterns positioned in a plurality of sub-pixel areas and respective sub-pixel areas, an initialization signal line pattern, and a conductive connection part pattern. The initialization signal line pattern includes a first body part and a first projection part which are coupled to each other. Orthogonal projection on the base of the first body part is positioned between orthogonal projection on the base of the first projection part and orthogonal projection on the base of the reset signal line pattern. The orthogonal projection on the base of a first end of the conductive connection part pattern and the orthogonal projection on the base of the first projection part include a first overlap region. In the first overlap region, the first end is coupled to the first projection pattern. A second end of the conductive connection part pattern is coupled to a target coupling part. The orthogonal projection on the base of the reset signal line pattern is positioned between orthogonal projection on the base of the target coupling part and orthogonal projection on the base of the initialization signal line pattern.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present disclosure relates to the technical field of displays, and in particular to a display panel and a manufacturing method thereof, and a display device do. [Background technology]

[0002] Organic Light-Emitting Diode With the rapid development of OLED (Electronic Display) display technology, the screen occupancy rate and Consumer demands for image quality and resolution are increasing. Active Area Ratio is the effective display area (active area) of the front panel of the display device. AA area) and the resolution of an OLED display is the ratio of the AA area The larger the screen occupancy rate of an OLED display, the more consumers will pay. The higher the resolution of an OLED display, the clearer the images displayed on it. becomes. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.

[0004] A first aspect of the present disclosure is a display panel, comprising: a base; and a function provided on the base. a film layer, and further including a plurality of sub-pixel areas arranged in an array; the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas. the reset signal line pattern extends along a first direction; The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. The initialization signal line pattern includes a first main body portion and a first protruding portion coupled to each other. the first body portion extends along the first direction and, in the same sub-pixel area, The orthogonal projection of the first body portion on the base is the orthogonal projection of the first protruding portion on the base. and an orthogonal projection of the reset signal line pattern on the base; the conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, In the same sub-pixel area, the positive electrode of the first end of the conductive connection pattern on the base and an orthogonal projection of the first protruding portion on the base, the projection having a first overlap region. and in the first overlap region, the first end is coupled to the first protruding portion. The second end of the conductive connection pattern is connected to a target in the sub-pixel area where the second end is located. The reset signal line pattern is coupled to a base coupling portion, and an orthogonal projection of the reset signal line pattern on the base is orthogonal projection of the target coupling portion on the base and the initialization signal line pattern on the base and a display panel positioned between the orthogonal projection at the

[0005] Optionally, the display panel comprises: The functional film layer has a plurality of sub-pixel areas, each of which corresponds to a base. A plurality of light emitting elements located on the opposite side; a plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas; The sub-pixel driving circuits each include a seventh transistor, and the gate of the seventh transistor The first electrode of the seventh transistor is connected to the corresponding reset signal line pattern. is used as the target coupling portion, and the second pole of the seventh transistor is connected to the second direction A plurality of sub-pixel drivers extending along the and an operating circuit, The conductive connection pattern is formed by a second body connected between the first end and the second end. the second body portion extends along a second direction and in the same sub-pixel area; In the first direction, a first end of the conductive connection pattern is connected to the seventh transformer. A second body portion projects from the second body portion in a direction away from the second pole of the resistor.

[0006] Optionally, the functional film layer further includes a data line pattern located in each sub-pixel area. the data line pattern includes a portion extending along the second direction; The initialization signal line pattern is orthogonally projected onto the base, and the conductive connection portion pattern is projected onto the base. There is a third overlap region between the orthogonal projection on the base, orthogonal projection of the initialization signal line pattern onto the base; and There is a fourth overlap area between the orthogonal projection on the base, along the second direction of the initialization signal line pattern in the fourth overlap region The width of the initialization signal line pattern in the third overlap region is smaller than the width along the

[0007] Optionally, in the same sub-pixel area, an orthogonal projection of the second body portion onto the base and the orthogonal projection of the second pole of the seventh transistor on the base, there is a first gap. The first gap is greater than a threshold value.

[0008] Optionally, the display panel comprises: Each of the sub-pixel areas has a driving transistor and a second further comprising a plurality of subpixel drive circuits including transistors; The gate of the second transistor is connected to a previous sub-pixel area adjacent to the first sub-pixel area in the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern in the the first sub-pixel area of ​​the second transistor; a bipolar electrode coupled to the gate of the drive transistor; The second transistor includes two semiconductor portions spaced apart from each other along the first direction. and a first conductor portion connected to the two semiconductor portions, respectively, The orthogonal projection of the first protruding portion on the base of the first sub-pixel area is It does not overlap with the orthographic projection on the source.

[0009] Optionally, an orthogonal projection of the first conductor portion onto the base is and an orthogonal projection of a first end of the conductive connection pattern on the base.

[0010] Optionally, each of the initialization signal line patterns is connected to a second projection coupled to the first body portion. and a second protruding portion on the base of the second protruding portion in the same sub-pixel area. The orthogonal projection is a projection of the first body portion onto the base, and the reset signal line pattern. and an orthogonal projection of the first conductor portion on the base. overlaps with the orthogonal projection of the second protruding portion on the base.

[0011] Optionally, the conductive connection pattern is connected between the first end and the second end. a second body portion extending along a second direction; An end of the first conductor portion close to the conductive connection pattern in the previous sub-pixel area extends along the second direction, and the orthogonal projection of the end on the base and the conductive connection portion There is a second gap between the orthogonal projection of the second body portion of the pattern on the base, and The gap between the two is greater than the threshold.

[0012] Optionally, in the same sub-pixel area, the base of the first end of the conductive connection pattern and a normal projection of the first main body portion of the initialization signal line pattern on the base. A second overlap area is also formed with the shadow. The functional film layer further includes a first connection hole located in each of the sub-pixel areas, In the area, the orthogonal projection of the first connection hole on the base is the conductive connection pattern overlaps the first overlap region and the second overlap region. A first end of the line is coupled to the initialization signal line pattern through the first contact hole.

[0013] Optionally, the orthogonal projection of the first conductor portion of the second transistor onto the base is and overlapping with an orthogonal projection of the first contact hole on the base in the sub-pixel area. do not have.

[0014] Optionally, the functional film layer further includes a power supply signal line layer, and the power supply signal line layer is a power supply signal line pattern provided in the pixel area, and a portion of the first and second electrodes extends along the second direction. the first conductor portion far from the conductive connection pattern in the previous sub-pixel area The edges extend along the second direction, and the orthogonal projections of the edges on the base are aligned along the same sub-pixel. The power supply signal line pattern located in the area is completely covered by the orthogonal projection on the base. can be.

[0015] Optionally, the display panel comprises: a plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas; Each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor is , a first electrode plate and a second electrode plate provided opposite to each other, The second electrode plate is opposite to the base of the first substrate. a plurality of subpixel driving circuits located on the side of the pixel; The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is connected to each of the sub-pixel areas. a power supply signal line pattern provided on the power supply signal line, and at least a part of the power supply signal line pattern is , extending along a second direction, and the power supply signal line pattern includes a first power supply portion and a second power supply portion. fruit, The orthogonal projection of the first power supply unit on the base is The signal line pattern is projected onto the base in a direction that overlaps the orthogonal projection of the signal line pattern. The orthogonal projection and overlap of each of the gate line patterns located in the pixel area on the base are and the orthogonal projection of the second power supply part on the base corresponds to the second electrode plate of the storage capacitor. and the first power supply unit is arranged to overlap with the orthogonal projection of the first power supply unit on the base along the first direction. The width of the second power supply unit is smaller than the width of the second power supply unit.

[0016] Optionally, the functional film layer further includes a power supply signal line layer, and the power supply signal line layer is a power supply signal line pattern provided in the pixel area, and a portion of the first and second electrodes extends along the second direction. The functional film layer further includes an auxiliary power supply layer, and the auxiliary power supply layer is provided in each of the sub-pixel areas. an auxiliary power supply pattern provided on the base, and an orthogonal projection of the auxiliary power supply pattern on the base; and a orthogonal projection onto the base of a power supply signal line pattern located in the same sub-pixel area. There is an overlapping area, and the auxiliary power supply pattern and the power supply signal line pattern are They are joined in the overlap region.

[0017] Optionally, the display panel has a one-to-one correspondence with the plurality of sub-pixel areas, each of which has a further comprising a plurality of subpixel drive circuits each including a drive transistor and a second transistor; The gate of the second transistor is connected to a previous sub-pixel area adjacent to the first sub-pixel area in the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern in the the first sub-pixel area of ​​the second transistor; The two poles include a first electrode portion and a second electrode portion coupled to each other, and the first electrode portion is coupled to a second electrode portion. the second electrode portion extends along a third direction, and the third direction is The first electrode portion intersects both the first direction and the second direction, and the first electrode portion of the second transistor The second electrode portion is located between the semiconductor portion and the driving transistor. coupled to the gate of The orthogonal projection of the first electrode portion on the base and the orthogonal projection of the second electrode portion on the base Any shadows are covered by the orthogonal projection of the corresponding auxiliary power pattern on the base. .

[0018] Optionally, the auxiliary power pattern includes a first auxiliary sub-pattern and a second auxiliary sub-pattern coupled to each other. the first auxiliary sub-pattern extends along a second direction; At least a portion of the second auxiliary sub-pattern extends along the first direction; The orthogonal projection of the first auxiliary sub-pattern on the base is and an orthogonal projection of the second electrode portion on the base.

[0019] Optionally, the width of the first auxiliary sub-pattern along the first direction is It is larger than the width of the source signal line pattern.

[0020] Optionally, an orthogonal projection of the first electrode portion on the base and an orthogonal projection of the second electrode portion on the base Each of the orthogonal projections on the base is obtained by orthogonally projecting the corresponding power supply signal line pattern onto the base. It is covered with

[0021] Optionally, the functional film layer may include a gate line pattern, a light emitting control pattern, and a gate insulating film. a signal line pattern, and in the same sub-pixel area, the gate electrode is arranged along a second direction; the light emission control signal line pattern, the reset signal line pattern, and the initial The signal line patterns are arranged in a sequential manner, The functional film layer includes a power supply signal line pattern and a data line pattern located in each sub-pixel area. the power supply signal line pattern and the data line pattern are both connected to the second direction. a portion extending along the direction of the The display panel includes: a light-emitting element that corresponds one-to-one to the plurality of sub-pixel areas; Each of the sub-pixel areas has a driving transistor, a first transistor, second transistor, fourth transistor, fifth transistor, sixth transistor a subpixel drive circuit including a first transistor and a seventh transistor; In the same sub-pixel area, the gate of the driving transistor is connected to the first transistor. the first electrode of the drive transistor is coupled to the second electrode of the fifth transistor; a second pole of the drive transistor coupled to a first pole of the first transistor; And, a gate of the first transistor is coupled to the gate line pattern; The gate of the second transistor is connected to a previous sub-pixel area adjacent to the first sub-pixel area in the second direction. and a first electrode of the second transistor is coupled to the reset signal line pattern in the the first sub-pixel area of ​​the second transistor; a bipolar electrode coupled to the gate of the drive transistor; The gate of the fourth transistor is coupled to the gate line pattern. a first pole of the fourth transistor is coupled to the data line pattern; and a second pole of the fourth transistor is coupled to the data line pattern. , coupled to the first pole of the drive transistor; The gate of the fifth transistor is coupled to the light emitting control signal line pattern, a first electrode of the transistor is coupled to the power supply signal line pattern; The gate of the sixth transistor is coupled to the light emitting control signal line pattern. A first electrode of the transistor is coupled to a second electrode of the drive transistor, and a second electrode of the sixth transistor is coupled to a second electrode of the drive transistor. a second pole of the first electrode is coupled to the corresponding light emitting element; The second electrode of the seventh transistor is coupled to the light emitting element, The gate is coupled to the reset signal line pattern, and the first electrode of the seventh transistor is It is coupled to the second initialization signal line pattern.

[0022] Based on the technical solution of the display panel, a second aspect of the present disclosure is a display including the display panel. A display device is provided.

[0023] Based on the above technical solution of the display panel, the third aspect of the present disclosure is a manufacturing method of the display panel. So, A functional film layer is fabricated on the base to form a plurality of sub-pixel areas arranged in an array. This includes: the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas. the reset signal line pattern extends along a first direction; The initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas. The initialization signal line pattern includes a first main body portion and a first protruding portion coupled to each other. the first body portion extends along the first direction and, in the same sub-pixel area, The orthogonal projection of the first body portion on the base is the orthogonal projection of the first protruding portion on the base. and an orthogonal projection of the reset signal line pattern on the base; the conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, In the same sub-pixel area, the positive electrode of the first end of the conductive connection pattern on the base and an orthogonal projection of the first protruding portion on the base, the projection having a first overlap region. and in the first overlap region, the first end is coupled to the first protruding portion. The second end of the conductive connection pattern is connected to a target in the sub-pixel area where the second end is located. The reset signal line pattern is coupled to a base coupling portion, and an orthogonal projection of the reset signal line pattern on the base is orthogonal projection of the target coupling portion on the base and the initialization signal line pattern on the base The present invention provides a method for manufacturing a display panel positioned between an orthogonal projection and a display panel.

[0024] The drawings described herein are intended to provide a further understanding of the present disclosure and are not to be construed as limiting the present disclosure. The illustrative examples and descriptions of the present disclosure are provided as part of the present disclosure. and do not constitute undue limitations on this disclosure. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a schematic diagram of a sub-pixel layout in the prior art. [Figure 2] FIG. 2 is a schematic diagram of the layout of the active layer in FIG. 1. [Figure 3] FIG. 2 is a schematic diagram of the layout of the first gate metal layer in FIG. [Figure 4] FIG. 2 is a schematic diagram of the layout of the second gate metal layer in FIG. 1. [Figure 5] FIG. 2 is a schematic diagram of the layout of the source-drain metal layer in FIG. 1. [Figure 6] FIG. 2 is a circuit diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure. [Figure 7] 10 is a driving time chart of a sub-pixel driving circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram of a first layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 9] FIG. 10 is a schematic diagram of a second layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 10] FIG. 9 is a schematic diagram of the layout of the active layer in FIG. 8. [Figure 11] FIG. 9 is a schematic diagram of the layout of the first gate metal layer in FIG. 8. [Figure 12] FIG. 9 is a schematic diagram of the layout of the second gate metal layer in FIG. 8. [Figure 13]FIG. 9 is a schematic diagram of the layout of the source-drain metal layer in FIG. 8. [Figure 14] FIG. 9 is a cross-sectional view taken along the A1A2 direction in FIG. [Figure 15] FIG. 10 is a schematic diagram of a third layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a first enlarged schematic view of the X1 portion in FIG. [Figure 17] FIG. 16 is a second enlarged schematic view of the X1 portion in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along the B1B2 direction in FIG. [Figure 19] FIG. 16 is a schematic diagram of the layout of the active layer in FIG. 15. [Figure 20] FIG. 16 is a schematic diagram of the layout of the first gate metal layer in FIG. [Figure 21] FIG. 16 is a schematic diagram of the layout of the second gate metal layer in FIG. 15. [Figure 22] FIG. 16 is a schematic diagram of the layout of the source-drain metal layer in FIG. 15. [Figure 23] FIG. 10 is a schematic diagram of a fourth layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 24] 1 is a structural schematic diagram of a power signal line pattern according to an embodiment of the present disclosure. [Figure 25] FIG. 10 is a schematic diagram of a fifth layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 26] FIG. 26 is a schematic diagram of the layout of the active layer in FIG. 25. [Figure 27] FIG. 26 is a schematic diagram of the layout of the first gate metal layer in FIG. 25. [Figure 28] FIG. 26 is a schematic diagram of the layout of the second gate metal layer in FIG. 25. [Figure 29] FIG. 26 is a schematic diagram of the layout of the source-drain metal layer in FIG. 25. [Figure 30] FIG. 2 is a schematic diagram of a layout of a second source-drain metal layer according to an embodiment of the present disclosure. [Figure 31]FIG. 2 is a schematic diagram of a layout of a second source-drain metal layer and an anode layer according to an embodiment of the present disclosure. [Figure 32] FIG. 10 is a schematic diagram of a sixth layout of sub-pixel areas according to an embodiment of the present disclosure. [Figure 33] FIG. 33 is a schematic diagram of the layout of the second gate metal layer and the second source-drain metal layer in FIG. 32. [Figure 34] 33 is a cross-sectional view taken along the C1C2 direction in FIG. 32. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] To further describe the display panel, the manufacturing method thereof, and the display device according to the embodiments of the present disclosure, The present invention will be described in detail below with reference to the specification and drawings.

[0027] The structure of an AMOLED display panel is a base and a plurality of sub-pixel drivers provided on the base. a driving circuit and a plurality of light-emitting elements provided on the opposite side of the base in the subpixel driving circuit; the light emitting element corresponds to the sub-pixel driving circuit in a one-to-one relationship, and the sub-pixel The driving circuit drives the corresponding light emitting element to emit light, thereby realizing the display function of the display panel. It is intended to

[0028] In the related art, the sub-pixel driving circuit generally comprises a plurality of thin film 1, the sub-pixel driving circuit includes seven thin film transistors M1 to The specific layout method of the seven thin film transistors when M7 is included is shown. When the layout is based on this method, the sub-pixel driving circuit is configured as shown in FIG. the active layer, the first metal layer as shown in FIG. 3, the second metal layer as shown in FIG. 4, and the the active layer includes a third metal layer such that the active layer is formed on the channel area of ​​each thin film transistor. an active pattern (for example, the portion enclosed by the dashed line in FIG. 2) for forming the A doped active pattern (e.g., 2) and the first metal layer is a gate electrode of each thin film transistor. a scanning signal line GATE coupled to the gate; one electrode plate CE1 of a capacitor, a reset signal line RST, and a light emission control signal line EM; The second metal layer is connected to an initialization signal line VINT and a storage capacitor in the subpixel driving circuit. The third metal layer includes the other electrode plate CE2, and the third metal layer includes the data line DATA and the power signal line VD D and several conductive connections (for example, reference numerals 341 to 343).

[0029] It should be noted that, as shown in FIG. 1, the layout of the subpixel driving circuit is In order to realize the connection between the functional patterns provided on the Reference numerals 381 to 388 may be provided.

[0030] As shown in FIGS. 6, 8 and 14, the present disclosure provides a display panel, includes a plurality of sub-pixel driving circuits, a power supply signal line pattern 901, a data line pattern 90 8, gate line pattern 902, light emission control signal line pattern 903, reset signal line pattern 905 and an initialization signal line pattern 904, At least a portion of the data line pattern 908 extends along a second direction, and the gate line pattern 902, the light emission control signal line pattern 903, the reset signal line pattern 9 05, the initialization signal line patterns 904 each extend along a first direction, The first direction intersects with the second direction. The two directions include the Y direction.

[0031] As shown in FIG. 9, the plurality of sub-pixel driving circuits are arranged sequentially along the second direction. a plurality of rows of subpixel driving circuits arranged in the first direction; and a plurality of columns of subpixel driving circuits arranged in the first direction. The sub-pixel driving circuits can be divided into sub-pixel driving circuits, and the sub-pixel driving circuits can be arranged in the same row. The initialization signal line pattern 904 is electrically connected in sequence and formed as an integral structure. The gate line patterns 902 corresponding to the sub-pixel driving circuits located in the same row are sequentially electrically connected. are electrically connected to each other and formed as an integral structure, and correspond to the subpixel driving circuits located in the same row. The light emitting control signal line pattern 903 is electrically connected in sequence and formed as an integral structure. The reset signal line pattern 905 corresponding to the subpixel driving circuit located in the same row is , the sub-pixel driving circuits are electrically connected in sequence, formed as an integral structure, and located in the same column. The data line patterns 908 corresponding to the paths are electrically connected in sequence to form an integral structure. The power supply signal line pattern 901 corresponding to the sub-pixel driving circuit located in the same column is formed. are electrically connected in sequence and formed as an integral structure.

[0032] For example, each row of the sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged sequentially along the X direction. The sub-pixel driving circuit includes the initialization signal line pattern 904, the gate line pattern 902, The light emission control signal line pattern 903 and the reset signal line pattern 905 are both oriented in the X direction. and any of the plurality of subpixel driving circuits included in the subpixel driving circuit of each row extends along The corresponding initialization signal line pattern 904, gate line pattern 902, and light emission control signal line pattern 904 are arranged in parallel. The sub-pixels of each column can be connected to the signal line pattern 903 and the reset signal line pattern 905. each of the pixel driving circuits includes a plurality of sub-pixel driving circuits arranged sequentially along the Y direction; The data line pattern 908 and the power signal line pattern 901 both extend along the Y direction. Each of the plurality of subpixel driving circuits included in the subpixel driving circuit of each column is It can be coupled to the corresponding data line pattern 908 and power signal line pattern 901 .

[0033] It should be noted that in the display panel, the physical partitioning of the sub-pixel areas There are various types of compartments, but below we will give two specific examples of compartmentalization.

[0034] As a first type of partitioning configuration, as shown in FIG. 8, the first transistor T1, The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, Transistor T5, sixth transistor T6 and seventh transistor T7 located at the top of FIG. , as well as the gate line pattern 902, the light emitting control signal line pattern 903, located at the top of FIG. 8. The reset signal line pattern 905' and the initialization signal line pattern 905' located at the top of FIG. 04′ may be divided into one sub-pixel area (i.e., the current sub-pixel area). The second transistor T2 at the bottom in Fig. 8, the seventh transistor T7 at the bottom in Fig. 8 8. The reset signal line pattern 905 located at the bottom of FIG. Any of the line patterns 904 is connected to the next sub-pixel adjacent to the current sub-pixel area along the Y direction. It is divided into areas.

[0035] As a second type of partitioning configuration, as shown in FIG. 8, the first transistor T1 is The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, Transistor T5, sixth transistor T6 and seventh transistor T7 located at the bottom of FIG. , as well as the gate line pattern 902, the light emitting control signal line pattern 903, located at the bottom of FIG. 8. The reset signal line pattern 905 located at the bottom of FIG. 4 may be divided into one sub-pixel area (i.e., the current sub-pixel area). the second transistor T2 at the top in FIG. 8, the seventh transistor T7 at the top in FIG. 8 The reset signal line pattern 905' at the top and the initialization signal line pattern 905' at the top of FIG. Any of the line patterns 904' is connected to the previous sub-pixel area adjacent to the current sub-pixel area along the Y direction. It is partitioned into pixel areas.

[0036] It should be noted that the partitioning form of the sub-pixel area described in the present disclosure is the second type In the second type of partitioning, the current sub-pixel area is The subpixel driving circuit (i.e., the subpixel driving circuit having the corresponding structure in FIG. 6) includes a first transistor. 8, the second transistor T2, the third transistor T3, and the third transistor T4. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the transistors located at the bottom of FIG. 8. The seventh transistor T7 is located at the top of the second transistor T2. The gate 202g is connected to the reset gate 202a in the previous sub-pixel area adjacent to the reset gate 202a in the second direction. The source S2 of the second transistor T2 is connected to the first signal line pattern 905'. The initialization signal line pattern 904′ in the sub-pixel area is connected to the second transistor T2. The drain D2 is coupled to the gate 203g of the third transistor T3.

[0037] As shown in FIGS. 6 and 8, taking one subpixel driving circuit as an example, The circuit includes seven thin film transistors and one capacitor. Each transistor is a P-type transistor, and the first transistor T1 has a double gate structure, and the gate 201g of the first transistor T1 is connected to the gate line The source S1 of the first transistor T1 is coupled to the pattern 902. 3 (i.e., the drive transistor) and the drain D3 of the first transistor T1. The input D1 is coupled to the gate 203g of the third transistor T3.

[0038] The second transistor T2 has a double-gate structure. 02g indicates the reset signal line pattern in the previous sub-pixel area adjacent along the second direction. The source S2 of the second transistor T2 is coupled to the turn 905'. The drain D of the second transistor T2 is connected to the initialization signal line pattern 904' in the rear. 2 is coupled to the gate 203g of the third transistor T3.

[0039] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902; The source S4 of the fourth transistor T4 is coupled to the data line pattern 908. The drain D4 of the transistor T4 is coupled to the source S3 of the third transistor T3.

[0040] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern 903. The source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901. The drain D5 of the transistor T5 is coupled to the source S3 of the third transistor T3.

[0041] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern 903. The source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3. The drain D6 of the sixth transistor T6 is coupled to the anode of the light-emitting element EL.

[0042] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905. The drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL. The source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904. can be.

[0043] The first plate Cst1 of the storage capacitor Cst is connected to the gate 203g of the third transistor T3. The second electrode Cst2 of the storage capacitor Cst is connected to the power supply signal line pattern 901. will be done.

[0044] As shown in FIG. 7, during the operation of the display subpixel driving circuit having the above structure, 7, each of which includes a reset period P1, a write compensation period P2, and a light emission period P3. E1 is the light-emitting signal transmitted on the light-emitting control signal line pattern 903 in the current sub-pixel area. R1 represents the light control signal, and R2 represents the reset signal line pattern 905 in the current sub-pixel area. D1 represents the reset signal transmitted in the current sub-pixel area, and D2 represents the data line pattern in the current sub-pixel area. 908, and G1 represents the gate line pattern in the current sub-pixel area. R1' represents the gate scan signal transmitted on turn 902, and R1' represents the gate scan signal transmitted on the current sub-pixel area. The reset signal line pattern 905' is transmitted in the previous sub-pixel adjacent to the reset signal line pattern 905' in the second direction. Represents the reset signal sent.

[0045] In the first reset period P1, the reset signal input from the reset signal line pattern 905′ The reset signal is at an active level, the second transistor T2 is turned on, and the initial The initialization signal transmitted by the initialization signal line pattern 904' is input to the gate of the third transistor T3. The signal held in the third transistor T3 in the previous frame is input to the third transistor T203g. The gate-source voltage Vgs is cleared, and the gate 203g of the third transistor T3 is A reset is realized.

[0046] In the write compensation period P2, the reset signal input from the reset signal line pattern 905' When the gate signal is at an inactive level, the second transistor T2 is turned off, and the gate line pad The gate scanning signal input from the gate 902 is at an active level, and the first transistor The first transistor T1 and the second transistor T4 are controlled to be turned on, and the data signal is applied to the data line pa The third transistor T3 is turned on through the fourth transistor T4. The first transistor T1 and the fourth transistor T4 are turned on. As a result, the third transistor T3 is formed as a diode structure, and the first transistor The third transistor T1, the third transistor T3 and the fourth transistor T4 cooperate to form a third If threshold voltage compensation for transistor T3 is realized and the compensation time is long enough, The potential of the gate 203g of the transistor T3 finally reaches Vdata+Vth. where Vdata represents the voltage value of the data signal, and Vth represents the third transistor voltage. represents the threshold voltage of transistor T3.

[0047] In the write compensation period P2, the reset signal input from the reset signal line pattern 905 The T7 signal is at an active level, controlling the seventh transistor T7 to turn on; The initialization signal transmitted by the initialization signal line pattern 904 is input to the light emitting element EL. The light is input to the light emitting element EL, and the light emitting element EL is controlled not to emit light.

[0048] During the light emission period P3, the light emission control signal written in the light emission control signal line pattern 903 is activated. active level, the fifth transistor T5 and the sixth transistor T6 are turned on. By controlling the power supply signal transmitted by the power supply signal line pattern 901, the power supply signal is transmitted to the third transistor. The input to the source S3 of the third transistor T3 is connected to the gate 203g of the third transistor T3. By maintaining the voltage at Vdata+Vth, the third transistor T3 is turned on, and the third transistor The gate-source voltage corresponding to transistor T3 is Vdata+Vth-VDD. Here, VDD is a voltage value corresponding to the power supply signal, and is generated based on the gate-source voltage. The generated leakage current flows to the anode of the corresponding light-emitting element EL, Drives the emission of L.

[0049] As shown in FIGS. 10 to 13, when the display subpixel driving circuit is manufactured, The layout of each film layer corresponding to the operating circuit is as follows: The active film layer and the gate insulating film are sequentially stacked in a direction away from the base. an edge layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first This becomes the source / drain metal layer and the third interlayer insulating layer.

[0050] As shown in FIG. 10, the active film layer is a transistor in the display subpixel drive circuit. The channel area (e.g., 101pg to 107pg), the source formation area (e.g., 101ps to 107ps) and drain formation area (e.g., 101pd to 107pd) The purpose is to form an active layer corresponding to the source forming area and the drain forming area. The conductive property of the active film layer is determined by the doping effect. The active film layer is better than amorphous silicon, polysilicon, It should be noted that the source and drain regions may be made of a material other than silicon dioxide, silicon dioxide, or silicon dioxide. The n-type region may be a region doped with n-type impurities or p-type impurities.

[0051] It should also be noted that the areas corresponding to the source and drain forming areas are The active film layer may be used as is as the corresponding source or drain, or The source contacting the source forming area is made of a metal material, and the drain forming area The drain in contact with the anode may be made of a metallic material.

[0052] As shown in FIG. 11, the first gate metal layer is connected to each transistor in the display subpixel driving circuit. The gates (e.g., 201g to 207g) of the display substrate and the gate line patterns included in the display substrate 902, a light emission control signal line pattern 903, a reset signal line pattern 905, etc. and the third transistor T3 in each display subpixel drive circuit is The gate 203g is connected to the first storage capacitor Cst of the display subpixel driving circuit. It is also used as electrode plate Cst1.

[0053] As shown in FIG. 12, the second gate metal layer is a second electrode Cst2 of the second storage capacitor Cst, and for forming the initialization signal line pattern 904 included in the display substrate.

[0054] As shown in FIGS. 6, 8 and 13, the first source-drain metal layer is The source (e.g., S1 to S7) and drain (e.g., D1 -D7), as well as the data line pattern 908 and the power signal line pattern 9 included in the display substrate. 01 and for forming several conductive connections.

[0055] More specifically, still referring to FIGS. 10 to 13, the gate 2 of the first transistor T1 01g covers the first channel area 101pg, and the source S1 of the first transistor T1 is , located in the first source forming area 101ps, and the drain D1 of the first transistor T1 is It is located in the first drain forming area 101pd.

[0056] The gate 202g of the second transistor T2 covers the second channel area 102pg. The source S2 of the second transistor T2 is located in the second source forming area 102ps. The drain D2 of the transistor T2 is located in the second drain formation area 102pd.

[0057] The gate 203g of the third transistor T3 covers the third channel area 103pg. The source S3 of the third transistor T3 is located in the third source forming area 103ps. The drain D3 of the transistor T3 is located in the third drain formation area 103pd.

[0058] The gate 204g of the fourth transistor T4 covers the fourth channel area 104pg. The source S4 of the fourth transistor T4 is located in the fourth source forming area 104ps. The drain D4 of the transistor T4 is located in the fourth drain forming area 104pd.

[0059] The gate 205g of the fifth transistor T5 covers the fifth channel area 105pg. The source S5 of the fifth transistor T5 is located in the fifth source forming area 105ps. The drain D5 of the transistor T5 is located in the fifth drain formation area 105pd.

[0060] The gate 206g of the sixth transistor T6 covers the sixth channel area 106pg. The source S6 of the sixth transistor T6 is located in the sixth source forming area 106ps. The drain D6 of the transistor T6 is located in the sixth drain formation area 106pd.

[0061] The gate 207g of the seventh transistor T7 covers the seventh channel area 107pg. The source S7 of the seventh transistor T7 is located in the seventh source forming area 107ps. The drain D7 of the transistor T7 is located in the seventh drain formation area 107pd.

[0062] The gate 203g of the third transistor T3 is connected to the first plate Cst1 of the storage capacitance Cst. The second electrode Cst2 of the storage capacitor Cst is connected to the power supply signal line pattern 901. do.

[0063] As shown in FIG. 8, in the display panel according to the present disclosure, the second direction (for example, the Y direction) In this case, the gate 204g of the fourth transistor T4 and the gate 20 The gate 202g of the second transistor T2 and the gate 202g of the drive transistor T3 are both connected to the gate That is, it is located on the first side of the gate 203g of the third transistor T3, and the seventh transistor T 7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 , both located on the second side of the gate of the driving transistor. The first and second sides of the gate of the motor are opposite sides along the second direction, and further The first side of the gate of the transistor may be above the gate of the drive transistor, The second side of the gate of the differential transistor may be below the gate of the drive transistor. The bottom side, for example, the side for bonding an IC on the display substrate, The bottom side of the substrate is the bottom side of the gate of the driving transistor. The upper side is the side opposite the lower side, and is the side closest to the IC in the drive transistor. It is the side of the station gate that is farthest from the IC.

[0064] In a first direction (for example, the X direction), the gate 204g of the fourth transistor T4 and The gates 205g of the five transistors T5 are all located on the third side of the gate of the drive transistor. The gate 201g of the first transistor T1 and the gate 206 of the sixth transistor T6 are connected to each other. g are both located on the fourth side of the gate of the driving transistor. The third side and the fourth side of the gate of the motor are opposite sides along the first direction, and further The third side of the gate of the transistor may be to the right of the gate of the drive transistor, The fourth side of the gate of the driving transistor may be to the left of the gate of the drive transistor. For the left and right sides, for example, in the same sub-pixel area, the data line pattern 90 8 is located on the right side of the power supply signal line pattern 901, and the power supply signal line pattern 901 is It is located to the right of line pattern 908.

[0065] Although the display panel can improve the resolution, the improvement effect is limited. Furthermore, as can be seen from FIG. 8, the second transistor T2 and the seventh transistor T7 The conductive portion 909 is connected to the initialization signal line pattern 904 (904') through a via hole. When a high-resolution display panel is combined with a glass substrate, the layout space is small and the space available for drilling holes is limited. Since the size is small, the via holes are not formed due to process variations during the hole drilling process. This causes an opening on the nearby reset signal line pattern 905, which can easily lead to signal disturbance.

[0066] Therefore, in order to solve the above problem, the display panel with high resolution is The pixel structure within the cell needs to be further optimized.

[0067] 15 and 16, an embodiment of the present disclosure is a display panel, comprising a base and a front a functional film layer provided on the base, and a plurality of sub-pixel areas arranged in an array. Further comprising: the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas. 905, the reset signal line pattern 905 extending along a first direction; The initialization signal line layer has an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, and the initialization signal line pattern 904 includes a first body portion 9041 coupled to each other. and a first protruding portion 9042, and the first body portion 9041 is Extending from the first body portion 9041, in the same subpixel area, The projection is a projection of the first protruding portion 9042 on the base and a projection of the reset signal line pas- sage 9043 on the base. and an orthogonal projection of the turn 905 on the base, The conductive connection layer has a conductive connection pattern 909 provided in each of the sub-pixel areas. In the same sub-pixel area, the first end 9091 of the conductive connection pattern 909 and the orthogonal projection of the first protruding portion 9042 on the base. There is a first overlap region F1, and in the first overlap region F1, The first end 9091 is connected to the first protruding portion 9042, and the conductive connection pattern The second end 9092 of 909 couples to the target coupling portion within the subpixel area in which it is located. The orthogonal projection of the reset signal line pattern 905 on the base is Orthogonal projection of the coupling portion on the base and the initialization signal line pattern 904 on the base The display panel is positioned between the orthogonal projection of the image.

[0068] Specifically, the plurality of sub-pixel areas arranged in an array are sequentially arranged along the second direction. A plurality of rows of sub-pixel areas arranged in a row, and a plurality of columns of sub-pixel areas arranged sequentially along a first direction. The sub-pixel areas of each row can be spaced apart along a first direction. The sub-pixel areas in each column are arranged in the second direction. The pixel area includes a plurality of sub-pixel areas spaced apart along the first direction and the second direction. The first direction includes the X direction, and the second direction includes the Y direction. Includes direction.

[0069] The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas. 905, and the reset signal line pattern 905 extends along the first direction. The reset signal line pattern 905 corresponds to the sub-pixel area one-to-one. The bit signal line pattern 905 is located in the corresponding sub-pixel area and is located in the same row. The reset signal line patterns 905 corresponding to the sub-pixel areas are electrically connected in sequence. and formed as a unitary structure.

[0070] The initialization signal line layer has an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, the initialization signal line patterns 904 correspond to the sub-pixel areas one-to-one; The initialization signal line patterns 904 are located in the corresponding sub-pixel areas and are located in the same row. The initialization signal line patterns 904 corresponding to the sub-pixel areas to be placed are sequentially electrically are connected and formed as a unitary structure.

[0071] As shown in FIG. 16, the initialization signal line patterns 904 are all connected to each other. a first body portion 9041 and a first protruding portion 9042, The first pixel areas extend along the first direction and correspond to the sub-pixel areas located in the same row. The first main body portions 9041 of the synchronization signal line pattern 904 are electrically connected in sequence. It should be noted that, taking into account the tolerances in the manufacturing process, The first main body portion does not necessarily have to be a straight body extending along the first direction.

[0072] The specific shape of the first protruding portion 9042 may vary. The first protruding portion 9042 protrudes from the first body portion 9041 to which it is connected. In the same sub-pixel area, the first body portion 9041 The orthogonal projection on the base is a projection of the first protruding portion 9042 on the base. The reset signal line pattern 905 is positioned between the reset signal line pattern 905 and the orthogonal projection of the reset signal line pattern 905 on the base. By doing so, the first protruding portion 9042 is opposite to the reset signal line pattern 905. Therefore, the first protruding portion 9042 and the reset recess 9043 can be provided so as to A large distance can be provided between the signal line pattern 905 and the ground line pattern 906.

[0073] It should be noted that in one initialization signal line pattern 904, the first body portion 90 41 and the first protruding portion 9042 may be formed as an integral structure, but is not limited thereto. I can't.

[0074] The conductive connection layer has a conductive connection pattern 909 provided in each of the sub-pixel areas. The conductive connection pattern 909 corresponds to the sub-pixel area one-to-one, and the conductive Electrical connection patterns 909 are located in the corresponding sub-pixel areas. an orthogonal projection of a first end 9091 of the conductive connection pattern 909 onto the base; The orthogonal projection of one protruding portion 9042 on the base has a first overlap region F1. The first end portion 9091 and the first protruding portion 9042 are disposed in the first overlap region. The connection can be achieved by opening a hole (for example, the first connection hole 70) in the region F1. The second end 9092 of the pattern 909 is a target bond within the sub-pixel area in which it is located. the target coupling portion is coupled to the seventh transistor corresponding to the current sub-pixel area; the first pole of the pixel, and the next sub-pixel adjacent to the current sub-pixel area along the second direction. The area may include a first pole of a second transistor corresponding thereto.

[0075] The target coupling portions may be disposed at various positions, for example, in the same sub-pixel area. The orthogonal projection of the reset signal line pattern 905 onto the base is The orthogonal projection of the junction on the base and the initialization signal line pattern 904 on the base. It may be provided so as to be located between the orthographic projection.

[0076] It should be noted that the display panel has an interlayer medium layer (i.e., the second interlayer insulating layer I The interlayer medium layer further includes a second gate metal layer and a first source metal layer in the display panel. The initialization signal line pattern 904 is located between the second gate electrode and the drain metal layer. It can be placed on the same layer as the metal layer and can be formed in the same patterning process. The conductive connection pattern 909 can be formed in the same layer as the first source / drain metal layer. As described above, the same patterning process can be used. A hole is drilled in the first overlap region F1 to expose the first end 9 of the conductive connection pattern 909. By realizing the coupling between the first protruding portion 9042 and the first protruding portion 9041, the via hole to be produced is , a via hole penetrating the ILD layer, and the position of the via hole is The distance between the pattern 905 becomes greater.

[0077] As can be seen from the specific structure of the display panel described above, the display panel according to the embodiment of the present disclosure has In this case, the initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The conductive connection pattern is configured to include a first protruding portion 9042 on the opposite side. The orthogonal projection of the first end 9091 of the base 909 and the first protruding portion 9042 There is a first overlap region F1 between the orthogonal projection on the base and the first end 90 91 and the first protruding portion 9042 form a hole in the first overlap region F1. According to this configuration, the conductive connection portion and the A via hole for coupling the initialization signal line pattern 904 and the reset signal line pattern The large distance between the turns 905 prevents unevenness during the drilling process. Due to this, the via hole is displaced and opened onto the nearby reset signal line pattern 905. This avoids the problem of signal distortion, and the yield of the display panel is further improved. is suitably guaranteed.

[0078] The initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The first protruding portion 9042 is disposed on the opposite side of the conductive connection portion and the initialization signal line pattern 904. a via hole for coupling to the first protruding portion 9042 is formed in the first protruding portion 9042. Therefore, the orthogonal projection of the via hole on the base is the same as the initialization signal line pattern 90. 4 can be wrapped by orthogonal projection onto the base, so that the initialization The reliability of the connection between the signal line pattern 904 and the conductive connection pattern 909 is suitably improved. This more suitably ensures stability during operation of the display panel.

[0079] As shown in FIGS. 15 and 16, in some embodiments, the display panel comprises: The functional film layer has a plurality of sub-pixel areas, each of which corresponds to a base. A plurality of light emitting elements located on the opposite side; a plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas; Each of the subpixel driving circuits includes a seventh transistor T7, and the seventh transistor The gate 207g of T7 is coupled to the corresponding reset signal line pattern 905, The first pole of the seventh transistor T7 is used as the target coupling part, and the seventh transistor The second pole of the transistor T7 (formed in the 107pd area) extends along the second direction. and a plurality of subpixel drive circuits coupled to the anodes of the corresponding light-emitting elements. Including, The conductive connection pattern 909 has a first end 9091 and a second end 9092. and a second body portion 9093 connected therebetween, the second body portion 9093 being In the same sub-pixel area, the conductive connections extend along the first direction. The first end 9091 of the part pattern 909 is oriented away from the second pole of the seventh transistor. The second body portion 9093 projects in the direction of the arrow A.

[0080] Specifically, the display panel is located on the opposite side of the functional film layer from the base. The light-emitting element further includes a plurality of light-emitting elements, and the plurality of light-emitting elements correspond to the plurality of sub-pixel areas in one-to-one correspondence. The light emitting elements are arranged in a direction away from the base. The display panel includes an anode, a light-emitting pattern, and a cathode, which are stacked together. A drive signal is supplied to the anode and a common signal is supplied to the cathode, An electric field is generated between the anode and the cathode, resulting in the light emission pattern being The light emitting element is controlled to emit light of a color corresponding to the color of the light emitting element. For example, the light emitting element can emit red light. a red light-emitting element capable of emitting green light, a green light-emitting element capable of emitting blue light, This includes blue light emitting elements that can be used.

[0081] The display panel includes a plurality of sub-pixel driving circuits that correspond one-to-one to the plurality of sub-pixel areas. Each of the sub-pixel driving circuits further includes a Illustratively, each of the sub-pixel driving circuits is , each of which includes a seventh transistor, the gate of which is connected to the corresponding reset terminal. The first electrode of the seventh transistor is coupled to the target signal line pattern 905. 909, and the corresponding first conductive connection pattern 909 is used as a first coupling portion. The second electrode of the seventh transistor T7 can be coupled to the first signal line pattern 904. The light emitting element extends along the second direction and is coupled to the anode of the corresponding light emitting element.

[0082] As shown in FIG. 6, the seventh transistor mainly connects the N2 node to the The seventh transistor is for resetting. , through the initialization signal line pattern 904 coupled to the conductive connection portion pattern 909 An initialization signal is supplied, and the initialization signal is transmitted to the N2 node by the seventh transistor. This allows resetting the N2 node. The internal pattern 909 is used as an intermediate layer to realize the jumper, and the conductive connection The connection between the conductive connection pattern 909 and the seventh transistor, and the conductive connection pattern 909 The connection between the pattern 904 and the pattern 906 may be realized by opening a hole. stomach.

[0083] The specific structure of the conductive connection pattern 909 may vary. For example, the conductive connection pattern 909 may have a structure as shown in FIG. Thus, the conductive connection pattern 909 has the first end 9091 and the second end 909 2, the second body portion 9093 comprising: The sub-pixel area may extend along the second direction and may extend along the first direction in the same sub-pixel area. Therefore, the first end 9091 of the conductive connection pattern 909 is connected to the first end 9092 of the seventh transistor. The second body portion 9093 projects away from the two poles. The conductive connection pattern 909 includes a first end 9091 and a seventh end 9092. Since the conductive connection pattern 909 is spaced far from the second pole of the transistor, a via hole for connecting the first end 9091 of the pattern 909 to the initialization signal line pattern 904; When the via hole is formed on the ILD, the via hole is formed at a position away from the second electrode of the seventh transistor. As a result, the distance between the via holes is increased due to process variations during the manufacture of the via holes. As a result, the via hole is misaligned and opened above the second electrode of the seventh transistor, which leads to signal distortion. This is advantageous in avoiding the problem of the display panel becoming easily broken, and the yield of the display panel is further improved. Guaranteed.

[0084] More specifically, as shown in FIG. 15, the second electrode of the seventh transistor is formed by the ploy layer ( That is, the active layer is fabricated, and the conductive connection pattern 909 is formed as the above structure. In this way, during the manufacturing of the via holes, the via holes are prevented from being damaged due to process variations. A hole is opened on the layer corresponding to the second electrode of the seventh transistor, This can more effectively avoid the problem of signal disturbance, and the yield of the display panel can be improved. It is further preferably guaranteed.

[0085] As shown in FIG. 15, in some embodiments, the functional film layer is formed on each sub-pixel area. The data line pattern 908 further includes a data line pattern 908 located at including portions extending along two directions, The initialization signal line pattern 904 is orthogonally projected onto the base, and the conductive connection pattern is and the orthogonal projection of the image 909 on the base has a third overlap region F3. The orthogonal projection of the initialization signal line pattern 904 onto the base and the data line pattern 908 and the orthogonal projection on the base there is a fourth overlap region F4, The second overlapping portion of the initialization signal line pattern 904 in the fourth overlapping region F4 The width L5 along the direction is the width of the initialization signal line pattern in the third overlap region F3. The width L6 of the section 904 in the second direction is smaller than the width L6 of the section 904 in the second direction.

[0086] Specifically, the data line patterns 908 correspond to the sub-pixel areas one-to-one. The data line pattern 908 is located in the corresponding sub-pixel area. The sub-pixel elements 908 include a portion extending along the second direction and are arranged in the same column. The data line patterns 908 corresponding to the rear are electrically connected in sequence to form an integral structure. It is formed by

[0087] The data line pattern 908 extends in the second direction, and the initialization signal line pattern A first body portion 9041 of the shaft 904 extends along the first direction and is and the second direction intersect, so that in a direction perpendicular to the base, the initialization signal line The pattern 904 always overlaps at least a part of the data line pattern 908. It's going to be rapping.

[0088] As described above, the orthogonal projection of the initialization signal line pattern 904 onto the base and the The orthogonal projection of the conductive connection pattern 909 on the base has a third overlap region F 3, and the initialization signal line pattern 904 is orthogonally projected onto the base, and the data line There is a fourth overlap region F4 between the orthogonal projection of the pattern 908 on the base. In both cases, the pattern in front of the initialization signal line pattern 904 in the fourth overlap region F4 The width in the second direction is By configuring the width of the first turn 904 to be smaller than the width of the first turn 904 along the second direction, The synchronization signal line pattern 904 is formed in several areas (specifically, the third overlap area, In the first region F3, the width along the second direction can be narrowed, so that the initialization signal line Reduction of the overlap area between the pattern 904 and the data line pattern 908, parasitic This is advantageous not only for reducing the capacitance value of the capacitor but also for improving the layout of the initialization signal line pattern 904. The output space can be effectively reduced, which is more advantageous in saving pixel space and improving the display performance. This is advantageous for the development of high-resolution panels.

[0089] As shown in FIGS. 15 to 17, in some embodiments, and the orthogonal projection of the second body portion 9093 on the base and the seventh transistor T7 There is a first gap L1 between the orthogonal projection of the second pole on the base, and the first gap is greater than the threshold.

[0090] Specifically, as described above, an orthogonal projection of the second body portion 9093 onto the base; A first gap L1 is formed between the orthogonal projection of the second pole of the seventh transistor T7 on the base. By configuring the second body portion 90 in a direction perpendicular to the base, 93 and the second pole of the seventh transistor T7. .

[0091] In addition, by configuring the first gap L1 to be larger than a threshold value, the second body the orthogonal projection of portion 9093 on the base and the base of the second pole of the seventh transistor; A large distance is provided between the orthogonal projections on the second body portion 9093. Damage to the second electrode of the seventh transistor during the process is preferably avoided. Importantly, the threshold value can be set according to actual needs. For example, the threshold value is 8. μm to 35 μm, and may include the endpoints.

[0092] As shown in FIGS. 15 and 16, in some embodiments, the display panel comprises: Each of the sub-pixel areas has a driving transistor and a second further comprising a plurality of subpixel drive circuits including transistor T2; The gate 202g of the second transistor T2 is connected to the gate of the previous transistor adjacent to the second transistor T2 in the second direction. The reset signal line pattern 905' is coupled to the second transistor in the pixel area. The first pole of T2 is used as the target coupling portion in the previous sub-pixel area, The second pole of the second transistor T2 is connected to the driving transistor (i.e., the third transistor T3) gate, The second transistor T2 is composed of two semiconductors spaced apart along the first direction. portion (located in the region denoted by reference numeral 102pg as shown in FIG. 19), and the two semiconductors a first conductor portion 80 connected to the base of each of the first conductor portions 80; The orthogonal projection on the base of the first protruding portion 9042 in the front sub-pixel area It does not overlap with the orthographic projection in

[0093] Specifically, each of the sub-pixel driving circuits includes a driving transistor and a second transistor. the driving transistor generates a driving signal that drives the light emitting element to emit light. The second transistor gate is arranged adjacent to the front gate along the second direction. is coupled to the reset signal line pattern 905 in the sub-pixel area of ​​the second transistor The first pole of the pixel is used as the target coupling portion in the front sub-pixel area, A second electrode of the second transistor is coupled to the gate of the drive transistor, The transistor is connected to the initialization signal line pattern 904 to which it is coupled before the pixel is charged. The initialization signal provided by the N1 node (coupled to the gate of the driving transistor) ) to achieve a reset for the N1 node.

[0094] Illustratively, the second transistor is optionally a double gate structure, and the second transistor Specifically, the transistor includes two semiconductor portions spaced apart along the first direction, and a first conductor portion 80 connected to the two semiconductor portions, respectively, The conductor portions each correspond to a channel area of ​​the second transistor. The conductor portion and the first conductor portion 80 may be formed as a unitary structure and may be pre-assembled during fabrication. After forming the two semiconductor portions and a third semiconductor portion corresponding to the first conductor portion 80, Then, the third semiconductor portion is doped to form the third semiconductor portion into the first conductor It may be formed as part 80.

[0095] As described above, the orthogonal projection of the first conductor portion 80 onto the base is The orthogonal projection of the first protruding portion 9042 on the base does not overlap the original area. By configuring the initialization signal line pattern 904 and the conductive connection pattern 9 When forming via holes to connect the 09, variations in the process can cause the via If the hole is misaligned and drilled on the first conductor portion 80, it will lead to signal distortion. This can more effectively avoid such problems, and the yield of the display panel can be more effectively guaranteed.

[0096] As shown in FIGS. 15 and 16, in some embodiments, the first conductor portion 80 Orthogonal projection on the base results in the conductive connection pattern 909 in the front sub-pixel area. 9091 on the base.

[0097] Specifically, as described above, the orthogonal projection of the first conductor portion 80 on the base is The base of the first end 9091 of the conductive connection pattern 909 in the previous sub-pixel area The conductive connection pattern 90 is configured to overlap with the orthogonal projection on the The first end 9091 of the 9 is a connecting via hole between it and the initialization signal line pattern 904. Not only can the conductive connection have a larger area for covering the wire, The layout position of the first end 9091 of the pattern 909 and the first conductor portion 80 is closer. It is advantageous for saving pixel space and is also suitable for the development of high resolution display panels. It is advantageous for realization.

[0098] As shown in FIGS. 15 and 16, in some embodiments, each of the initialization signal lines The pattern 904 further includes a second protruding portion 9043 coupled to the first body portion 9041. In the same sub-pixel area, the normal projection of the second protruding portion 9043 on the base The shadow is the result of the orthogonal projection of the first body portion 9041 on the base and the reset signal line pattern. the orthogonal projection of the first conductor portion 80 on the base of the first conductor portion 80. The orthogonal projection on the screen shows the base of the second protruding portion 9043 and / or the first body portion 9041. It overlaps with the orthographic projection on the source.

[0099] Specifically, each of the initialization signal line patterns 904 further includes a second protruding portion 9043. The second protruding portion 9043 may be specifically formed by connecting the first main body portion 9041 and the The second protruding portion 905 may be located between the reset signal line pattern 905. 043, the first protruding portion 9042 and the first body portion 9041 are formed as a unitary structure. It may be made.

[0100] As described above, the orthogonal projection of the first conductor portion 80 on the base is overlapping the orthogonal projection of the first body portion 9043 / or the first body portion 9041 on the base. By configuring in this manner, the initialization signal line pattern 904 does not shield the first conductor portion 80. Therefore, the initialization signals transmitted on the initialization signal line pattern 904 can be safely transmitted. Since the external data signal is a fixed signal, such shielding prevents the The stability of the signal on the first conductor portion 80 can be ensured, and the floating of the first conductor portion 80 When an external data signal changes, the first conductor portion 80 The problem of signal instability is avoided.

[0101] As shown in FIGS. 15 to 17, in some embodiments, the conductive connection pattern 9 909 is a second body portion connected between the first end 9091 and the second end 9092 9093, the second body portion 9093 extending along the second direction; The conductive connection pattern 9 in the previous sub-pixel area of ​​the first conductor portion 80 The end 801 near the end 809 extends along the second direction, and on the base of the end 801 and the second body portion 9093 of the conductive connection pattern 909 on the base. There is a second gap L2 between the orthogonal projection, and the second gap L2 is larger than a threshold value.

[0102] Specifically, the shape of the first conductor portion 80 may be various. For example, 0 has a "gate" structure, i.e., the previous sub-pixel element in the first conductor portion 80 The end 801 of the rear near the conductive connection pattern 909 extends along the second direction. The end 802 of the first conductor portion 80 that is close to the power signal line pattern 901 is A portion of the first conductor portion 80 extending along the second direction and positioned between these two ends extends along the first direction.

[0103] As described above, the conductive portion 80 in the previous sub-pixel area The orthogonal projection of the end 801 near the connection pattern 909 on the base and the conductive connection pattern A second gap L2 is formed between the orthogonal projection of the second body portion 9093 of the base 909 and the second body portion 9093 of the base 909. By configuring the second body portion 90 in a direction perpendicular to the base, 93 and the first conductor portion 80.

[0104] In addition, by configuring the second gap L2 to be larger than a threshold value, The orthogonal projection of the portion 9093 on the base and the orthogonal projection of the first conductor portion 80 on the base A large distance is provided between the projections, and during the process of fabricating the second body portion 9093 Damage to the first conductor portion 80 at the threshold voltage is preferably avoided. can be set according to actual needs, and for example, the threshold value is 8 μm to 35 μm. and may include endpoint values.

[0105] As shown in FIGS. 15 and 16, in some embodiments, an orthogonal projection of a first end 9091 of the conductive connection pattern 909 onto the base; and an orthogonal projection of the first main body portion 9041 of the initialization signal line pattern 904 onto the base. Also, a second overlap region F2 is formed, The functional film layer further includes a first connection hole 70 located in each of the sub-pixel areas, In the pixel area, the orthogonal projection of the first contact hole 70 on the base is The first overlap region F1 and the second overlap region F2 overlap with each other. The first end 9091 of the conductive connection pattern 909 is connected to the first connection hole 70. 9. The signal line pattern 904 is coupled to the signal line pattern 904.

[0106] Specifically, the positive electrode 9091 of the first end 9091 of the conductive connection pattern 909 on the base The shadow is a normal projection of the first protruding portion 9042 of the initialization signal line pattern 904 on the base. The shadow can have a first overlap region F1, and the initialization signal line The orthogonal projection of the first body portion 9041 of the turn 904 onto the base also overlaps the second It may have a region F2.

[0107] The first end 9091 of the conductive connection part is connected to the initialization signal line pin 70 through the first connection hole. When the first connecting hole 70 is connected to the turn 904, the orthogonal projection of the first connecting hole 70 on the base is The first overlap region F1 and the second overlap region F2 overlap each other. In this way, the layout space of the first connection hole 70 can be reduced. The conductive connection pattern 909 and the initialization pattern can be connected with each other with a high degree of accuracy. I can attest to this.

[0108] As shown in FIG. 18, in some embodiments, the The orthogonal projection of one conductor portion 80 onto the base 40 corresponds to the first conductor portion 80 in the front sub-pixel area. It does not overlap with the orthogonal projection of the connection hole 70 on the base 40 .

[0109] Specifically, as described above, the base of the first conductor portion 80 of the second transistor The orthogonal projection on the pixel 40 shows the base 4 of the first contact hole 70 in the front sub-pixel area. 0 and the orthographic projection on the first contact hole. In addition, due to process variations, the via hole may be misaligned and opened on the first conductor portion 80. This can more effectively avoid the problem of the signal being easily disturbed by the interference of the light. The yield is further ensured.

[0110] As shown in FIGS. 15 and 16, in some embodiments, the functional film layer The power supply signal line layer further includes a power supply signal line provided in each of the sub-pixel areas. a power signal line pattern 901, at least a portion of which is oriented in a second direction; Extending along, The conductive connection pattern 90 in the previous sub-pixel area of ​​the first conductor portion 80 The end 802 far from the 9 extends along the second direction, and on the base of the end 802 The orthogonal projection of the power supply signal line pattern 901 located in the same sub-pixel area It is completely covered by the orthographic projection above.

[0111] Specifically, the power signal line pattern 901 corresponds to the sub-pixel area one-to-one, The power supply signal line pattern 901 is located in the corresponding sub-pixel area. The power supply signal line patterns 901 provided in the pixel area are arranged sequentially along the second direction. and can be formed as a unitary structure.

[0112] As described above, the conductive portion 80 in the previous sub-pixel area The end 802 far from the connection portion pattern 909 extends along the second direction, and the end 80 2, the orthogonal projections of the power supply signal line patterns on the base are located in the same sub-pixel area. 901 on the base, the orthogonal projection of the The source signal line pattern 901 is located in the first conductor portion 80 in the previous sub-pixel area. The end far from the conductive connection pattern 909 can be shielded. Since the power signals transmitted over the 01 are all stable signals, such shielding does not This ensures that the signal on the first conductor portion 80 remains stable when the external data signal changes. Due to the floating of one conductor portion 80, a capacitance coupling occurs when the external data signal changes. The problem of signal instability in the first conductor portion 80 due to the effect of the ring is avoided.

[0113] Furthermore, according to the above configuration method, the first conductive portion and the power signal line pattern 901 This effectively reduces the layout space occupied by the display, advantageously reducing the pixel structure. This will be advantageous as display panels become more highly resolute.

[0114] The power signal line pattern 901 may have various structures, as shown in FIG. In this embodiment, the power signal line pattern 901 extends along the second direction and The width of the power supply signal line pattern 901 along the direction perpendicular to the second direction is approximately uniform. It may be configured as follows.

[0115] As shown in FIGS. 23 and 24, in some other embodiments, the display panel includes: a plurality of subpixel driving circuits each corresponding to the plurality of subpixel areas; Each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor is , a first electrode plate and a second electrode plate provided opposite to each other, The second electrode plate is opposite to the base of the first substrate. a plurality of subpixel driving circuits located on the side of the pixel; The functional film layer further includes a power supply signal line layer, and the power supply signal line layer is connected to each of the sub-pixel areas. The power supply signal line pattern 901 is provided in the At least a part of the power supply signal line pattern 901 extends along the second direction, and the power supply signal line pattern 901 is connected to the first power supply unit 9011 and a second power supply unit 9012, The orthogonal projection of the first power supply unit 9011 on the base is located in the same sub-pixel area. When each of the reset signal line patterns 905 overlaps with an orthogonal projection on the base, Both on the base of each of the gate line patterns 902 located in the same sub-pixel area The orthogonal projection of the second power supply unit 9012 on the base overlaps with the orthogonal projection of the second power supply unit 9012 on the base. The orthogonal projection and overlap of the second electrode Cts2 of the storage capacitance Cts on the base The width L3 of the first power supply unit 9011 is equal to the width L4 of the second power supply unit 90 12 smaller than width L4.

[0116] Specifically, each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor Ct s, and a first plate Cts1 of the storage capacitance Cts may be connected to a driving transistor The second electrode Cts2 of the storage capacitor is also used as the gate of the first electrode It is located on the opposite side of the base in Cts1 and can form a facing area with the first electrode plate. It is Noh.

[0117] The power signal line pattern 901 is specifically a first power supply unit 9011 and a second power supply unit 9021. 12, for example, the first power supply unit 9011 and the second power supply unit 9012 The first and second portions are alternately arranged along the second direction, and adjacent first and second portions are joined together. For example, the first power supply unit 9011 and the second power supply unit 9012 are formed as an integral structure. It is done.

[0118] The specific layout positions of the first power supply unit 9011 and the second power supply unit 9012 may vary. and exemplarily, the orthogonal projection of the first power supply unit 9011 on the base is The orthogonal projection and overlay of each of the reset signal line patterns 905 located in the area on the base are The gate line patterns 902 overlap and are located in the same sub-pixel area. and the orthogonal projection of the second power supply unit 9012 on the base. The orthogonal projection of the second electrode plate of the storage capacitor on the base overlaps with the orthogonal projection of the second electrode plate of the storage capacitor on the base. As described above, the first power supply unit 90 is configured to 11 is configured to be smaller than the width of the second power supply unit 9012, Since the width of the first power supply unit 9011 along the first direction is effectively narrowed, The overlap area between 9011 and the reset signal line pattern 905 is reduced. At the same time, the overlap between the first power supply part 9011 and the gate line pattern 902 As a result, the area of ​​the power supply signal line pattern 901 and the reset signal line is reduced. The coupling capacitance occurring between them is effectively reduced.

[0119] It should be noted that the width of the first power supply part 9011 in the first direction is The maximum or minimum distance between two opposing boundaries of the first power supply unit 9011 along the direction Similarly, the width of the second power supply unit 9012 along the first direction is the distance from the first power supply unit 9012 to the first power supply unit 9012. The maximum or minimum distance between two opposing boundaries of the second power supply unit 9012 along the direction is.

[0120] Please note that in FIG. 25, the current power supply signal line pattern 901 is connected to the first power supply unit. 9011 and the corresponding eight sub-pixel elements when the second power supply unit 9012 is used. The first connection hole 70 shown in FIG. 25 is a schematic diagram of the rear. The actual diameter of the first connection hole is shown in Fig. 25. The specific position where the first connection hole is formed may be determined by the above. an orthogonal projection of a first end 9091 of the conductive connection pattern 909 onto the base; Even if the signal line pattern 904 is located in an overlapping area with the orthogonal projection on the base, good.

[0121] 26 is a schematic diagram of the active layer in FIG. 25, and FIG. 27 is a schematic diagram of the active layer in FIG. 25. 25. FIG. 28 is a schematic diagram of the first gate metal layer in FIG. 25. 29 is a schematic diagram of the first source-drain metal layer in FIG. 25; 0 is a second source / drain metal layer when the display panel includes a second source / drain metal layer; FIG. 1 is a schematic diagram of eight sub-pixel areas corresponding to metal layers.

[0122] It should be noted that, as shown in FIGS. 30 and 31, the second source / drain metal layer Specifically, it may include a power compensation pattern 300 and an adapter pattern 310. The power supply compensation pattern 300 includes a horizontal connection portion 3001 and a vertical connection portion 3002. The power supply compensation pattern 300 reduces IR drop on the power supply signal line pattern. The power supply signal line pattern is connected to the power supply signal line pattern included in the display panel, and the adapter panel The adapter pattern 310 corresponds to the anode included in the display panel in one-to-one correspondence. The anode 310 has a corresponding anode 320 and a drive signal for supplying the anode 320 with a drive signal. This is for connecting the sub-pixel driving circuit for the pixel shifter.

[0123] In a specific embodiment, referring to FIG. 34, the adapter pattern 310 and the display pattern A second adapter pattern 906 may be further provided between the anode included in the panel. Preferably, the second adapter pattern 906 is located in the first source-drain metal layer.

[0124] It should be noted that the first source-drain metal layer and / or the second source-drain metal layer A passivation layer may be further provided on the metal layer, and the passivation layer may include For example, inorganic materials such as silicon nitride and silicon oxide may be used. There are no particular restrictions on this.

[0125] Continuing with reference to FIGS. 30 to 32, the display panel further includes a pixel defining layer; A pixel opening 330 is formed in the pixel defining layer, and the pixel opening 330 is connected to the anode 32 0, and each pixel aperture 330 corresponds to at least one of the corresponding anodes 320. The organic light-emitting material layer included in the display panel is used to expose the corresponding portions. It is formed in the pixel opening 330 .

[0126] It should be noted that the display panel may include sub-pixels of multiple colors, and different The light emitted by the light emitting elements corresponding to the color sub-pixels has different colors. Each pixel unit of the panel has one red sub-pixel R, two green sub-pixels G and one blue sub-pixel 31 and 32 show the different color sub-pixels in one pixel unit. The layout method of the pixel unit, that is, the arrangement method of the GGRB pixels, is shown.

[0127] Of course, the pixel unit in the display panel has one red sub-pixel R and one green sub-pixel G. and one blue sub-pixel B. The pixel unit of this structure specifically includes: A rip (strip) RGB arrangement may be used, i.e., the one red sub-pixel R, One green subpixel G and one blue subpixel B are arranged in sequence along the same direction (for example, the X direction). Or, the pixel unit of this structure is specifically arranged as follows: For example, one red sub-pixel R and one blue sub-pixel B may be The green subpixel G is located in the same row along the X direction, and the green subpixel G is located in a different row along the X direction. do.

[0128] Referring to FIG. 33, FIG. 33 shows a second gate metal layer and a second source electrode corresponding to FIG. In some embodiments, the lane metal layers correspond to different color sub-pixels. The orthogonal projection of the adapter pattern 310 onto the base and the corresponding second pole of the storage capacitor Even if the overlap area with the orthogonal projection of the plate Cst2 on the base is configured to be different, good.

[0129] More specifically, referring to FIGS. 32 and 33, the adapter pins 111 and 112 are connected to the red sub-pixel R. The orthogonal projection of the turn 310 on the base and the corresponding second plate Cst2 of the storage capacitor A first overlap area J1 is formed between the orthogonal projection on the base and the green sub-pixel G. Correspondingly, the orthogonal projection of the adapter pattern 310 onto the base and the corresponding storage capacitance A second overlap area J2 is formed between the second electrode plate Cst2 and the orthogonal projection of the second electrode plate Cst2 on the base. The orthogonal projection of the adapter pattern 310 on the base corresponds to the blue subpixel B. and the orthogonal projection of the second electrode Cst2 of the corresponding storage capacitor on the base, a third overhang is formed. The second overlap area J2 is formed by overlapping the first overlap area J3. The first overlap area J1 is smaller than the third overlap area J2. The tip area is smaller than J3.

[0130] According to the above configuration method, the power supply signal line patterns 901 corresponding to pixel units of different colors The RC loading can be better balanced. .

[0131] 34 is a cross-sectional view taken along the C1C2 direction in FIG. 34 and the base 40 in the sixth drain forming area 106pd (i.e., the active area of ​​the area The conductive layer is for forming the drain of the sixth transistor T6) Other film layers, such as a buffer layer, may also be included but are not shown in FIG. A gate insulating layer 41, a second gate insulating layer 42, an interlayer insulating layer 43, a first planar layer 44 and a second planar layer 45 are formed. A flat layer 45 is also shown.

[0132] As shown in FIGS. 15 and 21, in some embodiments, the functional film layer The power supply signal line layer further includes a power supply signal line provided in each of the sub-pixel areas. a power signal line pattern 901, at least a portion of which is oriented in a second direction; Extending along, The functional film layer further includes an auxiliary power supply layer, and the auxiliary power supply layer is provided in each of the sub-pixel areas. the auxiliary power supply pattern 60 is attached to the base of the The projection and the positive polarity of the power supply signal line pattern 901 located in the same sub-pixel area on the base There is an overlapping area between the auxiliary power supply pattern 60 and the power supply signal line. The pattern 901 is joined in the overlapping region.

[0133] Specifically, the auxiliary power supply pattern 60 corresponds to the sub-pixel area one-to-one, and The auxiliary power supply pattern 60 is located in the corresponding sub-pixel area. The pattern 60 is provided so as to be in the same layer and made of the same material as the second electrode plate of the storage capacitor. That is, they can be formed in the same patterning process.

[0134] When the auxiliary power supply pattern 60 is laid out, the base of the auxiliary power supply pattern 60 and the base of the power supply signal line pattern 901 located in the same sub-pixel area. There is an overlapping area between the auxiliary power supply pattern 60 and the orthographic projection above. The signal line pattern 901 is connected to the signal line pattern 902 through a via hole provided in the overlap region. It may be configured to be interlockable.

[0135] As described above, the auxiliary power supply pattern 60 and the power supply signal line pattern 901 are coupled. By configuring it so that the RC (resistance capacitance) lo on the power supply signal line pattern 901 The IR dro on the power supply signal line pattern 901 is suitably reduced. p (voltage drop) is reduced, so that the stability of the display panel operation is better guaranteed. .

[0136] As shown in FIGS. 15 and 19, in some embodiments, the display panel includes Each of the sub-pixel areas has a driving transistor and a second transistor. a plurality of subpixel drive circuits including a plurality of subpixel transistors; The gate of the second transistor is connected to a previous sub-pixel area adjacent to the first sub-pixel area in the second direction. , and the first electrode of the second transistor is coupled to the reset signal line pattern 905 in used as the target coupling portion in the front sub-pixel area, The second pole of the motor includes a first electrode portion 51 and a second electrode portion 52 coupled to each other, and the first electrode The first electrode portion 51 extends along a second direction, and the second electrode portion 52 extends along a third direction. The third direction intersects both the first direction and the second direction, and the first electrode portion 51 is located between the semiconductor portion of the second transistor and the second electrode portion 52, and the second The electrode portion 52 is coupled to the gate of the driving transistor, The orthogonal projection of the first electrode portion 51 on the base and the orthogonal projection of the second electrode portion 52 on the base Any orthogonal projection on the base is obtained by orthogonal projection of the corresponding auxiliary power supply pattern 60 on the base. It is covered with

[0137] Specifically, the second electrode of the second transistor is coupled to the gate of the driving transistor. For example, the second electrode is specifically a first electrode connected to each other. The first electrode portion 51 may be connected to the second transistor. The second electrode portion 52 is located between the semiconductor portion of the driving It is coupled to the gate of the transistor.

[0138] The specific layout of the first electrode portion 51 and the second electrode portion 52 may be various. For example, Illustratively, the first electrode portion 51 extends along a second direction, and the second electrode portion 52 extends along a third direction. The third direction intersects both the first direction and the second direction. As described above, the orthogonal projection of the first electrode portion 51 on the base and the second electrode portion 5 The orthogonal projection of each of the auxiliary power supply patterns 60 on the base is By configuring it so that it is covered by the orthogonal projection on the top, the potential of the N1 node is stable. In addition, the second electrode of the second transistor and the power signal line pattern 90 The layout space that needs to be occupied by a pixel structure is effectively reduced, It is advantageously scaled down and takes advantage of the development of high resolution display panels.

[0139] As shown in FIGS. 15 and 21, in some embodiments, the auxiliary power supply pattern 6 0 represents the first auxiliary sub-pattern 601 and the second auxiliary sub-pattern 602 that are connected to each other. the first auxiliary sub-pattern 601 extends along a second direction; and the second auxiliary sub-pattern At least a portion of the pattern 602 extends along the first direction, and the first auxiliary sub-pattern The orthogonal projection of the turn 601 on the base is the orthogonal projection of the first electrode portion 51 on the base. This covers the shadow and the orthogonal projection of the second electrode portion 52 on the base.

[0140] Specifically, the auxiliary power supply pattern 60 may have various specific structures. The auxiliary power supply pattern 60 includes a first auxiliary sub-pattern 601 and a second auxiliary sub-pattern 602 which are coupled to each other. pattern 602, the first auxiliary sub-pattern 601 and the second auxiliary sub-pattern 602 may be formed as a unitary structure.

[0141] For example, the first auxiliary sub-pattern 601 extends along the second direction, and the second auxiliary sub-pattern 602 extends along the second direction. At least a part of the auxiliary sub-pattern 602 extends along the first direction, The auxiliary power supply pattern 60 is formed in a substantially L-shape.

[0142] Since the auxiliary power supply pattern 60 is coupled to the power supply signal line pattern 901, The auxiliary power supply pattern 60 must have a stable potential. The orthogonal projection of one auxiliary sub-pattern 601 on the base is The orthogonal projection of the second electrode portion 52 on the base is configured to cover the orthogonal projection of the second electrode portion 52 on the base. This not only ensures stability of the potential of the N1 node, but also the second pole of the motor, the power signal line pattern 901 and the auxiliary power pattern 60 This effectively reduces the layout space that needs to be allocated, resulting in a favorable reduction in the pixel structure. , the development of high resolution of the display panel will be advantageous.

[0143] In some embodiments, the first auxiliary sub-pattern 601 along the first direction The width of each of the power supply signal line patterns 901 is larger than the width of the corresponding power supply signal line pattern 901 .

[0144] As described above, the width of the first auxiliary sub-pattern 601 is equal to the width of the corresponding power signal line pattern. By configuring the width of the auxiliary power supply pattern 60 to be larger than the width of the turn 901, Since the power signal line pattern 901 has a larger area, the IR dro p, and the auxiliary power supply pattern 60 and the power supply signal line pattern 901 is advantageous.

[0145] As shown in FIGS. 15, 19 and 22, in some embodiments, the first electrode portion The orthogonal projection of the first electrode portion 51 on the base and the orthogonal projection of the second electrode portion 52 on the base are both are also covered by the orthogonal projection of the corresponding power supply signal line patterns 901 on the base.

[0146] As described above, the orthogonal projection of the first electrode portion 51 on the base and the second electrode portion 5 The orthogonal projections of the two patterns on the base are the same as the base of the corresponding power supply signal line pattern 901. By configuring it so that it is covered by the orthogonal projection on the base, the potential of the N1 node is stabilized. In addition, the second pole of the second transistor and the power signal line pattern 90 The layout space that needs to be occupied by a pixel structure is effectively reduced, It is advantageously scaled down and takes advantage of the development of high resolution display panels.

[0147] In some embodiments, the functional film layer includes a gate line pattern located in each sub-pixel area. 902, a light-emitting control signal line pattern 903, and , along the second direction, the gate line pattern 902 and the light emitting control signal line pattern 903 The reset signal line pattern 905 and the initialization signal line pattern 904 are arranged in sequence. The functional film layer includes a power supply signal line pattern 901 and a device pattern 902 located in each sub-pixel area. The power supply signal line pattern 901 and the data line pattern 908 are connected to each other. Each of the sections 908 includes a portion that extends along the second direction.

[0148] The display panel includes light-emitting elements that correspond one-to-one to the plurality of sub-pixel areas, and Each of the sub-pixel areas has a driving transistor, a first transistor, and a a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and and a subpixel driving circuit including a seventh transistor.

[0149] In the same sub-pixel area, the gate of the driving transistor is connected to the first transistor. the first electrode of the drive transistor is coupled to the second electrode of the fifth transistor; a second pole of the drive transistor coupled to a first pole of the first transistor; the gate of the first transistor is coupled to the gate line pattern 902; The gate of the second transistor is connected to a previous sub-pixel area adjacent to the first sub-pixel area in the second direction. , and the first electrode of the second transistor is coupled to the reset signal line pattern 905 in used as the target coupling portion in the front sub-pixel area, a second pole of the capacitor coupled to the gate of the drive transistor; The gate of the fourth transistor is coupled to the gate line pattern 902. The first electrode of the transistor is coupled to the data line pattern 908, and the fourth transistor a second pole of the capacitor coupled to a first pole of the drive transistor; The gate of the fifth transistor is coupled to the light emitting control signal line pattern 903. a first electrode of the fifth transistor is coupled to the power signal line pattern 901; The gate of the sixth transistor is coupled to the light emitting control signal line pattern 903. a first electrode of the sixth transistor coupled to a second electrode of the drive transistor; a second electrode of the transistor is coupled to the corresponding light emitting element; The second electrode of the seventh transistor is coupled to the light emitting element, The gate is coupled to the reset signal line pattern 905, and the first The pole is coupled to a second initialization signal line pattern 904 .

[0150] Exemplarily, each of the sub-pixel driving circuits includes seven thin film transistors and one Each transistor included in the sub-pixel driving circuit is a P-type transistor. The driving transistor is the third transistor. The first pole of the transistor is the source and the second pole of each transistor is the drain.

[0151] As shown in FIGS. 6, 15, 19 to 22, the first transistor T1 is a double-gate The gate 201g of the first transistor T1 is coupled to the gate line pattern 902. The source S1 of the first transistor T1 is connected to the third transistor T3 (i.e., the driving transistor The drain D1 of the first transistor T1 is coupled to the drain D3 of the third transistor T2. The gate 203g of transistor T3 is coupled to the gate 203g of transistor T3.

[0152] The second transistor T2 has a double-gate structure. 02g indicates the reset signal line pattern in the previous sub-pixel area adjacent along the second direction. The source S2 of the second transistor T2 is coupled to the turn 905'. used as the target coupling portion in the rear and the initialization signal in the front sub-pixel area The drain D2 of the second transistor T2 is connected to the line pattern 904'. The gate 203g of the first transistor T1 is coupled to the gate 203g of the second transistor T2.

[0153] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902; The source S4 of the fourth transistor T4 is coupled to the data line pattern 908. The drain D4 of the transistor T4 is coupled to the source S3 of the third transistor T3.

[0154] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern 903. The source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901. The drain D5 of the transistor T5 is coupled to the source S3 of the third transistor T3.

[0155] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern 903. The source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3. The drain D6 of the sixth transistor T6 is coupled to the anode of the corresponding light-emitting element EL. can be.

[0156] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905. The drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL. The source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904. can be.

[0157] The pixel driving circuit further includes a storage capacitor Cst, and a first electrode Cs of the storage capacitor Cst t1 is also used as the gate 203g of the third transistor T3, and is the second The electrode plate Cst2 is coupled to the power supply signal line pattern 901.

[0158] In the subpixel driving circuit according to the above embodiment, there is a possibility that the process may vary during the hole drilling process. As a result, the via hole is misaligned and opened onto the nearby reset signal line pattern 905, This not only avoids the problem of signal distortion, but also improves the yield of the display panel. In addition, the size of the pixel structure using the sub-pixel driving circuit can be reduced. This is advantageous in realizing high resolution of the display panel.

[0159] An embodiment of the present disclosure further provides a display device including the display panel according to the above embodiment. .

[0160] In the display panel according to the above disclosed embodiment, the initialization signal line pattern 904 The first protruding portion 9042 is configured to be on the side opposite to the bit signal line pattern 905. and a first end 9091 of the conductive connection pattern 909 projected onto the base. and the orthogonal projection of the first protruding portion 9042 on the base, there is a first overlap region. The first end 9091 and the first protruding portion 9042 are connected to the first overhanging portion 9041. Since the structure is such that connection is possible by drilling holes in the wrap area F1, this structure According to the method, a conductive connection portion and an initialization signal line pattern 904 are connected to each other. A large distance is provided between the via hole and the reset signal line pattern 905. As a result, during the hole drilling process, the via hole may shift due to process variations, causing damage to the surrounding area. There is a problem that the reset signal line pattern 905 is opened, which easily leads to signal disturbance. This can avoid the above-mentioned problems and further ensure the yield of the display panel.

[0161] The initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The first protruding portion 9042 is disposed on the opposite side of the conductive connection portion and the initialization signal line pattern 904. a via hole for coupling to the first protruding portion 9042 is formed in the first protruding portion 9042. Therefore, the orthogonal projection of the via hole on the base is the same as the initialization signal line pattern 90. 4 can be wrapped by orthogonal projection onto the base, so that the initialization The reliability of the connection between the signal line pattern 904 and the conductive connection pattern 909 is suitably improved. This more suitably ensures stability during operation of the display panel.

[0162] Therefore, when the display device according to the embodiment of the present disclosure includes the display panel, the display panel may be similarly This has the following beneficial effects, which will not be repeated here.

[0163] It should be noted that the display device may be a television, a display, a digital photo frame, Any product or part with a display function, such as a mobile phone or tablet PC. .

[0164] The embodiment of the present disclosure provides a method for manufacturing a display panel according to the above embodiment. The present invention further provides a method for fabricating a semiconductor device, the method comprising: A functional film layer is fabricated on the base to form a plurality of sub-pixel areas arranged in an array. This includes: the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas. 905, the reset signal line pattern 905 extending along a first direction; The initialization signal line layer has an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, and the initialization signal line pattern 904 includes a first body portion 9041 coupled to each other. and a first protruding portion 9042, and the first body portion 9041 is Extending from the first body portion 9041, in the same subpixel area, The projection is a projection of the first protruding portion 9042 on the base and a projection of the reset signal line pas- sage 9043 on the base. and an orthogonal projection of the turn 905 on the base, The conductive connection layer has a conductive connection pattern 909 provided in each of the sub-pixel areas. In the same sub-pixel area, the first end 9091 of the conductive connection pattern 909 and the orthogonal projection of the first protruding portion 9042 on the base. There is a first overlap region F1, and in the first overlap region F1, The first end 9091 is connected to the first protruding portion 9042, and the conductive connection pattern The second end 9092 of 909 couples to the target coupling portion within the subpixel area in which it is located. The orthogonal projection of the reset signal line pattern 905 on the base is Orthogonal projection of the coupling portion on the base and the initialization signal line pattern 904 on the base It is located between the orthographic projection of

[0165] Specifically, the plurality of sub-pixel areas arranged in an array are sequentially arranged along the second direction. A plurality of rows of sub-pixel areas arranged in a row, and a plurality of columns of sub-pixel areas arranged sequentially along a first direction. The sub-pixel areas of each row can be spaced apart along a first direction. The sub-pixel areas in each column are arranged in the second direction. The pixel area includes a plurality of sub-pixel areas spaced apart along the first direction and the second direction. The first direction includes the X direction, and the second direction includes the Y direction. Includes direction.

[0166] The reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas. 905, and the reset signal line pattern 905 extends along the first direction. The reset signal line pattern 905 corresponds to the sub-pixel area one-to-one. The bit signal line pattern 905 is located in the corresponding sub-pixel area and is located in the same row. The reset signal line patterns 905 corresponding to the sub-pixel areas are electrically connected in sequence. and formed as a unitary structure.

[0167] The initialization signal line layer has an initialization signal line pattern 90 provided in each of the sub-pixel areas. 4, the initialization signal line patterns 904 correspond to the sub-pixel areas one-to-one; The initialization signal line patterns 904 are located in the corresponding sub-pixel areas and are located in the same row. The initialization signal line patterns 904 corresponding to the sub-pixel areas to be placed are sequentially electrically are connected and formed as a unitary structure.

[0168] Each of the initialization signal line patterns 904 is connected to the first body portion 90 41 and a first protruding portion 9042, and the first body portion 9041 extends in the first direction. The initialization signal line patterns 9 extend along the same line, and correspond to the sub-pixel areas located in the same row. The first body portion 9041 in 04 is electrically connected in series and formed as a unitary structure. It should be noted that, in consideration of the tolerances in the manufacturing process, the first body portion is necessarily It is not necessarily a linear type extending along the first direction.

[0169] The specific shape of the first protruding portion 9042 may vary. The first protruding portion 9042 protrudes from the first body portion 9041 to which it is connected. In the same sub-pixel area, the first body portion 9041 The orthogonal projection on the base is a projection of the first protruding portion 9042 on the base. The reset signal line pattern 905 is positioned between the reset signal line pattern 905 and the orthogonal projection of the reset signal line pattern 905 on the base. By doing so, the first protruding portion 9042 is opposite to the reset signal line pattern 905. Therefore, the first protruding portion 9042 and the reset recess 9043 can be provided so as to A large distance can be provided between the signal line pattern 905 and the ground line pattern 906.

[0170] It should be noted that in one initialization signal line pattern 904, the first body portion 9 041 and the first protruding portion 9042 may be formed as an integral structure, but is not limited thereto. It will not be done.

[0171] The conductive connection layer has a conductive connection pattern 909 provided in each of the sub-pixel areas. The conductive connection pattern 909 corresponds to the sub-pixel area one-to-one, and the conductive Electrical connection patterns 909 are located in the corresponding sub-pixel areas.

[0172] an orthogonal projection of a first end 9091 of the conductive connection pattern 909 onto the base; The orthogonal projection of the first protruding portion 9042 on the base has a first overlap region F1. The first end portion 9091 and the first protruding portion 9042 are overlapped by the first overlapping portion 9091. The second end of the conductive connection pattern 909 can be connected by drilling a hole in the region F1. 9092 is coupled to the target coupling portion in the sub-pixel area where it is located, and The dot junction connects the first pole of the seventh transistor corresponding to the current sub-pixel area and the current A second transistor corresponding to the next sub-pixel area adjacent to the sub-pixel area along the second direction The first pole of the transistor may be included.

[0173] The target coupling portions may be disposed at various positions, for example, in the same sub-pixel area. The orthogonal projection of the reset signal line pattern 905 onto the base is The orthogonal projection of the junction on the base and the initialization signal line pattern 904 on the base. It may be provided so as to be located between the orthographic projection.

[0174] It should be noted that the display panel has an interlayer medium layer (i.e., the second interlayer insulating layer I The interlayer medium layer further includes a second gate metal layer and a first source metal layer in the display panel. The initialization signal line pattern 904 is located between the second gate electrode and the drain metal layer. It can be placed on the same layer as the metal layer and can be formed in the same patterning process. The conductive connection pattern 909 can be formed in the same layer as the first source / drain metal layer. As described above, the same patterning process can be used. A hole is drilled in the first overlap region F1 to expose the first end 9 of the conductive connection pattern 909. By realizing the coupling between the first protruding portion 9042 and the first protruding portion 9041, the via hole to be produced is , a via hole penetrating the ILD layer, and the position of the via hole is The distance between the pattern 905 becomes greater.

[0175] In the display panel manufactured using the manufacturing method according to the embodiment of the present disclosure, the initialization signal line The pattern 904 has a first protruding portion 9 on the side opposite to the reset signal line pattern 905. 042, and the first end 909 of the conductive connection pattern 909 an orthogonal projection of the first protruding portion 9041 on the base; and an orthogonal projection of the first protruding portion 9042 on the base. There is a first overlap region F1, and the first end 9091 and the first protruding portion 9 042 can be connected by drilling holes in the first overlap region F1. According to this configuration, the conductive connection portion and the initialization signal line pattern 90 4 and the reset signal line pattern 905. The distance reduces the risk of via holes being formed due to process variations during the drilling process. The hole is opened on the nearby reset signal line pattern 905, which easily leads to signal disturbance. This avoids the problem of the display panel becoming thinner, and the yield of the display panel is further ensured.

[0176] The initialization signal line pattern 904 is opposite to the reset signal line pattern 905. The first protruding portion 9042 is disposed on the opposite side of the conductive connection portion and the initialization signal line pattern 904. a via hole for coupling to the first protruding portion 9042 is formed in the first protruding portion 9042. Therefore, the orthogonal projection of the via hole on the base is the same as the initialization signal line pattern 90. 4 can be wrapped by orthogonal projection onto the base, so that the initialization The reliability of the connection between the signal line pattern 904 and the conductive connection pattern 909 is suitably improved. This more suitably ensures stability during operation of the display panel.

[0177] It should be noted that each example herein is described in an incremental manner. The same or similar parts of each embodiment can be referred to each other, and each embodiment can be used in conjunction with other embodiments. The explanation focuses on the differences between the two. Although the present invention is briefly described due to its similarity to the product embodiment, the relevant portions are Please refer to the explanation section.

[0178] Unless otherwise defined, technical or scientific terms used in this disclosure are understood by those skilled in the art. As used in this disclosure, "first," "second," and similar terms have their ordinary meanings. It is not intended to imply any order, quantity or importance, but rather to distinguish between different components. The terms "comprise" or "include" or similar terms refer only to the elements described before the term. or element includes the elements or elements listed after that term and their equivalents, but does not include other elements It does not mean excluding any or all of the components. The term is not limited to physical or mechanical connections, but may refer to either direct or indirect connections. "Top," "bottom," "left," "right," etc., refer to relative positions. If the absolute position of the object to be explained changes, the relative positional relationship also changes accordingly. There is a possibility that it will become

[0179] It is understood that an element such as a layer, film, region, or substrate may be "above" or "below" another element. When an element is referred to as being located on or above another element, it does not mean that the element is located "directly" "above" or "below" another element. Alternatively, an intermediate element may be interposed.

[0180] In the description of the above embodiments, specific features, structures, materials or characteristics may be used in any one or more In several embodiments or examples, they may be combined in any suitable manner.

[0181] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Those skilled in the art will readily appreciate that modifications and substitutions may occur within the technical scope of the present disclosure. However, all of these modifications and substitutions should be considered to fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be according to the appended claims.

Claims

1. A display panel, comprising: a base; a functional film layer provided on the base; and a plurality of sub-pixel areas arranged in an array; the functional film layer includes a reset signal line layer, an initialization signal line layer, and a conductive connection layer; the reset signal line layer includes a reset signal line pattern provided in each of the sub-pixel areas, the reset signal line pattern extending along a first direction; the initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas, the initialization signal line pattern including a first body portion and a first protruding portion coupled to each other, the first body portion extending along the first direction, and in the same sub-pixel area, an orthogonal projection of the first body portion on the base is located between an orthogonal projection of the first protruding portion on the base and an orthogonal projection of the reset signal line pattern on the base; the conductive connection layer includes a conductive connection pattern provided in each of the sub-pixel areas, and in the same sub-pixel area, there is a first overlap region between an orthogonal projection of a first end of the conductive connection pattern on the base and an orthogonal projection of the first protruding portion on the base, and in the first overlap region, the first end is coupled to the first protruding portion and a second end of the conductive connection pattern is coupled to a target coupling portion in the sub-pixel area where the first end is located, and the orthogonal projection of the reset signal line pattern on the base is located between the orthogonal projection of the target coupling portion on the base and the orthogonal projection of the initialization signal line pattern on the base; the functional film layer further includes a power supply signal line layer, the power supply signal line layer including a power supply signal line pattern provided in each of the sub-pixel areas, at least a portion of the power supply signal line pattern extending along a second direction; The display panel includes: further comprising a plurality of subpixel driving circuits each including a driving transistor and a second transistor, the subpixel driving circuits corresponding to the plurality of subpixel areas in a one-to-one relationship; a gate of the second transistor is coupled to the reset signal line pattern in a previous sub-pixel area adjacent along the second direction, a first pole of the second transistor is used as the target coupling portion in the previous sub-pixel area, and a second pole of the second transistor is coupled to the gate of the driving transistor; The display panel includes: a plurality of subpixel driving circuits corresponding one-to-one to the plurality of subpixel areas, each of the subpixel driving circuits including a driving transistor and a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate provided opposite to each other, the first electrode plate also serving as a gate of the driving transistor, and the second electrode plate being located on the opposite side of the first electrode plate from the base; the functional film layer further includes a power supply signal line layer, the power supply signal line layer including a power supply signal line pattern provided in each of the sub-pixel areas, at least a portion of the power supply signal line pattern extending along the second direction, the power supply signal line pattern including a first power supply unit and a second power supply unit; a display panel, wherein an orthogonal projection of the first power supply unit on the base overlaps with an orthogonal projection of each of the reset signal line patterns located in the same sub-pixel area and also overlaps with an orthogonal projection of each of the gate line patterns located in the same sub-pixel area, and an orthogonal projection of the second power supply unit on the base overlaps with an orthogonal projection of a corresponding second electrode plate of the storage capacitor on the base, and a width of the first power supply unit along the first direction is smaller than a width of the second power supply unit.

2. The display panel includes: a plurality of light-emitting elements that correspond one-to-one to the plurality of sub-pixel areas and are located on the opposite side of the base in the functional film layer; a plurality of subpixel driving circuits corresponding to the plurality of subpixel areas in a one-to-one relationship, each of the subpixel driving circuits including a seventh transistor, a gate of the seventh transistor coupled to the corresponding reset signal line pattern, a first pole of the seventh transistor used as the target coupling portion, and a second pole of the seventh transistor extending along the second direction and coupled to the anode of the corresponding light-emitting element; the conductive connection pattern further includes a second body portion connected between the first end and the second end, the second body portion extending along the second direction, and in the same sub-pixel area, a first end of the conductive connection pattern protruding from the second body portion along the first direction in a direction away from the second pole of the seventh transistor; The display panel according to claim 1 .

3. the functional film layer further includes a data line pattern located in each sub-pixel area, the data line pattern including a portion extending along the second direction; a third overlap region between the orthogonal projection of the initialization signal line pattern on the base and the orthogonal projection of the conductive connection portion pattern on the base; a fourth overlap region between the orthogonal projection of the initialization signal line pattern on the base and the orthogonal projection of the data line pattern on the base; 3. The display panel of claim 2, wherein a width of the initialization signal line pattern in the fourth overlap region along the second direction is smaller than a width of the initialization signal line pattern in the third overlap region along the second direction.

4. 3. The display panel of claim 2, wherein in the same subpixel area, there is a first gap between the orthogonal projection of the second body portion on the base and the orthogonal projection of the second pole of the seventh transistor on the base, and the first gap is greater than 8 μm.

5. 2. The display panel of claim 1, wherein the second transistor includes two semiconductor portions spaced apart along the first direction and first conductor portions connected to the two semiconductor portions, respectively, and a positive projection of the first conductor portion on the base does not overlap a positive projection of the first protruding portion on the base in the previous subpixel area.

6. 6. The display panel of claim 5, wherein each of the initialization signal line patterns further includes a second protruding portion coupled to the first body portion, and in the same subpixel area, a orthogonal projection of the second protruding portion on the base is located between a orthogonal projection of the first body portion on the base and a orthogonal projection of the reset signal line pattern on the base, and a orthogonal projection of the first conductor portion on the base overlaps with a orthogonal projection of the second protruding portion on the base.

7. the functional film layer further includes a power supply signal line layer, the power supply signal line layer including a power supply signal line pattern provided in each of the sub-pixel areas, and at least a portion of the power supply signal line pattern extending along the second direction; The display panel according to claim 5 .

8. the display panel further includes a plurality of subpixel driving circuits, each of which corresponds to the plurality of subpixel areas in a one-to-one relationship, and each of which includes a driving transistor and a second transistor; a gate of the second transistor is coupled to the reset signal line pattern in an adjacent previous sub-pixel area along the second direction, a first pole of the second transistor is used as the target coupling portion in the previous sub-pixel area, a second pole of the second transistor includes a first electrode portion and a second electrode portion coupled to each other, the first electrode portion extends along the second direction and the second electrode portion extends along a third direction, the third direction intersects both the first direction and the second direction, the first electrode portion is located between a semiconductor portion of the second transistor and the second electrode portion, and the second electrode portion is coupled to the gate of the driving transistor; The display panel according to claim 1 .

9. 9. The display panel according to claim 8, wherein the orthogonal projection of the first electrode portion on the base and the orthogonal projection of the second electrode portion on the base are both covered by the orthogonal projection of the corresponding power signal line pattern on the base.

10. the functional film layer includes a gate line pattern and a light-emitting control signal line pattern located in each sub-pixel area, and in the same sub-pixel area, the gate line pattern, the light-emitting control signal line pattern, the initialization signal line pattern, and the reset signal line pattern are sequentially arranged along the second direction; the functional film layer further includes a power supply signal line pattern and a data line pattern located in each sub-pixel area, and the power supply signal line pattern and the data line pattern each include a portion extending along the second direction; The display panel includes: a light-emitting element that corresponds one-to-one to the plurality of sub-pixel areas; further comprising subpixel driving circuits each corresponding to the plurality of subpixel areas, the subpixel driving circuits each including a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; In the same subpixel area, the gate of the driving transistor is coupled to the second pole of the first transistor, the first pole of the driving transistor is coupled to the second pole of the fifth transistor, and the second pole of the driving transistor is coupled to the first pole of the first transistor; a gate of the first transistor is coupled to the gate line pattern; a gate of the second transistor is coupled to the reset signal line pattern in a previous sub-pixel area adjacent along the second direction, a first pole of the second transistor is used as the target coupling portion in the previous sub-pixel area, and a second pole of the second transistor is coupled to the gate of the driving transistor; a gate of the fourth transistor is coupled to the gate line pattern, a first pole of the fourth transistor is coupled to the data line pattern, and a second pole of the fourth transistor is coupled to the first pole of the driving transistor; a gate of the fifth transistor is coupled to the light emitting control signal line pattern, and a first electrode of the fifth transistor is coupled to the power supply signal line pattern; a gate of the sixth transistor is coupled to the light emitting control signal line pattern, a first electrode of the sixth transistor is coupled to a second electrode of the driving transistor, and a second electrode of the sixth transistor is coupled to a corresponding light emitting element; 2. The display panel of claim 1, wherein a second electrode of the seventh transistor is coupled to the light-emitting element, a gate of the seventh transistor is coupled to the reset signal line pattern, and a first electrode of the seventh transistor is coupled to a second initialization signal line pattern.

11. A display device comprising the display panel according to any one of claims 1 to 10.

Images