gaming machines

Abstract

To provide a game machine improved in a control in which a program to be executed is switched.SOLUTION: Interruption processing is constituted by a main routine (interruption), and a sub routine (interruption) called from the main routine (interruption) and executed. An IY register of plural registers used in the interruption processing is used by the sub routine (interruption) but not used by the main routine (interruption).SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to gaming machines such as pachinko machines and slot machines. [Background technology]

[0002] One gaming machine proposed for this type is capable of executing a basic process that is repeatedly executed for each unit of play, and an interrupt process that interrupts the basic process at regular time intervals to perform processing (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-39538 Summary of the Invention [Problem to be solved by the invention]

[0004] As in the gaming machine described in Patent Document 1, there is room for improvement in terms of data confusion in the control of switching between executed programs.

[0005] An object of the present invention is to provide a gaming machine with improved control over switching between programs to be executed. [Means for solving the problem]

[0006] The gaming machine of claim 1 comprises: In a gaming machine for playing games, a program execution means for executing a program using a plurality of registers; the program is composed of a main program, a first subprogram called and executed by the main program, and a second subprogram called and executed by the main program; a shared register among the plurality of registers is used by both the first subprogram and the second subprogram; a predetermined register among the plurality of registers is used by at least one of the first sub-program and the second sub-program, and is not used by the main program; The shared registers are also used by the main program. It is characterized by the following.

[0007] Furthermore, the present invention may have only the invention-specific matters set forth in the claims of the present invention, or may have the invention-specific matters set forth in the claims of the present invention as well as configurations other than the invention-specific matters. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a front view of a slot machine according to an embodiment of the present invention; [Figure 2] FIG. 1 is a block diagram showing the configuration of a slot machine. [Figure 3] FIG. 2 is a diagram showing a memory map of a ROM and a RAM of a main control unit. [Figure 4] FIG. 10 is a diagram illustrating the relationship between an internal capacity area and an external capacity area. [Figure 5] FIG. 2 is a diagram illustrating a register. [Figure 6] FIG. 2 is a diagram for explaining the correspondence between various processes and each register. [Figure 7] FIG. 2 is a diagram for explaining the correspondence between basic processes and each register. [Figure 8] FIG. 10 is a diagram for explaining the correspondence between interrupt processing and each register. [Figure 9] FIG. 10 is a diagram for explaining a modified example of a register. [Figure 10] 10A and 10B are diagrams for explaining the correspondence between in-capacity processing, out-capacity processing, and a shared register in a modified example of a register. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A gaming machine according to the present invention will be described below with reference to the following examples.

[0010] [Form 1] The gaming machine of type 1-1 is In a gaming machine (slot machine 1) for playing games, A program execution means (main control unit 41) is provided for executing a program using a plurality of registers, The specific program (interrupt processing) among the programs is composed of a main program (main routine (interrupt)) and a subprogram (subroutine (interrupt)) that is called and executed from the main program, Of the plurality of registers, a predetermined register (IY register) is used in the subprogram (subroutine (interrupt)) and is not used in the main program (main routine (interrupt)). It is characterized by the following. According to this feature, the specific program is composed of a main program and a subprogram that is called and executed from the main program, and a predetermined register among the multiple registers is used by the subprogram and not by the main program, thereby preventing data stored in the predetermined register from becoming confused between the main program and the subprogram.

[0011] The gaming machine of form 1-2 is the gaming machine according to form 1-1, The subprogram (subroutine (interrupt)) includes a plurality of types of subprograms, The predetermined register (IY register) is used in any one of the plurality of types of subprograms. It is characterized by the following. According to this feature, it is possible to prevent data stored in a predetermined register from being confused between the main program and a subprogram that uses the predetermined register among a plurality of subprograms.

[0012] The gaming machines of types 1-3 are: In a gaming machine (slot machine 1) for playing games, A program execution means (main control unit 41) is provided for executing a program using a plurality of registers, The specific program (interrupt processing) among the programs is composed of a main program (main routine (interrupt)) and a subprogram (subroutine (interrupt)) that is called and executed from the main program, Among the plurality of registers, a specific register (D'E' register) is used in the main program (main routine (interrupt)) and is not used in the subprogram (subroutine (interrupt)). It is characterized by the following. According to this feature, the specific program is composed of a main program and a subprogram that is called and executed from the main program, and among the multiple registers, the specific register is used by the main program and not by the subprogram, so that data stored in the specific register can be prevented from being confused between the main program and the subprogram.

[0013] The gaming machine of form 1-4 is the gaming machine according to form 1-3, The subprogram (subroutine (interrupt)) includes a plurality of types of subprograms, The specific register (D'E' register) is not used in any of the multiple types of subprograms. It is characterized by the following. According to this feature, it is possible to prevent data stored in specific registers from being mixed up between the main program and any type of subprogram.

[0014] A gaming machine of form 1-5 is a gaming machine according to any one of forms 1-1 to 1-4, The specific program is an interrupt program (interrupt processing) that is executed when an interrupt occurs. It is characterized by the following. This feature makes it possible to prevent data stored in registers between the main program and the subprogram from becoming mixed up during execution of the interrupt program.

[0015] [Form 2] The gaming machine of type 2-1 is In a gaming machine (slot machine 1) for playing games, A program execution means (main control unit 41) is provided for executing a program using a plurality of registers, The program includes a basic program (basic processing) and an interrupt program (interrupt processing) that is executed by interrupting the execution of the basic program, When executing the basic program (basic processing), a first register (table register) is used, The register used when executing the interrupt program (interrupt processing) is switched from the first register (front register) to the second register (back register), Returning the register used when terminating the interrupt program (interrupt processing) from the second register (back register) to the first register (front register), The plurality of registers include a special register (IX register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register), The special register (IX register) is used in the basic program (basic processing) and is not used in the interrupt program (interrupt processing). It is characterized by the following. According to this feature, the basic program uses the first register, but during the execution of an interrupt program that interrupts the basic program and is executed, the register used switches from the first register to the second register, and the multiple registers include a special register that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but the special register is used by the basic program and not by the interrupt program, so it is possible to prevent data stored in the special register from becoming confused between the basic program and the interrupt program.

[0016] A gaming machine according to aspect 2-2 is a gaming machine according to aspect 2-1, the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register), None of the shared registers (IX register, IY register) including the special register (IX register) is used in the interrupt program (interrupt processing). It is characterized by the following. According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but none of the multiple shared registers, including the special registers, are used in the interrupt program, thereby preventing confusion of data stored in the shared registers, including the special registers, between the basic program and the interrupt program.

[0017] A gaming machine according to aspect 2-3 is a gaming machine according to aspect 2-1, the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register), At least the special register (IX register) among the plurality of shared registers (IX register, IY register) is not used in the second program (interrupt processing). It is characterized by the following. According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but at least the special registers among the multiple shared registers are not used in the interrupt program, thereby preventing confusion between the basic program and the interrupt program over the data stored in at least the special registers.

[0018] The gaming machines of type 2-4 are: In a gaming machine (slot machine 1) for playing games, A program execution means (main control unit 41) is provided for executing a program using a plurality of registers, The program includes a basic program (basic processing) and an interrupt program (interrupt processing) that is executed by interrupting the execution of the basic program, When executing the basic program (basic processing), a first register (table register) is used, The register used when executing the interrupt program (interrupt processing) is switched from the first register (front register) to the second register (back register), Returning the register used when terminating the interrupt program (interrupt processing) from the second register (back register) to the first register (front register), the plurality of registers include a special register (IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register), The special register (IY register) is used in the interrupt program (interrupt processing) and is not used in the basic program (basic processing). It is characterized by the following. According to this feature, the basic program uses the first register, but during the execution of an interrupt program that interrupts the basic program and is executed, the register used switches from the first register to the second register, and the multiple registers include a special register that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but the special register is used by the interrupt program and not by the basic program, so it is possible to prevent data stored in the special register from becoming confused between the basic program and the interrupt program.

[0019] A gaming machine according to aspect 2-5 is a gaming machine according to aspect 2-4, the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register), None of the shared registers (IX register, IY register) including the special register (IY register) are used in the basic program (basic processing). It is characterized by the following. According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but none of the multiple shared registers, including the special registers, are used in the basic program, thereby preventing data stored in shared registers, including the special registers, from becoming mixed up between the basic program and the interrupt program.

[0020] A gaming machine according to aspect 2-6 is a gaming machine according to aspect 2-4, the plurality of registers include a plurality of shared registers (IX register, IY register) that can be used when executing the basic program (basic processing) and when executing the interrupt program (interrupt processing) in addition to the first register (front register) and the second register (back register), Of the multiple shared registers (IX register, IY register), at least the special register (IY register) is not used in the basic program (basic processing). It is characterized by the following. According to this feature, the multiple registers include multiple shared registers that can be used when executing both the basic program and the interrupt program, separate from the first and second registers, but at least the special registers among the multiple shared registers are not used in the basic program, thereby preventing confusion between the basic program and the interrupt program over the data stored in at least the special registers.

[0021] A gaming machine according to any one of the aspects 2-1 to 2-6 is a gaming machine according to the aspect 2-7. When the interrupt program (interrupt processing) is executed, a value is set in the second register (back register). It is characterized by the following. According to this feature, when an interrupt program is executed, a new value is set instead of the value originally stored in the second register, thereby preventing the interrupt program from being executed with an unintended value.

[0022] [Form 3] The gaming machine of type 3-1 is In a gaming machine (slot machine 1) for playing games, A program execution means (main control unit 41) is provided for executing a program using a plurality of registers, The programs include a first program (in-capacity program (in-capacity processing)) and a second program (out-of-capacity program (out-of-capacity processing)) that is called and executed by the first program, When the second program (out-of-capacity program (out-of-capacity processing)) is executed, data of the plurality of registers is saved, and when the second program (out-of-capacity program (out-of-capacity processing)) is terminated, the saved data of the plurality of registers is restored; When the first program (in-memory program (in-memory processing)) is executed, a specific number of registers among the plurality of registers are used, When the second program (out-of-capacity program (out-of-capacity processing)) is executed, a number of registers (a part of the registers used by the in-capacity program (in-capacity processing)) that is less than the specific number of registers among the plurality of registers is used. It is characterized by the following. According to this feature, when the second program is executed, data in multiple registers is saved, and when the second program is terminated, the saved data in multiple registers is restored. Furthermore, when the second program is executed, fewer registers are used than when the first program is executed, so that the second program can be prevented from using incorrect data.

[0023] The gaming machine of form 3-2 is the gaming machine according to form 3-1, the first program (in-capacity program (in-capacity processing)) includes a first specific program (in-capacity processing (basic processing)) and a first predetermined program (in-capacity processing (interrupt processing)); the second program (out-of-capacity program (out-of-capacity processing)) includes a second specific program (out-of-capacity processing (basic processing)) that is called and executed from the first specific program (in-capacity processing (basic processing)), and a second predetermined program (out-of-capacity processing (interrupt processing)) that is called and executed from the first predetermined program (in-capacity processing (interrupt processing)); When the first specific program (in-capacity processing (basic processing)) is executed, a first specific number of registers among the plurality of registers are used, When the second specific program (out-of-capacity processing (basic processing)) is executed, a number of registers among the plurality of registers that is less than the first specific number (a part of the registers used by the out-of-capacity processing (basic processing)) are used, When the first predetermined program (interrupt processing) is executed, a second specific number of registers among the plurality of registers are used; When the second predetermined program (out-of-capacity processing (interrupt processing)) is executed, a number of registers among the plurality of registers that is less than the second specific number (a part of the registers used by the out-of-capacity processing (interrupt processing)) are used. It is characterized by the following. According to this feature, when the second specific program is executed, fewer registers are used than when the first specific program is executed, and when the second predetermined program is executed, fewer registers are used than when the first predetermined program is executed, thereby preventing the second specific program and the second predetermined program from using incorrect data.

[0024] [Form 4] The gaming machine of type 4-1 is In a gaming machine (slot machine 1) for playing games, A program execution means (main control unit 41) for executing a program; A stack area for saving data, Equipped with The programs include a first program (in-capacity program (in-capacity processing)) and a second program (out-of-capacity program (out-of-capacity processing)) that is called and executed by the first program, the stack area includes a first stack area (internal stack area) for saving data by the first program (internal program (internal processing)), and a second stack area (external stack area) for saving data by the second program (external program (external processing)); when executing the second program (out-of-capacity program (out-of-capacity processing)), a stack pointer indicating a data save address is switched from the first stack area (internal stack area) to the second stack area (external stack area), and when terminating the second program (out-of-capacity program (out-of-capacity processing)), the stack pointer is returned to the first stack area (internal stack area); When the second program (out-of-capacity program (out-of-capacity processing)) is terminated, all data saved in the second stack area (out-of-capacity stack area) during execution of the second program is restored. It is characterized by the following. According to this feature, when the second program is executed, the stack pointer is switched from the first stack area to the second stack area, and when the second program is terminated, the stack pointer is returned to the first stack area. Furthermore, when the second program is terminated, all data that was saved in the second stack area during execution of the second program is restored, and then the stack pointer is returned to the first stack area. This prevents the second program from being executed again while the data used in the second program that was previously executed remains saved, and prevents confusion between the data used in the second program that was previously executed and the data that will be used in the second program that is currently being executed.

[0025] The gaming machine of form 4-2 is the gaming machine according to form 4-1, the second program (out-of-capacity program (out-of-capacity processing)) includes a plurality of types of second programs, When the second program is terminated, all data saved in the second stack area (extra-capacity stack area) during execution of the second program is restored, regardless of the type of the second program. It is characterized by the following. According to this feature, when the second program is terminated, regardless of the type of second program, all data saved in the second stack area during execution of the second program is restored, and then the stack pointer is returned to the first stack area. Therefore, regardless of the type of second program, it is possible to prevent confusion between data used in the second program executed last time and data to be used in the second program executed this time. [Example]

[0026] An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. As shown in Fig. 1, the slot machine 1 of this embodiment comprises a cabinet 1a with an open front and a front door 1b pivotally supported on a side edge of the cabinet 1a. Inside the slot machine 1, reels 2L, 2C, and 2R are arranged horizontally, each having the same number of different, mutually distinguishable symbols arranged in a predetermined order. As shown in Fig. 1, three consecutive symbols among the symbols arranged on the reels 2L, 2C, and 2R are displayed in three rows (top, middle, and bottom) in a see-through window 3 provided approximately in the center of the front of the slot machine 1 so as to be visible to the player.

[0027] In this embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, or a configuration using four or more reels may also be used. In this embodiment, the variable display unit that variably displays symbols is configured using reels 2L, 2C, and 2R, but the variable display unit may be something other than a reel. For example, the variable display unit may be configured to variably display symbols by moving a belt on the outer periphery of which multiple symbols are arranged. In this embodiment, the variable display unit is configured using physical reels, but the variable display unit may also be configured using an image display device such as a liquid crystal display.

[0028] As shown in FIG. 1, on the front of the slot machine 1, there are provided, each operable by the player, a medal insertion port 4 into which medals can be inserted, a medal payout port 9 from which medals are paid out, a MAXBET switch 6 which is operated to use credits (the number of medals stored as the gaming value owned by the player) to set the maximum bet number among a specified number of bets determined according to the gaming status within that range, a settlement switch 10 which is operated to settle the medals stored as credits and the medals used to set the bet number (to return the medals used to set the credits and the bet number), a start switch 7 which is operated to start the game, stop switches 8L, 8C, 8R which are operated to stop the rotation of reels 2L, 2C, 2R, respectively, and a performance switch 56 which is used for performances.

[0029] As shown in FIG. 1, on the front of the slot machine 1, there is provided a game display unit 13 which is provided with a credit indicator 11 which displays the number of medals stored as credits, a game auxiliary indicator 12 which displays the number of medals paid out when a win occurs, an error code indicating the content of an error when an error occurs, and operation information (navigation notification) corresponding to the operation mode of the stop switches 8L, 8C, and 8R, a 1BET LED 14 which lights up to indicate that the number of bets has been set to 1, a 2BET LED 15 which lights up to indicate that the number of bets has been set to 2, a 3BET LED 16 which lights up to indicate that the number of bets has been set to 3, a start valid LED 18 which lights up to indicate that the start operation of the game by operating the start switch 7 is valid, a zone indicator LED 19 which lights up to indicate that the game zone is controlled to a favorable zone, and a replay in progress LED 20 which lights up to indicate that a replay game is in progress.

[0030] Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see Figure 2) which lights up to indicate that the operation of setting the bet number by operating the MAXBET switch 6 is valid, and inside the stop switches 8L, 8C, 8R there are provided left, center, and right stop valid LEDs 22L, 22C, 22R (see Figure 2) which light up to indicate that the operation of stopping the reels by the corresponding stop switches 8L, 8C, 8R is valid.

[0031] A liquid crystal display 51 capable of displaying images is provided on the front of the slot machine 1. The liquid crystal display 51 has a liquid crystal panel that is transparent when no voltage is applied to the liquid crystal elements, and is provided so that its display area is located in front of the reels 2L, 2C, and 2R of the front door 1b (on the player's side). The reels 2L, 2C, and 2R on the back side of the liquid crystal display 51 can be seen from the player's side through the transparent area of ​​the display area of ​​the liquid crystal display 51 that corresponds to the see-through window 3 and through the see-through window 3.

[0032] On the inside of the front door 1b of the slot machine 1, there are provided a reset switch 23 that detects a reset operation to release an error state from outside the slot machine 1 by operating a predetermined key, a setting value display 24 that displays the setting value at that time while the setting value is being changed or checked, a door open detection switch 25 that detects the open state of the front door 1b, a flow path switching solenoid 30 that selectively switches the flow path of medals inserted from the medal insertion port 4 to either the hopper tank side or the medal payout outlet 9 side provided inside the slot machine 1, and a medal selector 29 having inserted medal sensors 31a to 31c that detect medals inserted from the medal insertion port 4 and flowing down to the hopper tank side.

[0033] Also provided inside the slot machine 1 are a reel unit 34 for rotating or stopping the aforementioned reels 2L, 2C, and 2R in response to a control signal from the main control unit 41, and a hopper unit 35 for paying out medals from the medal payout outlet 9 in response to a control signal from the main control unit 41.

[0034] Also provided inside the slot machine 1 are a setting key switch 37 for switching between a setting change state and a setting confirmation state, a reset / setting switch 38 which functions as a reset switch for canceling an error state under normal circumstances and functions as a setting switch for changing the set value of the winning probability (ball payout rate) of the internal lottery described below in the setting change state, and a power switch 39 which is operated to turn the power on / off.

[0035] Inside the slot machine 1, with the gaming control board 40 attached at a predetermined position inside the cabinet 1a, a gaming machine information display 50 (not shown) consisting of a four-digit seven-segment display is disposed below the front side (player side) of the gaming control board 40. With the gaming control board 40 sealed in a board case, the display content of the gaming machine information display 50 can be seen from outside the board case, and gaming machine information based on the game history of the slot machine 1, which is compiled by the main control unit 41 and displayed on the gaming machine information display 50, can be recognized by store staff and the like.

[0036] As shown in Figure 2, the slot machine 1 is provided with a game control board 40 and a presentation control board 90, and the game is controlled by the game control board 40, and the presentation control board 90 controls the presentation according to the game status.

[0037] The game control board 40 is connected to the aforementioned MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, inserted medal sensors 31a to 31c, reel sensor (not shown) of reel unit 34, payout sensor and full sensor (not shown) of hopper unit 35, setting key switch 37, and reset / setting switch 38, and detection signals from these connected switches etc. are input.

[0038] In addition, the game control board 40 is connected to the aforementioned credit indicator 11, game auxiliary indicator 12, 1 to 3 BET LEDs 14 to 16, start valid LED 18, section display LED 19, replay in progress LED 20, BET switch valid LED 21, left, center, right stop valid LEDs 22L, 22C, 22R, setting value indicator 24, flow path switching solenoid 30, reel unit 34, and hopper unit 35, and these electrical components and the game machine information indicator 50 mounted on the game control board 40 are driven based on the control of the main control unit 41 mounted on the game control board 40 and described below.

[0039] A main control unit 41 that controls games is also mounted on the game control board 40. The main control unit 41 includes a CPU 41a for performing calculations, a ROM 41b for storing programs and the like, and a RAM 41c for temporarily storing work data, and performs various controls according to the programs stored in the ROM 41b.

[0040] The CPU 41a executes instructions at addresses specified by a program counter in the programs stored in the ROM 41b. The program counter is incremented and updated each time an instruction is completed, so instructions stored in the ROM 41b are executed in order starting from the instruction specified at the address with the smallest value.

[0041] The main control unit 41 includes a plurality of registers used by the CPU 41a for performing arithmetic operations. The plurality of registers include an accumulator register (A register), a flag register (F register), general-purpose registers (B register, C register, D register, E register, H register, L register), index registers (IX register, IY register), an interrupt register (I register), a refresh register (R register), a stack pointer register (SP register), a program counter register (PC register), a transmit register, and other registers. Among these registers, the accumulator register, flag register, and general-purpose register each include a front register and a back register configured to form a pair (hereinafter, the front register and the back register may be simply referred to as registers). The CPU 41a executes various instructions, such as arithmetic instructions and read instructions, included in a program, to update the value of a specified register or to update a value (data) stored in a storage area of ​​the RAM 41c specified by the value (address) of the specified register.

[0042] In addition, the flag register among the registers provided in the main control unit 41 is configured so that its state changes to indicate the result of the calculation by the instruction executed by the CPU 41a, and by utilizing the change in the state of the flag register, the CPU 41a can perform processing according to the result of the calculation by the previous instruction.

[0043] In addition, the flag register is composed of multiple bits (8 bits in this embodiment), and the multiple bits include a first bit (hereinafter sometimes referred to as a zero flag) and a second bit (hereinafter sometimes referred to as a carry flag) whose state can be changed depending on the calculation result of the calculation instruction executed by the CPU 41a in order to reduce the processing burden on the CPU 41a.

[0044] Furthermore, the main control unit 41 transmits various commands to the sub-control unit 91. Commands transmitted from the main control unit 41 to the sub-control unit 91 are sent in only one direction, and commands are never transmitted from the sub-control unit 91 to the main control unit 41.

[0045] Furthermore, the main control unit 41 repeatedly loops processing according to the control state until the detection state of the various switches connected to the game control board 40 changes, and executes basic processing that transitions stepwise in response to changes in the detection state of the various switches. The main control unit 41 also interrupts the basic processing and executes interrupt processing every time a timer interrupt occurs (approximately 0.56 milliseconds in this embodiment). The execution interval of the interrupt processing is set to a time longer than the combined time of the processing required to complete one cycle of the basic processing repeated according to the control state and the execution time of the interrupt processing, so that at least one cycle of the processing required to complete one cycle of the control state is guaranteed between the current and next interrupt processing.

[0046] In addition, the main control unit 41 can back up the values ​​of the registers provided in the main control unit 41 by storing them in a predetermined order in the stack area of ​​RAM 41c indicated by the stack pointer SP, and can restore the state of the corresponding register to the state when it was backed up by sequentially reading the register values ​​that were backed up in the stack area of ​​RAM 41c from the stack area in the reverse order to when they were backed up and setting them in the registers corresponding to that order.

[0047] The performance control board 90 is connected to the aforementioned performance switch 56, and its detection signal is input thereto. In addition, performance devices such as the aforementioned liquid crystal display 51, a speaker capable of outputting sound, and a performance LED 57 used for performance and visible to the player are connected to the performance control board 90, and the output states of these performance devices can be controlled by a sub-controller 91 mounted on the performance control board 90. The sub-controller 91 receives commands sent from the main control unit 41 and detection signals from the performance switch 56, and performs various controls for producing performances.

[0048] The slot machine 1 of this embodiment is configured to change the medal payout rate according to a setting value. Specifically, the medal payout rate is changed by using the winning probability according to the setting value in a lottery that affects the player's advantage, such as an internal lottery or an AT lottery. The setting value has six levels, from 1 to 6, with 6 being the highest payout rate, and the payout rate decreasing as the value decreases in the order of 5, 4, 3, 2, and 1. In other words, when 6 is set as the setting value, the player has the highest advantage, and the advantage gradually decreases as the value decreases in the order of 5, 4, 3, 2, and 1.

[0049] To change the setting value, it is necessary to turn on the power switch 39 of the slot machine 1 after turning on the setting key switch 37. When the power is turned on with the setting key switch 37 in the ON state, the setting value read from the RAM 41c is displayed on the setting value display 24 as a display value, and the slot machine transitions to a setting change state in which the setting value can be changed by operating the reset / set switch 38. In the setting change state, when the reset / set switch 38 is operated, the display value displayed on the setting value display 24 is updated by 1 (when the reset / set switch 38 is operated again from setting value 6, it returns to setting value 1). Then, when the start switch 7 is operated, the displayed value is confirmed as the setting value. Then, when the setting key switch 37 is turned off, the confirmed display value (setting value) is stored in the RAM 41c of the main control unit 41, and the slot machine transitions to a state in which game play can proceed.

[0050] The setting key switch 37 and the reset / setting switch 38 are provided inside the slot machine 1 and cannot be operated unless the front door 1b, which can be opened by operating a predetermined key, is opened. Therefore, only staff members of the gaming establishment where the slot machine 1 is installed who possess a predetermined key can operate them. In particular, the setting key switch 37 requires an additional key operation, so only staff members of the gaming establishment who possess a key for operating the setting key switch 37 can operate them. The reset switch 23 does not require opening the front door 1b, but requires key operation using a predetermined key, so only staff members who possess the predetermined key can operate it. The reset / setting switch 38 also functions as a reset switch for resetting an error state under normal circumstances.

[0051] In the slot machine 1 of this embodiment, the main control unit 41 performs a power outage determination process to determine whether a voltage drop has been detected in the interrupt process, and if it determines that a voltage drop has been detected in the power outage determination process, it performs a power outage process (main) to set data to determine whether the data in RAM 41c is normal or not at the next recovery.

[0052] The main control unit 41 is capable of restoring the processing state of the main control unit 41 to the state before the power outage based on the data stored in the RAM 41c, provided that the data in the RAM 41c is normal at the time of startup. On the other hand, if the data in the RAM 41c is not normal at startup, it determines that a RAM abnormality has occurred, sets an error flag in the RAM 41c indicating a RAM abnormality, and controls the RAM to a RAM abnormality error state, disabling game progress. The RAM abnormality error state is released by transitioning to a setting change state, and a new setting value is set, allowing game progress to resume.

[0053] In the slot machine 1 of this embodiment, when the main control unit 41 detects an abnormality during game play, it sets an error flag in the RAM 41c indicating the type of abnormality detected, and controls the system to a general error state, disabling game play. The general error state is released by a reset operation using the reset switch 23 or the reset / setting switch 38, allowing game play to continue. In the following, when there is no need to distinguish between the RAM abnormality error state and the general error state, they are simply referred to as the error state.

[0054] To play a game on the slot machine 1 of this embodiment, first, medals are inserted into the medal insertion slot 4, or the MAXBET switch 6 is operated to set the number of bets using credits. Once the specified number of bets determined according to the game status is set, a predetermined pay line LN (see FIG. 1; in this embodiment, it is set in the middle of reels 2L, 2C, and 2R, i.e., across the horizontally aligned symbols in the middle row) becomes active, and operation of the start switch 7 becomes active, i.e., the game can be started. Note that if medals are inserted in excess of the maximum number of medals corresponding to the game status, the amount is added to the credits. Also, although only one pay line is used in this embodiment, multiple pay lines may be used.

[0055] In this embodiment, in order to make it easier to recognize that a combination of symbols that constitute a win has been lined up on the pay line LN, inactive lines LM1 to LM6 are set up separately from the pay line LN. A win is not determined by the combination of symbols that line up on these inactive lines LM1 to LM6, but rather, when a combination of symbols that constitute a win has been lined up on the pay line LN, a combination of symbols that suggests a win (for example, bell a-bell a-bell a) that is indicative of a win is lined up on one of the inactive lines LM1 to LM6, making it easier to recognize that a combination of symbols that constitute a win has been lined up on the pay line LN. In this embodiment, as shown in FIG. 1, six types of invalid lines are defined as invalid lines in this embodiment: an invalid line LM1 set across the upper row of reels 2L, 2C, and 2R, i.e., across the symbols lined up horizontally on the upper row; an invalid line LM2 set across the lower row of reels 2L, 2C, and 2R, i.e., across the symbols lined up horizontally on the lower row; an invalid line LM3 set across the upper row of reel 2L, the middle row of reel 2C, and the lower row of reel 2R, i.e., across the symbols lined up downward to the right; an invalid line LM4 set across the lower row of reel 2L, the middle row of reel 2C, and the upper row of reel 2R, i.e., across the symbols lined up upward to the right; an invalid line LM5 set across the upper row of reel 2L, the middle row of reel 2C, and the upper row of reel 2R, i.e., across the symbols lined up in a small V shape; and an invalid line LM6 set across the lower row of reel 2L, the middle row of reel 2C, and the lower row of reel 2R, i.e., across the symbols lined up in a small mound shape.

[0056] When the start switch 7 is operated in a state where the game is ready to start, each of the reels 2L, 2C, and 2R spins, and the symbols on each of the reels 2L, 2C, and 2R change continuously. When any of the stop switches 8L, 8C, and 8R is operated while the reels 2L, 2C, and 2R are spinning, stop control is performed on the corresponding reel 2L, 2C, and 2R, the spinning of that reel is stopped, and the symbol on that reel is derived and displayed as a display result in the see-through window 3.

[0057] In the stop control, control is performed to stop the rotation of reels 2L, 2C, and 2R corresponding to the operation within the maximum stop delay time (190 ms (milliseconds) in this embodiment) from when each stop switch is operated, and up to four frames of symbols can be pulled in before the maximum stop delay time (190 ms) has elapsed. In other words, in the stop control, it is possible to select one symbol from the symbols displayed when stop switches 8L, 8C, and 8R are operated and the symbols four frames ahead, a total of five frames (pulling-in range), and to lead it to reels 2L, 2C, and 2R.

[0058] As a result, in the stop control, when the corresponding stop switches 8L, 8C, and 8R for each reel 2L, 2C, and 2R are operated to stop rotation, if the pattern that constitutes the winning combination that has been won in the internal lottery described below is within a retraction range of four frames from the pattern when the stop switch is operated, the pattern is retracted onto the winning line LN, and the rotation of the reel for which the stop switch is operated is stopped, while if the pattern that constitutes the winning combination that has been won in the internal lottery is not within the retraction range, the pattern that does not constitute any winning combination is retracted onto the winning line LN, and the rotation of the reel for which the stop switch is operated is stopped, so that the patterns that constitute the winning combination that has not been won in the internal lottery do not stop on the winning line LN.

[0059] [Main control unit memory area and programs] The main control unit 41 includes a ROM 41b having a memory area for storing predetermined programs and data, and a RAM 41c for temporarily storing data.

[0060] 3 is an address map of the program / data area in the ROM 41b and the available area in the RAM 41c. As shown in FIG. 3(a), the program / data area in the ROM 41b includes an in-capacity program area in which in-capacity programs for controlling the progress of a game are stored, an in-capacity data area in which in-capacity data used by the in-capacity programs are stored, an unused area 1, an out-of-capacity program area in which out-of-capacity programs for controlling the progress of a game, such as detecting errors, generating test signals, and displaying gaming machine information such as payout rates, are stored, an out-of-capacity data area in which out-of-capacity data used by the out-of-capacity programs are stored, and an unused area 2.

[0061] The progression of a game refers to the progression of a series of processes that make up a game, and in the case of a slot machine, this refers to the progression of the stage of setting the number of bets and making it possible to start the game, the stage of starting the game and spinning the reels, the stage of stopping the reels and deriving the display result, and the stage of awarding value such as medals according to the display result. Also, in the case of a pachinko game machine, this refers to the progression of the stage of determining whether a start win has occurred, the stage of starting the variable display, the stage of stopping the variable display, and the stage of changing the game state.

[0062] Hereinafter, the processing performed by the in-capacity program may be referred to as in-capacity processing, and the processing performed by the out-capacity program may be referred to as in-capacity processing.

[0063] 3(b), the available area of ​​RAM 41c includes an internal RAM area used as a work area by internal programs, an external RAM area used as a work area by external programs, and an unused area 4. The internal RAM area includes an internal work area, an unused area 3, and an internal stack area, and the external RAM area includes an external work area and an external stack area. Note that in this embodiment, the internal stack area and the external stack area are configured to be provided in separate areas, but a configuration may also be adopted in which a single stack area is provided that is shared by internal programs and external programs.

[0064] The internal stack area is an area where the internal program temporarily saves data, and when the internal program saves data, the data is temporarily stored in an area at an address indicated by the internal stack pointer.

[0065] The off-capacity stack area is an area where an off-capacity program temporarily saves data, and when an off-capacity program saves data, the data is temporarily stored in an area at an address indicated by an off-capacity stack pointer.

[0066] The unused area 3 is an area that is not used by either the internal program or the external program, and is an area that is surplus to the internal RAM area of ​​a predetermined capacity.

[0067] The unused area 4 is an area of ​​16 bytes or more that is not used by either the internal or external programs. The internal RAM area and the external RAM area are allocated to discontinuous areas sandwiching the unused area 4, so that the internal RAM area used by the internal programs related to the progress of the game and the external RAM area used by the external programs unrelated to the progress of the game can be easily identified based on the difference in storage area.

[0068] In the following, the internal program area, internal data area, and internal RAM area may be collectively referred to as the internal area, and the external program area, external data area, and external RAM area may be collectively referred to as the external area.

[0069] [Regarding the relationship between the area within capacity and the area outside capacity] As shown in Figure 4, the CPU 41a of the main control unit 41 calls an out-of-capacity program during processing based on a program within capacity, executes processing based on the out-of-capacity program, and returns to processing based on the program within capacity after the processing based on the out-of-capacity program is completed.

[0070] 4, when the CPU 41a executes processing based on an internal program, it generally refers to the internal data in the internal data area to execute the processing based on the internal program, and can use the internal RAM area as a work area to refer to and update the contents of the internal RAM area. Also, when the CPU 41a executes processing based on an external program, it generally refers to the external data in the external data area to execute the processing based on the external program, and can use the external RAM area as a work area to refer to and update the contents of the external RAM area.

[0071] In addition, when executing processing based on an internal program, the CPU 41a does not update the external RAM area, but is able to refer to the external RAM area, and when executing processing based on an external program, the CPU 41a does not update the internal RAM area, but is able to refer to the internal RAM area.

[0072] [Register] The main control unit 41 has multiple registers that are used by the main CPU 41a to perform calculations. The multiple registers mainly include a front register, a back register, and a common register. The front register and the back register are in a paired relationship, and when the front register is used, the back register cannot be used, and when the back register is used, the front register cannot be used. Furthermore, by inverting the front register, the back register becomes usable, and by inverting the back register, the front register becomes usable. Furthermore, the common register can be used when both the front register and the back register are used.

[0073] The table registers include the A register, F register, general-purpose registers (B register, C register (B register and C register are collectively called BC register), D register, E register (D register and E register are collectively called DE register), H register, L register (H register and L register are collectively called HL register)), and Q register. The A register and general-purpose registers store values ​​used in operations, the F register stores flags according to the operation results, and the Q register stores the upper address when specifying an address in a special instruction.

[0074] The back registers include the A' register, F' register, and general-purpose registers (B' register, C' register (B' register and C' register are collectively called B'C' register), D' register, E' register (D' register and E' register are collectively called D'E' register), H' register, and L' register (H' register and L' register are collectively called H'L' register)) which are counterparts to the front registers A register, F register, and general-purpose register. The A' register and general-purpose registers store values ​​used in calculations, and the F' register stores flags according to the calculation results.

[0075] The common registers include the I register, R register, IX register, IY register, SP register, and PC register. The I register stores the upper address of the address (interrupt vector) to jump to when an interrupt occurs, the R register stores a value that counts the timing to refresh memory, the IX register and IY register store values ​​used in calculations, the SP register stores the value of the stack pointer that specifies the stack area, and the PC register stores the value of the program counter that indicates the address of the program being executed.

[0076] [Various processes performed by the main control unit] Next, there will be explained various processes executed by the main control unit 41. As shown in Fig. 6, the main control unit 41 is capable of executing basic processes and interrupt processes as processes for controlling the slot machine 1.

[0077] The basic processing is a process that repeatedly loops processing according to the control state until the control state changes, and is composed of a main routine (basic) and several types of subroutines (basic) that are called from the main routine (basic).

[0078] The main routine (basic) is a process that gradually transitions between multiple control states as the game progresses, and it is possible to call any of multiple types of subroutines (basic) depending on the progress of the program.

[0079] A subroutine (basic) starts by being called by the main routine (basic), and returns to the caller of the main routine (basic) when the subroutine (basic) ends.

[0080] As shown in FIG. 7, the basic processing is made up of in-capacity processing (basic) by an in-capacity program and out-of-capacity processing (basic) by an out-of-capacity program.

[0081] The in-capacity processing (basic) can call any type of out-of-capacity processing (basic) from among a plurality of types of out-of-capacity processing (basic) according to the progress of the program.

[0082] The out-of-capacity processing (basic) starts when it is called by the in-capacity processing (basic), and returns to the caller of the in-capacity processing (basic) when the out-of-capacity processing (basic) ends.

[0083] The out-of-capacity processing (basic) is made up of a main routine (out-of-capacity, basic) and a plurality of types of subroutines (out-of-capacity, basic) called from the main routine (out-of-capacity, basic).

[0084] The main routine (outside capacity, basic) can call any type of subroutine (outside capacity, basic) from among multiple types of subroutines (outside capacity, basic) according to the progress of the program.

[0085] A subroutine (out of capacity, basic) starts by being called by the main routine (out of capacity, basic), and returns to the caller of the main routine (out of capacity, basic) when the subroutine (out of capacity, basic) ends.

[0086] Interrupt processing is executed by interrupting the basic processing each time a timer interrupt occurs, and returns to the interrupt source of the basic processing when the interrupt processing is completed. It consists of a main routine (interrupt) and several types of subroutines (interrupts) called from the main routine (interrupt).

[0087] The main routine (interrupt) can call any of a plurality of types of subroutines (interrupts) according to the progress of the program.

[0088] A subroutine (interrupt) starts by being called by a main routine (interrupt), and when the subroutine (interrupt) ends, the process returns to the caller of the main routine (interrupt).

[0089] As shown in FIG. 8, the interrupt processing is made up of an in-capacity processing (interrupt) by an in-capacity program and an out-capacity processing (interrupt) by an out-capacity program.

[0090] The in-capacity processing (interrupt) can call any one of a plurality of types of out-of-capacity processing (interrupt) according to the progress of the program.

[0091] The out-of-capacity processing (interrupt) starts when it is called by the in-capacity processing (interrupt), and returns to the caller of the in-capacity processing (interrupt) when the out-of-capacity processing (interrupt) ends.

[0092] The out-of-capacity processing (interrupt) is made up of a main routine (out-of-capacity interrupt) and multiple types of subroutines (out-of-capacity interrupt) called from the main routine (out-of-capacity interrupt).

[0093] The main routine (out of capacity, interrupt) can call any of a plurality of types of subroutines (out of capacity, interrupt) according to the progress of the program.

[0094] The subroutine (out of capacity, interrupt) starts when it is called by the main routine (out of capacity, interrupt), and when the subroutine (out of capacity, interrupt) ends, it returns to the caller of the main routine (out of capacity, interrupt).

[0095] [Registers used in basic processing and interrupt processing] Next, the registers used by the main control unit 41 when executing basic processing and interrupt processing will be described.

[0096] As shown in Fig. 6, when executing the main routine (basic) in the basic processing, the main control unit 41 performs various processes using the table registers and the common registers. More specifically, the main routine (basic) uses the A register, F register, BC register, DE register, HL register, and Q register from the table registers, i.e., all registers included in the table registers. Also, although the main routine (basic) can use all registers included in the common registers, it uses the I register, R register, IX register, SP register, and PC register, but does not use the IY register.

[0097] Furthermore, when executing a subroutine (basic) in the basic processing, the main control unit 41 executes various processes using the table registers and the common registers. Specifically, in the subroutine (basic), the A register, F register, BC register, DE register, HL register, and Q register are used among the table registers, i.e., all registers included in the table registers. In addition, in the subroutine (basic), all registers included in the common registers can be used, but of these, the I register, R register, IX register, SP register, and PC register are used, and the IY register is not used.

[0098] As shown in FIG. 6, when a timer interrupt occurs during execution of a basic process and interrupt processing starts by interrupting the basic process being executed, the main control unit 41 first switches the register to be used from the front register to the back register.

[0099] The main control unit 41 executes various processes using the back registers and the shared registers when executing the main routine (interrupt) in interrupt processing. Specifically, the main routine (interrupt) uses the A' register, F' register, B'C' register, D'E' register, and H'L' register among the back registers, i.e., all registers included in the back registers. Also, although the main routine (interrupt) can use all registers included in the shared registers, it uses the R register, SP register, and PC register, and does not use the I register, IX register, or IY register.

[0100] In addition, when the main control unit 41 switches the register to be used from the front register to the back register, the value of the back register used in the previous interrupt processing is stored, but in the current interrupt processing, the value of the back register used in the previous interrupt processing is not used, and the necessary value is stored in the back register again.

[0101] Furthermore, when executing a subroutine (interrupt) in interrupt processing, the main control unit 41 executes various processes using the back registers and the common registers. Specifically, in a subroutine (interrupt), all registers included in the back registers can be used, but of these, the A' register, F' register, B'C' register, and H'L' register are used, and the D'E' register is not used. In addition, in a subroutine (interrupt), all registers included in the common registers can be used, but of these, the R register, IY register, SP register, and PC register are used, and the I register and IX register are not used.

[0102] Furthermore, when the main routine (interrupt) in the interrupt process ends, the main control unit 41 switches the registers used from the back registers to the front registers, and returns to the basic process that was being executed when the timer interrupt occurred.

[0103] In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that interrupts the basic process. The IY register can be used when the basic process is executed and when the interrupt process is executed, but the IY register is used in the interrupt process, not the basic process, so that data stored in the IY register can be prevented from being confused between the basic process and the interrupt process.

[0104] Furthermore, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is being executed and when interrupt processing is being executed, but of the IX register and the IY register, the IX register is used for basic processing and the IY register is not used for basic processing, so that it is possible to prevent confusion between basic processing and interrupt processing between the data stored in at least the IY register, of the multiple registers consisting of the IX register and the IY register.

[0105] In this embodiment, the IX register out of the multiple registers consisting of the IX register and the IY register is used in the basic processing, but it is also possible to configure the basic processing so that none of the multiple registers consisting of the IX register and the IY register are used.By configuring in this way, neither the IX register nor the IY register, which can be used when executing both the basic processing and the interrupt processing, is used in the basic processing, thereby preventing confusion of data stored in the multiple registers consisting of the IX register and the IY register between the basic processing and the interrupt processing.

[0106] In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that interrupts the basic process. Also, the IX register can be used when the basic process is executed and when the interrupt process is executed, but since the IX register is used in the basic process and not in the interrupt process, it is possible to prevent the data stored in the IX register from being confused between the basic process and the interrupt process.

[0107] Furthermore, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is being executed and when interrupt processing is being executed, but of the IX register and the IY register, the IY register is used for interrupt processing and the IX register is not used for interrupt processing, so that it is possible to prevent confusion between basic processing and interrupt processing of data stored in at least the IX register, of the multiple registers consisting of the IX register and the IY register.

[0108] In this embodiment, the IY register, one of the multiple registers consisting of the IX register and the IY register, is used in interrupt processing, but it is also possible to configure the multiple registers consisting of the IX register and the IY register so that none of them is used in interrupt processing.By configuring in this way, neither the IX register nor the IY register, which can be used when executing both basic processing and interrupt processing, is used in interrupt processing, thereby preventing confusion of data stored in the multiple registers consisting of the IX register and the IY register between basic processing and interrupt processing.

[0109] Furthermore, in this embodiment, when executing an interrupt process, if the register used is switched from the front register to the back register, the value of the back register used in the previous interrupt process is stored. However, in this interrupt process, the value of the back register used in the previous interrupt process is not used, and the required value is stored in the back register again, thereby preventing the interrupt process from being executed with an unintended value.

[0110] In this embodiment, the interrupt processing consists of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the IY register is used in the subroutine (interrupt) but not in the main routine (interrupt), thereby preventing the data stored in the IY register from becoming confused between the main routine (interrupt) and the subroutine (interrupt).

[0111] Furthermore, subroutines (interrupts) called from a main routine (interrupt) include multiple types of subroutines (interrupts), and the IY register is not used by all of the multiple types of subroutines (interrupts), but is used by one of the types of subroutines (interrupts). This prevents data stored in the IY register from being confused between the main routine (interrupt) and the subroutines (interrupts) that use the IY register.

[0112] In this embodiment, the IY register is configured to be used in some types of subroutines (interrupts), but it may also be configured to be used in all types of subroutines (interrupts). Even in such a configuration, it is possible to prevent the data stored in the IY register from becoming confused between the main routine (interrupt) and the subroutine (interrupt).

[0113] Furthermore, in this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and of the multiple registers used in the interrupt processing, the IY register is used in the subroutine (interrupt) and not used in the main routine (interrupt). However, it is also possible to configure a specific register among the multiple registers used in the basic processing to be used in the subroutine (basic) that constitutes the basic processing and not used in the main routine (basic). By configuring in this way, it is possible to prevent data stored in a specific register from becoming confused between the main routine (basic) and the subroutine (basic).

[0114] In this embodiment, the interrupt processing consists of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt), thereby preventing the data stored in the D'E' register from becoming confused between the main routine (interrupt) and the subroutine (interrupt).

[0115] Furthermore, subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the D'E' register is not used by any of the types of subroutines (interrupts). This prevents data stored in the D'E' register from being confused between the main routine (interrupt) and any type of subroutine (interrupt).

[0116] In this embodiment, the D'E' register is configured not to be used in any type of subroutine (interrupt), but it may also be configured not to be used in a specific type of subroutine (interrupt) but to be used in other types of subroutines (interrupts).Even in such a configuration, it is possible to prevent the data stored in the D'E' register from becoming confused between the main routine (interrupt) and a specific type of subroutine (interrupt).

[0117] Furthermore, in this embodiment, the interrupt processing is composed of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the D'E' register is used in the main routine (interrupt) and not used in the subroutine (interrupt). However, among the multiple registers used in the basic processing, a specific register may be used in the main routine (basic) that constitutes the basic processing and not used in the subroutine (basic). By using such a configuration, it is possible to prevent data stored in a specific register from becoming confused between the main routine (basic) and the subroutine (basic).

[0118] [Regarding registers used in on-chip and off-chip processing] Next, a description will be given of registers used by the main control unit 41 when performing in-capacity processing and out-capacity processing.

[0119] 7, when performing in-capacity processing (basic), the main control unit 41 performs various processes using the table registers and the common registers. Specifically, in the in-capacity processing (basic), the A register, F register, BC register, DE register, HL register, and Q register are used among the table registers, i.e., all registers included in the table registers. In addition, in the in-capacity processing (basic), all registers included in the common registers can be used, but of these, the I register, R register, IX register, SP register, and PC register are used, and the IY register is not used.

[0120] As shown in FIG. 7, when executing the out-of-capacity processing (basic), the main control unit 41 calls the main routine (out-of-capacity basic) from the in-capacity processing (basic).

[0121] When the main control unit 41 starts the main routine (external / basic), it first saves the value of the internal stack pointer stored in the SP register to a predetermined area in the external RAM area, and then stores a value indicating the 0th level of the external stack area in the SP register. This switches the area where data is saved from the internal stack area to the external stack area.

[0122] Thereafter, all values ​​in the table registers and the common registers are saved in a predetermined order to an area in the extra stack area indicated by the extra stack pointer.

[0123] When executing the main routine (outside capacity, basic), the main control unit 41 performs various calculations using the table registers and common registers. Specifically, in the main routine (outside capacity, basic), all registers included in the table registers can be used, but of these, the A register, F register, BC register, HL register, and Q register are used, and the DE register is not used. Also, in the main routine (outside capacity, basic), all registers included in the common registers can be used, but of these, the I register, R register, SP register, and PC register are used, and the IX register and IY register are not used.

[0124] Furthermore, the main control unit 41 executes a subroutine (outside capacity, basic) by calling the subroutine (outside capacity, basic) in the main routine (outside capacity, basic). At this time, the address of the caller is stored in the area of ​​the out-of-capacity stack area indicated by the value stored in the SP register. Also, the subroutine (outside capacity, basic) may save data in the out-of-capacity stack area, and a maximum of N levels of the out-of-capacity stack area will be used. At this time, the out-of-capacity stack pointer stored in the SP register becomes a value indicating the Nth level of the out-of-capacity stack area.

[0125] As shown in Figure 7, when executing a subroutine (outside capacity, basic), the main control unit 41 performs various processes using the table registers and common registers. More specifically, in a subroutine (outside capacity, basic), all registers included in the table registers can be used, but of these, the A register, F register, BC register, HL register, and Q register are used, and the DE register is not used. Also, in a subroutine (outside capacity, basic), all registers included in the common registers can be used, but of these, the I register, R register, SP register, and PC register are used, and the IX register and IY register are not used.

[0126] As shown in Figure 7, when the main control unit 41 ends the main routine (external / basic), it restores all values ​​of the table registers and common registers that were saved in the external stack area. As a result, all data saved in the external stack area is restored, and the external stack area becomes empty. The main control unit 41 then restores the value of the internal stack pointer that was saved in a specified area in the external RAM area to the SP register. As a result, the area for saving data is switched from the external stack area to the internal stack area. Then, the main routine (external / basic) is terminated and the process returns to the caller of the internal processing (basic).

[0127] As shown in Fig. 8, the main control unit 41 executes various processes using the back registers and the common registers when executing the in-capacity processing (interrupt). Specifically, in the in-capacity processing (interrupt), the A' register, F' register, B'C' register, D'E' register, and H'L' register are used among the back registers, i.e., all registers included in the back registers. In addition, in the in-capacity processing (interrupt), all registers included in the common registers can be used, but of these, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

[0128] As shown in FIG. 8, when executing out-of-capacity processing (interrupt), the main control unit 41 calls the main routine (out-of-capacity interrupt) from the in-capacity processing (interrupt).

[0129] When the main control unit 41 starts the main routine (external RAM interrupt), it first saves the value of the internal stack pointer stored in the SP register to a predetermined area in the external RAM area, and then stores a value indicating the 0th level of the external stack area in the SP register. This switches the area where data is saved from the internal stack area to the external stack area.

[0130] Thereafter, all values ​​in the back registers and the shared registers are saved in a predetermined order to an area in the extra stack area indicated by the extra stack pointer.

[0131] When the main control unit 41 executes the main routine (out of capacity / interrupt), it uses the back registers and the common registers to perform various processes. Specifically, all the registers included in the back registers can be used, but among them, the A' register, F' register, B'C' register, and H'L' register are used, and the D'E' register is not used. Also, all the registers included in the common registers can be used, but among them, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

[0132] Furthermore, the main control unit 41 executes a subroutine (extraneous interrupt) by calling the subroutine (extraneous interrupt) in the main routine (extraneous interrupt). At this time, the address of the caller is stored in the area of ​​the extraneous stack area indicated by the value stored in the SP register. Also, the subroutine (extraneous interrupt) may save data in the extraneous stack area, and a maximum of N levels of the extraneous stack area will be used. At this time, the extraneous stack pointer stored in the SP register becomes a value indicating the Nth level of the extraneous stack area.

[0133] As shown in Fig. 8, the main control unit 41 performs various processes using the back registers and the common registers when executing a subroutine (out of capacity, interrupt). More specifically, in a subroutine (out of capacity, interrupt), all registers included in the back registers can be used, but of these, the A' register, F' register, B'C' register, and H'L' register are used, and the D'E' register is not used. Also, all registers included in the common registers can be used, but of these, the R register, SP register, and PC register are used, and the I register, IX register, and IY register are not used.

[0134] As shown in Figure 8, when the main control unit 41 ends the main routine (external / basic), it restores all values ​​of the backed up registers and common registers that were saved to the external stack area. As a result, all data saved to the external stack area is restored, and the external stack area becomes empty. The main control unit 41 then restores the value of the internal stack pointer that was saved to a specified area in the external RAM area to the SP register. As a result, the area for saving data is switched from the external stack area to the internal stack area. Then, the main routine (external / interrupt) ends and the process returns to internal processing (interrupt).

[0135] In this way, in this embodiment, in basic processing, it is possible to execute in-capacity processing (basic) using an in-capacity program and out-capacity processing (basic) using an out-capacity program, and when out-capacity processing (basic) is called and executed from in-capacity processing (basic), the values ​​stored in all registers are first saved to the out-capacity stack area in RAM 41c, and when out-capacity processing (basic) is terminated, all values ​​saved in the out-capacity stack area are restored to all corresponding registers.

[0136] Furthermore, when performing in-capacity processing (basic), the A register, F register, BC register, DE register, HL register, Q register, I register, R register, SP register, and PC register, i.e., 13 registers, are used, whereas when performing out-of-capacity processing (basic), the A register, F register, BC register, HL register, I register, R register, SP register, and PC register, i.e., 10 registers, are used. For this reason, out-of-capacity processing (basic) uses only a portion of the multiple registers used by in-capacity processing (basic), and fewer registers are used when performing out-of-capacity processing (basic) than when performing in-capacity processing (basic), thereby preventing the use of incorrect data when performing out-of-capacity processing (basic).

[0137] In this embodiment, the out-of-capacity processing (basic) uses only a portion of the multiple registers used by the in-capacity processing (basic), so that fewer registers are used when executing the out-of-capacity processing (basic) than when executing the in-capacity processing (basic). However, different registers may be used for the out-of-capacity processing (basic) and the in-capacity processing (basic), and in such a configuration, the out-of-capacity processing (basic) may use fewer registers than the in-capacity processing (basic). Even in such a configuration, since fewer registers are used than when executing the in-capacity processing (basic), it is possible to prevent the use of incorrect data when executing the out-of-capacity processing (basic).

[0138] In addition, in this embodiment, in interrupt processing, it is possible to execute in-capacity processing (interrupt) by an in-capacity program and out-capacity processing (interrupt) by an out-capacity program, and when out-capacity processing (interrupt) is called and executed from in-capacity processing (interrupt), the values ​​stored in all registers are first saved to the out-capacity stack area in RAM 41c, and when the out-capacity processing (interrupt) is terminated, all values ​​saved in the out-capacity stack area are restored to all corresponding registers.

[0139] Furthermore, when executing in-capacity processing (interrupt), the A' register, F' register, B'C' register, D'E' register, H'L' register, R register, SP register, and PC register, i.e., 11 registers, are used, whereas when executing out-of-capacity processing (interrupt processing), the A' register, F' register, B'C' register, H'L' register, R register, SP register, and PC register, i.e., 9 registers, are used. Therefore, in out-of-capacity processing (interrupt), only a portion of the multiple registers used by in-capacity processing (interrupt) is used, and fewer registers are used when executing out-of-capacity processing (interrupt) than when executing in-capacity processing (interrupt), thereby preventing the use of incorrect data when executing out-of-capacity processing (interrupt).

[0140] In this embodiment, the out-of-capacity processing (interrupt) uses only a portion of the multiple registers used by the in-capacity processing (interrupt), so that fewer registers are used when executing the out-of-capacity processing (interrupt) than when executing the in-capacity processing (interrupt). However, different registers may be used for the out-of-capacity processing (interrupt) and the in-capacity processing (interrupt), and in such a configuration, the number of registers used by the out-of-capacity processing (interrupt) may be fewer than the number of registers used by the in-capacity processing (interrupt). Even in such a configuration, since fewer registers are used than when executing the in-capacity processing (interrupt), it is possible to prevent the use of incorrect data when executing the out-of-capacity processing (interrupt).

[0141] In this embodiment, it is possible to execute internal processing by an internal program and external processing by an external program, and when the external processing is called from the internal processing and executed, the value of the internal stack pointer stored in the SP register is saved and switched to a value indicating the external stack area, thereby switching the data saving destination from the internal stack area to the external stack area. Also, when the external processing (basic processing) is terminated, the saved value of the internal stack pointer is returned to the SP register, switching the data saving destination from the external stack area to the internal stack area.

[0142] When the out-of-capacity processing is terminated, all data saved in the out-of-capacity stack area during the execution of the out-of-capacity processing is restored, and then the data saving destination is switched from the out-of-capacity stack area to the in-capacity stack area, so that the data used in the out-of-capacity processing executed last time remains saved and no further out-of-capacity processing is executed, and it is possible to prevent the data used in the out-of-capacity processing executed last time from being mixed with the data to be used in the out-of-capacity processing executed this time.

[0143] In addition, the out-of-capacity processing called from the in-capacity processing includes multiple types of out-of-capacity processing, and regardless of the type of out-of-capacity processing, when the out-of-capacity processing is terminated, all data that was saved to the out-of-capacity stack area during the execution of the out-of-capacity processing is restored, and then the data saving destination is switched from the out-of-capacity stack area to the in-capacity stack area.Therefore, regardless of the type of out-of-capacity processing, the data used in the out-of-capacity processing executed last time remains saved and no further out-of-capacity processing is executed, preventing confusion between the data used in the out-of-capacity processing executed last time and the data to be used in the out-of-capacity processing executed this time.

[0144] Furthermore, regardless of the type of off-capacity processing, when the off-capacity processing is terminated, no data is stored in the off-capacity stack area. Therefore, when starting off-capacity processing, there is no need to restore the value of the off-capacity stack pointer that was set at the end of the previous off-capacity processing; the value of the off-capacity stack pointer can always be set to a value indicating the 0th level of the off-capacity stack area.

[0145] [Regarding register variants] Next, a modified example of a plurality of registers used by the CPU 41a for performing calculations will be described with reference to FIGS.

[0146] In the examples shown in Figures 5 to 8, the multiple registers mainly include front registers, back registers, and common registers, and for basic processing, the front registers and common registers are used whether the processing is within the capacity or outside the capacity, and for interrupt processing, the back registers and common registers are used whether the processing is within the capacity or outside the capacity.However, in the modified examples shown in Figures 9 and 10, the multiple registers include front registers, back registers, and common registers.

[0147] The in-capacity register comprises a set of front and rear registers, and the out-of-capacity register comprises a set of front and rear registers that is different from that comprised by the in-capacity register.

[0148] The main control unit 41 uses the in-capacity registers during in-capacity processing, and switches the registers used from the in-capacity registers to the out-capacity registers during out-capacity processing, and at the end of the out-capacity processing, switches the registers used back from the out-capacity registers to the in-capacity registers, so that the in-capacity registers are used during in-capacity processing and the out-capacity registers are used during out-capacity processing.

[0149] The common register is configured so that it can be used for both in-capacity processing and out-of-capacity processing.

[0150] 10, the IX register and the IY register among the common registers can be used in both on-chip processing and off-chip processing, but the IX register among the IX register and the IY register is configured to be used in on-chip processing and not used in off-chip processing. Also, the IY register among the IX register and the IY register is configured to be used in off-chip processing and not used in on-chip processing.

[0151] Thus, in a variant of the multiple registers, the multiple registers include in-capacity registers used in in-capacity processing, out-of-capacity registers used in out-of-capacity processing, and common registers that can be used in both in-capacity processing and out-of-capacity processing, and the in-capacity registers are used in in-capacity processing and the out-of-capacity registers are used in out-of-capacity processing called from the in-capacity processing.

[0152] Multiple registers consisting of the IX register and the IY register can be used for both in-capacity processing and out-of-capacity processing, but of the multiple registers consisting of the IX register and the IY register, the IX register is used in in-capacity processing and not in out-of-capacity processing, thereby preventing confusion of data stored in the IX register between in-capacity processing and out-of-capacity processing.

[0153] In addition, multiple registers consisting of the IX register and the IY register can be used for both in-capacity processing and out-of-capacity processing, but of the multiple registers consisting of the IX register and the IY register, the IY register is used in out-of-capacity processing and not in in-capacity processing, thereby preventing confusion of data stored in the IY register between in-capacity processing and out-of-capacity processing.

[0154] In addition, of the multiple registers consisting of the IX register and the IY register, the IX register is used only for in-capacity processing and the IY register is used only for out-capacity processing. However, it is also possible to use multiple registers consisting of the IX register and the IY register only for in-capacity processing, or multiple registers consisting of the IX register and the IY register only for out-capacity processing. By using such a configuration, it is possible to prevent confusion of data stored in multiple registers consisting of the IX register and the IY register between in-capacity processing and out-capacity processing.

[0155] [Effect 1] In this embodiment, the interrupt processing consists of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the IY register is used in the subroutine (interrupt) but not in the main routine (interrupt), thereby preventing the data stored in the IY register from becoming confused between the main routine (interrupt) and the subroutine (interrupt).

[0156] In this embodiment, the subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the IY register is not used by all of the multiple types of subroutines (interrupts), but is used by one of the types of subroutines (interrupts). This prevents data stored in the IY register from being confused between the main routine (interrupt) and the subroutines (interrupts) that use the IY register.

[0157] Furthermore, in this embodiment, interrupt processing is executed by interrupting basic processing each time a timer interrupt occurs, and the IY register is used in the subroutine (interrupt) and not in the main routine (interrupt), so that data stored in the IY register can be prevented from becoming confused between the main routine (interrupt) and the subroutine (interrupt) that uses the IY register during execution of interrupt processing.

[0158] In this embodiment, the interrupt processing consists of a main routine (interrupt) and a subroutine (interrupt) that is called and executed from the main routine (interrupt), and among the multiple registers used in the interrupt processing, the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt), thereby preventing the data stored in the D'E' register from becoming confused between the main routine (interrupt) and the subroutine (interrupt).

[0159] In this embodiment, the subroutines (interrupts) called from the main routine (interrupt) include multiple types of subroutines (interrupts), and the D'E' register is not used by any of the types of subroutines (interrupts). This prevents data stored in the D'E' register from being confused between the main routine (interrupt) and any type of subroutine (interrupt).

[0160] Furthermore, in this embodiment, the interrupt processing is executed by interrupting the basic processing each time a timer interrupt occurs, and the D'E' register is used in the main routine (interrupt) and not in the subroutine (interrupt), so that the data stored in the D'E' register can be prevented from becoming confused between the main routine (interrupt) and the subroutine (interrupt) while the interrupt processing is being executed.

[0161] [Effect 2] In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that interrupts the basic process. Also, the IX register can be used when the basic process is executed and when the interrupt process is executed, but since the IX register is used in the basic process and not in the interrupt process, it is possible to prevent the data stored in the IX register from being confused between the basic process and the interrupt process.

[0162] Furthermore, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is being executed and when interrupt processing is being executed, but of the IX register and the IY register, the IY register is used for interrupt processing and the IX register is not used for interrupt processing, so that it is possible to prevent confusion between basic processing and interrupt processing of data stored in at least the IX register, of the multiple registers consisting of the IX register and the IY register.

[0163] Furthermore, in this embodiment, multiple registers consisting of the IX register and the IY register can be used when basic processing is executed and when interrupt processing is executed, but it is also possible to configure the system so that neither the IX register nor the IY register is used for interrupt processing.By configuring the system in this way, neither the IX register nor the IY register, which can be used when basic processing is executed and when interrupt processing is executed, is used for interrupt processing, thereby preventing confusion of data stored in multiple registers consisting of the IX register and the IY register between basic processing and interrupt processing.

[0164] In this embodiment, the front register is used in the basic process, and the back register replaced with the front register is used in the interrupt process that interrupts the basic process. The IY register can be used when the basic process is executed and when the interrupt process is executed, but the IY register is used in the interrupt process, not the basic process, so that data stored in the IY register can be prevented from being confused between the basic process and the interrupt process.

[0165] Furthermore, in this embodiment, multiple registers consisting of the IX register and the IY register can be used both when basic processing is being executed and when interrupt processing is being executed, but of the IX register and the IY register, the IX register is used for basic processing and the IY register is not used for basic processing, so that it is possible to prevent confusion between basic processing and interrupt processing between the data stored in at least the IY register, of the multiple registers consisting of the IX register and the IY register.

[0166] Furthermore, in this embodiment, multiple registers consisting of the IX register and the IY register can be used when basic processing is executed and when interrupt processing is executed, but it is also possible to configure the system so that neither the IX register nor the IY register is used for basic processing.By configuring in this way, none of the multiple registers consisting of the IX register and the IY register that can be used when basic processing is executed and when interrupt processing is executed are used in basic processing, thereby preventing confusion of data stored in multiple registers consisting of the IX register and the IY register between basic processing and interrupt processing.

[0167] Furthermore, in this embodiment, when executing an interrupt process, if the register used is switched from the front register to the back register, the value of the back register used in the previous interrupt process is stored. However, in this interrupt process, the value of the back register used in the previous interrupt process is not used, and the required value is stored in the back register again, thereby preventing the interrupt process from being executed with an unintended value.

[0168] [Effect 3] In this embodiment, it is possible to execute in-capacity processing by an in-capacity program and out-capacity processing by an out-capacity program that is called and executed from the in-capacity program. When executing in-capacity processing, the values ​​stored in all registers are first saved to an out-capacity stack area in RAM 41c, and when the out-capacity processing is terminated, all values ​​saved in the out-capacity stack area are restored to all corresponding registers.

[0169] Furthermore, when out-of-capacity processing is performed, only some of the registers used by in-capacity processing are used, and therefore, since the number of registers used when out-of-capacity processing is smaller than when in-capacity processing is performed, it is possible to prevent the use of incorrect data due to the execution of out-of-capacity processing.

[0170] In addition, in this embodiment, in the basic processing, it is possible to execute in-capacity processing (basic) using an in-capacity program and out-capacity processing (basic) using an out-capacity program, and when out-capacity processing (basic) is called and executed from in-capacity processing (basic), the values ​​stored in all registers are first saved to the out-capacity stack area in RAM 41c, and when the out-capacity processing (basic) is terminated, all values ​​saved in the out-capacity stack area are restored to all corresponding registers.

[0171] Furthermore, when performing in-capacity processing (basic), the A register, F register, BC register, DE register, HL register, Q register, I register, R register, SP register, and PC register, i.e., 13 registers, are used, whereas when performing out-of-capacity processing (basic), the A register, F register, BC register, HL register, I register, R register, SP register, and PC register, i.e., 10 registers, are used. For this reason, out-of-capacity processing (basic) uses only a portion of the multiple registers used by in-capacity processing (basic), and fewer registers are used when performing out-of-capacity processing (basic) than when performing in-capacity processing (basic), thereby preventing the use of incorrect data when performing out-of-capacity processing (basic).

[0172] In addition, in this embodiment, in interrupt processing, it is possible to execute in-capacity processing (interrupt) by an in-capacity program and out-capacity processing (interrupt) by an out-capacity program, and when out-capacity processing (interrupt) is called and executed from in-capacity processing (interrupt), the values ​​stored in all registers are first saved to the out-capacity stack area in RAM 41c, and when the out-capacity processing (interrupt) is terminated, all values ​​saved in the out-capacity stack area are restored to all corresponding registers.

[0173] Furthermore, when executing in-capacity processing (interrupt), the A' register, F' register, B'C' register, D'E' register, H'L' register, R register, SP register, and PC register, i.e., 11 registers, are used, whereas when executing out-of-capacity processing (interrupt processing), the A' register, F' register, B'C' register, H'L' register, R register, SP register, and PC register, i.e., 9 registers, are used. Therefore, in out-of-capacity processing (interrupt), only a portion of the multiple registers used by in-capacity processing (interrupt) is used, and fewer registers are used when executing out-of-capacity processing (interrupt) than when executing in-capacity processing (interrupt), thereby preventing the use of incorrect data when executing out-of-capacity processing (interrupt).

[0174] [Effect 4] In this embodiment, it is possible to execute internal processing by an internal program and external processing by an external program, and when the external processing is called from the internal processing and executed, the value of the internal stack pointer stored in the SP register is saved and switched to a value indicating the external stack area, thereby switching the data saving destination from the internal stack area to the external stack area. Also, when the external processing (basic processing) is terminated, the saved value of the internal stack pointer is returned to the SP register, switching the data saving destination from the external stack area to the internal stack area.

[0175] When the out-of-capacity processing is terminated, all data saved in the out-of-capacity stack area during the execution of the out-of-capacity processing is restored, and then the data saving destination is switched from the out-of-capacity stack area to the in-capacity stack area, so that the data used in the out-of-capacity processing executed last time remains saved and no further out-of-capacity processing is executed, and it is possible to prevent the data used in the out-of-capacity processing executed last time from being mixed with the data to be used in the out-of-capacity processing executed this time.

[0176] In addition, the out-of-capacity processing called from the in-capacity processing includes multiple types of out-of-capacity processing, and regardless of the type of out-of-capacity processing, when the out-of-capacity processing is terminated, all data that was saved to the out-of-capacity stack area during the execution of the out-of-capacity processing is restored, and then the data saving destination is switched from the out-of-capacity stack area to the in-capacity stack area.Therefore, regardless of the type of out-of-capacity processing, the data used in the out-of-capacity processing executed last time remains saved and no further out-of-capacity processing is executed, preventing confusion between the data used in the out-of-capacity processing executed last time and the data to be used in the out-of-capacity processing executed this time.

[0177] Although an embodiment of the present invention has been described above with reference to the drawings, the present invention is not limited to this embodiment, and it goes without saying that modifications and additions that do not deviate from the spirit of the present invention are also included in the present invention.

[0178] In the above embodiment, an example was described in which the present invention is applied to a slot machine in which the number of bets is set using medals and credits as gaming value, but it may also be applied to a slot machine in which the number of bets is set using gaming balls as gaming value, or a full credit type slot machine in which the number of bets is set using only credits as gaming value.

[0179] Furthermore, in the above embodiment and modified example, an example of applying the present invention to a slot machine 1, which is an example of a gaming machine, has been shown, but the present invention is not limited to this and can be applied to any gaming machine that performs a predetermined game, such as a pachinko gaming machine in which a game is played by firing a gaming ball into a gaming area, or even a general gaming machine other than a slot machine or pachinko gaming machine. [Explanation of symbols]

[0180] 1. Slot Machine 2L, 2C, 2R reels 6 MAXBET switch 7 Start switch 8L, 8C, 8R stop switch 41 Main control unit 91 Sub-controller

Claims

[Claim 1] In a gaming machine for playing games, a program execution means for executing a program using a plurality of registers; the program is composed of a main program, a first subprogram called and executed by the main program, and a second subprogram called and executed by the main program; a shared register among the plurality of registers is used by both the first subprogram and the second subprogram; a predetermined register among the plurality of registers is used by at least one of the first sub-program and the second sub-program, and is not used by the main program; The shared register is also used by the main program.

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