Communication device and communication system

Abstract

[Problem] To carry out high-speed data transfer between a master device and a slave device. [Solution] This communication device comprises: a communication interface unit that receives, from a master, control data including data which is in a prescribed transfer format of a first protocol and which is to be transmitted to a slave by a communication mating device; a storage unit that stores the data of the first protocol received by the communication interface unit; an encapsulator that converts the data of the first protocol stored in the storage unit into data of a second protocol; and a communication unit that transfers the data of the second protocol converted by the encapsulator to the communication mating device.

Description

[Technical Field]

[0001] The present disclosure relates to a communication device and a communication system. [Background technology]

[0002] A technology for performing high-speed serial communication using SerDes has been proposed (Patent Document 1). SerDes is used in a variety of fields, including communication between in-vehicle devices, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-239011 Summary of the Invention [Problem to be solved by the invention]

[0004] Advances in autonomous driving technology have increased the need for high-speed communication between in-vehicle devices. ASA (Automotive SerDes Appliance) standardizes high-speed serial communication between Master SerDes and Slave SerDes, but does not standardize communication between Master SerDes and Master devices, or communication between Slave SerDes and Slave devices.

[0005] For example, when the slave device is an image sensor, I2C (Inter-Integrated Circuit) communication is often used between the slave device and the slave SerDes. However, because the transmission speed of existing I2C communication is slow, even if high-speed serial communication is performed between the master SerDes and the slave SerDes, when I2C communication is performed between the slave device and the slave SerDes, high-speed data transmission between the master device and the slave device is not possible.

[0006] Therefore, the present disclosure provides a communication device and a communication system that are capable of transmitting data at high speed between a master device and a slave device even when a low-speed communication protocol is used along the communication path between the master device and the slave device. [Means for solving the problem]

[0007] In order to solve the above problem, according to the present disclosure, there is provided a communication interface unit that receives control data from a master, the control data including data in a predetermined transmission format of a first protocol that is to be transmitted by a communication partner device to a slave; a storage unit that stores the data of the first protocol received by the communication interface unit; an encapsulator that converts the data of the first protocol stored in the storage unit into data of a second protocol; A communication device is provided, comprising: a communication unit that transmits the data of the second protocol converted by the encapsulator to the communication partner device.

[0008] The predetermined transmission format may be a format for receiving an ACK signal or a NACK signal from the communication partner device after completing transmission of multiple bytes of data to the communication partner device.

[0009] The predetermined transmission format of the first protocol may be an I2C bulk mode format defined in ASA (Automotive SerDes Alliance) standard ver1.01.

[0010] The storage unit may store the control data including identification information of the encapsulator, the number of pieces of data, and information on the I2C bulk mode format.

[0011] The data transmission rate in the communication interface unit may be faster than the data transmission rate between the communication partner device and the slave.

[0012] The communication device may further include a decapsulator that converts data of the second protocol received by the communication unit from the communication partner device into data of the first protocol and stores the converted data in the storage unit.

[0013] According to the present disclosure, a first communication device that performs data communication of a first protocol with a master; a second communication device that performs data communication with the first communication device according to a second protocol and performs data communication with a slave according to the first protocol, The first communication device a first communication interface unit that receives control data from the master, the control data including data in a predetermined transmission format of the first protocol, which is to be transmitted by the second communication device to the slave; a first storage unit that stores data of the first protocol received by the first communication interface unit; a first encapsulator that converts the data of the first protocol stored in the first storage unit into data of a second protocol; a first communication unit that transmits the data of the second protocol converted by the first encapsulator to the second communication device.

[0014] The communication device may further include a first decapsulator that converts data of the second protocol transmitted from the second communication device and received by the first communication unit into data of the first protocol and stores the converted data in the first storage unit.

[0015] The predetermined transmission format of the first protocol may be an I2C bulk mode format defined in ASA standard ver1.01.

[0016] The data transmission rate in the first communication interface unit may be higher than the data transmission rate between the second communication device and the slave.

[0017] The second communication device a second communication unit that receives data of the second protocol transmitted from the first communication device; a second decapsulator that converts the data of the second protocol received by the second communication unit into data of the first protocol; The communication device may further include a second communication interface unit that transmits the data of the first protocol converted by the second decapsulator to the slave.

[0018] the second communication device has a second encapsulator that converts the data of the first protocol transmitted by the slave and received by the second communication interface unit into data of the second protocol; The second communication unit may transmit the data of the second protocol converted by the second encapsulator to the first communication device.

[0019] The master a second storage unit that stores the control data including data of the first protocol that is to be transmitted by the second communication device to the slave; The communication device may further include a third communication interface unit that transmits the control data stored in the second storage unit to the first communication device.

[0020] an internal slave built into the second communication device and directly controlled by the master; The second communication device may include a third storage unit that stores data for the master to directly control the internal slave.

[0021] The third storage unit may store data of the first protocol to be transmitted to the slave.

[0022] The first communication device a third encapsulator that converts data from the master stored in the first storage unit into data of the second protocol; a third decapsulator that converts a protocol of the internal slave data that is received by the first communication unit and read from the third storage unit, The second communication device may store the data output from the third encapsulator in the third storage unit.

[0023] According to the present disclosure, control data including data in a predetermined transmission format of a first protocol, which is to be transmitted from a communication partner device to a slave, is received from a master by a communication interface unit; storing the data of the first protocol received by the communication interface unit in a storage unit; converting the data of the first protocol stored in the storage unit into data of a second protocol; A communication method is provided in which the converted data in the second protocol is transmitted to the communication partner device. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a block diagram showing a basic configuration that forms the basis of a communication system according to the present disclosure. [Figure 2] A diagram showing a typical I2C write sequence. [Figure 3] A diagram showing the I2C bulk mode format. [Figure 4] A diagram showing the data structure of the I2C bulk mode format. [Figure 5] 2 is a diagram showing the configuration of data and packets generated by each section in SerDes#1. FIG. [Figure 6] 1 is a block diagram showing a schematic configuration of a communication system including a communication device according to a first embodiment. [Figure 7A] 7 is a flowchart showing the processing procedure of the communication system of FIG. 6. [Figure 7B] Flowchart following Figure 7A. [Figure 8] This figure shows the memory map configuration when storing data in I2C bulk mode format in memory. [Figure 9] This is a data structure diagram when storing data in I2C bulk mode format in buffer memory. [Figure 10]FIG. 10 is a block diagram showing a schematic configuration of a communication system including a communication device according to a second embodiment. [Figure 11] FIG. 10 is a diagram showing an example of address mapping of a register. [Figure 12] FIG. 10 is a diagram showing the data structure of a memory Write / Read command packet format transmitted from SerDes#1. [Figure 13] FIG. 2 is a diagram showing the data structure of memory Write / Read commands stored in a memory in an ECU. [Figure 14] FIG. 10 is a diagram showing the data structure of memory Write / Read commands stored in a buffer memory in SerDes#1. [Figure 15A] 10 is a flowchart showing a processing procedure of a communication system according to a second embodiment. [Figure 15B] Flowchart following FIG. 15A. [Figure 16] FIG. 11 is a diagram showing a memory map when an ECU according to a third embodiment writes data in an I2C bulk mode format to a memory. [Figure 17A] 10 is a flowchart showing a processing procedure of a communication system according to a third embodiment. [Figure 17B] Flowchart following FIG. 17A. [Figure 18] FIG. 10 is a block diagram showing a schematic configuration of a communication system including a communication device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of a communication device and a communication system will be described with reference to the drawings. The following description will focus on the main components of the communication device and the communication system, but the communication device and the communication system may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0026] (Basic configuration of communication system) Fig. 1 is a block diagram showing a basic configuration that forms the basis of a communication system 1 according to the present disclosure. The communication system 1 in Fig. 1 constitutes part of an ADAS (Advanced Driver Assistance System). The communication system 1 in Fig. 1 includes a Master SerDes 20, a Slave SerDes 40, a Master device 10, and a Slave device 50.

[0027] The Master SerDes 20 and the Slave SerDes 40 perform high-speed serial communication, for example, according to a predetermined communication standard (second protocol). The predetermined communication standard is, for example, FPD-Link, A-phy, ASA, etc. The following mainly describes an example in which the Master device 10 and the Master SerDes 20 perform high-speed serial communication in accordance with ASA, which is a high-speed interface standard.

[0028] In this specification, the Master SerDes 20 may be referred to as a communication device, a first communication device, or SerDes#1 20, and the Slave SerDes 40 may be referred to as a second communication device or SerDes#2 40.

[0029] The SerDes#1 20 performs data transmission with the master device 10. The following mainly describes an example in which the master device 10 is an ECU 10 for vehicle control. The ECU 10 controls the entire communication system 1 shown in Fig. 1. The ECU 10 and the SerDes#1 20 perform serial transmission using a relatively slow communication protocol such as I2C or GPIO.

[0030] The ECU 10 includes an ECU core 10-1, a memory 10-2, a first low-speed interface unit (LS I / F#1) 10-4, and a second low-speed interface unit (LS I / F#2) 10-3. The memory 10-2 stores in advance register setting values ​​that the ECU 10 uses to set the operation of the slave device 50.

[0031] In the following, an example in which the slave device 50 is a sensor 50 (e.g., an image sensor) will be mainly described, but the type of the slave device 50 is not limited. The register setting values ​​stored in the memory 10-2 by the ECU 10 are set in the control register of the sensor 50 via the SerDes#1 20 and the SerDes#2 40 when the power is turned on, etc. In this way, the ECU 10 can control the operation of the sensor 50 using the register setting values ​​stored in the memory 10-2.

[0032] The SerDes#1 20 includes a low-speed interface unit (LS I / F#1) 20-1, an encapsulator (ENCP LS I / F#1) 20-2, a deencapsulator (DECP LS I / F#2) 20-3, an OAM (Operation, Administration, Maintenance) 20-6, a DLL 20-4, and a PHY 20-5.

[0033] The SerDes#2 40 has a PHY 40-5, a DLL 40-4, an OAM unit 40-6, a de-encapsulator (DECP LS I / F#1) 40-3, a low-speed interface unit (LS I / F#1) 40-1, and an encapsulator (ENCP LS I / F#2) 40-2.

[0034] The sensor 50, which is a slave device 50, has a low-speed interface unit (LS I / F#1) 50-2 and a register 50-1. The sensor 50 has an I2C communication function. The ASA standard version 1.01 specifies the use of I2C as a low-speed communication protocol and describes a method for converting the I2C signal format into the ASA standard communication protocol. The ENCP LS I / F#1 20-2 in SerDes#1 20 and the ENCP LS I / F#1 40-2 in SerDes#2 40 perform the process of converting from the I2C communication protocol to the ASA communication protocol.

[0035] The LS I / F#1 20-1 in the SerDes#1 20 performs serial communication with the LS I / F#1 10-4 in the ECU 10 using a predetermined protocol (e.g., I2C). The ENCP LS I / F#1 20-2 in the SerDes#1 20 converts the data received by the LS I / F#1 20-1 into a protocol that complies with ASA and generates packets. The DLL 20-4 combines the packets from the ENCP LS I / F#1 20-2 with other transmission packets (including the OAM 20-6) to generate uplink packets and transfers them to the PHY 20-5. The PHY 20-5 outputs the uplink packets to the cable 30 according to the uplink output timing based on TDD (Time Division Duplex).

[0036] The uplink packet sent from SerDes#1 20 is transferred to the DLL 40-4 via the PHY 40-5 in SerDes#2 40. The DLL 40-4 extracts the packet for the sensor 50 from the uplink packet and sends it to the DECP LS I / F#1 40-3. The DECP LS I / F#1 40-3 transmits I2C data, which is the result of protocol conversion of the packet for the sensor 50, to the LS I / F#1 40-1. The LS I / F#1 40-1 transmits the data from the DECP LS I / F#1 40-3 to the sensor 50.

[0037] The data transmitted by the ECU 10 is stored in the register 50-1 of the sensor 50 via the SerDes#1 20 and the SerDes#2 40.

[0038] When the sensor 50 receives data from the ECU 10, it transmits data in response to that data to the SerDes#2 40, for example, via I2C communication. The LS I / F#1 40-1 in the SerDes#2 40 transmits the received data to the ENCP LS I / F#1 40-2. The ENCP LS #1 40-2 converts the received data into a protocol compliant with ASA to generate a packet. The DLL 40-4 generates a downlink packet including the packet from the ENCP LS #1 40-2. The downlink packet is transmitted to the SerDes#1 20 via the PHY 40-5.

[0039] When the PHY 20-5 in the SerDes#1 20 receives a downlink packet, it transfers it to the DLL 20-4. The DLL 20-4 disassembles the downlink packet and sends the packet for the ECU 10 to the DECP LS I / F#1 20-3. The DECP LS I / F#1 20-3 performs protocol conversion on the packet for the ECU 10 to generate, for example, data for I2C and send it to the LS I / F #1 20-1. The LS I / F #1 10-4 in the ECU 10 receives the data sent from the LS I / F #1 20-1 in the SerDes#1 20 via I2C communication and stores it in the memory 10-2.

[0040] 2 is a diagram showing a typical I2C write sequence. The ECU 10 performing I2C communication issues a Start condition, followed by a 7-bit slave address indicating the I2C communication partner and a 1-bit bit indicating the write / read operation. In response, the I2C sensor 50, the I2C communication partner indicated by the slave address, returns an acknowledgement ACK.

[0041] After receiving an ACK from the sensor 50 performing I2C communication, in Write mode, the ECU 10 issues an offset address (in bytes) indicating the address of the register 50-1 of the sensor 50 to which data is to be written. In response to this, the sensor 50 returns an acknowledgment ACK. The ECU 10 then issues write data in byte units. The sensor 50 returns an acknowledgment ACK each time it receives data in byte units. The ECU 10 and the sensor 50 repeat the data write operation until the desired number of data have been written. After writing the last data, the ECU 10 issues a Stop condition to end the I2C communication.

[0042] The above operations are performed between LS I / F #1 10-4 of ECU 10 and LS I / F #1 20-1 of SerDes #1 20, and between LS I / F #1 40-1 of SerDes #2 40 and LS I / F #1 50-2 of Slave (sensor) 50 in FIG.

[0043] The ASA standard specifies not only the I2C byte mode, which transfers data byte by byte like normal I2C, but also a transfer mode called I2C bulk mode, which transfers multiple pieces of data together, when transferring I2C data between SerDes 20 or 40. In I2C bulk mode, the ECU 10 does not receive an ACK / NACK signal from the sensor 50 for each byte, but instead sends multiple bytes to the sensor 50 in bulk and receives the ACK / NACK signal from the sensor 50 all at once, enabling data transmission with the sensor 50, which dramatically improves the data transmission speed.

[0044] Figure 3 shows the I2C bulk mode format, which consists of an I2C header, command mode, Write / Read / ACKNACK / Read response command, and data.

[0045] The I2C header is composed of cmd_id, which indicates the command ID, I2C mode, which indicates the transfer mode (I2C bulk mode or I2C byte mode), and I2C error, which indicates an I2C bus error state.

[0046] The command mode consists of an I2C address mode, which indicates whether to specify an offset address for the write register, and an I2C format type, which indicates whether the command to be transmitted is a Write or Read command, an ACK / NACK reply, or read data (Read response) for a Read command.

[0047] The contents of the Write / Read / ACKNACK / Read response commands differ depending on the command selected in the I2C format type. For a Write or Read command, the response consists of the I2C slave address to be written, the offset address, and the number of bytes of data to be written or read. For an ACK / NACK or Read response command, the response consists of the slave address indicated in the Write / Read command and the number of bytes of data received from the Slave.

[0048] The data consists of write data, read data, or ACK / NACK data for each command.

[0049] Next, an operation will be described in the communication system 1 of FIG. 1 when the ECU 10 transmits data to the sensor 50 in the I2C bulk mode.

[0050] The ECU 10 transmits control data for controlling the sensor 50 to the register 50-1 in I2C bulk mode. To this end, the ECU core 10-1 controls the LS I / F #1 10-4, which performs I2C communication, and starts I2C communication with the SerDes #1 20. The LS I / F #1 10-4 outputs the slave address and offset address of the SerDes #1 20 according to an I2C write sequence. The ECU core 10-1 then generates a write command including the I2C slave address, offset address, and write data of the sensor 50 according to the I2C bulk mode format shown in FIG. 3, inserts the command into the data portion of the I2C write sequence sequentially byte by byte, and transmits it to the LS I / F #1 20-1 of the SerDes #1 20.

[0051] 4 is a diagram showing the data structure of the I2C bulk mode format that the ECU 10 sends to the SerDes#1 20 using the normal I2C write procedure. The I2C bulk mode format includes a data field after the slave address and offset address. The data field includes an I2C header, a command mode, a write / read command, and data.

[0052] The LS I / F#1 20-1 in SerDes#1 20 sequentially outputs the received I2C data to the ECNP LS I / F#1 20-2. The ECNP LS I / F#1 20-2 can determine that the received data format is I2C bulk mode by interpreting the mode information in the I2C header. If I2C bulk mode is described in the I2C header, it processes the subsequent data in I2C bulk mode. After receiving all the I2C bulk mode data, SerDes#1 20 compiles it into the I2C bulk mode format shown in Figure 3 and stores it in the packet payload of the packet format.

[0053] Fig. 5 shows the configuration of data and packets generated by each unit in SerDes#1 20. Fig. 5(A) shows the I2C bulk mode format, Fig. 5(B) shows the packet format generated by ENCP LS I / F#1 20-2, Fig. 5(C) shows the Link layer container format generated by DLL 20-4, and Fig. 5(D) shows the PHY format generated by PHY 20-5.

[0054] As shown in FIG. 5(B), the ENCP LS I / F#1 20-2 generates a packet format having a packet header indicating the type of packet and the like, and a packet payload including the I2C bulk mode format.

[0055] The ENCP LS I / F#1 20-2 outputs the packet format to the DLL 20-4, which generates a link layer container format based on the received packet format shown in Fig. 5B.

[0056] As shown in Fig. 5(C), the Link layer container format has a container header and a DLL payload. The container header includes information such as the packet's output destination. The DLL payload includes the Link layer container format of Fig. 5(B).

[0057] The DLL 20-4 further generates a link layer container format (FIG. 5(C)) that stores an OAM packet including a system control register and the like in the packet payload, and outputs this link layer container format (FIG. 5(C)) to the PHY 20-5.

[0058] The PHY 20-5 converts the Link layer container format (FIG. 5C) into a PHY format (FIG. 5D) conforming to the ASA standard. Furthermore, the PHY 20-5 uses the Uplink to output the PHY format (FIG. 5D) to the SerDes#2 40 via the cable 30.

[0059] The PHY 40-5 of the SerDes#2 40 extracts the Link layer container format (FIG. 5(C)) from the received PHY format (FIG. 5(D)), and outputs it to the DLL 40-4.

[0060] The DLL 40-4 analyzes the container header of the Link layer container format (Fig. 5(C)) and finds that the DLL payload stores data to be output to the DECP LS I / F#1 40-3. Accordingly, the DLL 40-4 outputs the DLL payload (Fig. 5(C)) to the DECP LS I / F#1 40-3.

[0061] The DECP LS I / F#1 40-3 analyzes the packet payload (Figure 5(B)) and determines from the I2C header (Figure 3) that I2C bulk mode has been transferred. It then analyzes the command mode (Figure 3) and determines that it is a Write command. It then analyzes the subsequent Write command (Figure 3) and determines the I2C slave address of the I2C communication destination, the register offset address, and the data length. This allows the DECP LS I / F#1 40-3 to correctly determine all write data.

[0062] The DECP LS I / F #1 40-3 controls the LS I / F #1 40-1 based on this information and starts I2C communication with the sensor 50. This I2C communication is a Write sequence, so the I2C format of FIG. 2 is used.

[0063] The LS I / F#1 40-1 communicates with the LS I / F#1 50-2 of the sensor 50 via I2C, and transfers data sequentially.

[0064] The LS I / F#1 50-2 of the sensor 50 writes the received data sequentially to the register 50-1. At the same time, the LS I / F#1 50-2 returns an ACK signal to the LS I / F#1 40-1 indicating that each byte was received correctly (FIG. 2).

[0065] The ENCP LS I / F#1 40-2 of SerDes#2 40 stores the ACK signal returned by the LS I / F#1 50-2 of the sensor 50 in this I2C communication, and when the I2C communication is completed, generates an I2C bulk mode ACK NACK command (Figure 3), stores all the ACK NACK signals in data, and outputs them to the DLL 40-4 in packet format (Figure 5(B)).

[0066] The DLL 40-4 stores the packet format in the payload of a link layer container format and outputs the link layer container format (Fig. 5(C)) to the PHY 40-5. The DLL 40-4 also generates a link layer container format (Fig. 5(C)) that stores the OAM packet and outputs it to the PHY 40-5.

[0067] The PHY 40-5 converts the link layer container format (FIG. 5(C)) into the PHY format (FIG. 5(D)). The PHY 40-5 outputs the PHY format (FIG. 5(D)) to the SerDes#1 20 using the down link. The PHY 20-5 of the SerDes#1 20 receives the PHY format (FIG. 5(D)), extracts the link layer container format (FIG. 5(C)) from the data payload, and outputs it to the DLL 20-4.

[0068] The DLL 20-4 analyzes the container header (FIG. 5(C)) and outputs the DLL payload to the DECP I / F#1 20-3 accordingly.

[0069] The DECP I / F#1 20-3 analyzes the I2C header and command mode of the I2C header (FIG. 5(A)) and determines that it is an ACK / NACK command. Then, it acquires all ACK / NACK data during I2C communication with the sensor 50 in data (FIG. 5(A), FIG. 3).

[0070] After the I2C communication for writing register data to the sensor 50 via SerDes#1 20 and SerDes#2 40 is completed, and an appropriate amount of time has elapsed, the ECU 10 reads the ACK / NACK data held by the DECP LS I / F#1 20-3 via I2C communication between LS I / F#1 10-4 and LS I / F#1 20-1 to confirm that the data was written correctly, and determines that the register setting in the sensor 50 was successful.

[0071] Through the above operations, the ECU 10 can set registers to control the operation of the sensor 50. The I2C bulk mode eliminates the need to exchange ACK / NACK signals between SerDes#1 20 and SerDes#2 40 to indicate that each byte of data has been received. This improves the I2C data transmission speed, but because the ECU 10 and SerDes#1 20, and the SerDes#2 40 and sensor 50 are connected via low-speed I2C, the I2C communication becomes a bottleneck in the transmission speed.

[0072] For example, the bottleneck in data transmission speed can be resolved by changing the interface between the ECU 10 and the SerDes#1 20 to an interface such as SPI (Serial Peripheral Interface), which is faster than I2C. However, in general image sensors 50, I2C is often used as the control interface, and in camera modules to which the image sensor 50, temperature sensor, power supply IC, etc. are connected, these devices are generally connected via an I2C bus and controlled from the ECU 10 side via I2C via the image sensor 50. For this reason, when the control interface on the ECU 10 side is changed to a high-speed interface such as SPI, the control interfaces on the ECU 10 side and the sensor 50 side will differ, and how to maintain compatibility between them becomes an issue.

[0073] The communication device and communication system 1 according to the present disclosure, which will be described below, are characterized by the ability to transmit control data at high speed between a sensor 50 that uses control data in the I2C transmission method defined in the ASA standard ver. 1.01 and an ECU 10 that transmits control data to the sensor 50 using an I / F that is faster than I2C.

[0074] (First embodiment) Fig. 6 is a block diagram showing a schematic configuration of a communication system 1 including a communication device according to the first embodiment. In Fig. 6, components common to those in Fig. 1 are given the same reference numerals, and the following description will focus on the differences.

[0075] The ECU 10 in FIG. 6 is equipped with an HS I / F 10-6 with a faster signal protocol instead of the low-speed LS I / F #1 10-4.

[0076] Similarly, instead of LS I / F#1 20-1, SerDes#1 20 is equipped with an HS I / F 20-7, which is the same type of high-speed interface as the HS I / F 10-6, for connection to the HS I / F 10-6. SerDes#1 20 also is equipped with a buffer memory 20-8 that temporarily stores data transmitted and received by the HS I / F 20-7, a decoder 20-9 that processes data received by the HS I / F 20-7, and an encoder 20-10 that processes data to be transmitted to the HS I / F 20-7. Hereinafter, the buffer memory 20-8 may be referred to as the buffer memory 20-8.

[0077] The SerDes#1 20 has a communication interface that receives control data from the ECU 10, including data in a predetermined transmission format of a first protocol (e.g., an I2C communication protocol) that the SerDes#2 40 transmits to the sensor 50. The predetermined transmission format is, for example, an I2C bulk mode format. This communication interface is capable of transmitting data at a higher speed than a normal I2C communication interface.

[0078] Individual IDs are preset for the ENCP LS I / F #1 20-2 and the ENCP LS I / F #1 20-3 in the SerDes #1 20. The ECU 10 knows this information in advance. In the following, as an example, the ID of the ENCP LS I / F #1 is "ENCP LS I / F #1" itself.

[0079] The ECU 10 performs a process of writing control data to the register 50-1 of the sensor 50 via the SerDes #1 20 and the SerDes #2 40 using the I2C bulk mode defined in the ASA standard version 1.01.

[0080] 7A and 7B are flowcharts showing the processing procedures of the communication system 1 of FIG. 6, FIG. 8 is a diagram showing the memory map configuration when data in I2C bulk mode format is stored in memory 10-2 in ECU 10-1, and FIG. 9 is a data configuration diagram when data in I2C bulk mode format is stored in buffer memory 20-8 in SerDes #1.

[0081] First, the ECU 10 generates all the data to be written to the register 50-1 of the sensor 50 (step S1).

[0082] 3 in Write command mode (I2C format type (000)), and generates data to store the slave address of the sensor 50, an offset address indicating the write destination address in register 50-1, and length information indicating the number of data to be written in the corresponding locations of register 50-1. Furthermore, the ECU 10 stores the first data in the data area of ​​the I2C bulk mode format (step S2).

[0083] The ECU 10 stores in memory 10-2 (step S3) the ENCP ID (FIG. 8(A)) of SerDes#1 20 that transmits the I2C bulk mode format, the total number of data in the I2C bulk mode format (FIG. 8(B)), and the I2C bulk mode format (FIG. 8(C)) generated in step S2. The address of memory 10-2 in FIG. 8 is for convenience and can be selected arbitrarily.

[0084] The ECU 10 instructs the HS I / F 10-6 in the SerDes#1 20 to transfer the data from 0x0100 to 0x01XX on the memory 10-2 (step S4). The HS I / F 10-6 retrieves the data from 0x0100 to 0x01XX from the memory 10-2 and outputs it sequentially according to the HS I / F protocol (step S5). The HS I / F 20-7 of the SerDes#1 20 sequentially receives the data from the HS I / F 10-6 and stores it in the buffer memory 20-8 (step S6).

[0085] As can be seen from a comparison of FIG. 8 and FIG. 9, the buffer memory 20-8 in the SerDes#1 stores data having the same data structure as the memory 10-2 in the ECU 10.

[0086] Next, the decoder 20-9 in the SerDes#1 20 reads the data from the buffer memory 20-8 (step S7). At this time, the decoder 20-9 analyzes the ENCP ID (FIG. 8A) written at the beginning of the I2C bulk mode format, and outputs the data to the ENCP LS I / F#1 20-2 via the ENCP ID = ENCP LS I / F#1. Although not shown, when there are multiple ENCPs, the data output destination is similarly selected based on the ENCP ID in the I2C bulk mode format.

[0087] The decoder 20-9 reads the number of data indicated by the "number of data" (FIG. 8B) from the buffer memory 20-8 and outputs it to the ENCP LS I / F#1 20-2. With the operations up to this point, the data required for the I2C bulk mode can be transferred to the ENCP LS I / F#1.

[0088] The ENCP LS I / F#1 20-2 stores the received I2C bulk mode format (FIG. 8(C)) in the packet payload of the packet format (FIG. 5(B)), adds a packet header indicating the packet type, etc., creates the packet format (FIG. 5(B)), and outputs it to the DLL 20-4 (step S8).

[0089] The operation procedure from when the DLL 20-4 receives the packet format (FIG. 5B) to when the data is written to the register 50-1 of the sensor 50 is the same as that of general ASA serial communication (step S9).

[0090] Meanwhile, the ACK / NACK response during I2C communication of the sensor 50 is also performed by the LS I / F#1 40-1, ENCP LS I / F#1 40-2, DLL 40-4, and PHY 40-5 of SerDes#2 40, and the PHY format shown in Figure 5(D) is output to the downlink (step S10).

[0091] Similar to typical ASA serial communication, the PHY 20-5, DLL 20-4, and DECP LS I / F #1 (20-3) of SerDes#1 20 receive the PHY format (Figure 5(D)) from SerDes#2 and obtain the I2C bulk mode format (Figure 5(A)), which is the ACK / NACK format (step S11).

[0092] The encoder 20-10 acquires the I2C bulk mode format (FIG. 5(A)) from the DECP LS I / F #1 20-3, generates a DECP ID (here, the DECP LS I / F #1 20-3) (FIG. 9(D)) and the number of data in the I2C bulk mode format (FIG. 5(A)) (FIG. 9(E)), and outputs them together with the I2C bulk mode format (FIG. 9(F)) to a memory area in the buffer memory 20-8 that has been allocated in advance (FIG. 9, step S12).

[0093] The ECU 10 measures a predetermined time using a watchdog timer or the like, and when an appropriate time has elapsed, it instructs the HS I / F 10-6 to read the I2C bulk mode (Figure 9(F)), which is the ACK / NACK format that is the I2C write result, from the buffer memory 20-8 of SerDes #20 via the HS I / F 20-7 (step S13).

[0094] The HS IF 10-6 reads the DECP ID (FIG. 9(D)), the number of data (FIG. 9(E)), and the I2C bulk mode (FIG. 9(F)) from the buffer memory 20-8 via the HS IF 20-7, and writes the read data to a predetermined area in the memory 10-2 (FIGS. 8(D), 8(E), 8(F), step S14).

[0095] The ECU 10 confirms that data has been returned from the desired DECP based on the DECP ID (Figure 8(D)) and the number of data (Figure 8(E)) in memory 10-2, obtains the ACK / NACK result stored in the data area (Figure 8(F)), confirms that the control data has been transferred to register 50-1 of sensor 50, and terminates the control data transmission operation (step S15).

[0096] In step S13, an example has been described in which the ECU 10 uses a watchdog timer to start the read operation of the buffer memory 20-8. However, when the data to be read into the buffer memory 20-8 (FIGS. 9(D), 9(E), 9(F)) is ready, the SerDes#1 20 may send an interrupt signal to the ECU 10, and the ECU 10 may start the read operation of the buffer memory 20-8 upon receiving this interrupt signal.

[0097] In addition, in this explanation, the I2C bulk mode format is stored in memory 10-2 and transmitted, but the same procedure can be applied to other formats (e.g., GPIO) stored in the packet payload of the packet format (Figure 5(B)).

[0098] As described above, in the first embodiment, the ECU 10 stores data in I2C bulk mode format to be transmitted to the sensor 50 in the memory 10-2 and transmits the data in the memory 10-2 to the SerDes#1 via the HS I / F 10-6, which is a high-speed interface. The ENCP LS I / F#1 20-2 in the SerDes#1 generates an ASA-compliant packet including the received data in I2C bulk mode format and transmits the packet to the SerDes#2 via the DLL 20-4 and the PHY 20-5. The ENCP LS I / F#1 40-3 in the SerDes#2 extracts the data in I2C bulk mode format from the received packet and transmits the data to the sensor 50 via the LS I / F#1 40-1.

[0099] According to the first embodiment, data in I2C bulk mode format is transmitted at high speed between the ECU 10 and the SerDes#1 20, so that even if the sensor 50 uses I2C communication, control data can be transmitted from the ECU 10 to the sensor 50 at high speed.

[0100] (Second embodiment) The communication system 1 according to the second embodiment is characterized in that the sensor 50 serving as the slave device 50 has a built-in SerDes#2 40.

[0101] Since the sensor 50 has a built-in SerDes#2 40, the ECU 10 can set control data in the control register of the sensor 50 without using a low-speed interface as in normal I2C communication or the first embodiment. This means that the limitation on the data transfer speed due to I2C, which has been an issue when the ECU 10 controls the sensor 50, can be completely eliminated.

[0102] Fig. 10 is a block diagram showing a schematic configuration of a communication system 1 including a communication device according to the second embodiment. In Fig. 10, components common to those in Fig. 6 are given the same reference numerals, and the following description will focus on the differences.

[0103] The communication system 1 in Fig. 10 includes an ECU 10 having the same configuration as that in Fig. 6, a SerDes#1 20 having a different configuration from that in Fig. 6, and a SerDes#2 40 having a different configuration from that in Fig. 6. The SerDes#2 40 is built into a sensor 50. A peripheral device 60 may be connected to the sensor 50 as shown in Fig. 10.

[0104] The SerDes#1 20 in Fig. 10 has an encapsulator ENCP MEM 20-11 and a deencapsulator DECP MEM 20-12 instead of the ENCP LS I / F#1 20-2 and DECP LS I / F#1 20-3 in the SerDes#1 20 in Fig. 6. The rest of the configuration is the same as that of the SerDes#1 20 in Fig. 6.

[0105] The SerDes#2 40 in Fig. 10 has an LS I / F#1 40-1, an ENCP LS I / F#1 40-2, a DECP LS I / F#1 40-3, a DLL 40-4, a PHY 40-5, and an OAM 40-6, similar to the SerDes#2 40 in Fig. 6. In addition, the SerDes#2 40 in Fig. 10 has an ENCP MEM 40-7, a DECP MEM 40-8, and a register 40-9, which are components not present in the SerDes#2 40 in Fig. 6.

[0106] The register 40-9 holds, for example, setting values ​​for controlling the sensor 50. The register 40-9 also stores data in I2C bulk mode format to be transmitted to the peripheral device 60 connected via the LS I / F#1 40-1.

[0107] The ENCP MEM 20-11 in the SerDes#1 20 generates a packet for the ENC 10 to transmit data directly to the register 40-9 in the SerDes#2 40. The DECP MEM 20-12 extracts data in the I2C bulk mode format from the sensor 50 from the downlink packet sent from the SerDes#2 40 and received by the PHY 20-5 and the DLL 20-4.

[0108] The DECP MEM 40-8 in the SerDes#2 40 built into the sensor 50 extracts the data in the I2C bulk mode format contained in the packet from the SerDes#1 20 and stores it in a register 40-9. The ENCP MEM 40-7 reads the data of the sensor 50 or the peripheral device 60 stored in the register 40-9, creates an ASA-compliant packet, and sends it to the DLL 40-4.

[0109] The DECP LS I / F #1 40-3 extracts data in I2C bulk mode format from the ECU 10 that is stored in the register 40-9 and transmits it to the peripheral device 60 via the LS I / F #1 40-1. The ENCP LS I / F #1 40-2 receives data transmitted by I2C communication from the peripheral device 60 via the LS I / F #1 40-1 and converts it into packets.

[0110] The following describes the operation of the communication system 1 in Fig. 10. It is assumed that the ECU 10 knows in advance the address mapping of the register 40-9 of the sensor 50. Fig. 11 is a diagram showing an example of the address mapping of the register 40-9.

[0111] As shown in FIG. 11, the register 40-9 has a sensor control register area (FIG. 11(A)), an I2C bulk mode format Write / Read area (FIG. 11(B)), and an I2C bulk mode format ACKNACK / Read response command area (FIG. 11(C)).

[0112] The sensor control register area in Fig. 11(A) is an area for storing register data for controlling the sensor 50. The I2C bulk mode format Write / Read area in Fig. 11(B) is an area for storing data in the I2C bulk mode format for controlling the peripheral device 60 connected to the sensor 50 via the I2C bus in the I2C bulk mode. The I2C bulk mode format is generated by the ECU 10. The I2C bulk mode format ACKNACK / Read response command area in Fig. 11(C) is an area for storing an ACKNACK / Read response command in the I2C bulk mode format from the peripheral device 60.

[0113] Fig. 12 is a diagram showing the data structure of a memory write / read command packet format transmitted from SerDes#1 20. Fig. 13 is a diagram showing the data structure of a memory write / read command stored in memory 10-2 in ECU 10. Fig. 14 is a diagram showing the data structure of a memory write / read command stored in buffer memory 20-8 in SerDes#1 20.

[0114] 15A and 15B are flowcharts showing the processing procedure of the communication system 1 according to the second embodiment. First, the ECU 10 stores data to be input to the ENCP MEM 20-11 in the memory 10-2 (FIG. 13, step S21). The memory 10-2 stores an ENCP ID (FIG. 13(A)), which is identification information for the ENCP MEM 20-11, the number of pieces of data to be input to the ENCP MEM 20-11 (FIG. 13(B)), and a memory Write / Read command format (FIG. 13(C)) including data to be written to the sensor control register area (FIG. 11(A)) of the register 40-9 of the sensor 50.

[0115] The write address of the sensor control register area (FIG. 11A) of the register 40-9 in the sensor 50 is stored by the ECU 10 in the offset address area (FIG. 12) in the memory write / read command format (FIG. 13C).

[0116] The ECU 10 instructs the HS I / F 10-6 to transfer the data from 0x0100 to 0x01XX on the memory 10-2 (step S22).

[0117] The HS I / F 10-6 retrieves the data from 0x0100 to 0x01XX from the memory 10-2 and outputs it to the SerDes#1 20 in sequence according to the HS I / F protocol (step S23).

[0118] The HS I / F 20-7 of the SerDes#1 20 sequentially receives data from the HS I / F 10-6 in the ECU 10 and stores the data in the buffer memory 20-8 (FIG. 14, step S24).

[0119] The decoder 20-9 reads the data from the buffer memory 20-8 (step S25). At this time, it analyzes the ENCP ID (FIG. 14(A)) written at the beginning, and outputs the data to the ENCP MEM 20-11 since the ENCP ID = ENCP MEM. The decoder 20-9 reads the number of data indicated by the number of data (FIG. 14(B)) from the buffer memory 20-8 and outputs it to the ENCP MEM 20-11. Through the operations up to this point, the data required for data writing is transferred to the ENCP MEM 20-11.

[0120] As with typical ASA serial communications, the ENCP MEM 20-11 stores the received memory Write / Read command packet format (FIG. 14(C)) in the packet payload of FIG. 5(B), adds a packet header indicating the packet type, etc., creates a packet format (FIG. 5(B)), and outputs it to the DLL 20-4 (step S26).

[0121] The subsequent processing by the DLL 20-4 and PHY 20-5 of SerDes#1 20 is basically the same as that of general ASA serial communication, but the DLL 20-4 stores information in the container header (FIG. 5(C)) indicating that the output destination of the packet format is the DECP MEM 40-8 (step S27). An uplink packet conforming to ASA is transmitted from SerDes#1 20 to SerDes#2 40.

[0122] The processing of the PHY 40-5 and DLL 40-4 of the SerDes#2 40 built into the sensor 50 is the same as that of general ASA serial communication (step S28).

[0123] The DLL 40-4 analyzes the container header of the Link layer container format (FIG. 5C) and finds that the DLL payload stores data to be output to the DECP MEM 40-8. Accordingly, the DLL 40-4 outputs the DLL payload (FIG. 5C) to the DECP MEM 40-8 (step S29).

[0124] The DECP MEM 40-8 analyzes the packet payload (FIG. 5(B)) and determines that a memory Write command is being transferred from the command mode of the memory Write / Read command format (FIG. 12) (step S30). It then analyzes the subsequent Write / Read / ACKNACK / Read response information (FIG. 12) to determine the register offset address and data length. This allows the DECP MEM 40-8 to correctly determine all write data.

[0125] The DECP MEM 40-8 writes data sequentially into the sensor control register area (FIG. 11(A)) of the register 40-9, starting from the address written in the offset address (step S31).

[0126] If all data has been written without error, the ENCP MEM (40-7) selects the ACK / NACK format, generates a memory Write / Read command packet format (FIG. 12) that stores "No error" in the ACKNACK information, and adds a packet header to generate the packet format (FIG. 5(B)) (step S32).

[0127] The processing of the DLL 40-4 and PHY 40-5 is the same as that of general ASA serial communication, and the PHY format (FIG. 5(D)) is finally output to the downlink (step S33).

[0128] The processing of the PHY 20-5 and DLL 20-4 of the SerDes#1 20 is the same as that of general ASA serial communication, but the DLL 20-4 analyzes the container header and outputs the packet format in the DLL payload to the DECP MEM 20-12 (step S34).

[0129] The DECP MEM 20-12 extracts the memory Write / Read command packet format (FIG. 12) stored in the packet payload from the packet format and outputs it to the encoder 20-10 (step S35).

[0130] The encoder 20-10 generates the DECP ID (here, ECU 10) (FIG. 14(D)) and the number of data (FIG. 14(E)) of the memory Write / Read command packet format (FIG. 12), and outputs them together with the memory Write / Read command packet format (FIG. 14(F)) to the memory 10-2 area of ​​the buffer memory 20-8 that has been allocated in advance (FIG. 14, step S36).

[0131] The subsequent processing is the same as that from step S13 onwards in the first embodiment, and finally, the ECU 10 confirms that there is no error written in the ACK / NACK information of the memory Write / Read command packet format (Figure 13(F)) stored in memory 10-2, confirms that the control data has been transferred to register 40-9 of sensor 50, and terminates the control data transfer operation (step S37).

[0132] To read data, the command mode of the memory Write / Read command packet format (FIG. 12) is set to Read command and transmitted to the sensor 50. The data read processing procedure is the same as that already explained. In response, the command mode of the memory Write / Read command packet format (FIG. 12) is set to Read response and transmitted to the SerDes#1 20. This processing procedure is also the same as that already explained.

[0133] As described above, in the second embodiment, when the sensor 50 has a built-in SerDes#2 40, the ECU 10 first stores control data for the sensor 50 in the memory 10-2, and then stores the control data from the memory 10-2 in the register 40-9 in the SerDes#2 40 via the SerDes#1 20 and the SerDes#2 40. This allows the ECU 10 to directly control the sensor 50. Because the ECU 10 and the SerDes#1 20 transmit signals via a high-speed interface, the ECU 10 can quickly transmit control data to the sensor 50 and can also quickly transmit data acquired by the sensor 50 to the ECU 10.

[0134] (Third embodiment) The second embodiment described above is characterized in that the ECU 10 can directly write to and read from the register 40-9 of the sensor 50 having the SerDes#2 40. In contrast, the third embodiment described below is characterized in that the ECU 10 can directly write to and read from the peripheral device 60 that communicates with the sensor 50 having the SerDes#2 40 via I2C.

[0135] The communication system 1 according to the third embodiment has the same block configuration as that shown in FIG. 10. The peripheral device 60 has an I2C communication function. The ECU 10 transmits data in the I2C bulk mode format to the peripheral device 60. More specifically, the ECU 10 writes the control data in the I2C bulk mode format to a register 40-9 of the peripheral device 60 via a sensor 50 incorporating a SerDes#1 20 and a SerDes#2 40.

[0136] 16 is a diagram showing a memory map when the ECU 10 according to the third embodiment writes data in the I2C bulk mode format to the memory 10-2. The memory 10-2 has an area (FIG. 16(A)) for storing an ENCP ID, which is identification information of the ENCP MEM 20-11 in the SerDes#1 20, an area (FIG. 16(B)) for storing the number of data items to be input to the ENCP MEM 20-11, a memory write / read command format (FIG. 16(C)) including data to be written to the sensor control register area (FIG. 11(A)) of the register 40-9 of the sensor 50, an area (FIG. 16(D)) for storing the ENCP ID, which is identification information of the ECU 10, an area (FIG. 16(E)) for storing the total number of data items to be input to the ECU 10, and an area (FIG. 16(F)) for storing memory write / read response information including the data to be input to the ECU 10. The data structure of the I2C command format stored in the area of ​​FIG. 16(C) is shown in FIG. 16(G), and the data structure of the I2C command format stored in the area of ​​FIG. 16(f) is shown in FIG. 16(H).

[0137] 17A and 17B are flowcharts showing the processing procedure of the communication system 1 according to the third embodiment. First, the ECU 10 stores the slave address of the peripheral device 60 in the slave address of the Write / Read / ACKNACK / Read response command in the I2C bulk mode format (FIG. 3), selects the Write command format, stores the write destination address as an offset address, and generates an I2C bulk mode format in which control data is stored in data (step S41).

[0138] The ECU 10 stores data in the I2C bulk mode format to be input to the ENCP MEM 20-11 in the memory 10-2 (FIG. 16, step S42). The output destination, ENCP MEM 20-11, is stored in the ENCP ID (FIG. 16(A)), and the number of data to be input to the ENCP MEM 20-11 is stored in the Number of data (FIG. 16(B)). The memory area following this area stores, as a Write command format, a memory Write / Read command packet format (FIG. 12) to be written to the sensor control register area (FIG. 11(B)) of the register 40-9 of the sensor 50. At this time, the previously generated data in the I2C bulk mode format is written in the Write data (FIG. 16(G)).

[0139] The subsequent procedure for writing to the I2C bulk mode format Write / Read / ACKNACK / Read response command area (FIG. 11B) of the register 40-9 of the sensor 50 is the same as the procedure described in the second embodiment (step S43).

[0140] The register 40-9, to which the data in the I2C bulk mode format has been written, outputs the I2C bulk mode format to the DECP LS I / F 40-3 (step S44).

[0141] The method in which the DECP LS I / F 40-3 controls the LS I / F #1 40-1 using data in the I2C bulk mode format to perform I2C communication is the same as normal I2C bulk mode communication (step S45).

[0142] The LS I / F#1 40-1 writes the control data in the I2C bulk mode format to the peripheral device 60 via I2C communication (step S46). At the same time, the ENCP LS I / F#1 40-2 stores the ACK signal sent back by the peripheral device 60 in response to this I2C communication, and when the I2C communication ends, generates data in the I2C bulk mode format that stores the settings for the I2C bulk mode ACK NACK command (FIG. 3) and all the ACK NACK signals, and writes this data to the I2C bulk mode format ACKNACK / Read response command area (FIG. 11(C)) of the register 40-9 (step S47).

[0143] The register 40-9, into which the data of the ACK / NACK response command in the I2C bulk mode format has been written, outputs the data in the I2C bulk mode format to the ENCP MEM 40-7 (step S48).

[0144] The ENCP MEM 40-7 sets the read response format and generates a memory write / read command packet format (FIG. 12) that stores data in the I2C bulk mode format of the ACK / NACK response command in the data area (step S49).

[0145] The packet in the memory write / read command packet format is output to the down link via the DLL 40-4 and PHY 40-5 in the same manner as in the procedures described above (step S50). A packet in the memory write / read command packet format (FIG. 8(B)) received via the PHY 20-5 and DLL 20-4 of the SerDes#1 20 is transferred to the DECP MEM 20-12 (step S51).

[0146] The memory Write / Read command packet format extracted from the payload by the DECP MEM 20-12 is transferred to the encoder 20-10 (step S52).

[0147] The encoder 20-10 generates a DECP ID (here, ECU 10) (FIG. 14(D)), a memory write / read command packet format (FIG. 12), and the total number of data (FIG. 14(E)), and outputs them together with the memory write / read command packet format (FIG. 14(F)) to the memory 10-2 area of ​​the pre-allocated buffer memory 20-8 (FIG. 14, step S53).

[0148] The subsequent processing is the same as that from step S13 onwards in the first embodiment, and finally, the ECU 10 acquires the ACK / NACK result (Fig. 16(H)) of the I2C bulk mode format written in the data area of ​​the memory Write / Read command packet format (Fig. 16(F)) stored in the memory 10-2, confirms that the control data has been transmitted to the peripheral device 60, and terminates the control data transmission operation (step S54).

[0149] As described above, in the third embodiment, when a peripheral device 60 that performs I2C communication is connected to a sensor 50 that incorporates a SerDes#2 40, the ECU 10 stores control data in the I2C bulk mode format for the peripheral device 60 in a register 40-9 in the sensor 50. This allows the ECU 10 to directly control the peripheral device 60.

[0150] (Fourth embodiment) The communication system 1 according to the fourth embodiment is characterized in that it can be applied to both cases where the sensor 50 has the function of the SerDes#2 40 and where it does not have that function.

[0151] Fig. 18 is a block diagram showing a schematic configuration of a communication system 1 including a communication device according to the fourth embodiment. The communication system 1 in Fig. 18 includes an ECU 10 which is a master device 10, a SerDes#1 20 which is a master SerDes 20, a SerDes#2 40 which is a slave SerDes 40, and a sensor 50 which is a slave device 50. The internal configuration of the SerDes#1 20 is different from that of the SerDes#1 20 according to the first to third embodiments.

[0152] The SerDes#1 20 in Fig. 18 includes an ENCP LS I / F#1 20-2, a DECP LS I / F#1 20-3, a DLL 20-4, a PHY 20-5, an OAM 20-6, an HS I / F 20-7, a buffer memory 20-8, a decoder 20-9, and an encoder 20-10, similar to the SerDes#1 20 in Fig. 6. In addition, the SerDes#1 20 in Fig. 18 includes an ENCP MEM 20-11 and a DECP MEM 20-12.

[0153] This allows high-speed serial communication conforming to ASA to be performed whether a SerDes#2 40 without a register as shown in FIG. 6 or FIG. 18 is connected, or a SerDes#2 40 with a register 40-9 as shown in FIG. 10 is connected.

[0154] The present technology can be configured as follows: (1) a communication interface unit that receives control data from a master, the control data including data in a predetermined transmission format of a first protocol, which is to be transmitted from a communication partner device to a slave; a storage unit that stores the data of the first protocol received by the communication interface unit; an encapsulator that converts the data of the first protocol stored in the storage unit into data of a second protocol; a communication unit that transmits the data of the second protocol converted by the encapsulator to the communication partner device. (2) The communication device according to (1), wherein the predetermined transmission format is a format for receiving an ACK signal or a NACK signal from the communication partner device after transmitting multiple bytes of data to the communication partner device. (3) The communication device according to (2), wherein the predetermined transmission format of the first protocol is an I2C bulk mode format defined in ASA (Automotive SerDes Alliance) standard ver. 1.01. (4) The communication device according to (3), wherein the memory unit stores the control data including identification information of the encapsulator, the number of data, and information on the I2C bulk mode format. (5) The communication device according to any one of (1) to (4), wherein the data transmission rate in the communication interface unit is faster than the data transmission rate between the communication partner device and the slave. (6) A communication device described in any one of (1) to (5), comprising a decapsulator that converts data of the second protocol received by the communication unit from the communication partner device into data of the first protocol and stores the data in the memory unit. (7) a first communication device that performs data communication of the first protocol with the master; a second communication device that performs data communication with the first communication device according to a second protocol and performs data communication with a slave according to the first protocol, The first communication device a first communication interface unit that receives control data from the master, the control data including data in a predetermined transmission format of the first protocol, which is to be transmitted by the second communication device to the slave; a first storage unit that stores data of the first protocol received by the first communication interface unit; a first encapsulator that converts the data of the first protocol stored in the first storage unit into data of a second protocol; a first communication unit that transmits the data of the second protocol converted by the first encapsulator to the second communication device. (8) The communication system described in (7), further comprising: a first decapsulator that converts data of the second protocol transmitted from the second communication device and received by the first communication unit into data of the first protocol and stores the data in the first memory unit. (9) The communication system according to (7) or (8), wherein the predetermined transmission format of the first protocol is the I2C bulk mode format defined in ASA standard ver. 1.01. (10) The communication system according to any one of (7) to (9), wherein the data transmission rate in the first communication interface unit is faster than the data transmission rate between the second communication device and the slave. (11) The second communication device is a second communication unit that receives data of the second protocol transmitted from the first communication device; a second decapsulator that converts the data of the second protocol received by the second communication unit into data of the first protocol; The communication system according to any one of (7) to (10), further comprising: a second communication interface unit that transmits the data of the first protocol converted by the second decapsulator to the slave. (12) The second communication device has a second encapsulator that converts the data of the first protocol transmitted by the slave and received by the second communication interface unit into data of the second protocol, The communication system according to (11), wherein the second communication unit transmits the data of the second protocol converted by the second encapsulator to the first communication device. (13) The master is a second storage unit that stores the control data including data of the first protocol that is to be transmitted by the second communication device to the slave; The communication system according to any one of (7) to (12), further comprising: a third communication interface unit that transmits the control data stored in the second storage unit to the first communication device. (14) An internal slave is built into the second communication device and is directly controlled by the master; The communication system according to any one of (7) to (13), wherein the second communication device has a third storage unit that stores data for the master to directly control the internal slave. (15) The communication system according to (14), wherein the third storage unit stores data of the first protocol to be transmitted to the slave. (16) The first communication device is a third encapsulator that converts data from the master stored in the first storage unit into data of the second protocol; a third decapsulator that converts a protocol of the internal slave data that is received by the first communication unit and read from the third storage unit, The communication system according to (14) or (15), wherein the second communication device stores the data output from the third encapsulator in the third storage unit. (17) receiving control data from the master at the communication interface unit, the control data including data in a predetermined transmission format of the first protocol to be transmitted by the communication partner device to the slave; storing the data of the first protocol received by the communication interface unit in a storage unit; converting the data of the first protocol stored in the storage unit into data of a second protocol; a communication method in which the converted data of the second protocol is transmitted to the communication partner device;

[0155] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0156] 1 Communication system, 10 ECU, 10-1 ECU core, 10-2 Memory, 10-3 Second low-speed interface unit (LS I / F#2), 10-4 First low-speed interface unit (LS I / F#1), 20 SerDes#1, 20-1 Low-speed interface unit (LS I / F#1), 20-2 Encapsulator (ENCP LS I / F#1), 20-3 Decapsulator (DECP LS I / F#2), 20-8 Buffer memory, 20-9 Decoder, 20-10 Encoder (ENCP MEM), 20-11 Encapsulator (ENCP LS I / F#1), 20-12 Decapsulator (DECP MEM), 30 Cable, 40 SerDes#2, 40-1 Low-speed interface unit (LS I / F#1), 40-2 Encapsulator (ENCP LS I / F#2), 40-3 De-encapsulator (DECP LS I / F#1), 40-6 OAM unit, 40-7 ENCP MEM, 40-8 DECP MEM, 40-9 Register, 50 Slave device, 50 Sensor, 50 Image sensor, 50-1 Register, 50-2 Low-speed interface unit (LS I / F#1), 60 Peripheral device

Claims

1. a communication interface unit that receives control data from the master, the control data including data in a predetermined transmission format of the first protocol, which is to be transmitted from the communication partner device to the slave; a storage unit that stores the data of the first protocol received by the communication interface unit; an encapsulator that converts the data of the first protocol stored in the storage unit into data of a second protocol; a communication unit that transmits the data of the second protocol converted by the encapsulator to the communication partner device, The communication device, wherein the predetermined transmission format is a format for receiving an ACK signal or a NACK signal from the communication partner device after completing transmission of multiple bytes of data to the communication partner device.

2. 2. The communication device according to claim 1, wherein the predetermined transmission format of the first protocol is an I2C bulk mode format defined in ASA (Automotive SerDes Alliance) standard version 1.

01.

3. 3. The communication device according to claim 2, wherein the storage unit stores the control data including identification information of the encapsulator, a number of pieces of data, and information on the I2C bulk mode format.

4. A communication interface unit that receives control data from a master, the control data including data in a predetermined transmission format of a first protocol, which is transmitted from a communication partner device to a slave; a storage unit that stores the data of the first protocol received by the communication interface unit; an encapsulator that converts the data of the first protocol stored in the storage unit into data of a second protocol; a communication unit that transmits the data of the second protocol converted by the encapsulator to the communication partner device, A communication device, wherein the data transmission rate in the communication interface unit is faster than the data transmission rate between the communication partner device and the slave.

5. 5. The communication device according to claim 1, further comprising: a decapsulator that converts data of the second protocol received by the communication unit from the communication partner device into data of the first protocol and stores the converted data in the memory unit.

6. a first communication device that performs data communication with a master according to a first protocol; a second communication device that performs data communication with the first communication device according to a second protocol and performs data communication with a slave according to the first protocol, The first communication device a first communication interface unit that receives, from the master, control data including data in a predetermined transmission format of the first protocol that is to be transmitted by the second communication device to the slave; a first storage unit that stores data of the first protocol received by the first communication interface unit; a first encapsulator that converts the data of the first protocol stored in the first storage unit into data of a second protocol; a first communication unit that transmits the data of the second protocol converted by the first encapsulator to the second communication device.

7. 7. The communication system according to claim 6, further comprising: a first decapsulator that converts data of the second protocol transmitted from the second communication device and received by the first communication unit into data of the first protocol and stores the data in the first storage unit.

8. 7. The communication system according to claim 6, wherein the predetermined transmission format of the first protocol is an I2C bulk mode format defined in ASA standard ver. 1.

01.

9. 7. The communication system according to claim 6, wherein a data transmission rate in said first communication interface unit is higher than a data transmission rate between said second communication device and said slave.

10. the second communication device, a second communication unit that receives data of the second protocol transmitted from the first communication device; a second decapsulator that converts the data of the second protocol received by the second communication unit into data of the first protocol; 7. The communication system according to claim 6, further comprising: a second communication interface unit that transmits the data of the first protocol converted by the second decapsulator to the slave.

11. the second communication device has a second encapsulator that converts the data of the first protocol transmitted by the slave and received by the second communication interface unit into data of the second protocol; The communication system according to claim 10 , wherein the second communication unit transmits the data of the second protocol converted by the second encapsulator to the first communication device.

12. The master a second storage unit configured to store the control data including data of the first protocol to be transmitted by the second communication device to the slave; The communication system according to claim 6 , further comprising: a third communication interface unit that transmits the control data stored in the second storage unit to the first communication device.

13. an internal slave that is built into the second communication device and is directly controlled by the master; 7. The communication system according to claim 6, wherein the second communication device has a third storage unit that stores data for the master to directly control the internal slave.

14. The communication system according to claim 13 , wherein the third storage unit stores data of the first protocol to be transmitted to the slave.

15. The first communication device a third encapsulator that converts data from the master stored in the first storage unit into data of the second protocol; a third decapsulator that converts a protocol of the internal slave data that is received by the first communication unit and read from the third storage unit, The communication system according to claim 13 , wherein the second communication device stores the data output from the third encapsulator in the third storage unit.

16. receiving, from the master, control data including data in a predetermined transmission format of the first protocol, which is to be transmitted from the communication partner device to the slave, at a communication interface unit; storing the data of the first protocol received by the communication interface unit in a storage unit; converting the data of the first protocol stored in the storage unit into data of a second protocol; transmitting the converted data of the second protocol to the communication partner device; The communication method, wherein the predetermined transmission format is a format for receiving an ACK signal or a NACK signal from the communication partner device after completing transmission of multiple bytes of data to the communication partner device.

17. A communication interface unit receives control data from a master, the control data including data in a predetermined transmission format of a first protocol, which is to be transmitted from a communication partner device to a slave; storing the data of the first protocol received by the communication interface unit in a storage unit; converting the data of the first protocol stored in the storage unit into data of a second protocol; transmitting the converted data of the second protocol to the communication partner device; A communication method, wherein the data transmission rate in the communication interface unit is faster than the data transmission rate between the communication partner device and the slave.

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