Link establishment apparatus, method and system

Abstract

A link establishment device (1600) which is configured to be connected to another device via an interface of JESD204B and to execute a link establishment procedure for establishing a link with the other device, the link establishment device comprising: a reception means (1610) that receives a first parameter of JESD204B from the other device in the link establishment procedure; and a changing means (1620) that, when a second parameter of JESD204B having been set in the link establishment device does not match the first parameter received by the reception means, changes the second parameter so as to match the first parameter.

Description

[Technical Field]

[0001] The present disclosure relates to a link establishment device, a method implemented in the link establishment device, and a system. [Background technology]

[0002] BACKGROUND ART In recent years, in the field of mobile communications, wireless communication devices (for example, base station devices) using MIMO (Multiple Input Multiple Output) have come into use to achieve multi-channel connections and high-speed data communications.

[0003] Furthermore, the number of antennas installed in wireless communication devices is also increasing year by year. The increased number of antennas also increases the number of DACs (Digital-to-Analog Converters) and ADCs (Analog-to-Digital Converters) implemented on wireless communication devices. As a result, the amount of wiring inside wireless communication devices also increases. To solve this problem, the JEDEC Solid State Technology Association established JESD204B / JESD204C. JESD204B / JESD204C are serial interface standards formulated for high-speed, high-resolution data converters (ADCs and DACs). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-009781 [Patent Document 2] Japanese Patent Application Publication No. 2018-046462 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-208398 Summary of the Invention [Problem to be solved by the invention]

[0005] A wireless communication device is required to have the number of antennas that matches the situation in which the device is installed. For example, wireless communication devices are designed to have 32 ANTs (antennas), 64 ANTs, or 128 ANTs.

[0006] For wireless communication devices, devices that integrate four ADCs and four DACs into one TRX_IC (transceiver IC) are generally used. For example, JESD204B is used to connect to this TRX_IC. Therefore, device designs that include JESD204B are required.

[0007] Suppose you are designing multiple devices with different JESD204B parameters. In this case, since the parameters cannot be changed, you need to design a circuit for each device. This poses the problem of longer circuit design and evaluation times.

[0008] The present disclosure provides techniques for standardizing circuits that use JESD204B. [Means for solving the problem]

[0009] In one or more embodiments, a link establishment device is provided, the link establishment device being connected to another device via a JESD204B interface and configured to execute a link establishment procedure to establish a link with the other device, the link establishment device further comprising: receiving means for receiving a first JESD204B parameter from the other device during the link establishment procedure; and, if a second JESD204B parameter set in the link establishment device does not match the first parameter received by the receiving means, changing means for changing the second parameter to match the first parameter.

[0010] In one or more embodiments, a method is provided for execution in a link establishment device, the link establishment device being connected to another device via a JESD204B interface and configured to execute a link establishment procedure to establish a link with the other device, the method including: receiving a first JESD204B parameter from the other device during the link establishment procedure; and, if a second JESD204B parameter set in the link establishment device does not match the received first parameter, changing the second parameter to match the first parameter.

[0011] In one or more embodiments, a system is provided that includes a first device configured to set a JESD204B first parameter and to change the first parameter, and a second device connected to the first device via a JESD204B interface. The first device and the second device are configured to execute a link establishment procedure to establish a link between the first device and the second device. The second device includes receiving means for receiving a JESD204B first parameter from the first device during the link establishment procedure, and changing means for changing a JESD204B second parameter set in the second device to match the first parameter if the second parameter does not match the first parameter received by the receiving means. [Effects of the Invention]

[0012] According to the above configuration, it is possible to standardize circuits that use JESD204B. Problems, configurations, and effects other than those described above will become clear from the following description of the embodiments. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram for explaining the basic contents of a JESD204B link establishment procedure (link-up sequence). [Figure 2]1 is a table showing some of the parameters used in JESD204B. [Figure 3] FIG. 2 is a diagram illustrating a basic configuration of a system including a transmitting device (TX device) and a receiving device (RX device) shown in FIG. [Figure 4] 1 is an example of a configuration of a system according to a first embodiment. [Figure 5] FIG. 10 is a diagram showing the contents of a plurality of setting files. [Figure 6] FIG. 10 is a diagram showing JESD204B parameters received by multiframe. [Figure 7] 10 is a flowchart showing an example of the flow of a process for changing a JESD204B parameter (second parameter) in a receiving device. [Figure 8] 10 is a diagram showing the contents of multiple setting files that define combinations of ADC JESD204B parameters and DAC JESD204B parameters. [Figure 9] FIG. 10 is a diagram illustrating an example of a system configuration according to a second modified example of the first embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of a system configuration according to a second modified example of the first embodiment. [Figure 11] FIG. 10 is a diagram illustrating an example of a system configuration according to a third modified example of the first embodiment. [Figure 12] FIG. 10 is a diagram illustrating an example of a system configuration according to a fourth modified example of the first embodiment. [Figure 13] FIG. 10 is a diagram illustrating an example of a system configuration according to a fourth modified example of the first embodiment. [Figure 14] FIG. 10 is a diagram illustrating an example of a system configuration according to a fourth modified example of the first embodiment. [Figure 15] FIG. 10 is a diagram illustrating an example of a system configuration according to a fourth modified example of the first embodiment. [Figure 16] FIG. 10 is a diagram illustrating an example of the configuration of a link establishment device according to a second embodiment. [Figure 17]10 is a flowchart showing an example of a flow of processing by the link establishment device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] One or more embodiments will be described below with reference to the accompanying drawings. In this specification and drawings, elements that can be similarly described will be designated by the same reference numerals, and redundant description will be omitted.

[0015] The explanation will be given in the following order: 1. Overview of the embodiment 2. First embodiment 2-1.JESD204B 2-2. Basic system configuration 2-3.Specific system configuration 2-4. Example of operation of receiving device and transmitting device 2-5. Processing flow of receiving device Effects 2-7. Variations 3. Second embodiment 3-1. Configuration of link establishment device 3-2. Processing flow 4. Other Embodiments

[0016] <<1. Overview of the embodiment>> An overview of one or more embodiments described below will be provided. In one or more embodiments, a link establishment device is provided. The link establishment device is connected to another device via a JESD204B interface and configured to perform a link establishment procedure to establish a link with the other device.

[0017] The link establishment device includes a receiver and a changer. The receiver receives a first JESD204B parameter from the other device during the link establishment procedure. If a second JESD204B parameter set in the link establishment device does not match the first parameter received by the receiver, the changer changes the second parameter to match the first parameter.

[0018] According to the above configuration, even when multiple devices with different JESD204B parameters are designed, the configuration of the link establishment device can be made common, thereby reducing the time required for designing and evaluating the device.

[0019] <<2. First Embodiment>> Next, the first embodiment and its modified examples will be described with reference to FIGS.

[0020] <2-1.JESD204B> First, JESD204B will be described as a technology related to the embodiment.

[0021] As mentioned above, JESD204B is a serial interface standard established for high-speed, high-resolution data converters (ADCs and DACs). JESD204B enables high-speed serial transmission with a fixed delay between the transmitting device and the receiving device by using the SYSREF signal as the reference timing.

[0022] This section explains the link establishment procedure in JESD204B. This procedure is also called the "link-up sequence." In JESD204B, a synchronization link is established using three states (phases): "CGS (Code Group Synchronization)," "ILAS (Initial Lane Alignment Sequence)," and "UserData." Specifically, after power-on or reset release, the state becomes the initial state, CGS. Next, the state transitions to ILAS, and then to UserData. UserData is the state in which the link is established.

[0023] Figure 1 is a diagram for explaining the basic contents of the JESD204B link establishment procedure. In Figure 1, "TX device" represents the "transmitting device" and "RX device" represents the "receiving device."

[0024] In the initial state, CGS, the transmitting device continues to transmit K (K28.5=BCh). When the transmitting device detects "SYSREF=1", it aligns (adjusts) the timing of the LMFC (Local Multi Frame Clock).

[0025] When the receiving device detects "SYSREF=1", it aligns the timing of the LMFC. After the receiving device receives the signal (K28.5) correctly and the alignment is complete, it sets "SYNCB" to "1" (i.e., SYNCB=1).

[0026] Furthermore, when the transmitting device detects "SYNCB=1", it transitions to ILAS at the timing of the next LMFC. As shown in Figure 1, the transmitting device and receiving device receive SYSREF at the same timing.

[0027] In ILAS, a transmitting device transmits four consecutive multiframes 1 to 4. The signals transmitted in the four multiframes 1 to 4 are as follows. In this specification, when several consecutive characters (octets) are transmitted as a single block of data, the block of data is called a "frame." Furthermore, when several consecutive frames are transmitted as a single block of data, the block of data is called a "multiframe."

[0028] Multiframe 1: Starts with the character / R / (K28.0), followed by a dummy signal, and ends with the character / A / (K28.3). Multiframe 2: Starts with the character / R / (K28.0), followed by / Q / (K28.4), followed by 14 octets of link configuration parameters, followed by a dummy signal, and ends with the character / A / (K28.3). Multiframe 3: It has the same content as multiframe 1. That is, it starts with the character / R / (K28.0), is followed by a dummy signal, and ends with the character / A / (K28.3). Multiframe 4: It has the same contents as multiframe 1. It starts with the character / R / (K28.0), followed by a dummy signal, and ends with the character / A / (K28.3).

[0029] The receiving device reads the link setting parameters from multiframe 2. If the receiving device determines that there is no problem with the link setting parameters, it continues to set "SYNCB=1". However, if the receiving device determines that there is a problem with the link setting parameters, it sets SYNCB to "0" (i.e., SYNCB=0).

[0030] If "SYNCB=1" continues to be set, the state transitions to UserData. On the other hand, if "SYNCB=0" is set, the state transitions to CGS.

[0031] The receiving device stores the received signal in a buffer at the character / R / (see "Buffer In" in Figure 1). Furthermore, the receiving device reads the signal from the buffer at the LMFC (see "Buffer Out" in Figure 1). This determines the delay between the transmitting device and the receiving device.

[0032] In UserData, the transmitting device transmits an IQ signal. The receiving device monitors the alignment. If an abnormality occurs, the receiving device sets "SYNCB" to "0" (i.e., SYNCB=0). In this case, the state transitions to CGS.

[0033] Figure 2 is a table showing some of the parameters used in JESD204B. The parameters shown in Figure 2 are used in transmitting devices and receiving devices. In this specification, the parameters shown in Figure 2 and parameters converted from the parameters shown in Figure 2 (e.g., data rate and LMFC) are collectively referred to as "JESD204B parameters."

[0034] <2-2. Basic system configuration> FIG. 3 is a diagram illustrating the basic configuration of a system 10 including the transmitting device (TX device) and receiving device (RX device) shown in FIG.

[0035] The system 10 includes a transmitting device 100 and a receiving device 200. The transmitting device 100 and the receiving device 200 are connected via a JESD204B interface. The transmitting device 100 and the receiving device 200 are configured to execute a link establishment procedure (link-up sequence) for establishing a link.

[0036] The transmitting device 100 is a transmitting circuit implemented in accordance with JESD204B, and in this example is an ADC.

[0037] The receiving device 200 is a receiving circuit implemented in accordance with JESD204B and includes a processing circuit (processor) 210 and a clock driver 220.

[0038] In this example, the processing circuit 210 is implemented by an FPGA (Field Programmable Gate Array). The FPGA includes, as its internal structure, logic elements (logic cells), an I / O unit, internal wiring, dedicated clock wiring, a multiplier, and block storage elements (e.g., RAM).

[0039] In another example, the processing circuitry 210 may be implemented by an Application Specific Integrated Circuit (ASIC).

[0040] In yet another example, the processing circuit 210 may be configured using other devices, such as a semiconductor device including a CPU (Central Processing Unit) and memory. In this case, the functions of the processing circuit 210 may be realized by a processor executing a program read from the memory. Furthermore, the functions of the processing circuit 210 may be realized by an FPGA and a CPU and memory provided around the FPGA.

[0041] The processing circuit 210 includes, as functional blocks, a JESD processing unit 211 and a JESD synchronization monitoring unit 214. The JESD processing unit 211 includes a physical layer (PHY) unit 212 and a JESD synchronization detection unit 213.

[0042] Hereinafter, for simplicity of notation, the physical layer unit 212 will be referred to as the "PHY unit 212", the JESD synchronization detection unit 213 will be referred to as the "synchronization detection unit 213", and the JESD synchronization monitoring unit 214 will be referred to as the "synchronization monitoring unit 214".

[0043] The PHY unit 212 is connected to the transmitting device 100 via a JESD204B interface. The PHY unit 212 has a CDR (Clock Data Recovery) function and a serial-to-parallel conversion function.

[0044] The synchronization detector 213 has an 8B / 10B decoding function. In JESD204B data transmission, converted data is divided into 8-bit blocks, and this data (octets) is converted into 10-bit data (characters) and transmitted. This conversion technology is called "8B / 10B." Furthermore, the synchronization detector 213 has a function to detect the JESD synchronization state (i.e., the synchronization state between the transmitting device 100 and the receiving device 200).

[0045] The synchronization monitor 214 monitors the synchronization state between the transmitting device 100 and the receiving device 200. Furthermore, the synchronization monitor 214 has a function of changing the settings of the PHY unit 212 and the synchronization detector 213.

[0046] The clock driver 220 supplies (outputs) a clock signal and a synchronization signal.

[0047] Next, signals 301 to 314 shown in FIG. 3 will be described.

[0048] The serial data 301 is a signal transmitted from the transmitting device 100 to the PHY unit 212. The serial data 301 is a high-speed serial signal used in JESD204B.

[0049] CDR_LOCK 302 is a signal transmitted from the PHY unit 212 to the synchronization monitor unit 214. CDR_LOCK 302 is a signal that indicates the synchronization state of the serial signal received by the PHY unit 212.

[0050] The parallel data 303 is a signal transmitted from the PHY unit 212 to the synchronization detection unit 213. The parallel data 303 is a parallel signal that has been SP (Serial to Parallel) converted by the PHY unit 212, and is a signal in an 8B / 10B decoded format.

[0051] The control / notification 304 includes a signal transmitted from the PHY unit 212 to the synchronization detection unit 213, and a signal transmitted from the synchronization detection unit 213 to the PHY unit 212. The control / notification 304 includes control signals (reset, disable, etc.) for the PHY unit 212, and access signals to internal registers of the PHY unit 212. Furthermore, the control / notification 304 includes a signal notifying the state of the CDR.

[0052] SYNC control 305 is a signal transmitted from the synchronization detection unit 213 to the synchronization monitoring unit 214. SYNC control 305 becomes "1" when there is no abnormality in the parallel data 303 received by the synchronization detection unit 213 in the CGS. Furthermore, SYNC control 305 becomes "0" when there is an abnormality in the LMFC or 8B / 10B processing in the ILAS and UserData. Note that in existing (conventional) JESD circuits, SYNC control 305 is used as a signal that provides the same function as SYNCB 308, which will be described later.

[0053] The control / notification 306 includes a signal transmitted from the synchronization detection unit 213 to the synchronization monitoring unit 214, and a signal transmitted from the synchronization monitoring unit 214 to the synchronization detection unit 213. The control / notification 306 includes a signal indicating the state of the signal detected by the synchronization detection unit 213, a signal indicating the synchronization state detected by the synchronization detection unit 213, and the like. The control / notification 306 includes a signal indicating the 8B / 10B decoding state, a signal indicating an abnormality in the JESD204B parameters, and the like. Furthermore, the control / notification 306 includes an interrupt request, a control signal for an internal register of the synchronization detection unit 213, and the like.

[0054] The PHY setting 307 is a signal transmitted from the synchronization monitor 214 to the PHY unit 212. The PHY setting 307 is a signal that changes the setting of the internal register of the PHY unit 212.

[0055] SYNCB 308 is a signal transmitted from the synchronization monitor 214 to the transmitting device 100. SYNCB 308 is a signal that notifies the transmitting device 100 of the state of the signal received by the processing circuit 210, and corresponds to "SYNCB" described in FIG.

[0056] The clock driver control 309 is a signal transmitted from the synchronization monitor 214 to the clock driver 220. The clock driver control 309 includes a signal for controlling the clock driver 220. For example, the clock driver control 309 includes a signal for performing internal settings of the clock driver 220 using an SPI (Serial Peripheral Interface) or the like, and a signal for monitoring the state of the clock driver 220.

[0057] SYSREF 310 is a signal transmitted from the clock driver 220 to the transmitting device 100. SYSREF 310 corresponds to "SYSREF" described in FIG.

[0058] SYSREF311 is a signal transmitted from the clock driver 220 to the processing circuit 210 (specifically, the synchronization detection unit 213). SYSREF311 corresponds to "SYSREF" described with reference to FIG.

[0059] The parameter setting 312 is a signal transmitted from the synchronization monitor 214 to the synchronization detector 213. The parameter setting 312 is a signal for changing the setting of the JESD204B parameters that the synchronization detector 213 has.

[0060] The device clock 313 is a signal transmitted from the clock driver 220 to the transmitting device 100. The device clock 313 is a signal indicating an operating clock.

[0061] The device clock 314 is a signal transmitted from the clock driver 220 to the processing circuit 210. The device clock 314 is a signal indicating an operation clock.

[0062] <2-3. Specific system configuration> Fig. 4 shows an example of the configuration of a system 400 according to the first embodiment. In Fig. 4, the same components as those in Fig. 3 are denoted by the same reference numerals as those in Fig. 3, and the description thereof will be omitted.

[0063] The system 400 is configured as, for example, a part of a wireless communication system, and includes a transmitting device 100, a receiving device 200, and a control computer 300.

[0064] The transmitting device 100 is an ADC, as described above. The transmitting device 100 includes four antennas. The receiving device 200 includes a processing circuit 210 and a clock driver 220, as described above. The transmitting device 100 and the receiving device 200 are mounted on a PWB (printed wiring board).

[0065] The transmitting device 100 and the receiving device 200 are connected by a JESD204B interface. The transmitting device 100 and the receiving device 200 are connected by four lines (Lane #0 to #3) for transmitting serial data 301. Furthermore, the transmitting device 100 and the receiving device 200 are connected by one line for transmitting SYNCB 308.

[0066] The control computer 300 is an information processing device for setting JESD204B parameters of the transmitting device 100. In this example, the control computer 300 can set (change) the JESD204B parameters of the transmitting device 100 in accordance with four setting files #0 to #3.

[0067] Fig. 5 shows the contents of setting files #0 to #3. Each of setting files #0 to #3 includes some of the parameters shown in Fig. 2 and parameters converted from the parameters shown in Fig. 2 (for example, data rate and LMFC).

[0068] <2-4. Operational examples of receiving and transmitting devices> Next, four operation examples of the transmitting device 100 and the receiving device 200 will be described. Note that, for simplicity of notation, the initial JESD204B parameters set in the transmitting device 100 will be referred to as "first parameters." The initial JESD204B parameters set in the processing circuit 210 of the receiving device 200 will be referred to as "second parameters."

[0069] (Example 1) Operation example 1 is an operation when the first parameter in the transmitting device 100 is the setting file #0 in FIG. 5, and the second parameter in the processing circuit 210 is the setting file #0 in FIG.

[0070] In this example, a first parameter in the transmitting device 100 matches a second parameter in the processing circuit 210. For example, a data rate (data rate for the serial data 301) set in the transmitting device 100 matches a data rate (data rate for the serial data 301) set in the PHY unit 212. Other first parameters and other second parameters also match. In this case, after the system 400 is started up or released from reset, no link is established between the transmitting device 100 and the processing circuit 210 of the receiving device 200. Therefore, the JESD204B state is the initial state, CGS. The transmitting device 100 and the receiving device 200 perform a link establishment procedure (link up sequence) as follows.

[0071] In the CGS, the transmitting device 100 continues to transmit K (K28.5=BCh). Since the data rate of the serial data 301 transmitted by the transmitting device 100 matches the data rate set in the PHY unit 212, the CDR function of the PHY unit 212 is locked.

[0072] CDR_LOCK302 is represented by one bit per lane (i.e., 1 bit / lane). When the CDR function is locked, CDR_LOCK302 becomes "1111". The synchronization monitor 214 receives CDR_LOCK302. When the synchronization monitor 214 detects that the CDR function corresponding to Lane #0 is locked (i.e., when it detects that the bit corresponding to Lane #0 is "1"), it causes the clock driver 220 to output SYSREF310 and SYSREF311. Specifically, the synchronization monitor 214 outputs clock driver control 309 to the clock driver 220. In response to this, the clock driver 220 outputs SYSREF310 to the transmitting device 100 and outputs SYSREF311 to the synchronization detector 213.

[0073] The synchronization detection unit 213 detects "SYSREF311=1". The synchronization detection unit 213 resets the LMFC timing in the processing circuit 210. Furthermore, when the synchronization detection unit 213 detects that there is no 8B / 10B error in the parallel data 303, it sets the SYNC control 305 to "1" and outputs the SYNC control 305 to the synchronization monitoring unit 214.

[0074] The synchronization monitor 214 receives the SYNC control 305. In response to this, the synchronization monitor 214 sets SYNCB 308 to "1" and outputs SYNCB 308 to the transmitting device 100. Alternatively, the synchronization monitor 214 detects via CDR_LOCK 302 that the CDR function corresponding to Lane #0 is locked, and also detects via control / notification 306 that there is no 8B / 10B error in the parallel data 303. In response to this detection, the synchronization monitor 214 sets SYNCB 308 to "1" and outputs SYNCB 308 to the transmitting device 100.

[0075] The transmitting device 100 detects "SYSREF310=1". The transmitting device 100 resets the internal LMFC timing of the transmitting device 100. Next, the transmitting device 100 detects "SYNCB308=1". This causes the transmitting device 100 to transition to the ILAS from the next LMFC timing.

[0076] In the ILAS, the synchronization detection unit 213 receives the above-mentioned four consecutive multiframes (multiframes 1 to 4) via the PHY unit 212. The synchronization detection unit 213 extracts the JESD204B parameters (i.e., the first parameters in the transmitting device 100) shown in Fig. 6. The synchronization detection unit 213 stores the extracted first parameters in a register.

[0077] When the synchronization detection unit 213 has completed storing the parameters in the register, the synchronization detection unit 213 sends a control / notification 306 to the synchronization monitoring unit 214 .

[0078] In response to the control / notification 306, the synchronization monitor 214 compares the content of the parameter stored in the register (i.e., the first parameter in the transmitting device 100) with the second parameter in the processing circuit 210. As described above, the content of the first parameter stored in the register matches the content of the second parameter in the processing circuit 210.

[0079] Furthermore, the synchronization monitor 214 calculates a predetermined parameter from the first parameter stored in the register. Hereinafter, the JESD204B parameter calculated from the first parameter stored in the register will be referred to as the "third parameter." Furthermore, the JESD204B parameter set in the clock driver 220 will be referred to as the "fourth parameter."

[0080] The synchronization monitor 214 compares the calculated third parameter with the fourth parameter in the clock driver 220. In this example, the third parameter and the fourth parameter are the periods of the LMFC. The synchronization monitor 214 determines whether the period of the LMFC (fourth parameter) set in the clock driver 220 matches the calculated period of the LMFC (third parameter). Here, "match" means that the period of the LMFC (fourth parameter) set in the clock driver 220 is a power of 1 / 2 of the calculated period of the LMFC (third parameter). If the period of the LMFC (fourth parameter) set in the clock driver 220 matches the calculated period of the LMFC (third parameter), the synchronization monitor 214 transmits a control / notification 306 to the synchronization detection unit 213 to notify the establishment of a link (i.e., link up).

[0081] (Example 2) Operation example 2 is an operation when the first parameter in the transmitting device 100 is the setting file #1 in FIG. 5, and the second parameter in the processing circuit 210 is the setting file #0 in FIG.

[0082] In this example, a first parameter in the transmitting device 100 does not match a second parameter in the processing circuit 210. For example, the data rate (4.9152 Gbps) of the serial data 301 transmitted by the transmitting device 100 does not match the data rate (9.8304 Gbps) set in the PHY unit 212. In this case, after the system 400 is started up or released from reset, a link is not established between the transmitting device 100 and the processing circuit 210 of the receiving device 200. Therefore, the JESD204B state is the initial state, CGS. The transmitting device 100 and the receiving device 200 perform a link establishment procedure (link-up sequence) as follows.

[0083] In the CGS, the transmitting device 100 continues to transmit K (K28.5=BCh).

[0084] As described above, the data rate of the serial data 301 transmitted by the transmitting device 100 differs from the data rate set in the PHY unit 212, so the CDR function of the PHY unit 212 is not locked. Therefore, CDR_LOCK 302 becomes "0000." The state of CDR_LOCK 302="0000" continues.

[0085] If the state of CDR_LOCK302="0000" continues for a predetermined period of time, the synchronization monitor 214 determines that the data rate of the serial data 301 transmitted by the transmitting device 100 does not match the data rate set in the PHY unit 212. Then, the synchronization monitor 214 changes the data rate in the PHY unit 212 (i.e., 9.8304 Gbps) to "4.9152 Gbps" in the PHY setting 307. Furthermore, the synchronization monitor 214 resets the PHY unit 212 in the PHY setting 307.

[0086] During the above process, the state remains CGS, so the transmitting device 100 continues to transmit K (K28.5=BCh).

[0087] After the PHY unit 212 is reset, the data rate of the serial data 301 transmitted by the transmitting device 100 matches the data rate set in the PHY unit 212. Therefore, the CDR function is locked, and CDR_LOCK 302 becomes "1111".

[0088] The synchronization monitor 214 receives CDR_LOCK 302. As in the case of operation example 1, the synchronization monitor 214 causes the clock driver 220 to output SYSREF 310 and SYSREF 311. Specifically, the synchronization monitor 214 outputs clock driver control 309 to the clock driver 220. In response to this, the clock driver 220 outputs SYSREF 310 to the transmitting device 100 and outputs SYSREF 311 to the synchronization detection unit 213.

[0089] The synchronization detection unit 213 detects "SYSREF311=1". The synchronization detection unit 213 resets the LMFC timing in the processing circuit 210. Next, when the synchronization detection unit 213 detects that there is no 8B / 10B error in the parallel data 303 of Lane #0, it notifies the synchronization monitoring unit 214 of this fact in control / notification 306. Therefore, the synchronization monitoring unit 214 detects that the CDR function corresponding to Lane #0 is locked in CDR_LOCK 302, and also detects that there is no 8B / 10B error in the parallel data 303. In response to this detection, the synchronization monitoring unit 214 sets SYNCB 308 to "1" and outputs SYNCB 308 to the transmitting device 100.

[0090] The transmitting device 100 detects "SYSREF310=1". The transmitting device 100 resets the internal LMFC timing of the transmitting device 100. Next, the transmitting device 100 detects "SYNCB308=1". This causes the transmitting device 100 to transition to the ILAS from the next LMFC timing.

[0091] In the ILAS, the synchronization detection unit 213 receives the above-mentioned four consecutive multiframes (multiframes 1 to 4) via the PHY unit 212. The synchronization detection unit 213 extracts the JESD204B parameters (i.e., the first parameters in the transmitting device 100) shown in Fig. 6. The synchronization detection unit 213 stores the extracted first parameters in a register.

[0092] When the synchronization detection unit 213 has completed storing the parameters in the register, the synchronization detection unit 213 sends a control / notification 306 to the synchronization monitoring unit 214 .

[0093] In response to the control / notification 306, the synchronization monitor 214 compares the content of the parameter stored in the register (i.e., the first parameter in the transmitting device 100) with the second parameter in the processing circuit 210. The content of the first parameter stored in the register does not match the content of the second parameter in the processing circuit 210. Specifically, M and F in the first parameter are different from M and F in the second parameter, respectively.

[0094] Furthermore, the synchronization monitor 214 calculates a third parameter from the first parameter stored in the register. The synchronization monitor 214 compares the calculated third parameter with a fourth parameter in the clock driver 220. The third and fourth parameters are the periods of the LMFC. In this example, the period of the LMFC set in the clock driver 220 (the fourth parameter) does not match the calculated period of the LMFC (the third parameter).

[0095] Therefore, the synchronization monitor 214 changes the content of the second parameters (specifically, M and F) in the synchronization detector 213 to match the content of the first parameters using the parameter setting 312. As a result, the content of the second parameters in the processing circuit 210 and the content of the first parameters in the transmitting device 100 match.

[0096] The synchronization monitor 214 changes the LMFC period (fourth parameter) set in the clock driver 220 using the clock driver control 309 so that it matches the calculated LMFC period (third parameter). Specifically, the synchronization monitor 214 changes the setting of the SYSREF generation period in the clock driver 220.

[0097] Thereafter, the JESD processing unit 211 (i.e., the PHY unit 212 and the synchronization detection unit 213) is reset. After the second parameter in the processing circuit 210 is changed in this manner, the processing circuit 210 executes the link establishment procedure again. As a result, a link between the transmitting device 100 and the receiving device 200 is established.

[0098] (Example 3) Operation example 3 is an operation when the first parameter in the transmitting device 100 is the setting file #2 in FIG. 5, and the second parameter in the processing circuit 210 is the setting file #0 in FIG.

[0099] In this example, the data rate of the serial data 301 transmitted by the transmitting device 100 matches the data rate set in the PHY unit 212. However, other first parameters in the transmitting device 100 do not match other second parameters in the processing circuit 210. In this case, after the system 400 is started up or released from reset, a link is not established between the transmitting device 100 and the processing circuit 210 of the receiving device 200. Therefore, the JESD204B state is the initial state, CGS. The transmitting device 100 and the receiving device 200 perform a link establishment procedure (link-up sequence) as follows.

[0100] In the CGS, the transmitting device 100 continues to transmit K (K28.5=BCh). However, L in the first parameter is "2" (i.e., L=2). The CDR function of the PHY unit 212 is locked for only two lanes. CDR_LOCK 302 becomes "0011".

[0101] The synchronization monitor 214 receives CDR_LOCK 302. When the synchronization monitor 214 detects that the CDR function is locked (for example, when it detects "1" in the bit corresponding to Lane #0), it causes the clock driver 220 to output SYSREF 310 and SYSREF 311. Specifically, the synchronization monitor 214 outputs clock driver control 309 to the clock driver 220. In response to this, the clock driver 220 outputs SYSREF 310 to the transmitting device 100 and outputs SYSREF 311 to the synchronization detector 213.

[0102] The synchronization detection unit 213 detects "SYSREF311=1". The synchronization detection unit 213 resets the LMFC timing in the processing circuit 210. Next, when the synchronization detection unit 213 detects that there is no 8B / 10B error in the parallel data 303, it notifies the synchronization monitoring unit 214 of this fact in control / notification 306. Therefore, the synchronization monitoring unit 214 detects that the CDR function corresponding to Lane #0 is locked in CDR_LOCK 302, and also detects that there is no 8B / 10B error in the parallel data 303. In response to this detection, the synchronization monitoring unit 214 sets SYNCB 308 to "1" and outputs SYNCB 308 to the transmitting device 100.

[0103] The transmitting device 100 detects "SYSREF310=1". The transmitting device 100 resets the internal LMFC timing of the transmitting device 100. Next, the transmitting device 100 detects "SYNCB308=1". This causes the transmitting device 100 to transition to the ILAS from the next LMFC timing.

[0104] In the ILAS, the synchronization detection unit 213 receives the above-mentioned four consecutive multiframes (multiframes 1 to 4) via the PHY unit 212. The synchronization detection unit 213 extracts the JESD204B parameters (i.e., the first parameters in the transmitting device 100) shown in Fig. 6. The synchronization detection unit 213 stores the extracted first parameters in a register.

[0105] When the synchronization detection unit 213 has completed storing the parameters in the register, the synchronization detection unit 213 sends a control / notification 306 to the synchronization monitoring unit 214 .

[0106] In response to the control / notification 306, the synchronization monitor 214 compares the content of the parameter stored in the register (i.e., the first parameter in the transmitting device 100) with the second parameter in the processing circuit 210. The content of the first parameter stored in the register does not match the content of the second parameter in the processing circuit 210. Specifically, L and M in the first parameter are different from L and M in the second parameter, respectively.

[0107] Furthermore, the synchronization monitor 214 calculates a third parameter from the first parameter stored in the register. The synchronization monitor 214 compares the calculated third parameter with a fourth parameter in the clock driver 220. In this example, the third parameter and the fourth parameter are the periods of the LMFC. The period of the LMFC set in the clock driver 220 (the fourth parameter) matches the calculated period of the LMFC (the third parameter).

[0108] Therefore, the synchronization monitor 214 changes the contents of the second parameters (specifically, L and M) in the synchronization detector 213 to match the contents of the first parameters using the parameter setting 312. As a result, the contents of the second parameters in the processing circuit 210 and the contents of the first parameters in the transmitting device 100 match.

[0109] Thereafter, the JESD processing unit 211 (i.e., the PHY unit 212 and the synchronization detection unit 213) is reset. After the second parameter in the processing circuit 210 is changed in this manner, the processing circuit 210 executes the link establishment procedure again. As a result, a link between the transmitting device 100 and the receiving device 200 is established.

[0110] (Example 4) Operation example 4 is an operation when the first parameter in the transmitting device 100 is the setting file #3 in FIG. 5, and the second parameter in the processing circuit 210 is the setting file #0 in FIG.

[0111] In this example, the data rate of the serial data 301 transmitted by the transmitting device 100 matches the data rate set in the PHY unit 212. However, other first parameters in the transmitting device 100 do not match other second parameters in the processing circuit 210. In this case, after the system 400 is started up or released from reset, a link is not established between the transmitting device 100 and the processing circuit 210 of the receiving device 200. Therefore, the JESD204B state is the initial state, CGS. The transmitting device 100 and the receiving device 200 perform a link establishment procedure (link-up sequence) as follows.

[0112] In the CGS, the transmitting device 100 continues to transmit K (K28.5=BCh). The data rate of the serial data 301 transmitted by the transmitting device 100 matches the data rate set in the PHY unit 212. However, L in the first parameter is "2" (i.e., L=2). As described above, CDR_LOCK 302 becomes "0011".

[0113] The synchronization monitor 214 receives CDR_LOCK 302. When the synchronization monitor 214 detects that the CDR function is locked (for example, when it detects "1" in the bit corresponding to Lane #0), it causes the clock driver 220 to output SYSREF 310 and SYSREF 311. Specifically, the synchronization monitor 214 outputs clock driver control 309 to the clock driver 220. In response to this, the clock driver 220 outputs SYSREF 310 to the transmitting device 100 and outputs SYSREF 311 to the synchronization detector 213.

[0114] The synchronization detection unit 213 detects "SYSREF311=1". The synchronization detection unit 213 resets the LMFC timing in the processing circuit 210. Furthermore, when the synchronization detection unit 213 detects that there is no 8B / 10B error in the parallel data 303, it notifies the synchronization monitoring unit 214 of this fact in control / notification 306. Therefore, the synchronization monitoring unit 214 detects that the CDR function corresponding to Lane #0 is locked in CDR_LOCK 302, and also detects that there is no 8B / 10B error in the parallel data 303. In response to this detection, the synchronization monitoring unit 214 sets SYNCB 308 to "1" and outputs SYNCB 308 to the transmitting device 100.

[0115] The transmitting device 100 detects "SYSREF310=1". The transmitting device 100 resets the internal LMFC timing of the transmitting device 100. Next, the transmitting device 100 detects "SYNCB308=1". This causes the transmitting device 100 to transition to the ILAS from the next LMFC timing.

[0116] In the ILAS, the synchronization detection unit 213 receives the above-mentioned four consecutive multiframes (multiframes 1 to 4) via the PHY unit 212. The synchronization detection unit 213 extracts the JESD204B parameters (i.e., the first parameters in the transmitting device 100) shown in Fig. 6. The synchronization detection unit 213 stores the extracted first parameters in a register.

[0117] When the synchronization detection unit 213 has completed storing the parameters in the register, the synchronization detection unit 213 sends a control / notification 306 to the synchronization monitoring unit 214 .

[0118] In response to the control / notification 306, the synchronization monitor 214 compares the content of the parameter stored in the register (i.e., the first parameter in the transmitting device 100) with the second parameter in the processing circuit 210. The content of the first parameter stored in the register does not match the content of the second parameter in the processing circuit 210. Specifically, L and F in the first parameter are different from L and F in the second parameter, respectively.

[0119] Furthermore, the synchronization monitor 214 calculates a third parameter from the first parameter stored in the register. The synchronization monitor 214 compares the calculated third parameter with a fourth parameter in the clock driver 220. The third and fourth parameters are the periods of the LMFC. In this example, the period of the LMFC set in the clock driver 220 (the fourth parameter) does not match the calculated period of the LMFC (the third parameter).

[0120] Therefore, the synchronization monitor 214 changes the content of the second parameters (specifically, L and F) in the synchronization detector 213 to match the content of the first parameters using the parameter setting 312. As a result, the content of the second parameters in the processing circuit 210 and the content of the first parameters in the transmitting device 100 match.

[0121] The synchronization monitor 214 changes the LMFC cycle (fourth parameter) set in the clock driver 220 using the clock driver control 309 so that it matches the content of the third parameter. Specifically, the synchronization monitor 214 changes the setting of the SYSREF generation cycle in the clock driver 220.

[0122] Thereafter, the JESD processing unit 211 (i.e., the PHY unit 212 and the synchronization detection unit 213) is reset. After the second parameter in the processing circuit 210 is changed in this manner, the processing circuit 210 executes the link establishment procedure again. As a result, a link between the transmitting device 100 and the receiving device 200 is established.

[0123] <2-5. Processing flow of receiving device> Next, the flow of the second parameter change process in the receiving device 200 (specifically, the processing circuit 210) will be described with reference to Fig. 7. Fig. 7 is a flowchart showing an example of the flow of the second parameter change process.

[0124] As described above, in the CGS, if the data rate of the serial data 301 transmitted by the transmitting device 100 does not match the data rate set in the PHY unit 212, the processing circuit 210 changes the data rate in the PHY unit 212 to match the data rate set in the transmitting device 100 (701).

[0125] If the data rate of the serial data 301 transmitted by the transmitting device 100 matches the data rate set in the PHY unit 212, step 701 is omitted.

[0126] After step 701, the state transitions from CGS to ILAS. As described above, in the ILAS, processing circuit 210 compares the content of the parameter stored in the register (i.e., the first parameter in transmitting device 100) with the second parameter in processing circuit 210. If the content of the first parameter stored in the register does not match the content of the second parameter in processing circuit 210, processing circuit 210 changes (702) the content of the second parameter in processing circuit 210 to match the content of the first parameter.

[0127] If the content of the first parameter stored in the register matches the content of the second parameter in the processing circuit 210, step 702 is omitted.

[0128] As described above, in the ILAS, the processing circuit 210 compares the third parameter calculated from the first parameter with the fourth parameter in the clock driver 220. In this example, the third and fourth parameters are the periods of the LMFC. If the period of the LMFC (fourth parameter) set in the clock driver 220 does not match the calculated period of the LMFC (third parameter), the processing circuit 210 changes the setting of the period of SYSREF generation in the clock driver 220 (703), as described above.

[0129] If the period of the LMFC set in the clock driver 220 (fourth parameter) matches the period of the LMFC calculated above (third parameter), step 703 is omitted.

[0130] Thereafter, the JESD processing unit 211 in the processing circuit 210 is reset (704). Then, the processing circuit 210 executes the link establishment procedure again (705). As a result, a link between the transmitting device 100 and the receiving device 200 is established.

[0131] <2-6. Effects> According to the above configuration, the processing circuit 210 of the receiving device 200 has a function of receiving JESD204 parameters (i.e., first parameters) from the transmitting device 100 and a function of changing the JESD204 parameters (i.e., second parameters) in the processing circuit 210 to match the first parameters. That is, the processing circuit 210 can select JESD204 parameters corresponding to an appropriate setting file from among a plurality of preset setting files 0# to #3, and execute a link establishment procedure (link-up sequence) to establish a link with the transmitting device 100. According to this configuration, even if the first parameters in the transmitting device 100 are changed using the control computer 300 (i.e., if the setting file is changed), the processing circuit 210 can automatically change its own second parameters to realize link-up in response to the change.

[0132] Furthermore, with the above configuration, the configuration (for example, FPGA) of the receiving device 200 can be made common regardless of the transmitting device 100. When evaluating the FPGA, reconfiguration of the FPGA is not required, and the evaluation time can be shortened.

[0133] When designing a plurality of devices with different JESD204B parameters, the configuration of the receiving device 200 can be reused, thereby reducing the time required to design the devices.

[0134] Because the link establishment procedure (JESD link-up sequence) is controlled by hardware, software does not need to be involved in link-up, and resources can be allocated to other settings, etc. Furthermore, the load on elements (e.g., CPU) present around the receiving device 200 can be reduced.

[0135] <2-7. Variations> The technology according to the present disclosure is not limited to the above-described embodiments.

[0136] (1) First Modification As described above, an example in which an ADC and a DAC are implemented in one TRX_IC will be described. For example, the TRX_IC includes a first receiving device connected to the ADC and a second receiving device connected to the DAC. The first receiving device and the second receiving device have the same configuration as the receiving device 200 described above. In such a configuration, a combination of JESD204B parameters of the ADC and JESD204B parameters of the DAC may be set as one configuration file.

[0137] 8 shows configuration files #0 to #3 that define combinations of JESD204B parameters for the ADC and JESD204B parameters for the DAC. In this example, when one configuration file is selected, the combination of ADC parameters and DAC parameters is determined. After a link between the ADC and a first receiving device is established according to the above-described method, a link establishment procedure between the DAC and a second receiving device may be performed. With this configuration, link-up with the ADC and link-up with the DAC can be completed in sequence.

[0138] The parameters of the ADC and the DAC may be set to the same content. In this case, the link establishment procedure between the DAC and the second receiving device may be performed after the link between the ADC and the first receiving device is established according to the above-described method.

[0139] (2) Second Modification FIG. 9 is a diagram showing an example of a system configuration according to a second modified example. In this example, a receiving device 200 is connected to a plurality of transmitting devices (ADCs) 100-0 to 100-3. The receiving device 200 is implemented in a main PWB 900. The plurality of transmitting devices 100-0 to 100-3 are implemented in a plurality of sub PWBs #0 to #3, respectively. Furthermore, different setting files are set for the plurality of transmitting devices 100-0 to 100-3. Conventionally, in such a configuration, the receiving device 200 needs to be reconfigured to match the connecting transmitting device (ADC). With the common receiving device 200 of this example, a link establishment procedure (link-up sequence) can be executed without reconfiguration.

[0140] 10 is a diagram showing another example of the configuration of a system according to the second modification. The processing circuit 210 includes a plurality of JESD processing units 211 (including a PHY unit 212 and a synchronization detection unit 213) corresponding to a plurality of transmitting devices 100-0 to 100-3. Even in this configuration, similar to the above, the common receiving device 200 of this example can execute a link-up sequence without reconfiguration.

[0141] (3) Third Modification 11 is a diagram showing an example of the configuration of a system according to the third modification. Each of the devices A to D includes a transmitting device (ADC) 100 and a receiving device 200. S The D parameters are different from each other. In such a configuration, there is no need to change the configuration of the receiving device 200 for each of the devices A to D. The common receiving device 200 in this example can establish a link-up with the transmitting device without changing the configuration.

[0142] (4) Fourth Modification 12 is a diagram showing an example of a system configuration according to a fourth modification. In this example, a Common Public Radio Interface (CPRI) is applied to the connection between the transmitting device 100 and the receiving device 200. In a system in which the radio digital processing unit (BBU: Base Band Unit) of a base station and the remote radio head (RRH) are separated, the CPRI is an interface used for communication between the BBU and the remote radio head. In this configuration, the processing circuit 210 includes a CPRI transceiver 1200. The FPGA 1100 on the transmitting device 100 side also includes a CPRI transceiver 1110. Various signals can be transmitted and received between the transceiver 1200 and the transceiver 1110 in a link establishment procedure.

[0143] 13 is a diagram showing another example of the configuration of a system according to Modification 4. In this example, QSFP (Quad Small Form-factor Pluggable) and SFP (Small Form-factor Pluggable) are used as derivative models of CPRI.

[0144] 14 is a diagram showing another example of a system configuration according to the fourth modification. In this example, QSFP is used as a derived model of CPRI. A main PWB and a sub PWB are connected by a single optical cable.

[0145] The effects of the examples shown in Figs. 12 to 14 will be explained. In the example shown in Fig. 9, the signals between the main PWB and the sub PWB include a device clock and control signals (SYSREF, SYNCB) in addition to the main signals. When control in the ADC is added (for example, when control by SPI is added), the signals between the main PWB and the sub PWB must include a serial clock (SCLK) signal, a serial data input (SDI) signal, a serial data output (SDO) signal, and a chip select bar (CSB) signal. The number of such signals is determined by the number of sub PWBs. PWB The increase in the number of ADCs implemented in the

[0146] Hereinafter, the above-mentioned CPRI and its derivative models will be simply referred to as "CPRI." To address the above-mentioned issues, by using the receiving device 200, control signals can be integrated using a high-speed serial interface with a clock transmission function like CPRI. Furthermore, by using CPRI, the amount of delay between the main PWB and the sub PWB can be determined by the round trip delay (T12+T34), so that the timing discrepancy between the control signal on the transmitting device 100 side and the control signal on the receiving device 200 side can be corrected.

[0147] Furthermore, the clock driver may be configured to use the CPRI recovery clock as the reference clock, which allows the generation of a clock synchronized with the device clock of the main PWB.

[0148] Since the delay deviation due to CPRI is 1 clk, a deviation of 1 clk also occurs in the generation of SYSREF. Considering a delay deviation of +0 clk and a delay deviation of +1 clk, the TX (DL: downlink) delay will be +1 clk and the RX (UL: uplink) delay will be -1 clk, resulting in delay variation. If the operating clock is 245.76 MHz, the delay deviation will be approximately plus or minus 2 ns, which is equivalent to the delay deviation of existing equipment.

[0149] FIG. 15 is a diagram showing another example of a system configuration according to the fourth modification. In the examples of FIGS. 12 to 14, a clock driver is implemented in each of the main PWB and the sub-PWB. Furthermore, a SYSREF is generated in each of the main PWB and the sub-PWB. Because the SYSREF is generated by dividing the frequency of the device clock source, it is not possible to align the phases between the multiple PWBs. However, when the FPGA of the main PWB and the FPGA of the sub-PWB are connected via CPRI, it is possible to align the timing of the control signals. With this configuration, the SYSREF generation function can be implemented on the FPGA of the main PWB.

[0150] 15, the FPGA in which the processing circuit 210 is implemented further includes a SYSREF generation function 1500. Note that the phase of the SYSREF generated by the SYSREF generation function 1500 needs to be matched with the phase of the device clock of the ADC so that the ADC can reliably capture it. This can be achieved by timing constraints within the FPGA and retiming in the clock driver, etc.

[0151] <<3. Second Embodiment>> Next, a second embodiment will be described with reference to Figures 16 and 17. The first embodiment described above is a specific embodiment, but the second embodiment is a more generalized embodiment.

[0152] <3-1. Configuration of link establishment device> 16 is a diagram illustrating an example of the configuration of a link establishment device 1600. The link establishment device 1600 is connected to another device 1630 via a JESD204B interface. The link establishment device 1600 is configured to execute a link establishment procedure to establish a link with the other device 1630. The other device 1630 may be the transmitting device 100 described above.

[0153] The link establishment device 1600 includes a receiver 1610 and a changer 1620. The receiver 1610 receives a first parameter of JESD204B from another device 1630 during a link establishment procedure. If a second parameter of JESD204B set in the link establishment device 1600 does not match the first parameter received by the receiver 1610, the changer 1620 changes the second parameter to match the first parameter.

[0154] The receiving unit 1610 may operate in the same manner as the above-described JESD processing unit 211. The changing unit 1620 may operate in the same manner as the above-described synchronization monitoring unit 214.

[0155] <3-2. Processing flow> 17 is a flowchart illustrating an example of the processing flow of the link establishment device 1600. In the link establishment procedure, the receiver 1610 receives a first parameter of JESD204B from another device 1630 (1701). If a second parameter of JESD204B set in the link establishment device 1600 does not match the first parameter received by the receiver 1610, the change unit 1620 changes the second parameter to match the first parameter (1702).

[0156] According to the above configuration, even when multiple devices with different JESD204B parameters are designed, the configuration of the link establishment device 1600 can be made common, thereby reducing the time required for designing and evaluating the device.

[0157] <<4. Other Embodiments>> It should be noted that the above-described embodiment and modified examples are merely examples, and the scope of the technical idea of ​​the present disclosure is not limited to the above-described configurations. Other aspects conceivable within the scope of the technical idea of ​​the present disclosure are also included in the scope of the present disclosure.

[0158] The above-mentioned device is applicable to 5G (5th Generation) RUs (Radio Units or Remote Units), 6G (6th Generation) RUs, MIMO-compatible wireless communication devices, multi-antenna-compatible wireless communication devices, and communication devices using JESD204B.

[0159] Some or all of the above-described embodiments and modified examples can be described as, but are not limited to, the following supplementary notes.

[0160] (Appendix 1) A link establishment device connected to another device via a JESD204B interface and configured to perform a link establishment procedure to establish a link with the other device, receiving means for receiving a first parameter of JESD204B from the other device in the link establishment procedure; a change means for changing a second parameter of JESD204B set in the link establishment device to match the first parameter when the second parameter does not match the first parameter received by the receiving means; A link establishment device comprising:

[0161] (Appendix 2) the receiving means receives a multiframe from the other device in an ILAS (Initial Lane Alignment Sequence) state of JESD204B and extracts the first parameter from the multiframe; the change means compares the extracted first parameter with the second parameter to determine whether the second parameter matches the first parameter; 2. The link establishment device of claim 1.

[0162] (Appendix 3) A clock driver is further provided for transmitting a SYSREF signal in JESD204B to the link establishment device and the other device; The change means is comparing a third parameter calculated from the extracted first parameter with a fourth parameter set in the clock driver; If the third parameter does not match the fourth parameter, change the fourth parameter set in the clock driver. 3. A link establishment device as described in appended claim 2.

[0163] (Appendix 4) the third parameter and the fourth parameter are periods of a Local Multi Frame Clock (LMFC); 4. The link establishment device of claim 3.

[0164] (Appendix 5) the first parameter includes a first data rate; the second parameters include a second data rate; when the first data rate and the second data rate do not match, the changing means changes the second data rate to match the first data rate; 5. A link establishment device according to any one of appendices 1 to 4.

[0165] (Appendix 6) the link establishment device executes the link establishment procedure again after the change means changes the second parameter. 6. A link establishment device according to any one of appendices 1 to 5.

[0166] (Appendix 7) 1. A method performed in a link establishment device connected to another device via a JESD204B interface and configured to perform a link establishment procedure to establish a link with the other device, comprising: receiving a first parameter of JESD204B from the other device in the link establishment procedure; If a second parameter of JESD204B set in the link establishment device does not match the received first parameter, changing the second parameter to match the first parameter; A method comprising:

[0167] (Appendix 8) a first device in which a first parameter of JESD is set, the first device being configured to be changeable; a second device connected to the first device via a JESD204B interface; Equipped with the first device and the second device are configured to perform a link establishment procedure to establish a link between the first device and the second device; The second device is receiving means for receiving a first parameter of JESD204B from the first device in the link establishment procedure; a change means for changing a second parameter of JESD204B set in the second device so that the second parameter matches the first parameter when the second parameter does not match the first parameter received by the receiving means; Equipped with system. The above Supplementary Notes 1 to 8 may be implemented by at least one circuit (or processor). [Industrial Applicability]

[0168] The present disclosure provides techniques for standardizing circuits that use JESD204B. [Explanation of symbols]

[0169] 100: Sending device 200: Receiving device 210: Processing circuit 211: JESD processing section 212: Physical layer (PHY) section 213: JESD sync detector 214:JESD synchronization monitoring section 220: Clock driver 300: Control computer

Claims

1. A link establishment device connected to another device via a JESD204B interface and configured to perform a link establishment procedure to establish a link with the other device, receiving means for receiving a first parameter of JESD204B from the other device in the link establishment procedure; a change means for changing a second parameter of JESD204B set in the link establishment device so that the second parameter matches the first parameter when the second parameter does not match the first parameter received by the receiving means; the receiving means receives a multiframe from the other device in an ILAS (Initial Lane Alignment Sequence) state of JESD204B and extracts the first parameter from the multiframe; the change means compares the extracted first parameter with the second parameter to determine whether the second parameter matches the first parameter; a clock driver for transmitting a SYSREF signal in JESD204B to the link establishment device and the other device; The change means is comparing a third parameter calculated from the extracted first parameter with a fourth parameter set in the clock driver; If the third parameter does not match the fourth parameter, the fourth parameter set in the clock driver is changed. Link establishment device.

2. the third parameter and the fourth parameter are periods of a Local Multi Frame Clock (LMFC); 2. The link establishment device according to claim 1.

3. the first parameter includes a first data rate; the second parameters include a second data rate; when the first data rate and the second data rate do not match, the changing means changes the second data rate to match the first data rate; 3. The link establishment device according to claim 1 or 2.

4. the link establishment device executes the link establishment procedure again after the change means changes the second parameter. A link establishment device according to any one of claims 1 to 3.

5. 1. A method performed in a link establishment device connected to another device via a JESD204B interface and configured to perform a link establishment procedure to establish a link with the other device, the link establishment device comprising a clock driver that transmits a SYSREF signal in JESD204B to the link establishment device and the other device, the method comprising: receiving a first parameter of JESD204B from the other device in the link establishment procedure; If a second parameter of JESD204B set in the link establishment device does not match the received first parameter, changing the second parameter to match the first parameter; receiving a multiframe from the other device in an ILAS (Initial Lane Alignment Sequence) state of JESD204B and extracting the first parameter from the multiframe; comparing the extracted first parameter with the second parameter to determine whether the second parameter matches the first parameter; comparing a third parameter calculated from the extracted first parameter with a fourth parameter set in the clock driver; If the third parameter does not match the fourth parameter, changing the fourth parameter set in the clock driver; A method comprising:

6. a first device in which a first parameter of JESD is set, the first device being configured to be changeable; a second device connected to the first device via a JESD204B interface; Equipped with the first device and the second device are configured to perform a link establishment procedure to establish a link between the first device and the second device; The second device is receiving means for receiving a first parameter of JESD204B from the first device in the link establishment procedure; and a change means for changing a second parameter of JESD204B set in the second device so that the second parameter matches the first parameter when the second parameter does not match the first parameter received by the receiving means; the receiving means receives a multiframe from the first device in an ILAS (Initial Lane Alignment Sequence) state of JESD204B and extracts the first parameter from the multiframe; the change means compares the extracted first parameter with the second parameter to determine whether the second parameter matches the first parameter; a clock driver for transmitting a SYSREF signal in JESD204B to the second device and the first device; The change means is comparing a third parameter calculated from the extracted first parameter with a fourth parameter set in the clock driver; If the third parameter does not match the fourth parameter, the fourth parameter set in the clock driver is changed. system.

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