Lossless encoding / decoding modes for video encoding / decoding

Abstract

To provide methods and apparatuses for improving and simplifying video coding / decoding in lossless coding / decoding modes.SOLUTION: Methods for video coding / decoding include: partitioning a video picture into a plurality of coding / decoding units (CUs) including a lossless CU; determining a residual coding / decoding block size of the lossless CU; and, in response to determining that the residual coding / decoding block size of the lossless CU is greater than a predefined maximum value, splitting the residual coding / decoding block into two or more residual blocks for residual coding / decoding.SELECTED DRAWING: Figure 8

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a division of "Lossless Code for Video Encoding and Decoding" filed on June 28, 2019. No. 62 / 868,857, entitled "Compact Decoding Mode," and U.S. Provisional Application No. 62 / 868,857, filed July 6, 2019. A paper entitled "Lossless Coding / Decoding Modes for Video Coding / Decoding" was submitted to the U.S. This application claims priority to Provisional Application No. 62 / 871134, which is hereby incorporated by reference. The entire specification of which is incorporated herein by reference. [Technical Field]

[0002] This application relates generally to video encoding, decoding, and compression. In particular, this disclosure relates to video encoding, decoding, and compression. This invention relates to the improvement and simplification of lossless encoding and decoding for encoding and decoding. [Background technology]

[0003] A variety of video encoding and decoding techniques can be used to compress video data. Video encoding and decoding is performed in accordance with one or more video encoding and decoding standards. Exemplary video encoding and decoding standards include Versatile Video Coding (VVC) and deo Coding), Joint Exploration Test Model (JEM), High Efficiency Video coding and decoding (H.265 / HEVC: High Efficiency Video Coding), advanced Video coding and decoding (H.264 / AVC: Advanced Video Coding), and video expert group Video coding includes MPEG (Moving Picture Experts Group) coding and decoding. In encoding and decoding, prediction methods are generally used due to the redundancy present in the video image or sequence. (e.g., inter-prediction, intra-prediction, etc.) The main goal is to stream more video data while avoiding or minimizing video quality degradation. Compressing it into a lower bitrate format.

[0004] The first version of the HEVC standard was finalized in October 2013 and supersedes previous generations of video codecs. Approximately 50% bitrate savings compared to standard H.264 / MPEG AVC decoding or equivalent visual quality. The HEVC standard offers significant decoding improvements over its predecessor. It adds on top of HEVC, offering improved coding efficiency but better coding efficiency than HEVC. There is evidence that this can be achieved with encoding / decoding tools. Based on this, VCEG and Both MPEG and IEEE have proposed new coding and decoding techniques for future video coding and decoding standards. The Joint Video Experts Team (JVET) ) was concluded in October 2015 by ITU-TVECG and ISO / IEC MPEG. This has led to significant research into advanced technologies that will enable significant improvements in coding and decoding efficiency. A reference solution called the Joint Exploration Model (JEM) was developed. The software integrates several additional coding tools on top of the HEVC Test Model (HM). It is maintained by JVET.

[0005] Call for proposals for video compression beyond HEVC sals) was published by ITU-T and ISO / IEC in October 2017. 20 In April 2018, 23 CfP responses were received and evaluated at the 10th JVET Conference. It was demonstrated that compression efficiency was improved by approximately 40% compared to HEVC. Based on the results, a new generation of video coding and decoding called Versatile Video Coding and Decoding (VVC) is proposed. In the same month, the VVC standard was adopted. To demonstrate the reference implementation, a reference called the VVC Test Model (VTM) is used. The software code base was established. Summary of the Invention

[0006] This disclosure generally provides examples of techniques related to lossless encoding and decoding in video encoding and decoding. state.

[0007] According to a first aspect of the present disclosure, a video image is encoded by a plurality of lossless encoding / decoding units (CUs), and determining a residual coding / decoding block size of the lossless CU. and the residual encoding / decoding block size of the lossless CU is greater than a predetermined maximum value. and determining, in response to the determination of the residual coding block being larger than the threshold, two or more residuals for residual coding the residual coding block. and dividing the video signal into difference blocks. Provide.

[0008] According to a second aspect of the present disclosure, a video image is encoded by a plurality of lossless encoding / decoding units (CUs). and for the lossless CU, a non-transformed skip mode CU is used. and selecting the same residual coding / decoding scheme for the video coding / decoding. This provides a method for lossless encoding / decoding modes.

[0009] According to a third aspect of the present disclosure, there is provided a method for controlling a computer system, comprising: one or more processors; a memory configured to store instructions executable by said processor; Alternatively, the processors may, upon execution of the instructions, perform lossless encoding / decoding of video images. The reversible CU is divided into a plurality of CUs each including a residual coding / decoding block size. and determining whether the residual encoding / decoding block size of the lossless CU is greater than a predetermined maximum value. Residual-decoding the residual coding / decoding block in response to determining that the residual coding / decoding block is greater than the a video encoding / decoding method configured to divide the residual block into two or more residual blocks for The present invention provides a device for a lossless encoding / decoding mode.

[0010] According to a fourth aspect of the present disclosure, there is provided a method for controlling a computer system, comprising: one or more processors; a memory configured to store instructions executable by said processor; Alternatively, the processors may, upon execution of the instructions, perform lossless encoding / decoding of video images. The lossless CU is divided into a plurality of CUs each including a non-transform skip mode C The video coding scheme is configured to select the same residual coding / decoding scheme as used in U. A lossless encoding / decoding mode device for encoding / decoding is provided.

[0011] According to a fifth aspect of the present disclosure, there is provided a method for controlling a computer system, comprising: one or more processors; a non-transitory storage medium configured to store instructions executable by the processor; The instructions, when executed, cause the one or more processors to losslessly encode video images. The reversible CU is divided into a plurality of CUs including a coding / decoding unit (CU), and the reversible CU is subjected to residual coding / decoding. a residual encoding / decoding block size of the lossless CU is determined in advance; In response to determining that the residual coding / decoding block is greater than the predetermined maximum value, Operations such as dividing the residual into two or more blocks for encoding and decoding are performed. The present invention provides an apparatus for video encoding and decoding that enables

[0012] According to a sixth aspect of the present disclosure, there is provided a method for controlling a computer system, comprising: a non-transitory storage medium configured to store instructions executable by the processor; The instructions, when executed, cause the one or more processors to losslessly encode video images. The reversible CU is divided into a plurality of CUs including a coding / decoding unit (CU), and the reversible CU is not transformed. selecting the same residual encoding / decoding scheme used in the skip mode CU; The present invention provides an apparatus for video encoding and decoding that performs the above operations. [Brief explanation of the drawings]

[0013] A more particular description of the examples of the present disclosure will be given by reference to specific examples which are illustrated in the accompanying drawings. These drawings show only some examples and are therefore not limiting in scope. These examples may be used to illustrate additional features and advantages of the present invention, provided that they are not intended to be limiting. The isomerism and details are explained. [Figure 1] FIG. 1 is a block diagram illustrating an example video encoder according to an embodiment of this disclosure. [Figure 2A] FIG. 2A is a schematic diagram illustrating quaternary block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a schematic diagram illustrating horizontal dual block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2C]FIG. 2C is a schematic diagram illustrating vertical dual block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2D] FIG. 2D is a schematic diagram illustrating horizontal ternary block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 2E] FIG. 2E is a schematic diagram illustrating vertical ternary block partitions in a multi-type tree structure according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a block diagram illustrating an example video decoder according to an embodiment of this disclosure. [Figure 3A] FIG. 3A is a schematic diagram illustrating an example of decoder-side motion vector refinement (DMVR), according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram illustrating an example of an image divided into CTUs, tiles, and tile groups, according to one embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic diagram illustrating another example of an image divided into CTUs, and further into tiles and tile groups, according to an embodiment of the present disclosure. [Figure 6] 6A-H are schematic diagrams illustrating examples of disallowed TT and BT partitions according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram illustrating an example apparatus for a lossless encoding / decoding mode for video encoding / decoding, according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a flowchart illustrating an example process of a lossless encoding / decoding mode for video encoding / decoding according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a flowchart illustrating another exemplary process of a lossless encoding / decoding mode for video encoding / decoding, according to an embodiment of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. In order to facilitate understanding of the concepts set forth herein, a number of specific, non-limiting details are provided. However, it will be apparent to those skilled in the art that the present invention can be implemented in various modifications. For example, the subject matter described herein may be applied to many devices with digital video capabilities. It will be apparent to those skilled in the art that the present invention may be implemented in any type of electronic device.

[0015] As used herein, the terms "one embodiment," "embodiment," "example," "an example," "an embodiment ... "One embodiment," "one example," or similar phrases may be used to describe a particular feature, structure, or characteristic that is not necessarily present. It is meant to be included in at least one embodiment or example. Any features, structures, elements or characteristics described in connection with a configuration are not necessarily intended to be used unless expressly indicated otherwise. The present invention is also applicable to other embodiments.

[0016] Throughout this disclosure, terms such as "first," "second," "third," etc., all refer to associated elements, e.g. For example, use only to refer to an apparatus, component, configuration, step, etc. and does not imply spatial or chronological order unless the context clearly indicates otherwise. For example, "first device" and "second device" refer to two separately formed devices, or two parts, components, or states of operation of the same device, It is possible to give a name to something.

[0017] The expressions used here are "(if)...tara" or "(if)...ba" and "(if)...to" Such terms may be understood to mean "when" or "according to," depending on the context. These terms, when they appear in the claims, are used to define the relevant limitation or feature. This does not mean that the terms are conditional or selective.

[0018] "Module", "Sub-module", "Circuit", "Sub-circuit", "Unit" or " The term "subunit" refers to a piece of code or instructions that can be executed by one or more processors. Contains memory (shared, private, or group) that stores instructions. A module is a collection of code or may contain one or more circuits that may or may not store instructions. A module or circuit is a set of one or more components connected directly or indirectly. These components may be physically connected to each other. They may be physically separated or adjacent to each other.

[0019] A unit or module may be realized entirely by software or entirely by hardware. may be realized by software or by a combination of hardware and software. In a fully software implementation, the unit or module may be modules are linked together directly or indirectly to perform specific functions. may contain related code blocks or software components .

[0020] Figure 1 shows the block-based processing used in conjunction with many video encoding and decoding standards. Block diagrams of an exemplary block-based hybrid video encoder 100 that can be used include: VVC is based on a block-based hybrid video coding and decoding framework. In the encoder 100, an input video signal is sent to an encoding / decoding unit ( In VTM-1.0, CU is It can be up to 128 x 128 pixels. However, VVC is based only on the quadtree. Unlike HEVC, which divides blocks based on a single coding / decoding tree unit (CTU), coding tree unit) is converted into quadtree / binarytree / ternarytree to adapt to various local characteristics. Just as the division of components into CTBs is a partition, ,A coding and decoding tree block (CTB) is,by definition, the number of samples for some value of,N,. The CTU is an NxN block of luminance samples from an image with three sample arrays. TB, two corresponding CTBs for chroma samples, or CTBs for monochrome image samples An image coded with three separate color planes and the number of samples used to code and decode it. It also provides an overview of the different partition unit types in HEVC. The CU, prediction unit (PU) and transform unit are removed. Separation of transform units (CUs) no longer exists in VVC. Instead, each CU is It is always used as the basic unit for both prediction and transformation, without further partitioning.

[0021] In the multi-type tree structure, one CTU is first divided into quadtrees. Then, each quadtree Leaf nodes can be further divided into binary and ternary tree structures, as shown in Figures 2A-2E. , four-way compartment (Figure 2A), horizontal two-way compartment (Figure 2B), vertical two-way compartment (Figure 2C), horizontal three-way compartment There are five division types, such as the vertical triad (Figure 2D), the vertical triad (Figure 2E), and the vertical triad (Figure 2F).

[0022] For a given video block, prediction can be performed using either an inter-prediction approach or an intra-prediction approach. In inter prediction, the image is generated from a previously reconstructed frame. Based on the pixels, one or more predictors are formed by motion estimation and motion compensation. Intra-prediction forms a predictor based on reconstructed pixels in the current frame. The mode decision determines the selection of the best predictor to predict the current block. It is possible.

[0023] A prediction residual, which represents the difference between the current video block and its predictor, is sent to the transform circuit 102. Then, for entropy reduction, the transform coefficients are transferred from the transform circuit 102 to the quantization circuit. The quantized coefficients are then sent to the entropy coding / decoding circuit 106. The resulting compressed video bitstream is fed to the Video block partition information from the intra-prediction circuitry and / or intra-prediction circuitry 112, motion Prediction-related information 110 such as vectors, reference image indices, and intra-prediction modes The video signal is also supplied through an entropy coding / decoding circuit 106 to be compressed into video bits. The image is stored in the stream 114.

[0024] The encoder 100 also includes decoder-related circuitry for reconstructing pixels for prediction purposes. First, the prediction residual is reconstructed through the inverse quantification 116 and inverse transformation circuit 118. This reconstructed prediction residual is combined with the block predictor 120 to generate the current block. An unfiltered reconstruction of the image block is generated.

[0025] Spatial prediction (also called "intra prediction") is a method of predicting a video block that is within the same video frame as the current video block. The samples of adjacent blocks already coded and decoded in the frame (also called reference samples) ) to predict the current video block.

[0026] Temporal prediction (also called "inter prediction") is a method for predicting the time course of an already coded video image. Temporal prediction predicts the current video block using reconstructed pixels from the video It reduces the time redundancy inherent in the signal. ) or the temporal prediction signal for the encoding / decoding block is usually the current CU and its temporal One or more motion vectors (MVs) that indicate the amount and direction of movement between the reference Furthermore, if multiple reference images are supported, temporal prediction A reference signal for identifying which reference image in the reference image store the signal comes from. The image index is additionally transmitted.

[0027] After spatial and / or temporal prediction is performed, the intra / internal The inter mode decision circuit 121 determines the optimal prediction, for example, based on a rate distortion optimization method. Then, the block predictor 120 is subtracted from the current video block. The resulting prediction residuals are decorrelated by the transform circuit 102 and the quantification circuit 104. The resulting residual coefficients of the quantification are inversely quantified by the inverse quantification circuit 116 and then transformed by the inverse transform circuit 117. 118 to generate a reconstruction residual, which is then This reconstructed signal is added to the clock to generate the reconstructed signal for this CU. The CU is placed in the reference picture store of picture buffer 117 to store the code for future video blocks. Before being used for decoding, a deblocking filter, a sample adaptive offset (SAO) sample adaptive offset, and / or adaptive in-loop filter (ALF) An in-loop filter 115, such as a ve in-loop filter, is used for this reconstructed CU. To generate the output video bitstream 114, decoding mode (inter or intra), prediction mode information, motion information, and quantification All the residual coefficients are transmitted to the entropy coding / decoding unit 106 for further compression and decoding. The data is then packed together to generate the bitstream.

[0028] For example, current versions of AVC, HEVC, and VVC use deblocking filters. In HEVC, SAO is used to further improve coding efficiency. An additional in-loop filter called (sample adaptive offset) is defined. The current version of the VVC standard introduces yet another filter called ALF (Adaptive Loop Filter). In-loop filters that are readily available are being actively researched and are being included in the final standard. There is a possibility.

[0029] These in-loop filter operations are selectable. By performing these operations, These operations contribute to improving the coding / decoding efficiency and visual quality. It can be turned off as determined by the encoder 100 to conserve energy.

[0030] Note that if these filter options are turned on by the encoder 100, While the prediction is usually based on the pixels of the unfiltered reconstruction, The target prediction is based on the pixels of the filtered reconstruction.

[0031] FIG. 3 shows an example of a video encoding / decoding system that can be used in conjunction with many video encoding / decoding standards. 2 is a block diagram illustrating a typical block-based video decoder 200. 0 is similar to the reconstruction-related portion present in the encoder 100 of FIG. In 2000, the input video bitstream 201 is first decoded via entropy decoding 202. The quantified coefficient levels and prediction related information are then derived. The calculated coefficient levels are processed by inverse quantization 204 and inverse transformation 206 to produce a reconstructed The intra / inter mode selector 212 obtains the predicted residual. The lock predictor mechanism performs intra prediction 208 or is configured to perform motion compensation 210. The prediction residual of the reconstruction from the inverse transform 206 and , and the predicted output generated by the block predictor mechanism are added by the adder 214. to obtain a set of unfiltered reconstructed pixels.

[0032] The reconstructed blocks are stored in an image buffer 213, which functions as a reference image store. Before passing through the image buffer 2, the image may be passed through an in-loop filter 209. The reconstructed video at 13 can be sent out to drive a display device or used for future video recordings. In-loop filters can be used to predict video blocks. When 209 is turned on, a filtering operation is performed on these reconstructed pixels. 222.

[0033] In general, the basic intra prediction scheme applied in VVC is, for example, intra sub-frames. Partition (ISP) coding / decoding mode, wide-angle intra-direction extended intra-prediction, position Some of them, such as Dependent Intra Prediction Combining (PDPC) and 4-tap intra interpolation, The HEVC scheme, except that the modules in is kept the same. Images, Tile Groups, Tiles and CTU Partitions in VVC

[0034] In VVC, a tile is a CTU in a particular tile column and a particular tile row in an image. A tile group is defined as a rectangular region that is exclusively contained within a single NAL unit. It contains a group of an integer number of tiles in the image. Essentially, a tile group The concept of slices is the same as that defined in HEVC. For example, an image is a tiled group. It is divided into loops and tiles.

[0035] A tile is a set of CTUs that contain rectangular regions in an image. A tile group can contain: It contains multiple tiles of an image. There are two modes of tile group: raster scan and Tile group mode and rectangular tile group mode are supported. In Raster Scan Tile Group mode, the tile group contains the raster scan of the image tiles. In rectangular tile group mode, the image contains a series of tiles in a rectangular scan. A rectangular tile group contains multiple tiles of an image that collectively form a rectangular area of ​​the image. The tiles in the loop are in the order of the tile raster scan of the tile group.

[0036] Figure 4 shows the image divided into 12 tiles and three raster scan tile groups. An example of a raster scan tile group division of an image is shown.

[0037] Figure 5 shows that the image has 24 tiles (6 tile columns and 4 tile rows) and 9 rectangles. Figure 1 shows an example of a rectangular tile group partition of an image divided into tile groups. Large block size transform with high frequency zeroing in VVC.

[0038] VTM4 offers the highest quality video quality, primarily for high-resolution video such as 1080p and 4K sequences. It is possible to convert large block sizes up to 64x64. For a transform block of 100 MHz or 100 MHz (width or height, or both width and height), the high frequency transform coefficients are Only low frequency coefficients are kept because they are zeroed. For example, if the block width is M and the block For an MxN transform block with block height N, if M equals 64, the transform coefficients Similarly, if N is equal to 64, only the leftmost 32 columns of the transform coefficients are retained. Only the value of the large block is kept. The entire block is used without zeroing. Virtual Pipeline Data Unit (VPDU) in VVC

[0039] A Virtual Pipeline Data Unit (VPDU) is a non-overlapping unit within an image. In a hardware decoder, consecutive VPDUs are split into multiple pipes. The VPDU size is 100% for most pipeline stages. It is important to keep the VPDU size small because it is roughly proportional to the buffer size used. Most hardware decoders limit the VPDU size to the maximum transform block ( However, VVC supports ternary tree (TT) and binary tree (BT) sizes. Partitioning can result in larger VPDU sizes.

[0040] To keep the VPDU size as 64x64 luma samples, the following canonical partitioning rules are used: The restrictions (with syntax notification changes) apply to VTM5 as shown in Figures 6A-6H. Above, for the upper example, we label the examples in Figures 6A-6D from left to right, and for the lower example, ,The examples in Figures 6E-6H are labeled from left to right. - for CUs where either width or height, or both width and height, equals 128 TT division is not permitted (Figures 6A, 6B, 6E, 6F, 6G, and 6H). C is -128×N (N≦128, i.e., width is equal to 128 and height is less than or equal to 128) For U, horizontal BT is not allowed (Figure 6D). -N (N≦128, that is, height is equal to 128 and width is less than or equal to 128) × 128 C For U, no vertical BT is allowed (Figure 6C). Transform Coefficient Coding in VVC

[0041] Transform coefficient coding and decoding refers to the coding and decoding process of the transform coefficient quantification level value of TU. In HEVC, the transform coefficients of a coded / decoded block are organized into non-overlapping coefficient groups (or Each CG contains 4x the number of coding / decoding blocks. It contains four blocks of coefficients. The CG in the coding / decoding block and the transform coefficients in the CG are , are coded and decoded in a predetermined scan order. A CG with at least one non-zero transform coefficient The encoding and decoding of the transform coefficient levels can be separated into multiple scan passes. In the first pass, the first bin (denoted as bin0) indicates that the coefficient magnitude is greater than 0. Then the second / third The bins (denoted as bin1 and bin2, respectively) are coeff_abs_greater1_flag and coeff_a Two scan passes for context encoding and decoding of the bs_greater2_flag (also called bs_greater2_flag) Finally, the remaining values ​​of the sign information and coefficient levels (coeff_abs_ Two further scan passes to encode and decode the level (also called level_remaining) are called Note that only the bins in the first three scan passes are encoded and decoded in the normal mode. These are called regular bins in the following description.

[0042] In VVC3, for each sub-block, normal coded and decoded bins and bypass coded The decoded bins are separated in encoding / decoding order. First, all the normal The decoded bins are transmitted, followed by the bypass decoded bins. The transform coefficient levels of the sub-block are coded in four passes at the scanning position as follows: The data is decoded. - Pass 1: Severity (sig_flag), greater than 1 flag (gt1_flag), parity (par_ level_flag) and flags greater than 2 (gt2_flag) are coded and decoded in the coding / decoding order. If sig_flag is equal to 1, gt1_flag is first decoded (absolute level If gt1_flag is equal to 1, par_flag is additionally Encoding and decoding are performed (specify the parity as absolute level minus 2). - Pass 2: The remaining absolute levels (remainders) are coded when gt2_flag is 1 or gt1_flag is 1 Non-binary syntax elements are binarized using Golomb-Rice coding, The resulting bins are coded and decoded in the bypass mode of the arithmetic coding / decoding engine. Pass 3: Absolute level (ab) of coefficients whose sig_flag has not been coded / decoded in the first pass sLevel) (because the limit of normal coded bins has been reached) uses Golomb-Rice coding The data is then completely encoded and decoded in the bypass mode of the arithmetic encoding / decoding engine. - Pass 4: Sign (sign_flag ) encoding and decoding

[0043] For a 4x4 sub-block, there are 32 or fewer normally coded and decoded bins (sig_flag, par_flag, gt1_flag, and gt2_flag) are guaranteed to be encoded or decoded. For 2x2 chroma sub-blocks, the number of encoded and decoded bins is usually limited to 8. can be.

[0044] Rice parameters (ricePar) for encoding and decoding the remainder of non-binary syntax elements (pass 3) ) is derived in the same way as in HEVC. At the beginning of each sub-block, ricePar is set to 0. After encoding and decoding the remainder of the syntax elements, the Rice parameters are changed according to a given formula. To encode / decode the non-binary syntax element absLevel (pass 4), the local template is The sum of the absolute values ​​of the plates, sumAbs, is determined. The variables ricePar and posZero are used in the table lookup. The intermediate variable codeValue is determined based on the dependent quantification and sumAbs by the backup. , is derived as follows: If -absLevel[k] is equal to 0, then codeValue is set equal to posZero. - Otherwise, if absLevel[k] is less than or equal to posZero, codeValue is absLevel[k] - It is set equal to 1. - Otherwise (absLevel[k] is greater than posZero), codeValue is absLevel[k] The value of codeValue is set equal to Golomb-Rice by the Rice parameter ricePar. It is encoded and decoded using the code.

[0045] In the remainder of this disclosure, transform coefficient coding and decoding is also referred to as residual coding and decoding. Decoder-side Motion Vector Refinement (DMVR) in VVC

[0046] Decoder-side motion vector refinement (DMVR) is used for decoding in bi-predictive merge mode. A technique for a block that is notified by an SPS signal using the sps_dmvr_enabled_flag flag. In this mode, the two motion vectors of a block (M V) can be further refined by bilateral matching (BM) prediction. This can be done.

[0047] FIG. 3A is a schematic diagram illustrating an example of decoder-side motion vector refinement (DMVR). As shown in Fig. 1, the bilateral matching method uses the current C Two related reference images of U322, namely refPic and Along the current CU's movement trajectory in refPic in List L1 310, The current CU is found by searching for the closest match between the two reference blocks 302, 312. The pattern rectangular blocks 322 and 30 are used to refine the motion information. 2 and 312 are the current CU and its two CUs based on the initial motion information from the merge mode. The pattern rectangular blocks 304 and 314 are used for motion refinement search. A pair of reference vectors based on MV candidates is used in the motion vector refinement process. 1 shows a reference block.

[0048] The MV difference between the candidate MV and the initial MV (also called the original MV) is MV diff and -MV dif f Both the MV candidate and the initial motion vector are bidirectional motion vectors. During the DMVR process, , the number of such MV candidates around the initial MV can be checked. For each given MV candidate, its references in List0 and List1 are The two related reference blocks are located in the reference image, and the difference between them is calculated. Such block differences are usually expressed as SAD (or sum of absolute differences) or row subsamples. The sum of the summed SAD (i.e., the SAD calculated for every other row of the relevant block) Finally, the MV candidate with the lowest SAD between the two reference blocks is selected as the refined MV. V, which is used to generate the bi-predicted signal as the actual prediction for the current CU. .

[0049] In VVC, DMVR applies to CUs that meet the following conditions: Bi-predictive MV CU level merge mode (not sub-block merge mode) It was encoded and decoded using With respect to the current image, one of the reference images of the CU is in the past (i.e., the POC is the current The other reference image is in the future (i.e., the POC is smaller than the current (larger than the image POC). The POC distance (i.e., absolute POC difference) from both reference images to the current image is It's the same. CUs are over 64 luma samples in size, and the height of a CU is 8 luma samples. Beyond the sample.

[0050] The refined MVs derived by the DMVR process are used to generate inter-prediction samples. It is also used for temporal motion vector prediction for future image coding and decoding. The original MV is used as the spatial motion vector for the deblocking process and future CU encoding / decoding. It is also used for torque prediction. Some additional features of DMVR are presented in the following subsections. Bi-directional Optical Flow (BDOF) in VVC

[0051] The Bidirectional Optical Flow (BDOF) tool is included in VTM5. Previously, it was available in BIO The BDOF, which was called the BDOF, is included in the JEM version. Compared to the JEM version, the VTM BDOF in 5 requires far fewer operations, especially in terms of the number of multiplications and the size of the multiplier. This is a simple version that requires BDOF enabled by the SPS sps_bdof_enabled_flag flag. It is controlled by

[0052] BDOF is used to refine the bi-predictive signal of a CU at the 4x4 sub-block level. BDOF is applied to a CU when the following conditions are met: 1) The height of the CU is not 4 1) The CU is not 4x8 in size; 2) The CU is in affine mode or ATMVP mode. 3) CU is coded / decoded in "true" bi-predictive mode; This means that one of the two reference images is before the current image in the display order, and the other is after the current image. It comes after the current image in display order. BDOF only applies to the luma component.

[0053] As the name suggests, BDOF mode assumes that the subject's movement is smooth. It is based on the concept of optical flow, which is calculated by dividing the gradient of the current block by The calculated predicted samples are adjusted to improve coding efficiency. Decoder-side control for DMVR and BDOF in VVC

[0054] Currently, VVC supports normal merge candidates with the SPS flag enabled and some bi-predictors. If the measurement and size constraints are met, BDOF / DMVR is always applied.

[0055] DMVR applies to normal merge mode when all of the following conditions are met: - sps_dmvr_enabled_flag equals 1 - general_merge_flag [xCb] [yCb] equals 1 - predFlagL0[0][0] and predFlagL1[0][0] are both equal to 1 - mmvd_merge_flag [xCb] [yCb] equals 0 -DiffPicOrderCnt(currPic, RefPicList [0] [refIdxL0]) becomes DiffPicOrderCnt(RefP icList[1][refIdxL1], currPic) - BcwIdx[xCb][yCb] equals 0 - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both set to 0 equal - cbWidth is 8 or greater - cbHeight is 8 or greater - cbHeight * cbWidth is 128 or greater

[0056] BDOF is applied to bi-prediction when all of the following conditions are met: - sps_bdof_enabled_flag is equal to 1. - predFlagL0 [xSbIdx] [ySbIdx] and predFlagL1 [xSbIdx] [ySbIdx] are both equal to 1. stomach. - DiffPicOrderCnt(currPic, RefPicList [0] [refIdxL0])* DiffPicOrderCnt(currP ic, RefPicList[1][refIdxL1]) is less than 0. - MotionModelIdc[xCb][yCb] is equal to 0. - merge_subblock_flag[xCb][yCb] is equal to 0. - sym_mvd_flag[xCb][yCb] is equal to 0. - BcwIdx[xCb][yCb] is equal to 0. - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both 0. be. - cbHeight is 8 or greater. - cIdx is equal to 0. Residual coding for transform skip mode CUs in VVC Decryption

[0057] In VTM5, conversion skip mode is used for luminance blocks up to 32x32 in size (inclusive). If a CU is encoded / decoded in transform skip mode, its prediction residual is quantized and coded by a transform skip residual coding / decoding process. This residual coding / decoding process is a direct sequel to the transform coefficient coding / decoding process described in the previous section. In transform skip mode, the residuals of the CU are also overlapped with each other in 4x4 size. In transform skip mode, the encoding and decoding is performed on a sub-block basis. Unlike the usual transform coefficient coding / decoding process, the last coefficient position is notified by a signal. Instead, coded_subblock_flag is set to the forward direction for all 4x4 subblocks in the CU. In forward scanning order, i.e., from the upper left sub-block to the last sub-block, will be done.

[0058] For each sub-block, coded_subblock_flag is equal to 1 (i.e., the sub-block has zero If there is at least one quantified residual other than B, the sign of the quantified residual level Decoding is performed in three scan passes: - First scan pass: Significance flag (sig_coeff_flag), Sign flag (coeff_sign_fla g), absolute level flag greater than 1 (abs_level_gtx_flag[0]), and parity (par_ For a certain scanning position, coeff_sig_flag is equal to 1. If so, coeff_sign_flag is coded and decoded, and then abs_level_gtx_flag[0](absolute abs_level_gtx_fl (specifies whether the pair level is greater than 1) is encoded and decoded. If ag[0] is equal to 1, par_level_flag specifies absolute level parity. are additionally encoded and decoded. - Scan paths greater than x: For every scan position with an absolute level greater than 1, Four options are provided to specify whether the absolute level at the specified position is greater than 3, 5, 7, or 9. abs_level_gtx_flag[i] (i = 1 ... 4) up to are encoded and decoded. - Remaining scan paths: abs_level_gtx_flag[4] is equal to 1 (i.e., absolute level is 9 For all scan positions (greater than 100), the absolute level remainder is coded and decoded. The absolute level of the signal is binarized using a reduced Rice parameter derivation template.

[0059] The bins in scan passes #1 and #2 (the first scan pass and scan passes greater than x) are , the context coding in the CU is repeated until the maximum number of bins to be decoded is reached. The maximum number of context-decoded bins in a residual block is 2* block_width*block_height, or equivalently, an average of 2 contexts per sample location The bins in the last scan pass (the remaining scan passes) are limited to the bins that are coded. The path is encoded and decoded. Lossless encoding in HEVC

[0060] The lossless encoding / decoding mode in HEVC uses transform, quantization, and in-loop filters ( non-blocking filters, sample adaptive offset, and adaptive loop filters) simply This design is a typical H Lossless encoding and decoding with minimal changes required to implement EVC encoder and decoder The aim is to make it possible.

[0061] In HEVC, lossless encoding / decoding mode can be turned on or off at the per-CU level. This is signaled at the CU level using the syntax cu_transquant_bypass_flag. Lossless encoding / decoding mode reduces unnecessary signaling overhead. To avoid this, the cu_transquant_bypass_flag syntax is not always signaled. This is true if another syntax called transquant_bypass_enabled_flag has a value of 1. In other words, the syntax transquant_bypass_enabled_flag is This is to turn on signaling with the _transquant_bypass_flag syntax.

[0062] In HEVC, the syntax transquant_bypass_enabled_flag is included in the Picture Parameter Set (PPS). For each CU in the image that references this PPS, use the syntax cu_transquan Indicates whether the t_bypass_flag should be signaled. If this flag is set to 1, If so, the syntax cu_transquant_bypass_flag is sent at the CU level to This flag indicates whether the PPS is encoded and decoded in lossless mode. If set, cu_transquant_bypass_flag is not sent and all C U is encoded and decoded using the transform, quantization, and loop filter included in the process, This usually results in some level of video quality degradation. For each CU in the image to be decoded, the transquant flag in the PPS is used. Set _bypass_enabled_flag to 1 and set the CU-level flag cu_transquant_bypass_flag to 1 The detailed syntax signaling related to lossless modes in HEVC is The notice states as follows: - transquant_bypass_enabled_flag equal to 1 indicates that cu_transquant_bypass_flag is present. transquant_bypass_enabled_flag equal to 0 specifies that cu_transquant_bypass Specifies that ss_flag is not present. - cu_transquant_bypass_flag equal to 1 specifies the scale and transformation specified in Section 8.6. The in-loop filter process specified in Section 8.7 is bypassed. If cu_transquant_bypass_flag is not present, it is inferred to be equal to 0. [Table 1]

[0063] In VVC, the maximum CU size is 64x64, and the VPDU is also set to 64x64. Coefficient sign in VVC due to coefficient zeroing mechanism for width / height greater than 32 The maximum block size for decoding is 32x32. Under this constraint, The maximum block size for residual coding / decoding is 1 / 2 for coefficient coding / decoding. To fit the maximum block size of 32x32, only CUs up to 32x32 are used. However, VVC does not support the block size restriction for residual coding / decoding of lossless CUs. As a result, currently VVC supports 32x3 in lossless encoding / decoding mode. It is possible to generate residual blocks of size larger than 2, which is larger than 32x32. Support for residual coding and decoding for blocks larger than 100 is needed. This disclosure addresses this issue by using several A method has been proposed.

[0064] Another issue related to supporting lossless coding / decoding in VVC is that residuals (also called coefficients) The current VVC has two options: Different residual coding / decoding schemes are available. For a given block (or CU), Therefore, the selection of the residual coding / decoding scheme depends on the transform skipping of this block (or CU). Therefore, VVC, like HEVC, does not support lossless mode. Assuming the transform skip flag is 1, the residual used in transform skip mode is The encoding / decoding scheme is always used for lossless mode CUs, except for the transform skip flag The current residual encoding / decoding scheme used when is true is primarily based on screen content. It is designed for encoding and decoding normal content (i.e., content other than the screen). ) may not be optimal for lossless encoding / decoding. Several methods are proposed for selecting the residual coding / decoding for

[0065] In the current VVC, two decoder-side tools, namely BDOF and DMVR, are used to By filtering the blocks, the decoded pixels are refined and the coding / decoding is performed. Improves performance, but lossless coding / decoding requires that the predicted pixels are already perfectly As predicted, BDOF and DMVR do not contribute to the coding / decoding gain. ,BDOF and DMVR on the decoder side have no advantage over VVC, so these tools should not be applied to lossless encoding / decoding. However, in the current VVC, For a page candidate, the SPS flag is enabled and some bi-prediction and size constraints are met. Therefore, lossless VVC coding / decoding is DMVR and BDOF at lower levels, i.e., slice level and CU level. Controlling with this has benefits for the performance efficiency of VVC lossless encoding and decoding. Residual block partition of reversible CU

[0066] According to an example of the present disclosure, the maximum residual encoding / decoding block size of a lossless CU is set to It is suggested to match the maximum block size supported by the mode. In one example, the transform skip mode is set for residual blocks whose width and height are both less than or equal to 32. This is the maximum residual coding / decoding block in transform skip mode. This means that the block size is 32 x 32. According to this example, the remaining The maximum width and / or height of the difference block is also set to 32, and the maximum residual block size is set to 3 2 × 32. If the width / height of a lossless CU is greater than 32, the remaining CU is always set to The difference block is 32×N and / or multiple smaller residual blocks of size 32×N The width or height of the smaller residual block is 32 or less. For example, The 128x32 lossless CU is divided into four 32x32 residual blocks for residual encoding and decoding. In another example, a 64x64 lossless CU is divided into four 32x32 residual blocks. do.

[0067] According to another example of the present disclosure, the maximum block size for residual encoding / decoding of lossless CUs is set to V It is proposed to match the PDU size. Width / height is set to the VPDU size (e.g. 64x64 in current VVC). Whenever the width / height of a CU is greater than 64, the residual blocks of the CU are 64×N and / or or N × 64, and these smaller residual blocks are The width or height of the residual block is less than or equal to the width and / or height of the VPDU. For example, The 8x128 lossless CU is divided into four 64x64 residual blocks for residual encoding and decoding. In another example, a 128x32 lossless CU is split into two 64x32 residual blocks. It will be divided. Residual coding / decoding scheme selection for lossless mode CU

[0068] In the current VVC, depending on whether the CU is encoding / decoding in transform skip mode, , a different residual coding / decoding scheme is used by this CU. Transform Skip Mode Current residual coding and decoding used in is generally better suited to coding screen content. do.

[0069] According to one example of the present disclosure, a lossless CU is a residual code used by a transform skip mode CU. The same encryption and decoding scheme is used.

[0070] According to another example of the present disclosure, lossless CUs can be used to store the residuals used by non-transformed skip mode CUs. The same differential encoding and decoding scheme is used.

[0071] According to another example of the present disclosure, a residual encoding / decoding scheme for a lossless CU may be implemented under certain conditions and and / or adaptively extracting residuals from existing residual coding / decoding schemes based on a predetermined procedure. After such conditions and / or predetermined procedures, the bitstream is selected. The encoder and decoder are sequential so that no signaling is required to indicate the selection. In one example, a simple screen content detection scheme is used in both the encoder and decoder. Based on this detection scheme, the current video block Blocks can be classified as screen content or regular content. If , the residual coding / decoding scheme used in transform skip mode is selected. Otherwise, another residual coding / decoding scheme is selected.

[0072] According to another example of the present disclosure, the syntax may include a method for determining which residual encoding / decoding scheme is used by a lossless CU. signaled in the bitstream to explicitly specify that Such a syntax is a binary flag, where each binary value represents two residual encoding / decoding operations. The syntax indicates the choice of one of the schemes. For example, this can be done by creating a sequence parameter set (SPS), an image parameter set, Signal in tile set (PPS), slice header, tile group header, or tile It may also be signaled at the CTU or CU level. When such a construct is signaled, all possible constructs at the same level or lower are signaled. The inverse CU uses the same residual encoding-decoding scheme indicated by this syntax. For example, If the syntax is signaled at the SPS level, then all reversible CUs in the sequence uses the indicated residual encoding / decoding scheme. If a lossless CU is specified, all lossless CUs in the image are reconstructed using the residual coding method indicated in the associated PPS. C indicates whether the CU is encoded or decoded in lossless mode. If U-level syntax, such as cu_transquant_bypass_flag, is present, the residual coding / decoding sequence is The syntax for indicating the scheme is conditionally signaled based on the lossless mode flag of this CU. For example, the lossless mode flag cu_transquant_bypass_flag indicates whether the current CU is lossless. Specifies the residual coding / decoding scheme only when specifying that the coding / decoding is to be performed in reverse mode. The syntax indicated is signaled for this CU. If signaled by a flag, the data in this slice is encoded in lossless mode. All decoded CUs are identified by the residual code based on the flag signaled by the signal. A residual encoding / decoding scheme is used for each of the multiple CUs. The scheme is selected based on the first flag signaled, where slice The residual coding selected for the lossless CU by the flag signaled in the header. The encoding scheme is used by either a transform skip mode CU or a non-transform skip mode CU. This is a residual coding and decoding scheme.

[0073] According to an example of the present disclosure, even for CUs encoded and decoded in a lossless mode, the transform skip The mode flag is signaled. In this case, the CU is encoded and decoded in lossless mode. The selection of the residual coding / decoding scheme for a CU depends on the transform sequence, regardless of whether it is a It is based on the skip mode flag. Disable DMVR

[0074] In the current VVC, the DMVR on / off control is defined for lossless encoding / decoding modes. In one example of the present disclosure, a notification by a 1-bit signal slice_disable_dmvr_flag flag is not provided. It is proposed to control the turn-on / off of DMVR at the slice level by lag. In one example, the sps_dmvr_enabled_flag flag is set to 1 and the transquant_bypass If the _enabled_flag flag is set to 0, signal the slice_disable_dmvr_flag flag. If the slice_disable_dmvr_flag flag is not notified, If slice_disable_dmvr_flag is equal to 1, the DMVR is turned off. In this case, the signalling shall be as follows: [Table 2]

[0075] In another example, cu_transquant_bypass_flag controls DMVR turn on / off at the cu level. In one example, the cu level control for the DMVR is as follows: It is. DMVR applies to normal merge mode if all of the following conditions are true: . - sps_dmvr_enabled_flag equals 1; - cu_transquant_bypass_flag is set to 0; - general_merge_flag[xCb][yCb] equals 1; - predFlagL0[0][0] and predFlagL1[0][0] are both equal to 1; - mmvd_merge_flag[xCb][yCb] equals 0; - DiffPicOrderCnt(currPic,RefPicList [0] [refIdxL0]) is now DiffPicOrderCnt(Ref PicList[1][refIdxL1],currPic); - BcwIdx[xCb][yCb] equals 0; - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both set to 0 equal; - cbWidth is greater than or equal to 8; - cbHeight is greater than or equal to 8; - cbHeight * cbWidth is 128 or greater. Disable BDOF

[0076] In the current VVC, the BDOF on / off control is defined for the lossless encoding / decoding mode. In one example of the present disclosure, a notification by a 1-bit signal slice_disable_bdof_flag flag is not provided. It has been proposed to control the turn-on / off of the BDOF by a lag. The sps_bdof_enabled_flag flag is set to 1 or the transquant_bypass_enabled_fla If the g flag is set to 0, the slice_disable_bdof_flag flag is signaled. If the slice_disable_bdof_flag flag is not signaled, it is assumed to be 1. If the slice_disable_bdof_flag flag is equal to 1, BDOF is turned off. In this case, the signal notification is shown as follows: [Table 3]

[0077] In another example of the present disclosure, the cu_transquant_bypass_flag controls the turn of the BDOF at the cu level. On / off control is proposed. In one example, cu level control for BDOF is It is as follows: BDOF is applied to the normal merge mode if all of the following conditions are met: . - sps_bdof_enabled_flag equals 1; - cu_transquant_bypass_flag is set to 0; - predFlagL0[xSbIdx][ySbIdx] and predFlagL1[xSbIdx][ySbIdx] are both equal to 1. stomach; - DiffPicOrderCnt(currPic,RefPicList [0] [refIdxL0])* DiffPicOrderCnt(currP ic,RefPicList[1][refIdxL1]) is less than 0; - MotionModelIdc[xCb][yCb] is equal to 0; - merge_subblock_flag[xCb][yCb] equals 0; - sym_mvd_flag[xCb][yCb] equals 0; - BcwIdx[xCb][yCb] equals 0; - luma_weight_l0_flag [refIdxL0] and luma_weight_l1_flag [refIdxL1] are both 0. be; - cbHeight is greater than or equal to 8; - cIdx is equal to 0. Disable BDOF and DMVR

[0078] In the current VVC, for a given merge candidate, there are several bi-predictive and size constraints. If the conditions are met, BDOF and DMVR are used to improve the efficiency of coding and decoding. Both always apply to decoder-side refinement and are controlled by the respective SPS flags. In the disclosed example, a 1-bit signal slice_disable_bdof_dmvr_flag slice flag is used. It is proposed to disable both BDOF and DMVR by slice_disabling. If the ble_bdof_dmvr_flag flag is set to 1, both BDOF and DMVR are tagged. If the slice_disable_bdof_dmvr_flag flag is not signaled, it is set to 1. In one example, slice_disable_bdof_dmvr_ is set when the following conditions are met: The flag is signaled. [Table 4]

[0079] The above method can be implemented using an application specific integrated circuit (ASIC), a digital signal processor (DSP), ,Digital Signal Processor (DSPD), Programmable Logic Device (PLD), Field Programmable gate arrays (FPGAs), controllers, microcontrollers, A device containing one or more circuits that contain a microprocessor or other electronic components To realize the above method, these circuits may be implemented by other hardware. Each of the models disclosed above can be used in combination with other hardware or software components. A module, submodule, unit, or subunit is a device that contains one or more circuits. This may be implemented at least in part using

[0080] FIG. 7 is a block diagram illustrating an apparatus for video encoding and decoding according to an embodiment of the present disclosure. The device 700 may be a mobile phone, a tablet computer, a digital broadcast terminal, a tablet The device may be a wireless device or a terminal such as a personal digital assistant.

[0081] As shown in FIG. 7, the device 700 includes a processing unit 702, a memory 704, a power supply unit 706, a memory 708, a memory 709, a memory 710, a memory 711, a memory 712, a memory 713, a memory 714, a memory 715, a memory 716, a memory 717, a memory 718, a memory 719, a memory 7 Multimedia section 708, audio section 710, input / output (I / O) interface 7 12, a sensor unit 714, and a communication unit 716.

[0082] The processing unit 702 typically handles display, telephone calls, data communications, camera operations, and recording operations. The processing unit 702 controls the overall operation of the device 700, including related operations. One or more processes for executing instructions for realizing all or part of the steps of The processing unit 702 may include a processor 720. Can contain one or more modules that contribute to the interaction between the component For example, the processing unit 702 may be configured to provide an interface between the multimedia unit 708 and the processing unit 702. It may also include a multimedia module for contributing to interaction.

[0083] The memory 704 stores different types of data to support the operation of the device 700. Examples of such data include the data of any application running on the device 700. instructions for applications or methods, contact data, phone book data, messages, images, Video, etc. Memory 704 may be any type of volatile or non-volatile storage device. It is realized by static random access memory (SRAM) :Static Random Access Memory), electrically erasable programmable read-only Memory (EEPROM: Electrically Erasable Programmable Read-Only Memory), Erasable Programmable Read-Only Memory (EPROM) Programmable Read-Only Memory (PROM) emory, read-only memory (ROM), magnetic memory, flash It may be a memory, a magnetic disk, or a compact disk.

[0084] A power supply 706 provides power to the different components in the device 700. A power management system, which generates, manages, and controls power for one or more power sources and devices 700. and other components related to dispensing.

[0085] The multimedia section 708 provides an output interface between the device 700 and the user. In one example, the screen includes a liquid crystal display (LCD) and a touch screen. If the screen includes a touch panel, the screen The touch screen may be implemented as a touch screen that receives input signals from a user. The panel uses a touch panel to sense touches, slides, and gestures on this touch panel. It may include one or more touch sensors. The touch sensors are It not only senses the boundaries of the touch or slide action, but also the duration and time associated with the touch or slide action. In one example, the multimedia unit 708 may detect the temperature and pressure of the The device 700 may include a front camera and / or a rear camera. When the camera is in an operating mode such as external Partial multimedia data can be received.

[0086] The audio section 710 is configured to output and / or input audio signals. For example, the audio unit 710 includes a microphone (MIC). , the device 700 is in an operating mode such as a call mode, a recording mode, and a voice recognition mode. The device is configured to receive an external audio signal when the device is connected to the external audio device. The received audio signal is It may further be stored in memory 704 or transmitted via communication unit 716 . In one example, the audio section 710 further includes a speaker for outputting the audio signal. Included.

[0087] The I / O interface 712 connects the processing unit 702 to the peripheral interface module. The peripheral interface module mentioned above provides an interface between the keyboard and These buttons may include a home button, a click wheel, or a button. , volume buttons, start button, and lock button. stomach.

[0088] The sensor unit 714 may include one or more sensors for providing status assessments to the device 700 in different ways. For example, the sensor unit 714 may detect the on / off state of the device 700 and It is possible to detect the relative position of the components. For example, the components may be located at the The sensor section 714 is also a display and keypad. The position of the components of the device 700 may change, the presence or absence of a user's touch on the device 700, the orientation of the device 700, etc. It is possible to detect the speed, acceleration / deceleration, and temperature change of the device 700. 14 is a proximity sensor configured to detect the presence of a nearby object without physical contact The sensor portion 714 may include a CMOS or The sensor unit 7 may further include an optical sensor such as a CCD image sensor. 14 is an acceleration sensor, gyro sensor, magnetic sensor, pressure sensor, or temperature It may further include a sensor.

[0089] The communication unit 716 is configured to facilitate wired or wireless communication between the device 700 and other devices. The device 700 may be based on a communication standard such as WiFi, 4G, or a combination thereof. In one example, the communication unit 716 may Receives a notification signal or notification-related information from an external notification management system via a channel. In an example, the communication unit 716 may include a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module may include a radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra-Wideband (UWB) technology, Bluetooth It may be implemented based on Bluetooth technology and other technologies.

[0090] In one example, the apparatus 700 may include an application specific integrated circuit (ASIC) for performing the above-described methods. ), digital signal processor (DSP), digital signal processing device (DSPD), program Programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controller, microcontroller, microprocessor, or other electronic element This may be achieved by one or more of the following:

[0091] The non-transitory computer-readable storage medium is, for example, a hard disk drive (HD D), solid state drives (SSD), flash memory, hybrid drives and solid state drives lid drive (SSHD), read-only memory (ROM), compact disc read These include dedicated memory (CD-ROM), magnetic tape, and floppy disks.

[0092] FIG. 8 illustrates a lossless encoding / decoding model for video encoding / decoding according to an embodiment of the present disclosure. 1 is a flowchart illustrating an example process of a technique related to a card.

[0093] In step 801, the processor 720 processes the video image in at least one lossless coded form. The data is divided into multiple CUs (Clocks).

[0094] In step 802, the processor 720 performs a residual coding / decoding block subroutine for a lossless CU. Determine the size.

[0095] In step 803, the processor 720 performs a residual encoding / decoding process on the lossless CU. In response to determining that the error size is greater than a predetermined maximum value, A block is divided into two or more residual blocks for residual coding and decoding.

[0096] In one example, an apparatus for video encoding and decoding is provided. The apparatus includes a processor. 720 and a memory configured to store instructions executable by the processor. 704, where the processor, upon execution of these instructions, The method is configured to perform the following steps:

[0097] In another example, a non-transitory computer-readable storage medium 704 having instructions stored thereon. These instructions, when executed by the processor 720, The processor executes the method shown in FIG.

[0098] FIG. 9 illustrates a lossless encoding / decoding model for video encoding / decoding according to an embodiment of the present disclosure. 1 is a flowchart illustrating an example process of a technique related to a card.

[0099] In step 901, the processor 720 processes the video image in at least one lossless encoded form. The data is divided into multiple CUs (Clocks).

[0100] In step 902, the processor 720 performs non-transform skip for this lossless CU. Select the same residual encoding / decoding scheme as used by the mode CU.

[0101] In one example, an apparatus for video encoding and decoding is provided. The apparatus includes a processor. 720 and a memory configured to store instructions executable by the processor. 704, where the processor, upon execution of these instructions, The method is configured to perform the following steps:

[0102] In another example, a non-transitory computer-readable storage medium 704 having instructions stored thereon. These instructions, when executed by the processor 720, The processor executes the method shown in FIG.

[0103] The description of the present disclosure is presented for purposes of illustration and is not intended to be exhaustive or limiting of the present disclosure. Numerous modifications, variations, and alternative implementations are possible in accordance with the foregoing description and the accompanying drawings. It will be apparent to one skilled in the art having the benefit of the teachings presented in this specification and the associated drawings.

[0104] The embodiments illustrate the principles of the present disclosure and allow those skilled in the art to understand the present disclosure and make various implementations and specific The underlying principles and various implementations can be best utilized with various modifications to suit the application. The invention has been selected and described in this way. Accordingly, the scope of the present disclosure extends to the It is not limited to the specific examples of implementation, and modifications and other implementations are intended to be within the scope of the present disclosure. It should be understood.

Claims

1. determining whether the current block is in a lossless mode; In response to determining that the current block is in the lossless mode, determining whether a first residual encoding / decoding scheme, the first residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for a non-transform skip block, or a second residual encoding / decoding scheme, the second residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for a transform skip block, is applied to the current block in the lossless mode; signaling a first indication indicating whether the current block is in the lossless mode, and signaling a second indication indicating whether the first residual encoding / decoding scheme or the second residual encoding / decoding scheme is applied to a plurality of blocks in the lossless mode; 1. A method for video encoding comprising:

2. signaling a one-bit flag for controlling turn-on and turn-off of decoder-side motion vector refinement (DMVR) at slice level or picture level for the current block; The method for video encoding of claim 1 further comprising:

3. signaling a one-bit flag for controlling turn-on and turn-off of decoder-side motion vector refinement (DMVR) at a CU level for the current block; The method for video encoding of claim 1 further comprising:

4. signaling a one-bit flag for controlling bidirectional optical flow (BDOF) turn-on and turn-off at a slice level or a picture level for the current block; The method for video encoding of claim 1 further comprising:

5. signaling a one-bit flag for controlling bidirectional optical flow (BDOF) turn-on and turn-off at a CU level for the current block; The method for video encoding of claim 1 further comprising:

6. signaling a one-bit flag for controlling turn-on and turn-off of both decoder-side motion vector refinement (DMVR) and bidirectional optical flow (BDOF) at slice or picture level for the current block; The method for video encoding of claim 1 further comprising:

7. one or more processors; a memory configured to store instructions executable by the one or more processors; Equipped with The one or more processors, upon executing the instructions, Determines whether the current block is in lossless mode, In response to determining that the current block is in the lossless mode, determine whether a first residual encoding / decoding scheme, the first residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for a non-transform skip block, or a second residual encoding / decoding scheme, the second residual encoding / decoding scheme being a predefined residual encoding / decoding scheme for a transform skip block, is applied to the current block in the lossless mode; signaling a first indication indicating whether the current block is in the lossless mode, and signaling a second indication indicating whether the first residual encoding / decoding scheme or the second residual encoding / decoding scheme is applied to a plurality of blocks in the lossless mode.

1. An apparatus for video encoding, configured to:

8. The one or more processors, upon executing the instructions, further signaling a one-bit flag for controlling the turn-on and turn-off of decoder-side motion vector refinement (DMVR) at slice level or picture level for the current block; 8. An apparatus for video encoding according to claim 7, configured to:

9. The one or more processors further signaling a one-bit flag for controlling turn-on and turn-off of decoder-side motion vector refinement (DMVR) at a CU level for the current block; 8. An apparatus for video encoding according to claim 7, configured to:

10. The one or more processors further signaling a one-bit flag for controlling the turn-on and turn-off of bidirectional optical flow (BDOF) at a slice level or a picture level for the current block; 8. An apparatus for video encoding according to claim 7, configured to:

11. The one or more processors further signaling a one-bit flag for controlling bidirectional optical flow (BDOF) turn-on and turn-off at a CU level for the current block; 8. An apparatus for video encoding according to claim 7, configured to:

12. The one or more processors, upon executing the instructions, further signaling a one-bit flag for controlling decoder-side motion vector refinement (DMVR) turn-on and turn-off and bidirectional optical flow (BDOF) at slice level or picture level for the current block; 8. An apparatus for video encoding according to claim 7, configured to:

13. When executed by one or more processors, causes said one or more processors to perform the method for video encoding according to any of claims 1 to 6 to generate a bitstream. A non-transitory computer-readable storage medium having instructions and bitstreams recorded thereon.

14. A method for storing a bitstream generated by a method for video coding according to any one of claims 1 to 6.

15. A computer program product storing instructions for storing a bitstream containing encoded video data produced by a method for video encoding according to any one of claims 1 to 6.

Images