gaming machines

Abstract

To provide a game machine capable of preferably performing distribution of game balls in a game area.SOLUTION: A window panel is arranged on a front side of a game board 261, and a game area PA is regulated by being sandwiched by the game board 261 and the window panel. A distance from the surface of the game board 261 to a back face of the window panel is set to become larger than a diameter of the game ball. The game board 261 has a front / rear distribution nail 262 for distributing a route in a depth direction in the game area PA of the game ball which contacts thereto. The front / rear distribution nail 262 has: a first distribution plane which exists from the surface of the game board 261 to a halfway position of the game area PA toward the window panel, and bounces the game balls which flow down from an upstream of the game area PA and collide, to a depth side; and a second distribution plane which exists from a halfway position of the game area PA to the vicinity of the back face of the window panel, and bounces the game balls which flow down from the upstream side of the game area PA and collide, to the near side.SELECTED DRAWING: Figure 63

Description

[Technical Field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Known gaming machines include pachinko machines and slot machines. For example, a pachinko machine is equipped with a gaming board that defines a gaming area through which gaming balls flow. The gaming board is provided with various components, such as nails and windmills, for appropriately dispersing and adjusting the direction of the falling gaming balls as they flow down the gaming area. The gaming board also has openings from which gaming balls are paid out, such as a general winning hole, a special winning device, and an operating hole. A gaming ball launched from a gaming ball launching device flows down the gaming area while colliding with nails and the like, and when the gaming ball enters the general winning hole, the special winning device, or the operating hole, a predetermined number of gaming balls are paid out to the player (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-146319 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, in the gaming machines such as those exemplified above, Gaming machines must be properly managed, There is still room for improvement in this regard.

[0005] The present invention has been made in consideration of the above-mentioned circumstances, It is possible to manage gaming machines appropriately The object of the present invention is to provide a gaming machine that is [Means for solving the problem]

[0006] In order to solve the above problem, the invention described in claim 1 is as follows: a predetermined storage execution means for executing a predetermined storage process so that when a predetermined event occurs as a result of a game, information corresponding to the event is stored in the predetermined storage means, thereby causing the predetermined information to be stored in the predetermined storage means; an information calculation means for calculating, each time a predetermined calculation trigger occurs, behavior information corresponding to a game result during a predetermined period using the predetermined information; a result storage execution means for sequentially storing the aspect information obtained by the calculation by the information calculation means in a calculation result storage means; Equipped with the result storage execution means includes means for causing the mode information to be stored among the mode information obtained by the calculation by the information calculation means to be stored in the calculation result storage means; the state information obtained by the calculation by the information calculation means, which is not a storage target, is not stored in the calculation result storage means; This gaming machine is a predetermined control means capable of executing a predetermined progress process for progressing a game; A means for generating a specific advantageous period when a specific opportunity occurs; a notification means capable of notifying the user of the content corresponding to the aspect information stored in the calculation result storage means; Equipped with When a specific event occurs that stops the game progress control, the predetermined storage process is not executed by the predetermined storage execution means. The information calculation means calculates the status information using the predetermined information during the specific advantageous period as the status information corresponding to the game results during the predetermined period. It is characterized by: [Effects of the Invention]

[0007] According to the present invention, Properly manage gaming machines This becomes possible. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing a pachinko machine according to a first embodiment. [Figure 2] FIG. 1 is an exploded perspective view showing the main components of a pachinko machine. [Figure 3] FIG. 2 is a front view showing the configuration of the game board. [Figure 4] FIG. 10 is an explanatory diagram for explaining the configuration for discharging game balls that have flowed down the game area. [Figure 5] FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. [Figure 6] This is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. [Figure 7] 10 is a flowchart showing a main process executed by a main CPU. [Figure 8] 10 is a flowchart showing a timer interrupt process executed by the main CPU. [Figure 9] This is an explanatory diagram to explain the configuration in which the detection results of the ball entry detection sensor are input to the main CPU. [Figure 10]This is a flowchart showing the ball entry detection process executed by the main CPU. [Figure 11] A block diagram for explaining the electrical configuration of a dispensing control device and various devices that communicate with the dispensing control device. [Figure 12] 10 is a flowchart showing the timer interrupt processing executed by the dispensing CPU. [Figure 13] FIG. 2 is a block diagram for explaining the electrical configuration of a management IC. [Figure 14] FIG. 10 is an explanatory diagram illustrating the configuration of an input port of a management side I / F. [Figure 15] FIG. 2 is an explanatory diagram for explaining the configuration of a correspondence relationship memory; [Figure 16] FIG. 2 is an explanatory diagram illustrating the configuration of a history memory. [Figure 17] 10 is a flowchart showing a recognition process executed by a main CPU. [Figure 18] 10 is a flowchart showing a management process executed by a management-side CPU. [Figure 19] 10(a) to 10(d) are time charts showing how information on the correspondence between the first to fifteenth buffers and the types of signals is stored in the correspondence memory. [Figure 20] 10 is a flowchart showing a management output process executed by the main CPU. [Figure 21] 10 is a flowchart showing a history setting process executed by a management-side CPU. [Figure 22] 10(a) to 10(e) are time charts showing how history information is stored in a history memory. [Figure 23] 10 is a flowchart showing a data output process executed by the main CPU. [Figure 24] 10 is a flowchart showing an external output process executed by a management CPU. [Figure 25] FIG. 10 is an explanatory diagram illustrating the configuration of an input port of a management side I / F in the second embodiment. [Figure 26]10 is a flowchart showing a recognition process executed by a main CPU. [Figure 27] 10 is a flowchart showing a management process executed by a management-side CPU. [Figure 28] 10(a) to 10(h) are time charts showing how information on the correspondence between the first to twelfth buffers and the types of signals is stored in the correspondence memory. [Figure 29] FIG. 10 is a block diagram illustrating the electrical configuration of a management IC according to a third embodiment. [Figure 30] FIG. 10 is an explanatory diagram illustrating the configuration of an input port of a management side I / F. [Figure 31] 10 is a flowchart showing a power outage information storage process executed by a main CPU. [Figure 32] 10 is a flowchart showing a power failure response process executed by a management CPU. [Figure 33] 10 is a flowchart showing an external output process executed by a management CPU. [Figure 34] 13 is a flowchart showing a power failure response process executed by a control CPU in the fourth embodiment. [Figure 35] 13A is a flowchart showing a trigger identification process executed by a main CPU in the fifth embodiment, and FIG. 13B is a flowchart showing a calculation process executed by a management CPU. [Figure 36] 13 is a flowchart showing a trigger identification process executed by a main CPU in the sixth embodiment. [Figure 37] 13 is a flowchart showing a calculation process executed by a control-side CPU in the seventh embodiment. [Figure 38] 13 is a flowchart showing a history setting process executed by a management-side CPU in the eighth embodiment. [Figure 39] FIG. 20 is an explanatory diagram illustrating the configuration of a history memory in the ninth embodiment. [Figure 40] 10 is a flowchart showing a history setting process executed by a management-side CPU. [Figure 41] FIG. 22 is a block diagram for explaining the electrical configuration of the MPU of the main control device in the tenth embodiment. [Figure 42] This is a flowchart showing the ball entry detection process executed by the main CPU. [Figure 43] FIG. 22 is a block diagram for explaining the electrical configuration of a main control device in the eleventh embodiment. [Figure 44] FIG. 10 is an explanatory diagram illustrating the configuration of an input port of a management side I / F. [Figure 45] FIG. 2 is an explanatory diagram illustrating the configuration of a history memory. [Figure 46] 10 is a flowchart showing a history setting process executed by a management-side CPU. [Figure 47] 10 is a flowchart showing an external output process executed by a management CPU. [Figure 48] 10 is a flowchart showing a parameter management process executed by a main CPU. [Figure 49] This is a block diagram to explain the configuration of the signal path that transmits the detection results of each ball entry detection sensor to the main CPU and management IC in the 12th embodiment. [Figure 50] FIG. 22 is a front view of the game board in the thirteenth embodiment. [Figure 51] 1A is a perspective view of a first distributing nail, FIG. 1B is a plan view of a first distributing member, and FIG. 1C is a rear view of the first distributing member. [Figure 52] 1(a) is a perspective view of a fixing member, and FIG. 1(b) is an end view of a cut surface of a first left-right dividing nail when cut along a plane perpendicular to the surface of the game board. [Figure 53] (a) An end view of the longitudinal section of the first left and right distributing nail showing a game ball colliding with the first distributing surface; (b) An explanatory diagram for explaining the path of a game ball falling from above and colliding with the first distributing surface; (c) An explanatory diagram for explaining the path of a game ball flowing down from the upper left side and colliding with the first distributing surface. [Figure 54](a) An end view of the longitudinal section of the first left and right sorting nail showing a game ball colliding with the second sorting surface; (b) An explanatory diagram to explain the path of a game ball falling from above and colliding with the second sorting surface; (c) An explanatory diagram to explain the path of a game ball flowing down from the upper left side and colliding with the second sorting surface. [Figure 55] 1A is a perspective view of a second distributing nail, FIG. 1B is a plan view of a second distributing member, and FIG. 1C is a rear view of the second distributing member. [Figure 56] (a) A table showing the direction of the resistance force experienced by a game ball that collides with the first left / right dividing nail, (b) A table showing the direction of the resistance force experienced by a game ball that collides with the second left / right dividing nail, and (c) A table showing the direction of the resistance force experienced by a game ball that collides with an obstructing nail. [Figure 57] (a) An explanatory diagram to explain how a game ball located at the back is guided to the left-side guide nail group, and (b) an explanatory diagram to explain how a game ball located at the front is guided to the left-side guide nail group. [Figure 58] (a) An explanatory diagram to explain how a game ball located at the back is guided to the right-side guide nail group, and (b) an explanatory diagram to explain how a game ball located at the front is guided to the right-side guide nail group. [Figure 59] A front view of the game board showing an enlarged view of the area around the left guide member in another form of the thirteenth embodiment. [Figure 60] 1A and 1B are a front view and an enlarged view of a game board in which a first left-right dividing nail and a second left-right dividing nail are provided near the upstream side of an operating port, respectively. [Figure 61] 1A is a perspective view of a first left-right dividing nail, and FIG. 1B is an end view of a cut surface of the first left-right dividing nail when cut along a plane perpendicular to the surface of the game board. [Figure 62] (a) An oblique view of an inverted nail, (b) An end view of the cut surface when the inverted nail is cut on a plane perpendicular to the surface of the game board, (c) An explanatory diagram for explaining the path of a game ball that collides with the first inverted surface, and (d) An explanatory diagram for explaining the path of a game ball that collides with the second inverted surface. [Figure 63]A front view of the game board in the 14th embodiment and an enlarged view of the upstream area of ​​the left guide nail group. [Figure 64] (a) is an oblique view of a front-rear dividing nail, (b) is a plan view of a front-rear dividing member, and (c) and (d) are end views of the cut surface of the front-rear dividing nail when cut along a plane perpendicular to the surface of the game board. [Figure 65] (a) is an oblique view of a rear nail, and (b) and (c) are end views of the cut surface of the rear nail when cut along a plane perpendicular to the surface of the game board. [Figure 66] (a) An explanatory diagram for explaining the path of a game ball located at the back of the game area in the left-side guide pin group, and (b) an explanatory diagram for explaining the path of a game ball located at the front of the game area in the left-side guide pin group. [Figure 67] FIG. 20(a) is a plan view of a front priority member in another form of the fourteenth embodiment, and FIG. 20(b) is an explanatory diagram for explaining the path of a game ball in a left-side guide nail group including a front priority member. [Figure 68] A front view of the game board in the 15th embodiment and an enlarged view of the area around the rebound nail. [Figure 69] FIG. 2(a) is an exploded perspective view of a rebound nail, and FIG. 2(b) is a longitudinal sectional view of the rebound nail. [Figure 70] (a) An end view of the cut surface when the rebound nail is cut on a plane perpendicular to the plane of the game board, (b) An explanatory diagram for explaining the path of a game ball that collides with the high-rebound part, (c) An end view of the cut surface when the rebound nail is cut on a plane perpendicular to the plane of the game board, and (d) An explanatory diagram for explaining the path of a game ball that collides with the low-rebound part. [Figure 71] (a) An explanatory diagram to explain the path of a game ball that collides with the high-resilience part of a resilience nail, and (b) An explanatory diagram to explain the path of a game ball after collision with the low-resilience part of a resilience nail. [Figure 72] FIG. 20 is a front view of the game board in the sixteenth embodiment. [Figure 73] (a) is an oblique view of the front and rear distributing table, (b) is a plan view of the front and rear distributing table, and (c) and (d) are end views of the cross section when the front and rear distributing table is cut by a plane perpendicular to the surface of the game board. [Figure 74] FIG. 2 is a front view of the game board showing an enlarged central portion on the left side. [Figure 75] FIG. 20 is a front view of a game board in another form of the 16th embodiment. [Figure 76] 10A and 10B are front views of the game board showing an enlarged view of the area around the front and rear sorting table and the left guide nail group. [Figure 77] (a) is an oblique view of a front-to-back distributing table that has a groove that guides the game balls on the back side to the backmost side, and a groove that guides the game balls on the front side to the frontmost side, and (b) is an oblique view of a front-to-back distributing table that has a groove that guides the game balls on the back side to the frontmost side, and a groove that guides the game balls on the front side to the backmost side. [Figure 78] FIG. 22 is a front view of the game board in the seventeenth embodiment and an enlarged view of the area around the position change passage. [Figure 79] (a) is an oblique view of the passage forming member, (b) is a front view of the passage forming member, and (c) and (d) are end views of the cut surface when the passage forming member is cut by a plane perpendicular to the surface of the game board. [Figure 80] 10(a) and 10(b) are enlarged front views of the game board showing the downstream area of ​​the position change passage. [Figure 81] 10(a) and 10(b) are end views of the cut surface when the replacement passage forming member is cut along a plane perpendicular to the surface of the game board. [Figure 82] FIG. 20 is a front view of the game board in the 18th embodiment. [Figure 83] FIG. 2A is an exploded perspective view of the guide member, and FIG. 2B is a left side view of the guide member. [Figure 84] 10 is an end view of the cross section of the guide member cut along a plane perpendicular to the surface of the game board. FIG. [Figure 85] 10(a) and 10(b) are enlarged front views of the game board showing the downstream area of ​​the guide passage. [Figure 86] 10 is an end view of the cross section of the replacement guide member cut along a plane perpendicular to the surface of the game board. FIG. [Figure 87](a) An end view of the cross section when a guide member is cut on a plane perpendicular to the surface of the game board in another form of the 18th embodiment, and (b) an end view of the cross section when a replacement guide member is cut on a plane perpendicular to the surface of the game board. [Figure 88] FIG. 20(a) is a front view of the main control board showing an enlarged view of a portion of the main control board in the 19th embodiment, and FIG. 20(b) is a front view of the main control board showing an enlarged view of the area around the single-row connector. [Figure 89] FIG. 1A is a perspective view of a single-row connector, FIG. 1B is a perspective view of a two-pole connector, and FIG. 1C is a perspective view of a dual-row connector. [Figure 90] 1A is an enlarged perspective view of a portion of the back surface of a printed wiring board, and FIG. 1B is an enlarged longitudinal cross-sectional view of the printed wiring board cut along a plane perpendicular to the front surface, showing the area around a via hole. [Figure 91] 1 is an enlarged longitudinal cross-sectional view of a printed wiring board cut along a plane perpendicular to the surface, showing the area around a pin. [Figure 92] FIG. 1A is a rear view showing an enlarged view of a portion of the main control board, and FIG. 1B is a rear view of the printed wiring board showing an enlarged view of the single-row rear area before the single-row connector is attached. [Figure 93] FIG. 1A is an explanatory diagram for explaining a jet of molten solder, and FIG. 1B is an explanatory diagram for explaining the state in which the jet hits the rear surface of a printed wiring board. [Figure 94] (a) A longitudinal cross-sectional view of a comparative printed wiring board shown to explain the state in which the second, third, and fourth pins of the single-row connector are in contact with the jet, (b) A longitudinal cross-sectional view of a comparative printed wiring board shown to explain the state in which the second pin of the single-row connector is released from contact with the jet, and (c) A longitudinal cross-sectional view of a comparative printed wiring board shown to explain the state in which the third pin of the single-row connector is released from contact with the jet. [Figure 95](a) A longitudinal cross-sectional view of a comparative printed wiring board shown to explain the state in which the third pin of the single-row connector has come out of contact with the jet, (b) A longitudinal cross-sectional view of a comparative printed wiring board shown to explain the state in which the fourth pin of the single-row connector has come out of contact with the jet, and (c) A longitudinal cross-sectional view of a comparative printed wiring board showing the state in which a solder bridge has been formed between the third and fourth pins of the single-row connector. [Figure 96] FIG. 10 is a vertical cross-sectional view of a printed wiring board shown to explain a solder fillet formed around a fourth pin of a single-row connector. [Figure 97] FIG. 1A is a rear view of a printed wiring board showing an enlarged view of a two-pole rear surface area before a two-pole connector is attached, and FIG. 1B is a rear view of a printed wiring board showing an enlarged view of a two-row rear surface area before a two-row connector is attached. [Figure 98] (a) A rear view of a printed wiring board showing an enlarged view of a single-row rear area having an inclined short-circuit prevention hole in another form of the 19th embodiment, (b) a rear view of a printed wiring board showing an enlarged view of a single-row rear area, and (c) a rear view of a printed wiring board showing an enlarged view of a single-row rear area on the printed wiring board. [Figure 99] 13A is a rear view of a printed wiring board showing an enlarged view of a single-row rear surface area in the twentieth embodiment, and FIG. 13B is a longitudinal cross-sectional view of a printed wiring board showing an enlarged view of the periphery of the pins of a single-row connector. [Figure 100] (a) is a rear view of a printed wiring board showing an enlarged view of a single-row rear surface area in which six separate short-circuit prevention holes are formed in another form of the 20th embodiment, and (b) is a rear view of a printed wiring board showing an enlarged view of a single-row rear surface area in which two three-way separate short-circuit prevention holes are formed. [Figure 101] FIG. 21 is a rear view of a printed wiring board showing an enlarged view of a single-row rear area in which a group of short-circuit prevention holes for suppressing the occurrence of solder bridges is formed in the twenty-first embodiment. [Figure 102] A front view of the game board in the 22nd embodiment. [Figure 103](a) An explanatory diagram for explaining the connection mode between the first actuation port detection sensor and the second actuation port detection sensor and the main control board, and (b) a rear view of the printed wiring board showing an enlarged view of the first actuation port area and the second actuation port area. DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment A first embodiment of a pachinko gaming machine (hereinafter referred to as "pachinko machine"), which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a perspective view of the pachinko machine 10, and Fig. 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded form. For convenience, Fig. 2 omits the components within the gaming area PA of the pachinko machine 10.

[0010] As shown in Figure 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so that it can rotate forward. The outer frame 11 is made up of wooden boards connected at all four sides, forming a rectangular frame. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and the outer frame 11 may be attached to island equipment in the amusement hall.

[0011] 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 can be rotated forward with the left side as the base end of rotation and the right side as the tip end of rotation when viewed from the front.

[0012] A front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side being the base end and the right side being the tip end when viewed from the front. A back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated rearward with the left side being the base end and the right side being the tip end when viewed from the front.

[0013] The gaming machine main body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine main body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states can be released by using an unlocking key to unlock the cylinder lock 17, which is exposed on the front of the pachinko machine 10.

[0014] Next, the configuration of the front side of the gaming machine main body 12 will be described.

[0015] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 in the resin base 21.

[0016] Here, the configuration of the game board 24 will be described with reference to Fig. 3. Fig. 3 is a front view of the game board 24.

[0017] An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and these inner rail section 25 and outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0018] The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeding device 27b that supplies game balls stored in an upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c that is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. When a launching operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0019] A plurality of large and small openings are formed in the game board 24, penetrating in the front-to-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a general symbol unit 38. There are four general winning openings 31 in total, and one of each of the others.

[0020] Even if a ball enters the through gate 35, no game balls will be paid out. On the other hand, if balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls will be paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball will be paid out; when one game ball enters the general winning opening 31, ten prize balls will be paid out; and when one game ball enters the special electric winning device 32, fifteen prize balls will be paid out.

[0021] The number of prize balls is arbitrary, and for example, the second actuation port 34 may be configured to have fewer prize balls than the first actuation port 33, or the second actuation port 34 may be configured to have more prize balls than the first actuation port 33.

[0022] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes etc. are discharged from the game area PA through the outlet 24a. Also, on the game board 24, a large number of nails 24b are planted to appropriately distribute and adjust the falling direction of the game balls, and various components such as windmills are also arranged.

[0023] Here, "entering" means that a gaming ball passes through a predetermined opening, and includes not only the case where the gaming ball passes through the opening and is discharged from the gaming area PA, but also the case where the gaming ball continues to flow down the gaming area PA without being discharged from the gaming area PA after passing through the opening. However, in the following explanation, in order to clearly distinguish from the gaming ball entering the outlet 24a, the gaming ball entering the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the through gate 35 will also be referred to as "winning."

[0024] The first actuation port 33 and the second actuation port 34 are united as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 open upward. Furthermore, the first actuation port 33 is at the top, and both actuation ports 33, 34 are aligned vertically. The second actuation port 34 is provided with a normal power device 34a serving as a guide piece made up of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

[0025] A through gate 35 is provided upstream of the second operating port 34 in the direction in which the gaming ball flows down. The through gate 35 has a through hole (not shown) that penetrates vertically, and a gaming ball that enters the through gate 35 flows down through the gaming area PA after winning. This allows a gaming ball that enters the through gate 35 to enter the second operating port 34.

[0026] Based on a win at the through gate 35, the normal power device 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the win at the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38, which is located in the lower right corner of the game area PA, an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role release, the stop result corresponding to that result is displayed, and the variable display on the normal map display section 38a is terminated, the game transitions to the normal power open state. In the normal power open state, the normal power device 34a is opened in a predetermined manner.

[0027] The map display unit 38a is configured with a segment display in which a plurality of segment light-emitting elements are arranged in a predetermined manner, but is not limited to this and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display. As for the image displayed variably on the map display unit 38a, a configuration in which a plurality of types of letters are displayed variably, a configuration in which a plurality of types of symbols are displayed variably, a configuration in which a plurality of types of characters are displayed variably, or a configuration in which a plurality of types of colors are displayed in an alternating manner may be considered.

[0028] In the normal map unit 38, a normal map reserve display unit 38b is provided adjacent to the normal map display unit 38a. Up to four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display unit 38b.

[0029] A winning lottery is triggered by the entry into the first operating port 33 or the second operating port 34. The result of the lottery is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0030] Specifically, the special symbol unit 37 includes a special symbol display section 37a. The display area of ​​the special symbol display section 37a is smaller than the display surface 41a of the symbol display device 41. A winning lottery is triggered by a win through the first operating port 33 or the second operating port 34, and the special symbol display section 37a displays a variable or predetermined symbol. The result corresponding to the lottery result is then displayed. While the special symbol display section 37a is configured as a segment display device in which multiple segment light-emitting elements are arranged in a predetermined manner, it is not limited to this and may be configured as a liquid crystal display device, an organic electroluminescence display device, a cathode ray tube (CRT), a dot matrix display, or another type of display device. The symbol displayed on the special symbol display section 37a may be configured to display multiple characters, multiple symbols, multiple characters, or multiple colors.

[0031] In the special symbol unit 37, a special symbol reserve display unit 37b is provided adjacent to the special symbol display unit 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special symbol reserve display unit 37b.

[0032] More specifically, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

[0033] In the symbol display device 41, when a variable or predetermined display of symbols is performed in the special symbol display unit 37a based on a winning entry in the first actuation port 33 or a winning entry in the second actuation port 34, a variable or predetermined display of symbols is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows (top, middle, and bottom) set as multiple display areas, and in each symbol row, main symbols numbered "1" through "9" are scrolled and displayed in ascending or descending order. In this scrolling display, scrolling of all symbol rows is first started, then switched from scrolling display to standby display in the order of the top symbol row → bottom symbol row → middle symbol row, and finally ended with a predetermined symbol being statically displayed in each symbol row. Then, for example, in a game where the game result is a jackpot, a predetermined combination of symbols is displayed stationary on a predetermined pay line on the display surface 41a of the symbol display device 41.

[0034] In addition, the symbol display device 41 not only displays effects triggered by winning a prize in the first actuation port 33 or the second actuation port 34, but also displays effects during the opening / closing execution mode to which the game enters after a winning combination is achieved. Furthermore, based on a winning combination in either actuation port 33, 34, display begins on the special symbol display unit 37a and the symbol display device 41, and one game session is played until a predetermined result is displayed and the game ends. Furthermore, the manner in which the symbols are displayed in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol rows, the direction of the symbol display in the symbol rows, the number of symbols in each symbol row, etc. can be changed as appropriate. Furthermore, the symbols displayed in the symbol display device 41 are not limited to the above-described symbols; for example, a configuration in which only numbers are displayed as symbols may be used.

[0035] If a jackpot is won in a lottery based on a win through the first operating port 33 or the second operating port 34, the system transitions to an open / close execution mode in which a prize can be won in the special electric winning device 32. The special electric winning device 32 includes a large prize opening (not shown) that leads to the back side of the game board 24, and an open / close door 32a that opens and closes the large prize opening. The open / close door 32a is positioned in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which game balls cannot win, and is switched to an open state in which game balls can win if an internal lottery is selected to transition to the open / close execution mode. The open / close execution mode is a mode that is transitioned to when a win is achieved. Note that while a prize can be won in the closed state, it may be configured to be less likely to win than in the open state.

[0036] FIG. 4 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

[0037] As already explained, a gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the gaming area PA. In other words, a gaming ball that is launched from the gaming ball launching mechanism 27 and flows into the gaming area PA is discharged from the gaming area PA by entering any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the gaming board 24.

[0038] On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, respectively. The game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, and are guided to the lower end of the game board 24 on the back side of the game board 24, where they are collected by a discharge ball collection section (not shown). The game balls collected by the discharge ball collection section are then discharged to a ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

[0039] Each of the discharge passage sections 42-48 is provided with various detection sensors 42a-48a for detecting gaming balls. These discharge passage sections 42-48 and detection sensors 42a-48a will be described below. As already explained, four general winning openings 31 are provided, and therefore, there are discharge passage sections 42-44 corresponding to each of the four general winning openings. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage section 42 corresponding to the leftmost general winning opening 31 and the second discharge passage section 43 corresponding to the general winning opening 31 adjacent to it on the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located midway along the first discharge passage section 42, and the second winning opening detection sensor 43a is provided so that its detection range is located midway along the second discharge passage section 43. A gaming ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a as it passes through the first discharge passage 42, and a gaming ball that enters the general winning opening 31 adjacent to it on the right is detected by the second winning opening detection sensor 43a as it passes through the second discharge passage 43. A third discharge passage 44 is provided for the two general winning openings 31 on the right, and is formed so that the two general winning openings 31 merge midway. The third discharge passage 44 has entrance-side regions corresponding to the two general winning openings 31, and these entrance-side regions merge midway to form a single exit-side region. A third winning opening detection sensor 44a is provided so that a detection range is located midway in the exit-side region of the third discharge passage 44. A gaming ball that enters either of the two general winning openings 31 on the right is detected by the third winning opening detection sensor 44a as it passes through the third discharge passage 44.

[0040] A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at a position midway through the fourth discharge passage section 45, and a gaming ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a as it passes through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists at a position midway through the fifth discharge passage section 46, and a gaming ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a as it passes through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second operating port detection sensor 47a is provided so that its detection range exists at a midpoint of the sixth discharge passage section 47, and a gaming ball that enters the second operating port 34 is detected by the second operating port detection sensor 47a as it passes through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that its detection range exists at a midpoint of the seventh discharge passage section 48, and a gaming ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage section 48.

[0041] A gaming ball that is detected by one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on its way down the gaming area PA is detected by the gate detection sensor 49a.

[0042] Although electromagnetic induction type proximity sensors are used as the various detection sensors 42a-49a, any sensor can be used as long as it can detect gaming balls individually. The various detection sensors 42a-49a are electrically connected to the main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a gaming ball, and output a HI level signal when they are detecting a gaming ball. However, this is not a limitation, and the relationship between HI and LOW may be reversed.

[0043] As shown in Fig. 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the game board 24 having the above-described configuration to the resin base 21. As shown in Fig. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of ​​the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into the window portion 51. The window panel 52 is formed of colorless and transparent glass, but is not limited to this and may be formed of colorless and transparent synthetic resin, or may be formed of colored and transparent as long as the game area PA is visible through the window panel 52 from the front of the pachinko machine 10.

[0044] A display light-emitting unit 53 is provided above the window 51. A pair of left and right speakers 54 are also provided to output sound effects according to the game status. An upper bulge 55 and a lower bulge 56, which bulge toward the front, are arranged vertically below the window 51. An upper tray 55a that opens upward is provided inside the upper bulge 55, and a lower tray 56a that also opens upward is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls dispensed from the dispensing device (described later) and guiding them in a row toward the game ball launching mechanism 27. The lower tray 56a also has the function of storing surplus game balls in the upper tray 55a.

[0045] Next, the configuration of the rear side of the gaming machine main body 12 will be described.

[0046] As shown in FIG. 2, a main control device 60, which is responsible for the primary control of the game, is mounted on the back of the inner frame 13 (specifically, the game board 24). The main control device 60 is configured by housing a main control board 61 in a board box 60a. The board box 60a may be provided with a trace means or a trace structure for leaving a trace of its opening. Possible trace means include a joint structure that inseparably connects the multiple case bodies constituting the board box 60a and requires destruction of a predetermined portion upon separation, or a structure in which a seal is attached across the boundaries between the multiple case bodies, leaving a trace of its removal by leaving an adhesive layer on the bonded object upon peeling. Another possible trace structure is a structure in which an adhesive is applied to the boundaries between the multiple case bodies constituting the board box 60a.

[0047] A back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 has a back pack 72 formed from a transparent synthetic resin, and a dispensing mechanism section 73 and a control device assembly unit 74 are attached to the back pack 72.

[0048] The payout mechanism 73 includes a tank 75 to which gaming balls supplied from the island equipment of the gaming hall are successively replenished, and a payout device 76 for paying out the gaming balls stored in the tank 75. The gaming balls paid out from the payout device 76 are discharged into the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power on and off.

[0049] The control device aggregate unit 74 is equipped with a payout control device 77 having the function of controlling the payout device 76, and a power supply / launch control device 78 which generates and outputs the predetermined power required by the various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply / launch control device 78 are stacked one behind the other so that the payout control device 77 is at the rear of the pachinko machine 10.

[0050] <Electrical configuration of pachinko machine 10> FIG. 5 is a block diagram showing the electrical configuration of the pachinko machine 10. As shown in FIG.

[0051] The main control device 60 comprises a main control board 61 that is responsible for the main control of the game, and a power outage monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 has a main CPU 63, which is an arithmetic processing device including a control unit and an arithmetic unit, as well as a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also has built-in interrupt circuits, timer circuits, data input / output circuits, various counter circuits such as random number generators, etc.

[0052] The main ROM 64 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0053] The main RAM 65 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM or DRAM, and is used for both reading and writing. The main RAM 65 is randomly accessible and takes less time to read data than the main ROM 64 when compared for the same data capacity. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0054] The management IC 66 is a management device that manages the entry patterns of game balls in the game area PA based on information supplied from the main CPU 63. As will be described in detail later, the management IC 66 grasps the entry history of game balls into the general winning opening 31, the special electric winning device 32, the first actuation opening 33, the second actuation opening 34, and the outlet 24a, and also grasps the entry frequency into the general winning opening 31, the special electric winning device 32, the first actuation opening 33, and the second actuation opening 34 according to the grasped ball entry history.

[0055] The MPU 62 is provided with an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply / launch control device 78 having the function of supplying operating power, and operating power is supplied to the MPU 62 via the power outage monitoring board 67.

[0056] Various sensors, such as the ball entry detection sensors 42a-49a, are connected to the input side of the MPU 62. As already explained, the ball entry detection sensors 42a-49a are the first prize entry detection sensor 42a, the second prize entry detection sensor 43a, the third prize entry detection sensor 44a, the special electric current detection sensor 45a, the first operation port detection sensor 46a, the second operation port detection sensor 47a, the outlet detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a-49a, the main CPU 63 determines whether a ball has entered each entry area. In addition, the main CPU 63 executes various lotteries based on whether a ball has entered the first operation port 33, and also executes various lotteries based on whether a ball has entered the second operation port 34.

[0057] The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio / light emitting control device 81. A prize ball command is output to the payout control device 77, for example, when a gaming ball enters a prize ball entry section among the entry sections, where the occurrence of the ball entry corresponds to the payout of the gaming ball. Various commands such as a variation command, a type command, and an opening command are output to the audio / light emitting control device 81.

[0058] The output side of the MPU 62 is connected to a special power drive unit 32b that opens and closes the opening / closing door 32a of the special power winning device 32, a normal power drive unit 34b that opens and closes the normal power device 34a of the second operating port 34, a special power unit 37, and a normal power unit 38. Incidentally, the special power unit 37 is provided with a special power display unit 37a and a special power reserve display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal power unit 38 is provided with a normal power display unit 38a and a normal power reserve display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 controls the drive of various drive units and various display units through these driver circuits.

[0059] That is, in the opening / closing execution mode, the main CPU 63 executes drive control of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the normal power device 34a is won, the main CPU 63 executes drive control of the normal power drive unit 34b so that the normal power device 34a is opened and closed. Also, during each game round, the main CPU 63 executes display control of the special chart display unit 37a. Also, when the lottery result of whether or not the normal power device 34a is to be opened is clearly displayed, the main CPU 63 executes display control of the normal chart display unit 38a. In addition, when a prize is won at the first operating port 33 or the second operating port 34, or when a changing display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart reserve display unit 37b, and when a prize is won at the through gate 35, or when a changing display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart reserve display unit 38b.

[0060] The power failure monitoring board 67 relays between the main control board 61 and the power supply / launch control device 78, and monitors the stable DC voltage of 24 volts, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0061] The power supply and launch control device 78 is connected to a commercial power source (external power source) in, for example, an amusement hall. Based on the external power supplied from the commercial power source, the power supply and launch control device 78 generates the operating power required for the main control board 61, the payout control device 77, and the like, and supplies the generated operating power. Incidentally, the power supply and launch control device 78 is provided with a power supply unit for use in the event of a power outage, such as a backup capacitor, and even when the power to the pachinko machine 10 is turned off, power for maintaining memory is supplied from the power supply unit for use in the event of a power outage to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply and launch control device 78 is also responsible for controlling the launch of the game ball launching mechanism 27, which is driven when predetermined launch conditions are met.

[0062] The audio and light emitting control device 81 drives and controls the display light emitting unit 53 and speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 executes display control of the pattern display device 41 based on commands received from the audio and light emitting control device 81.

[0063] <Electrical configuration for performing various lotteries in the main CPU 63> Next, the electrical configuration for performing various lotteries in the main CPU 63 will be described with reference to FIG.

[0064] During play, the master CPU 63 uses various counter information to determine whether a jackpot occurs, set the display of the special symbol display unit 37a, set the symbol display of the symbol display unit 41, and set the display of the normal symbol display unit 38a. Specifically, as shown in FIG. 6, the master CPU 63 uses a hit random number counter C1 used to determine whether a jackpot occurs, a jackpot type counter C2 used to determine the type of jackpot, a reach random number counter C3 used to determine whether a reach occurs when the symbol display unit 41 changes due to a miss, a random number initial value counter CINI used to set the initial value of the hit random number counter C1, and a change type counter CS used to determine the display duration of the special symbol display unit 37a and the symbol display unit 41. Furthermore, the master CPU 63 uses a normal power feature release counter C4 used to determine whether the normal power feature 34a of the second operating port 34 is set to a normal power release state. The counters C1-C3, CINI, CS, and C4 are provided in the various counter area 65b of the master RAM 65.

[0065] Each counter C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

[0066] The reserve storage area 65a comprises a reserve area RE and an execution area AE. The reserve area RE comprises a first reserve area RE1, a second reserve area RE2, a third reserve area RE3 and a fourth reserve area RE4, and a combination of numerical information of the win random number counter C1, the jackpot type counter C2 and the reach random number counter C3 is stored as reserve information in one of the reserve areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

[0067] In this case, when multiple consecutive wins occur in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first hold area RE1 to the fourth hold area RE4 in chronological order from the first hold area RE1 to the second hold area RE2 to the third hold area RE3 to the fourth hold area RE4. By providing four hold areas RE1 to RE4 in this way, up to four winning histories of game balls entering the first actuation port 33 or the second actuation port 34 can be reserved and stored.

[0068] The number of items that can be stored on hold is not limited to four and can be any number, such as two, three, five or more, or it can be singular.

[0069] The execution area AE is an area for moving each piece of numerical information stored in the first holding area RE1 of the holding area RE when the variable display of the special chart display section 37a begins, and when one game round starts, a win / loss determination is made based on the various numerical information stored in the execution area AE.

[0070] Each of the counters will now be described in detail.

[0071] First, the normal power accessory opening counter C4 will be described. The normal power accessory opening counter C4 is configured to be incremented by one in sequence within a range of, for example, 0 to 250, and to return to "0" after reaching the maximum value. The normal power accessory opening counter C4 is periodically updated, and is stored in the normal power reserve area 65c of the main RAM 65 when a gaming ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the normal power accessory 34a to the open state based on the value of the stored normal power accessory opening counter C4.

[0072] In the present pachinko machine 10, a plurality of types of support modes are set so that the manner of support by the normal power device 34a differs from one another. In detail, the support modes are set to a high frequency support mode and a low frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 is opened per unit time is relatively high or low when compared in a situation where game balls are continuously launched in the same manner into the game area PA.

[0073] In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power device opening counter C4 is the same (for example, 4 / 5 in both), but in the high-frequency support mode, the number of times the normal power device 34a opens when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for each opening is set to be longer.In this case, if the normal power opening state is won in the high-frequency support mode and the normal power device 34a opens multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each opening.Furthermore, in the high-frequency support mode, the minimum time ensured between one normal power opening lottery and the next normal power opening lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0074] As described above, in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into first actuation port 33 is higher than in second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in first actuation port 33. When a winning entry into second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

[0075] The configuration for increasing the frequency of normal power release per unit time in the high-frequency support mode compared to the low-frequency support mode is not limited to the above, and may be configured to increase the probability of winning the normal power release state in the normal power release lottery, for example. In addition, in a configuration in which multiple types of reserved time (e.g., the time of variable display executed by the normal power display unit 38a based on winning at the through gate 35) are available for the period between one normal power release lottery and the next, the high-frequency support mode may be configured to be more likely to select a shorter reserved time or to have a shorter average reserved time than the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of the following conditions: increasing the number of releases, lengthening the open time, shortening the reserved time between one normal power release lottery and the next, shortening the average reserved time, and increasing the winning probability.

[0076] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to increment by one within a range of, for example, 0 to 599, and return to "0" after reaching a maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated, and is stored in the reserve storage area 65a of the main RAM 65 when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0077] The random number value that results in a jackpot win is stored as a hit / miss table in the main ROM 64. As the hit / miss table, a hit / miss table for a low probability mode and a hit / miss table for a high probability mode are set. In other words, in this pachinko machine 10, a low probability mode and a high probability mode are set as the lottery modes in the hit / miss lottery means.

[0078] In a gaming state where the winning / losing table for the low probability mode is referenced in the lottery, the number of random numbers that will result in a jackpot is 2. On the other hand, in a gaming state where the winning / losing table for the high probability mode is referenced in the lottery, the number of random numbers that will result in a jackpot is 20. Note that the number of random numbers that will result in a jackpot can be any number as long as the winning probability is higher in the high probability mode than in the low probability mode.

[0079] The jackpot type counter C2 is configured to be incremented by 1 in sequence within a range of 0 to 29, and to return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically, and is stored in the reserve storage area 65a when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0080] A plurality of jackpot results are set in this pachinko machine 10. These plurality of jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special power winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning / losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the normal power device 34a of the second operating port 34 after the opening and closing execution mode ends.

[0081] As the manner of opening and closing control of the special power winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special power winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds of play are played up to the upper limit.

[0082] Here, a round game is a game that continues until one of the following conditions is met: a predetermined upper limit duration has elapsed, or a predetermined upper limit number of game balls have entered the special winning device 32. Furthermore, the number of round games in the open / close execution mode triggered by a jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the jackpot result, the upper limit for the number of round games is set to 15.

[0083] Furthermore, in this pachinko machine 10, a plurality of types are set for one opening mode of the special electric winning device 32, with different opening durations from when the special electric winning device 32 is opened until when it is closed. In detail, a long-time mode in which the opening duration is set to 29 seconds, which is a long time, and a short-time mode in which the opening duration is set to 0.06 seconds, which is a short time shorter than the long time, are set.

[0084] In this pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched toward the play area PA every 0.6 seconds. The upper limit for the number of balls required to complete a round game is set to nine. In this case, the long-time mode among the above-mentioned release modes sets the release duration to a time longer than the product of the game ball launch cycle and one round game. On the other hand, the short-time mode sets the release duration to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when a single release is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of prizes in one round game. When a single release is performed in the short-time mode, it is expected that the special electric winning device 32 will not win, or that only one prize will be won, even if one prize is won.

[0085] In the high frequency winning mode, the special power winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special power winning device 32 is opened once in each round of play in a short time mode.

[0086] In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of rounds of play in one round in the high frequency winning mode and low frequency winning mode are not limited to the above values ​​and are arbitrary, as long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

[0087] The allocation destination of the game result for the jackpot type counter C2 is stored as an allocation table in the main ROM 64. The allocation destinations are set to a low probability jackpot result, a low winning high probability jackpot result, and a most advantageous jackpot result.

[0088] A low probability jackpot result is a jackpot result in which the opening / closing execution mode becomes a high frequency winning mode, and after the opening / closing execution mode ends, the winning / losing lottery mode becomes a low probability mode and the support mode becomes a high frequency support mode. However, this high frequency support mode will transition to a low frequency support mode if the number of games played after the transition reaches the termination reference number (specifically, 100 times).

[0089] A low-prize, high-probability jackpot result is a jackpot result in which the open / close execution mode becomes a low-frequency win mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0090] The most favorable jackpot result is a jackpot result in which the open / close execution mode becomes a high-frequency winning mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0091] In relation to the above game states, the normal game state refers to a state in which the win / lose lottery mode is a low probability mode and the support mode is a low frequency support mode, rather than the open / close execution mode. Also, a low-prize, high-probability jackpot result may not be set as a game result. In addition, in the open / close execution mode in a low-prize, high-probability jackpot result, the number of rounds of play may be fewer than in the case of a low-probability jackpot result and a most favorable jackpot result.

[0092] In the distribution table, of the values ​​of the jackpot type counter C2 from "0 to 29", "0 to 9" corresponds to a low probability jackpot result, "10 to 14" corresponds to a low probability jackpot result with a high probability of winning, and "15 to 29" corresponds to the most favorable jackpot result.

[0093] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to increment by one within a range of, for example, 0 to 238, and return to "0" after reaching a maximum value. Here, the pachinko machine 10 is configured with an expectation effect as one type of display effect on the symbol display device 41. The expectation effect refers to a display state that makes a player believe that a variable display state that is likely to result in a prize-related result is achieved in a gaming machine equipped with a symbol display device 41 capable of displaying variable symbols, and in which the final stop result in a game round resulting in a predetermined jackpot result is a prize-related result, from the start of the variable display of symbols on the symbol display device 41 until the stop result is derived and displayed. Specifically, the prize-related result is a combination of symbols with the same number displayed on any of the pay lines.

[0094] There are two types of expectation effects: a reach display and a notice display that is set to anticipate the occurrence of a reach display or a corresponding result before the reach display occurs.

[0095] The reach display includes a display state in which a reach symbol combination is displayed by stopping the display of symbols in some of the multiple symbol rows displayed on the display surface 41a of the symbol display device 41, and in that state, a variable display of symbols is performed in the remaining symbol rows. Also included are a reach effect in which, in a state in which a reach symbol combination is displayed as described above, a variable display of symbols is performed in the remaining symbol rows, and a reach effect is performed by displaying predetermined characters or the like as a moving image on the background screen, and a reach effect in which a reach symbol combination is displayed in a reduced size or is not displayed, and then a predetermined character or the like is displayed as a moving image on almost the entire display surface 41a.

[0096] The preview display includes a mode in which a character is displayed separately from the symbols on the symbol row when symbols are displayed variably in all symbol rows or when symbols are displayed variably in some symbol rows after the display of the variable symbols on the display surface 41a of the symbol display device 41 has started. It also includes a mode in which the background screen is displayed in a predetermined mode different from its previous mode, or a mode in which the symbols on the symbol row are displayed in a predetermined mode different from their previous mode. Such a preview display can occur in both game rounds when a reach display is made and when a reach display is not made, but is set to occur with a higher probability when a reach display is made than when a reach display is not made.

[0097] The reach display is executed regardless of the value of the reach random number counter C3 in a game in which the same symbol combination is finally stopped and displayed. Also, in a game in which a jackpot result is reached and the same symbol combination is not stopped and displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Also, in a game in which a miss result is reached, the reach display is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0098] On the other hand, the decision on whether to display a notice is not made by the main control device 60 but by the audio and light emitting control device 81. In this case, the audio and light emitting control device 81 executes a lottery process for the notice display so as to satisfy at least one of the conditions that a notice display is more likely to occur in a game round corresponding to a jackpot result than a game round corresponding to a loss result, and that a notice display with a low occurrence rate is more likely to occur. Incidentally, this lottery result is reflected when the effect for the game round is executed by the symbol display device 41.

[0099] Next, the variation type counter CS will be explained. The variation type counter CS is configured to be incremented by 1 in sequence within a range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variation type counter CS is used by the main CPU 63 to determine the display duration in the special symbol display unit 37a and the display duration of the symbol in the symbol display device 41. The variation type counter CS is updated once each time the normal processing described below is executed, and is also repeatedly updated within the remaining time in the normal processing. Then, the buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variable display in the special symbol display unit 37a and at the start of the symbol variation by the symbol display device 41.

[0100] <Regarding the processing configuration of the main CPU 63> Next, we will explain each process executed to progress the game by the main CPU 63. The processes of the main CPU 63 are roughly divided into main processing that is started when the power is turned on, and timer interrupt processing that is started periodically (every 4 msec in this embodiment).

[0101] <Main processing> First, the main processing will be described with reference to the flowchart of FIG.

[0102] First, a power-on wait process is executed (step S101). In this power-on wait process, for example, the main process is started and a predetermined wait time (specifically, 1 second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial setting of the pattern display device 41 are completed. Thereafter, access to the main RAM 65 is permitted (step S102), and the internal function register of the main CPU 63 is set (step S103).

[0103] Thereafter, it is determined whether the RAM erase switch provided on the power supply / launch control device 78 has been manually operated (step S104), and further whether the power outage flag of the main RAM 65 has been set to "1" (step S105). Also, a checksum calculation process is executed to calculate a checksum (step S106), and it is determined whether the checksum matches the checksum saved when the power was shut off, i.e., the validity of the stored data (step S107).

[0104] In this pachinko machine 10, when the power is turned on, for example, when the gaming hall opens for business, the RAM data is initialized by pressing the RAM clear switch while the power is turned on. Therefore, if the RAM clear switch is pressed, the process proceeds to step S108. Similarly, if the power interruption occurrence information is not set or if an abnormality in the stored data is confirmed by the checksum, the process proceeds to step S108. In step S108, the main RAM 65 is cleared. Then, the process proceeds to step S109.

[0105] On the other hand, if the RAM erase switch has not been pressed, the process proceeds to step S109 without executing the process of step S108, provided that the power outage flag is set to "1" and the checksum is normal. In step S109, a power-on setting process is executed. In the power-on setting process, a predetermined area of ​​the main RAM 65 is set to an initial value, such as initializing the power outage flag, and a command corresponding to the current game status is sent to the sound and light emission control device 81. After executing the process of step S109, a recognition process (step S110) is executed to have the management IC 66 recognize various information, and a data output process is executed to output various data to a reader connected to the MPU 62 (step S111). The details of the recognition process and the data output process will be described later.

[0106] The main CPU 63 is configured to periodically execute timer interrupt processing, but the occurrence of timer interrupt processing is prohibited when the main processing is started. This state in which the occurrence of timer interrupt processing is prohibited is released when the processing of step S111 is completed and before the processing of step S112 is executed, and execution of the timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 starts, the data output processing of step S111 ends and the timer interrupt processing is not executed until the stage before the processing of step S112 is started. Therefore, processing for progressing the game in the main CPU 63 is not started until this situation is reached.

[0107] Thereafter, the process proceeds to the remaining process of steps S112 to S115. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining process of steps S112 to S115. In this respect, the remaining process of steps S112 to S115 can be said to be non-periodic processing that is executed non-periodically.

[0108] In the remaining process, first, in step S112, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing. In the following step S113, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S114, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, current numerical information is read from the corresponding counter in the main RAM 65, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value reaches its maximum value, it is cleared to "0". Thereafter, in step S115, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is prohibited to a state in which it is permitted. After executing the processing of step S115, the process returns to step S112, and the processing of steps S112 to S115 is repeated.

[0109] <Timer interrupt processing> Next, the timer interrupt process will be described with reference to the flowchart of Fig. 8. The timer interrupt process is executed periodically (for example, every 4 msec).

[0110] First, a power outage information storage process is executed (step S201). In the power outage information storage process, it is monitored whether a power outage signal corresponding to the occurrence of a power outage has been received from the power outage monitoring board 67, and if a power outage is identified, a power outage process is executed and then an infinite loop is entered. In the power outage process, the power outage flag in the main RAM 65 is set to "1", and a checksum is calculated and stored.

[0111] Then, a lottery random number update process is executed (step S202). In the lottery random number update process, the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power feature release counter C4 are updated. Specifically, the current numerical information is sequentially read from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power feature release counter C4, and after executing a process of adding 1 to each of the read numerical information, a process of overwriting the counter from which it was read is executed. In this case, when the counter value reaches its maximum value, each is cleared to "0". Then, in step S203, a random number initial value update process is executed as in step S113, and in step S204, a variable counter update process is executed as in step S114.

[0112] Thereafter, a fraud detection process is executed to monitor whether or not a predetermined event set as a target for fraudulent use has occurred (step S205). In this fraud detection process, the occurrence of multiple types of events is monitored, and if a predetermined event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S206, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S206, the process from step S207 onwards is executed.

[0113] In step S207, port output processing is executed. In the port output processing, if output information has been set in the previous timer interrupt processing, processing is executed to output corresponding to that output information to the various drive units 32b, 34b. For example, if information to switch the special power winning device 32 to an open state is set, output of a drive signal to the special power drive unit 32b is started, and if information to switch to a closed state is set, output of the drive signal is stopped. Also, if information to switch the normal power device 34a of the second operating port 34 to an open state is set, output of a drive signal to the normal power drive unit 34b is started, and if information to switch to a closed state is set, output of the drive signal is stopped.

[0114] Then, a read process is executed (step S208). In the read process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in subsequent processes.

[0115] Thereafter, a ball entry detection process is executed (step S209). In the ball entry detection process, signals received from each ball entry detection sensor 42a-49a are read, and based on the read results, it is determined whether or not a ball has entered the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, the second operating hole 34, and the through gate 35. Details of the ball entry detection process will be explained later.

[0116] Thereafter, a timer update process is executed (step S210) for collectively updating the numerical information of the multiple types of timer counters provided in the main RAM 65. In this case, the timer counters in which the stored numerical information is updated by subtraction are handled collectively, but it is also possible to collectively update both the subtraction type timer counters and the addition type timer counters.

[0117] Thereafter, a launch control process is executed to control the launch of game balls (step S211). While the launch operation to the launch operation device 28 continues, one game ball is launched every 0.6 seconds, which is a predetermined launch cycle. In the following step S212, as an input status monitoring process, based on the information read in the reading process of step S208, a disconnection check is performed for each ball entry detection sensor 42a-49a, and the opening of the gaming machine main body 12 and the front door frame 14 is checked.

[0118] Thereafter, a special symbol special electric control process is executed to control the execution of a game round and the execution of the open / close execution mode (step S213). In this special symbol special electric control process, when a win occurs in the first actuation port 33 or the second actuation port 34 while the number of reserved information stored in the reserved storage area 65a is less than the upper limit, the numerical information of the win random number counter C1, the jackpot type counter C2, and the reach random number counter C3 at that time is stored as reserved information in chronological order in the reserved storage area 65a. In addition, in the special symbol special electric control process, on the condition that the game round or the open / close execution mode is not in progress and reserved information is stored, a hit / miss determination process is executed to determine whether the reserved information corresponds to a jackpot win, and if it corresponds to a jackpot win, an allocation determination process is executed to determine which jackpot result the reserved information corresponds to. In addition, the special symbol special signal control process not only performs a win / loss determination process and a distribution determination process, but also performs a reach determination process to determine whether the pending information corresponds to a jackpot win if the pending information does not correspond to a reach, and performs a process to select the duration of the game using the numerical information of the variation type counter CS at that time. Then, a variation command containing duration information corresponding to the results of each process and a type command containing information on the game result are sent to the audio and light-emitting control device 81, and the special symbol display unit 37a begins displaying the varying symbols. Upon receiving the variation command and the type command, the audio and light-emitting control device 81 initiates the display and light-emitting unit 53 and the speaker unit 54 to display the corresponding game effect. The audio and light-emitting control device 81 also transmits a variation pattern command corresponding to the variation command and the type command to the display control device 82. Upon receiving the variation pattern command, the display control device 82 begins displaying the varying symbols corresponding to the variation pattern command on the symbol display device 41. This marks the start of one game.

[0119] During a game round, the special symbol special signal control process determines whether the game round's duration determined at the start of the game round has elapsed, thereby determining whether the time for the game round to end has arrived. If the time for the game round to end has arrived, the process ends the game round with a display corresponding to the game result. In this case, if the current game round corresponds to the occurrence of a jackpot, a symbol corresponding to the type of jackpot result is displayed frozen on the special symbol display unit 37a. If the current game round corresponds to a loss result, a symbol corresponding to the loss result is displayed frozen on the special symbol display unit 37a. A final stop command indicating that the game round should end is sent to the audio and light-emitting control device 81. Upon receiving the final stop command, the audio and light-emitting control device 81 terminates the effects for the current game round on the display light-emitting unit 53 and speaker unit 54. The audio and light-emitting control device 81 also transmits the final stop command to the display control device 82. Upon receiving the final stop command, the display control device 82 terminates the effects for the current game round on the symbol display device 41.

[0120] In the special symbol special electric control process, if the result of a game round corresponds to a transition to the open / close execution mode, a process is executed to start the open / close execution mode. To start the open / close execution mode, an opening command indicating the start of the open / close execution mode is sent to the audio / light-emitting control device 81. The special symbol special electric control process also executes processes to start each round of play and to end each round of play. When a round of play starts, the special electric winning device 32 enters an open state, and when a round of play ends, the special electric winning device 32 enters a closed state. During each of these processes, an open command indicating the start of a round of play is sent to the audio / light-emitting control device 81, and a close command indicating the end of a round of play is sent to the audio / light-emitting control device 81. In addition, when the special symbol special electric control process ends the open / close execution mode, an ending command indicating this is sent to the audio / light-emitting control device 81. The audio / light-emitting control device 81 controls the display / light-emitting unit 53 and the speaker unit 54 to execute effects for the open / close execution mode in a manner corresponding to the various commands received during the open / close execution mode. Furthermore, the sound and light emission control device 81 transmits a command corresponding to the command received during the opening and closing execution mode to the display control device 82. The display control device 82 causes the pattern display device 41 to execute the effects for the opening and closing execution mode in a manner corresponding to the various commands received during the opening and closing execution mode. Furthermore, in the special pattern special electricity control process, when the opening and closing execution mode is to be ended, a process is executed so that the win / loss lottery mode and support mode after the end of the opening and closing execution mode become modes corresponding to the type of jackpot result that triggered the execution of the opening and closing execution mode.

[0121] After executing the special power control process of step S213 in the timer interrupt process, the normal power control process is executed (step S214). In the normal power control process, if a win has occurred in the through gate 35, a process is executed to acquire the reserved information on the normal side, and if the reserved information on the normal side is stored, an opening judgment is made for the reserved information, and further, a process is executed to perform a normal power performance triggered by the opening judgment. Also, based on the result of the opening judgment, a process is executed to open and close the normal power role 34a of the second operating port 34. In this case, if the support mode is the low-frequency support mode, a corresponding process is executed, and if the support mode is the high-frequency support mode, a corresponding process is executed. Also, if the opening and closing execution mode is selected, the support mode immediately before will be the low-frequency support mode even if it was the high-frequency support mode.

[0122] In the following step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set to reflect the increase or decrease in the number of reserved information related to the special map display unit 37a in the special map reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the ordinary map display unit 38a in the ordinary map reserved display unit 38b. Also, in step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set to update the display contents of the special map display unit 37a, and output information is set to update the display contents of the ordinary map display unit 38a.

[0123] Thereafter, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation result (step S216). Also, a payout output process is executed to set the prize ball command as an output target (step S217). Also, an external information setting process is executed to control the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process (step S218). Thereafter, a management output process is executed to output information corresponding to the ball entry result in the game area PA to the management IC 66 (step S219). The details of the management output process will be explained later.

[0124] Next, we will explain the configuration in the main CPU 63 for determining whether or not a gaming ball has entered the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, second operating port 34, and through gate 35 based on the detection results of each ball entry detection sensor 42a to 49a. Figure 9 is an explanatory diagram for explaining the configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0125] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so that it can handle eight types of signals simultaneously. An area in which information "0" or "1" is stored according to the voltage of each signal is provided in one-to-one correspondence with each terminal. That is, this area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals are input to the input port 63a, in order to limit the number of signals that can be input simultaneously to eight, the group of signals to be input to the input port 63a is switched through switching control by a driver IC.

[0126] In the ball entry detection process (step S209) of the timer interrupt process (FIG. 8), the signal group to be input to the input port 63a is set to the signal group from each ball entry detection sensor 42a-49a. In such a setting, the 0th bit D0 stores information corresponding to the detection signal from the first winning opening detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the second winning opening detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the third winning opening detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special power detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the first operating opening detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the second operating opening detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the outlet detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0127] Each of the ball entry detection sensors 42a-49a outputs a LOW-level signal indicating that it is not detecting a ball when it has not detected the passage of a game ball, and outputs a HI-level signal indicating that it is detecting a ball when it has detected the passage of a game ball. The input port 63a stores "0" in the corresponding bit when it receives a LOW-level signal, and stores "1" in the corresponding bit when it receives a HI-level signal. In other words, when the ball entry detection sensors 42a-49a have not detected the passage of a game ball, the corresponding bit stores "0" indicating that it is not detecting a game ball, and when it has detected the passage of a game ball, the corresponding bit stores "1" indicating that it is detecting a game ball.

[0128] FIG. 10 is a flowchart showing the ball scoring detection process executed in step S209 of the timer interrupt process (FIG. 8).

[0129] When it is confirmed that the 0th bit D0 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the first winning opening detection sensor 42a (step S301: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S302), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by 1 (step S303). The first output flag is a flag that specifies to the main CPU 63 that information indicating that one gaming ball has been detected by the first winning opening detection sensor 42a should be output to the management IC 66. The 10-prize ball counter is a counter that specifies to the main CPU 63 the number of times that 10 gaming balls should be paid out. If the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (Fig. 8), and when the 10 prize ball command is output once, the value of the 10 prize ball counter is decremented by 1. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0130] When it is confirmed that the first bit D1 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the second winning opening detection sensor 43a (step S304: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S305), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S306). The second output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the second winning opening detection sensor 43a should be output to the management IC 66.

[0131] When it is confirmed that the second bit D2 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the third winning opening detection sensor 44a (step S307: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S308), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S309). The third output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the third winning opening detection sensor 44a should be output to the management IC 66.

[0132] When it is confirmed that the third bit D3 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the special electric detection sensor 45a (step S310: YES). In this case, the special electric winning flag provided in the main RAM 65 is set to "1" (step S311), the fourth output flag provided in the main RAM 65 is set to "1" (step S312), and further, the value of the 15-ball counter provided in the main RAM 65 is incremented by 1 (step S313). The special electric winning flag is a flag that allows the main CPU 63 to identify that one game ball has entered the special electric winning device 32 during round play in the open / close execution mode. In the special chart special electric control process (step S213) of the timer interrupt process (Figure 8), by confirming that the special electric winning flag is set to "1," it is determined that one game ball has entered the special electric winning device 32, and the number of remaining balls that can enter the special electric winning device 32 in a round of play is subtracted by 1. When the process of subtracting 1 from the number of remaining balls that can enter is executed, the special electric winning flag is cleared to "0." The fourth output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the special electric detection sensor 45a should be output to the management IC 66. The 15-ball counter is a counter that specifies to the main CPU 63 the number of times that 15 game balls should be paid out. If the value of the 15 prize ball counter is 1 or more, a 15 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (Fig. 8), and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0133] When it is confirmed that the fourth bit D4 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the first actuation port detection sensor 46a (step S314: YES). In this case, the first actuation winning flag provided in the main RAM 65 is set to "1" (step S315), the fifth output flag provided in the main RAM 65 is set to "1" (step S316), and further the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S317). The first actuation winning flag is a flag for the main CPU 63 to identify that one gaming ball has entered the first actuation port 33. In the special power control process (step S213) of the timer interrupt process (FIG. 8), by confirming that the first activation winning flag is set to "1," a process is executed to store new reserved information, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power control process (step S213), it is confirmed that the first activation winning flag is set to "1," and when a process corresponding to that confirmation is executed, the first activation winning flag is cleared to "0." The fifth output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the first activation port detection sensor 46a should be output to the management IC 66. The single prize ball counter is a counter that specifies to the main CPU 63 the number of times one game ball should be paid out. If the value of the 1 prize ball counter is 1 or more, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (Fig. 8), and when the 1 prize ball command is output once, the value of the 1 prize ball counter is decremented by 1. When the payout control device 77 receives the 1 prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0134] When it is confirmed that the fifth bit D5 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the second actuation port detection sensor 47a (step S318: YES). In this case, the second actuation winning flag provided in the main RAM 65 is set to "1" (step S319), and the sixth output flag provided in the main RAM 65 is set to "1" (step S320), and further the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S321). The second actuation winning flag is a flag that allows the main CPU 63 to identify that one gaming ball has entered the second actuation port 34. In the special power control process (step S213) of the timer interrupt process (FIG. 8), by confirming that the second activation winning flag is set to "1," a process is executed to store new reserved information, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power control process (step S213), it is confirmed that the second activation winning flag is set to "1," and when a process corresponding to that confirmation is executed, the second activation winning flag is cleared to "0." The sixth output flag is a flag for specifying in the main CPU 63 that information indicating that one game ball has been detected by the second activation port detection sensor 47a should be output to the management IC 66.

[0135] When it is confirmed that the sixth bit D6 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the outlet detection sensor 48a (step S322: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S323). The seventh output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the outlet detection sensor 48a should be output to the management IC 66.

[0136] When it is confirmed that the seventh bit D7 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S324: YES). In this case, the gate winning flag provided in the main RAM 65 is set to "1" (step S325). The gate winning flag is a flag for the main CPU 63 to identify that one game ball has entered the through gate 35. In the normal map normal power control process (step S214) of the timer interrupt process (FIG. 8), by confirming that the gate winning flag is set to "1", the process is executed to store the current numerical information of the normal power device opening counter C4 as normal map side reserved information in the normal power reserve area 65c, provided that the number of normal map side reserved information stored in the normal power reserve area 65c is less than the upper limit number of 4. In the normal map normal power control process (step S214), it is confirmed that the gate winning flag is set to "1", and when the process corresponding to that confirmation is executed, the gate winning flag is cleared to "0".

[0137] As already explained, the timer interrupt process (FIG. 8) is started at a 4 msec cycle, so when one of the ball entry detection sensors 42a-49a starts detecting one game ball, the main CPU 63 determines that one game ball has been detected by the ball entry detection sensor 42a-49a while the ball entry detection sensor 42a-49a continues to detect that one game ball. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0138] Next, we will explain the processing executed by the dispensing control device 77. First, we will explain the electrical configuration of the dispensing control device 77 and various devices that communicate with the dispensing control device 77, with reference to the block diagram in Figure 11.

[0139] The dispensing control device 77 is equipped with an MPU 91. The MPU 91 includes a dispensing side CPU 92, which is a processing unit including a control unit and a calculation unit, as well as a dispensing side ROM 93, a dispensing side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, etc.

[0140] The dispensing ROM 93 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The dispensing ROM 93 stores various control programs and fixed value data executed by the dispensing CPU 92.

[0141] The dispensing-side RAM 94 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM and DRAM, and is used for both reading and writing. The dispensing-side RAM 94 is randomly accessible and takes less time to read data than the dispensing-side ROM 93 when compared for the same data capacity. The dispensing-side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing-side ROM 93.

[0142] The payout CPU 92 is capable of bidirectional communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout CPU 92 controls the operation of the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. The payout CPU 92 also monitors whether the payout device 76 is in a state where game balls can be paid out normally, and if it determines that the payout device 76 is in a state where game balls cannot be paid out normally, it stops the payout device 76 even if information on the number of unpaid prize balls is stored in the payout RAM 94. The payout CPU 92 also transmits a payout limit command to the main CPU 63 indicating that the payout device 76 is in a state where game balls cannot be paid out normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the audio / light-emitting control device 81 so that the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54 issue a notification indicating that the payout device 76 is in a state where game balls cannot be paid out normally. The states in which game balls cannot be dispensed normally include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been replenished with game balls, an abnormal dispense state in which the dispenser 76 does not operate normally, a main body open state in which the game machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

[0143] A full tank detection sensor (not shown) is provided midway along the game ball passageway leading from the payout device 76 to the lower tray 56a, and the detection result of the full tank detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

[0144] A no-ball detection sensor (not shown) is provided midway along the game ball passageway leading from tank 75 to payout device 76, and the detection result of the no-ball detection sensor is input to payout-side CPU 92. Payout-side CPU 92 determines that a no-ball state exists when the no-ball detection sensor continues to not detect a game ball, and determines that the no-ball state has been released when the state in which the no-ball detection sensor continues to not detect a game ball is released.

[0145] The payout device 76 is provided with a payout detection sensor (not shown) for detecting game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout side CPU 92. When a game ball is detected by the payout detection sensor, the payout side CPU 92 determines that one game ball has been paid out from the payout device 76. Furthermore, the payout side CPU 92 determines that an abnormal payout state exists when the payout detection sensor continues to not detect a game ball even though the payout device 76 is being driven and controlled so that a game ball is paid out, and determines that the abnormal payout state has been released when the state in which the payout detection sensor continues to not detect a game ball is released.

[0146] A front door open sensor 95 is provided on the front portion of the inner frame 13 (see FIG. 2), and the detection result of the front door open sensor 95 is input to the dispensing-side CPU 92. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing-side CPU 92, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that the front door frame 14 is closed when it receives a closed detection signal from the front door open sensor 95, and determines that the front door frame 14 is open when it receives an open detection signal from the front door open sensor 95. In addition, the dispensing-side CPU 92 transmits a front door open command to the main-side CPU 63 when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main-side CPU 63 when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

[0147] A main body open sensor 96 is provided on the front portion of the rear pack unit 15 (see FIG. 2), and the detection result of the main body open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the payout side CPU 92. When the payout side CPU 92 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when the payout side CPU 92 receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state. In addition, the payout side CPU 92 transmits a main body open command to the main side CPU 63 when it determines that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body close command to the main side CPU 63 when it determines that the gaming machine main body 12 has changed from an open state to a closed state. The main CPU 63 determines that the gaming machine main body 12 is in an open state when it receives a main body open command, and determines that the gaming machine main body 12 is in a closed state when it receives a main body close command.

[0148] The timer interrupt process executed by the dispensing CPU 92 will be described with reference to the time chart of Fig. 12. The timer interrupt process is repeatedly started at a predetermined cycle (for example, every 2 msec).

[0149] First, a full tank process is executed (step S401). In the full tank process, as already explained, it is determined whether the tank is full based on the detection result of the full tank detection sensor, and if the tank is full, it executes a process to stop the payout of game balls and sends a command indicating the full tank state to the main CPU 63. Furthermore, if the full tank state is released, it executes a process to enable the payout of game balls and sends a command indicating that the full tank state has been released to the main CPU 63.

[0150] Thereafter, no-ball processing is executed (step S402). In the no-ball processing, as already explained, it is determined whether or not the no-ball state is present based on the detection result of the no-ball detection sensor, and if the no-ball state is present, it executes processing to stop the payout of game balls and sends a command indicating the no-ball state to the main CPU 63. Furthermore, if the no-ball state is released, it executes processing to enable the payout of game balls and sends a command indicating that the no-ball state has been released to the main CPU 63.

[0151] Thereafter, a payout abnormality monitoring process is executed (step S403). In the payout abnormality monitoring process, as already explained, it is determined whether or not a payout abnormality state exists based on the detection result of the payout detection sensor, and if a payout abnormality state exists, a process to stop the payout of game balls is executed, and a command indicating that a payout abnormality state exists is sent to the main CPU 63. Furthermore, if the payout abnormality state is released, a process to enable the payout of game balls is executed, and a command indicating that the payout abnormality state has been released is sent to the main CPU 63.

[0152] Thereafter, a front door open monitoring process is executed (step S404). In the front door open monitoring process, as already explained, it is determined whether or not the front door frame 14 is in the open state based on the detection result of the front door open sensor 95, and if the front door frame 14 is in the open state, a process to stop the payout of game balls is executed and a front door open command is sent to the main CPU 63. Furthermore, if the front door frame 14 is closed, a process to enable the payout of game balls is executed and a front door close command is sent to the main CPU 63.

[0153] Thereafter, a main body open monitoring process is executed (step S405). In the main body open monitoring process, as already explained, it is determined whether or not the gaming machine main body 12 is in the open state based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is in the open state, a process to stop the payout of game balls is executed and a main body open command is sent to the main CPU 63. Furthermore, if the gaming machine main body 12 is closed, a process to enable the payout of game balls is executed and a main body close command is sent to the main CPU 63.

[0154] Then, a command read process is executed (step S406). In this command read process, a process is executed to read the prize ball command sent by the main CPU 63. Then, the prize ball command is stored in the payout RAM 94. Then, a prize ball setting process is executed to add the number corresponding to the received prize ball command to the unpaid prize ball number information in the payout RAM 94 (step S407), and then a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S408). In the payout control process, when the unpaid prize ball number information stored in the payout RAM 94 is a value of 1 or more, the payout device 76 is driven and controlled, and when the payout detection sensor detects one game ball, the value of the prize ball number information is decremented by 1. Then, when the value of the prize ball number information becomes "0," the drive control of the payout device 76 is stopped. Thereafter, an external information setting process is executed to control the start and end of output of an external signal according to the results of the various processes executed in this timer interrupt process (step S409).

[0155] Next, a configuration for externally outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall will be described.

[0156] As shown in Fig. 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with a large number of external terminals, some of which, i.e., a plurality of external terminals, are electrically connected to the main CPU 63, and some of which, i.e., a plurality of external terminals, are electrically connected to the dispensing CPU 92. In this way, the main CPU 63 and the dispensing CPU 92 are each electrically connected to the external terminal board 97, so that the main CPU 63 and the dispensing CPU 92 can externally output information to the hall computer HC, as shown in Fig. 11.

[0157] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and another external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the configuration of this electrical connection in detail, a signal relay board 98 is provided midway along the signal path from the front door open sensor 95 to the dispensing side CPU 92. The signal relay board 98 has a branch path SL2 branching from the signal path SL1 from the front door open sensor 95 to the dispensing side CPU 92. The branch path SL2 is connected to the front door open external terminal on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the dispensing side CPU 92, but also to the front door open external terminal on the external terminal board 97. This allows a signal indicating whether the front door frame 14 is open to be output to the hall computer HC without control by the dispensing side CPU 92.

[0158] Regarding the main body open sensor 96 in more detail, the signal relay board 98 is provided with a branch path SL4 that branches off from the signal path SL3 that runs from the main body open sensor 96 toward the payout CPU 92. The branch path SL4 is connected to an external terminal for main body open on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the main body open sensor 96 is not only input to the payout CPU 92, but also to the external terminal for main body open on the external terminal board 97. This makes it possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through control by the payout CPU 92.

[0159] Next, we will explain the content of the information externally output to the hall computer HC from the main CPU 63 and the payout CPU 92. First, we will explain the content of the information externally output from the main CPU 63 to the hall computer HC.

[0160] In the external information setting process (step S218) in the timer interrupt process (FIG. 8), the main CPU 63 performs setting for outputting information to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the opening / closing execution mode is in progress, information indicating that the support mode is in the high frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (for example, 100) of game balls have been discharged from the game area PA through any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, information indicating that a game ball has entered the first operating port 33, and information indicating that a game ball has entered the second operating port 34.

[0161] In the external information setting process (step S409) in the timer interrupt process (FIG. 12), the payout side CPU 92 sets the output of information to each external terminal assigned to the payout side CPU 92 on the external terminal board 97. The information output from the payout side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0162] The hall computer HC can grasp the manner in which game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, The payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10. - Ball payout rate in normal game mode, not in open / close execution mode or high frequency support mode (hereinafter, this ball payout rate will be referred to as "B") Ball payout rate in open / close execution mode - Ball payout rate in high frequency support mode The number of times a game is played until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S"). BS x "Number of winning balls for winning into the first actuation port 33 and the second actuation port 34" The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1") The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2") B-(S1 x "number of winning balls for winning into the first operating port 33" + S2 x "number of winning balls for winning into the second operating port 34") This allows the hall computer HC to manage the manner in which game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are paid out when one game ball enters the corresponding ball entry section.

[0163] <Configuration for managing winning status of gaming balls> Next, we will explain the configuration for managing the winning status of game balls using the management IC 66. First, we will explain the electrical configuration of the management IC 66 with reference to the block diagram of FIG.

[0164] As already explained, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 also includes an I / F 101 and a read terminal 102.

[0165] The I / F 101 is an interface for transmitting and receiving signals to and from devices external to the MPU 62. The I / F 101 is electrically connected to the main CPU 63 via an internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a-49a and commands from the dispensing CPU 92 are input to the MPU 62 through the input port of the I / F 101, and the main CPU 63 executes various processes based on the input detection results and command contents, as described above. Furthermore, when a signal is output to a device such as the special call driver 32b as a result of the execution of various processes by the main CPU 63, the signal is output through the output port of the I / F 101. Furthermore, when a command is output to the dispensing CPU 92 and the audio / light-emitting control device 81 as a result of the execution of various processes by the main CPU 63, the command is output through the output port of the I / F 101.

[0166] The reading terminal 102 is a terminal for electrically connecting the MPU 62 to a reading device, which is an external device of the pachinko machine 10, and is provided on the surface of the MPU 62 so that the connection terminal portion is exposed. However, as already explained, the main control board 61 on which the MPU 62 is mounted is housed in the board box 60a, and the reading terminal 102 faces the wall of the board box 60a so as not to be exposed to the outside of the main control device 60. Therefore, in order to electrically connect the reading device to the reading terminal 102, it is necessary to open the board box 60a to expose the MPU 62. This makes it possible to prevent unauthorized electrical connection of the reading device to the reading terminal 102. Note that this is not limited to this, and a configuration may also be adopted in which an opening is formed in the board box 60a to expose the reading terminal 102 to the outside of the main control device 60, and the reading device can be electrically connected to the reading terminal 102 without having to destroy the board box 60a.

[0167] The management IC 66 includes a management I / F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, and a history memory 117. These devices are connected to each other via an internal bus 66a provided in the management IC 66 so as to enable two-way communication.

[0168] The management side I / F 111 is an interface for receiving various signals from the main CPU 63 via a group of signal paths 118 for one-way communication built in the MPU 62, and for transmitting various signals to the reading terminal 102 via a group of signal paths 119 for one-way communication built in the MPU 62. Various signals from the main CPU 63 are input to an input port of the management side I / F 111, and various signals to the reading terminal 102 are output from an output port of the management side I / F 111. The main CPU 63 is electrically connected to the reading terminal 102 via a group of signal paths 120 for two-way communication built in the MPU 62.

[0169] The management CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., non-volatile storage means) such as a NOR flash memory or a NAND flash memory that does not require an external power supply to retain its memory, and is used as a read-only memory. The management ROM 113 stores various control programs executed by the management CPU 112 and fixed value data. The management RAM 114 is a memory (i.e., volatile storage means) such as an SRAM or a DRAM that requires an external power supply to retain its memory, and is used as a read / write memory. The management RAM 114 is randomly accessible, and when compared for the same data capacity, requires a faster read time than the management ROM 113. The management RAM 114 temporarily stores various data and the like in response to the execution of the control programs stored in the management ROM 113.

[0170] The RTC 115 is a real-time clock that constantly measures date and time information and is configured to be able to output the measured date and time information in accordance with instructions from the management CPU 112. The RTC 115 is equipped with a backup power supply, so that it can measure date and time information even when the power to the pachinko machine 10 is cut off.

[0171] The correspondence memory 116 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as an SRAM or DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a-122p provided in the input port 121 of the management side I / F 111 and the types of signals input to those buffers 122a-122p. The contents of the correspondence memory 116 will be described in detail later.

[0172] The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information regarding balls entering the game ball slot, which is received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be explained later.

[0173] Next, a description will be given of the configuration of the input port 121 provided in the management side I / F 111. Fig. 14 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111.

[0174] The input port 121 is provided with a plurality of buffers 122a to 122p. Specifically, first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can receive one type of signal via signal paths 118a to 118p, and each of the first to sixteenth buffers 122a to 122p stores information of "0" as first data when the signal to be input is at a LOW level, and stores information of "1" as second data when the signal to be input is at a HI level. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0175] A first signal corresponding to the detection result of the first winning opening detection sensor 42a is input to the first buffer 122a. In this case, the main CPU 63 outputs a LOW level first signal when the first winning opening detection sensor 42a does not detect a new gaming ball, and outputs a HI level first signal for a specific period when the first winning opening detection sensor 42a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level first signal has been input to the first buffer 122a.

[0176] A second signal corresponding to the detection result of the second winning opening detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a LOW level second signal when the second winning opening detection sensor 43a does not detect a new gaming ball, and outputs a HI level second signal for a specific period when the second winning opening detection sensor 43a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

[0177] A third signal corresponding to the detection result of the third winning opening detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a LOW level third signal when the third winning opening detection sensor 44a does not detect a new gaming ball, and outputs a HI level third signal for a specific period when the third winning opening detection sensor 44a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

[0178] A fourth signal corresponding to the detection result of the special electric charge detection sensor 45a is input to the fourth buffer 122d. In this case, the main CPU 63 outputs a LOW level fourth signal when the special electric charge detection sensor 45a has not detected a new gaming ball, and outputs a HI level fourth signal for a specific period when the special electric charge detection sensor 45a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

[0179] A fifth signal corresponding to the detection result of the first actuation port detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a LOW level fifth signal when the first actuation port detection sensor 46a does not detect a new gaming ball, and outputs a HI level fifth signal for a specific period when the first actuation port detection sensor 46a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

[0180] A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW-level sixth signal when the second actuation port detection sensor 47a does not detect a new gaming ball, and outputs a HI-level sixth signal for a specific period when the second actuation port detection sensor 47a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI-level sixth signal has been input to the sixth buffer 122f.

[0181] A seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g. In this case, the main CPU 63 outputs a LOW level seventh signal when the outlet detection sensor 48a does not detect a new gaming ball, and outputs a HI level seventh signal for a specific period when the outlet detection sensor 48a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0182] An eighth signal corresponding to whether or not the open / close execution mode is in progress is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs the eighth signal at a low level when the open / close execution mode is not in progress, and continuously outputs the eighth signal at a high level when the open / close execution mode is in progress.

[0183] A ninth signal corresponding to whether or not the high frequency support mode is in effect is input to the ninth buffer 122i. In this case, the primary CPU 63 continuously outputs a LOW level ninth signal when the high frequency support mode is not in effect, and continuously outputs a HI level ninth signal when the high frequency support mode is in effect.

[0184] A tenth signal corresponding to whether or not the front door frame 14 is open is input to the tenth buffer 122j. In this case, the main CPU 63 continuously outputs a low-level tenth signal when the front door frame 14 is closed, and continuously outputs a high-level tenth signal when the front door frame 14 is open.

[0185] An output instruction signal is input to the sixteenth buffer 122p to cause the management CPU 112 to recognize an opportunity to output history information stored in the history memory 117 to the reading terminal 102. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output history information, and outputs a HI level output instruction signal for a specific period when there is a need to output history information. This specific period is long enough for the management CPU 112 to determine that a HI level output instruction signal has been input to the sixteenth buffer 122p.

[0186] Although the eleventh buffer 122k, the twelfth buffer 122l, the thirteenth buffer 122m, the fourteenth buffer 122n, and the fifteenth buffer 122o can receive signals from the main CPU 63, they are blank buffers that do not receive normal signals in the present pachinko machine 10. In this way, by providing the input port 121 of the management I / F 111 with a greater number of buffers 122a-122p than the number of types of signals output from the main CPU 63 to the management IC 66 in the present pachinko machine 10, the management IC 66 can be used in models other than the present pachinko machine 10. This makes it possible to increase the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and the first to sixteenth buffers 122a to 122p so as to correspond one-to-one to the first to sixteenth buffers 122a to 122p, respectively, but this is not limited to this, and the signal paths 118k to 118o may not be formed between the main CPU 63 and the buffers 122k to 122o to be blanked.

[0187] It was determined at the design stage of the management IC 66 that an output instruction signal will be input to the 16th buffer 122p in the input port 121 of the management I / F 111, and the management CPU 112 can identify that an output instruction signal will be input to the 16th buffer 122p without receiving an instruction from the main CPU 63. On the other hand, the types of signals that will be input to the first to fifteenth buffers 122a to 122o were not determined at the design stage of the management IC 66, and the types of these signals are identified by the management CPU 112 upon receiving an instruction from the main CPU 63. The identification of the types of these signals by the management CPU 112 will be described in detail below, when control is started in the main CPU 63 and the management CPU 112 in response to the supply of operating power to the MPU 62, and a type identification command is sent from the main CPU 63 to the management CPU 112. In this case, the information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of various signals while operating power is being supplied, the information stored in the correspondence memory 116 is referenced.

[0188] 15 is an explanatory diagram for explaining the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to fifteenth correspondence areas 123a to 123o in one-to-one correspondence with the first to fifteenth buffers 122a to 122o provided in the input port 121 of the management side I / F 111.

[0189] The first correspondence area 123a stores information indicating that the signal input to the first buffer 122a is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the first buffer 122a. The first correspondence area 123a also stores information indicating that the signal is the general winning opening 31, as well as information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The second correspondence area 123b stores information indicating that the signal is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the second buffer 122b. The second correspondence area 123b also stores information indicating that the signal is the general winning opening 31, as well as information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The third correspondence area 123c stores information indicating that the signal input to the third buffer 122c is from the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the third buffer 122c. In addition to the information indicating that the signal is from the general winning opening 31, the third correspondence area 123c also stores information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31.

[0190] The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is the special electric winning device 32, as information for the management CPU 112 to identify the type of signal input to the fourth buffer 122d. The fourth correspondence area 123d also stores information indicating that the signal is the special electric winning device 32, as well as information on the number of game balls (15) that will be paid out when one game ball enters the special electric winning device 32. The fifth correspondence area 123e stores information indicating that the signal is the first actuation port 33, as information for the management CPU 112 to identify the type of signal input to the fifth buffer 122e. The fifth correspondence area 123e also stores information indicating that the signal is the first actuation port 33, as well as information on the number of game balls (1) that will be paid out when one game ball enters the first actuation port 33. The sixth correspondence area 123f stores information indicating that the signal input to the sixth buffer 122f is the second actuation port 34, as information for the management CPU 112 to identify the type of signal. The sixth correspondence area 123f also stores information indicating that the signal is the second actuation port 34, as well as information on the number of game balls (1) that will be paid out when one game ball enters the second actuation port 34. The seventh correspondence area 123g stores information indicating that the signal is the outlet 24a, as information for the management CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0191] The eighth correspondence area 123h stores information indicating the open / close execution mode as information for the management CPU 112 to identify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating the high frequency support mode as information for the management CPU 112 to identify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating the front door frame 14 as information for the management CPU 112 to identify the type of signal input to the tenth buffer 122j.

[0192] The eleventh correspondence area 123k stores information indicating a blank that does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the eleventh buffer 122k. The twelfth correspondence area 123l stores information indicating a blank that does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the twelfth buffer 122l. The thirteenth correspondence area 123m stores information indicating a blank that does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the thirteenth buffer 122m. The fourteenth correspondence area 123n stores information indicating a blank that does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the fourteenth buffer 122n. The fifteenth correspondence area 123o stores information indicating a blank that does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the fifteenth buffer 122o.

[0193] As described above, by configuring the management CPU 112 to specify what kind of signals are input to the first to fifteenth buffers 122a to 122o by receiving instructions from the main CPU 63, it becomes possible to use the management IC 66 for models other than this pachinko machine 10. This makes it possible to increase the versatility of the management IC 66.

[0194] Furthermore, instead of outputting information for recognizing the type of signal each time a signal corresponding to the storage of history information is output to the first to fifteenth buffers 122a to 122o, information for recognizing the type of signal is output in advance, and information for specifying the type of signal to be input to the first to fifteenth buffers 122a to 122o by the management CPU 112 based on the output information is stored in the correspondence memory 116. This makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration in which information for recognizing the type of signal is output each time a signal corresponding to the storage of history information is output to the first to fifteenth buffers 122a to 122o.

[0195] Furthermore, the information for specifying the types of signals input to the first to fifteenth buffers 122a to 122o by the management CPU 112 is output when the supply of operating power starts. This allows the management CPU 112 to specify the types of signals input to the first to fifteenth buffers 122a to 122o when a game is started in the pachinko machine 10.

[0196] Furthermore, the information that an output instruction signal is input to the 16th buffer 122p is set at the design stage of the management IC 66. This makes it possible to omit the process for identifying the type of signal input to the 16th buffer 122p for output instruction signals that are reliably used not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load of the process for identifying the type of such signal.

[0197] Next, a description will be given of the history memory 117 of the management IC 66. FIG.

[0198] The history memory 117 is provided with a history area 124 for sequentially storing history information. The history area 124 contains a plurality of pointer information items set with consecutive numbers, and a history information storage area 125 is set in one-to-one correspondence with each pointer information item. The history information storage area 125 can store a combination of RTC information and correspondence information. Each history information storage area 125 has a data capacity of 2 bytes, with 1 byte of data allocated as an area for storing RTC information and 1 byte of data allocated as an area for storing correspondence information. When it becomes necessary to store correspondence information in response to signals input to the first to fifteenth buffers 122a to 122o (actually, the first to tenth buffers 122a to 122j in this pachinko machine 10), the date information and time information currently measured by the RTC 115 are first stored in the area for storing RTC information in the history information storage area 125 corresponding to the pointer information currently being written. Thereafter, the correspondence information corresponding to the buffers 122a to 122o that triggered the current information storage is read from the correspondence areas 123a to 123o corresponding to the buffers 122a to 122o in the correspondence memory 116, and the read correspondence information is stored in an area for storing correspondence information in the history information storage area 125 that corresponds to the pointer information currently being written.

[0199] Specifically, regarding the correspondence information stored in the history information storage area 125, as already explained, signals corresponding to the detection results of the ball entry detection sensors 42a-48a are input to the first to seventh buffers 122a-122g, and therefore, information corresponding to the types of the ball entry detection sensors 42a-48a is stored in the first to seventh correspondence areas 123a-123g in the correspondence memory 116. More specifically, information corresponding to the types of ball entry sections corresponding to the ball entry detection sensors 42a-48a is stored in the first to seventh correspondence areas 123a-123g. As already explained, in this pachinko machine 10, the first to third prize entry opening detection sensors 42a-44a all detect game balls that have entered the general prize entry opening 31, and therefore, the first to third correspondence areas 123a-123c corresponding to these first to third prize entry opening detection sensors 42a-44a all store information indicating that it is the general prize entry opening 31. Further, the fourth correspondence area 123d stores information indicating that it is the special electric winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the outlet 24a. If the buffer 122a-122o that triggered the current information storage is any of the first to seventh buffers 122a-122g, information on the type of ball entry portion corresponding to that buffer 122a-122g is read from any of the first to seventh correspondence areas 123a-123g, and the read information on the type of ball entry portion is stored as is in the area for storing correspondence information in the history information storage area 125.

[0200] On the other hand, the eighth buffer 122h receives a signal indicating whether or not it is in the opening / closing execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in the high frequency support mode, and the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open. Therefore, the eighth correspondence area 123h stores information indicating the opening / closing execution mode, the ninth correspondence area 123i stores information indicating the high frequency support mode, and the tenth correspondence area 123j stores information indicating the front door frame 14.

[0201] As already explained, the main CPU 63 continuously outputs the eighth signal at a low level when the open / close execution mode is not in effect, and continuously outputs the eighth signal at a high level when the open / close execution mode is in effect. Therefore, the control CPU 112 can determine that the open / close execution mode has started when the eighth signal changes from a low level to a high level, and can determine that the open / close execution mode has ended when the eighth signal changes from a high level to a low level. When the eighth signal changes from a low level to a high level, or when it changes from a high level to a low level, the control CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the eighth signal changes from a low level to a high level, not only the information indicating the open / close execution mode read from the eighth correspondence area 123h but also the start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the eighth signal changes from HI level to LOW level, not only the information indicating the opening / closing execution mode read from the eighth correspondence area 123h but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

[0202] As already explained, the main CPU 63 continuously outputs the ninth signal at a low level when the high-frequency support mode is not active, and continuously outputs the ninth signal at a high level when the high-frequency support mode is active. This allows the management CPU 112 to determine that the high-frequency support mode has started when the ninth signal changes from a low level to a high level, and to determine that the high-frequency support mode has ended when the ninth signal changes from a high level to a low level. When the ninth signal changes from a low level to a high level, or when it changes from a high level to a low level, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from a low level to a high level, not only the information indicating the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the 9th signal changes from HI level to LOW level, not only the information indicating the high frequency support mode read from the 9th correspondence area 123i but also the termination information are stored in an area for storing correspondence information in the history information storage area 125.

[0203] As already explained, the main CPU 63 continuously outputs a LOW-level tenth signal when the front door frame 14 is closed, and continuously outputs a HI-level tenth signal when the front door frame 14 is open. Therefore, the management CPU 112 determines that the front door frame 14 is open when the tenth signal changes from a LOW level to a HI-level, and determines that the front door frame 14 is closed when the tenth signal changes from a HI-level to a LOW-level. When the tenth signal changes from a LOW level to a HI-level, or when it changes from a HI-level to a LOW-level, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the tenth signal changes from a LOW level to a HI-level, not only the information indicating the front door frame 14 read from the tenth correspondence area 123j but also the opening start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence relationship area 123j but also the opening completion information are stored in an area for storing correspondence relationship information in the history information storage area 125.

[0204] The history information storage area 125 is provided for a number of times that will enable storage of all the history information generated during ten consecutive business days, during which game balls are continuously shot in the pachinko machine 10 from opening to closing. For example, if history information is generated 60,000 times per day, more than 600,000 history information storage areas 125 will be provided. This makes it possible to store and hold all the history information for at least ten days in the history memory 117.

[0205] The history memory 117 is provided with a pointer area 126 separate from the history area 124. The pointer area 126 stores information that allows the management CPU 112 to identify the pointer information currently being written to in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, information specifying pointer information of "0" as the write target is set in the pointer area 126. Then, each time a new piece of history information is stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information is to be written and history information is stored in the history information storage area 125 corresponding to the last pointer information, the information in the pointer area 126 is updated so that pointer information of "0" is the write target. As a result, when a trigger occurs to store history information that exceeds the storable number of pieces of history information, the history information is overwritten with new history information, starting with the oldest history information stored in the history information storage area 125.

[0206] Furthermore, when the reading device reads history information from the history memory 117, the history information storage area 125 is cleared to all "0"s, and the information in the pointer area 126 is updated so that pointer information of "0" becomes the write target. This makes it possible to prevent history information that has once been read from becoming the read target again.

[0207] Next, a specific processing configuration for managing the winning status of gaming balls using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence between the first to fifteenth buffers 122a to 122o provided in the input port 121 of the management side I / F 111 and the signal types in the correspondence memory 116 will be described. Fig. 17 is a flowchart showing the recognition processing executed by the main side CPU 63. The recognition processing is executed in step S110 in the main processing (Fig. 7).

[0208] First, "15" is set in a recognition output counter provided in the main RAM 65 (step S501). The recognition output counter is a counter used by the main CPU 63 to identify the remaining number of times information output is required to make the management CPU 112 recognize which type of signal each of the buffers 122a to 122p of the input port 121 in the management I / F 111 corresponds to. As already explained, the 15 buffers, the 1st to 15th buffers 122a to 122o, are the targets for signal type recognition, so "15" is set in the recognition output counter.

[0209] Thereafter, an output process of an identification start command is executed (step S502). The primary CPU 63 outputs various commands to the management CPU 112 to make the management CPU 112 recognize which types of signals the first to fifteenth buffers 122a to 122o correspond to. When outputting these commands, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 to store history information are used to output commands to make the management CPU 112 recognize which types of signals the first to fifteenth buffers 122a to 122o correspond to. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which a signal path for outputting the commands is provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Furthermore, in the output process of the identification start command, the output state of the ninth signal is switched to HI level at the timing when the output of the identification start command is started so that the management CPU 112 recognizes that a new command has been sent. Furthermore, the output period of the identification start command and the period during which the output state of the ninth signal is maintained at HI level are set to be long enough for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. Upon receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the first to fifteenth buffers 122a to 122o and the signal types in the correspondence memory 116.

[0210] Thereafter, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S503). In this case, the first buffer 122a is the first to be set as the signal type, and thereafter, the signal type recognition setting corresponding to the first to fifteenth buffers 122a to 122o is performed so that the signal type is set for the nth buffer and then the (n+1)th buffer. Therefore, if the recognition output counter is "15" to "13", a type identification command indicating that it is the general winning port 31 and the number of prize balls is read out; if the recognition output counter is "12", a type identification command indicating that it is the special winning device 32 and the number of prize balls is read out; if the recognition output counter is "11", a type identification command indicating that it is the first operating port 33 and the number of prize balls is read out; if the recognition output counter is "10", a type identification command indicating that it is the second operating port 34 and the number of prize balls is read out; if the recognition output counter is "9", a type identification command indicating that it is the outlet 24a is read out; if the recognition output counter is "8", a type identification command indicating that it is in the opening / closing execution mode is read out; if the recognition output counter is "7", a type identification command indicating that it is in the high frequency support mode is read out; if the recognition output counter is "6", a type identification command indicating that it is the front door frame 14 is read out; and if the recognition output counter is "5" to "1", a type identification command indicating that it is blank is read out.

[0211] Thereafter, the control unit 112 executes an output process of the read type identification command (step S504). The type identification command, like the identification start command, has an 8-bit data capacity, and each bit of data is input as the first to eighth signals to the first to eighth buffers 122a to 122h, respectively. In the output process of the identification type command, the control unit 112 switches the output state of the ninth signal to a high level at the timing when output of the identification type command starts to allow the control unit CPU 112 to recognize that a new command has been sent. The output period of the identification type command and the period during which the output state of the ninth signal is maintained at a high level are set to a period sufficient for the control unit CPU 112 to recognize the identification type command and the output state of the ninth signal. Upon receiving the identification type command, the control unit CPU 112 stores information corresponding to the identification type command in the correspondence areas 123a to 123o corresponding to the buffer currently being set among the first to fifteenth buffers 122a to 122o.

[0212] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S505), and it is determined whether the value of the recognition output counter after decrementing by 1 is "0" (step S506). If the value of the recognition output counter is 1 or more (step S506: NO), processing is executed to output a type identification command corresponding to the value of the recognition output counter after decrementing by 1 (steps S503 and S504).

[0213] On the other hand, if the value of the recognition output counter is "0" (step S506: YES), an identification end command output process is executed (step S507). The identification end command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the identification end command output process, the output state of the ninth signal is switched to HI level at the timing when output of the identification end command is started so that the management CPU 112 recognizes that a new command has been transmitted. In addition, the output period of the identification end command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identification end command and the output state of the ninth signal. By receiving the identification end command, the management CPU 112 determines that the process of storing information on the correspondence between the first to fifteenth buffers 122a to 122o and the signal types in the correspondence memory 116 has been completed.

[0214] Next, the management processing executed by the management CPU 112 will be described with reference to the flowchart in Fig. 18. The management processing is started when the supply of operating power to the management CPU 112 is started. The processing speed of the management CPU 112 is configured to be faster than the processing speed of the main CPU 63, and the combination of processing from step S606 onwards in the management processing is executed 16 or more times from the time one timer interrupt processing (Fig. 8) is started in the main CPU 63 until the next timer interrupt processing (Fig. 8) is started.

[0215] When an identification start command is received from the main CPU 63 (step S601: YES), the value of a setting target counter provided in the control RAM 114 is cleared to "0" (step S602). The setting target counter is a counter that allows the control CPU 112 to identify the types of buffers 122a to 122o for which a signal type is to be set. The first buffer 122a is the first to be set as a signal type, and thereafter the nth buffer and then the (n+1)th buffer are set as signal type settings.

[0216] Thereafter, on the condition that a type identification command has been received from the main CPU 63 (step S603: YES), a correspondence setting process is executed (step S604). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter in the control RAM 114, among the first to fifteenth correspondence areas 123a to 123o of the correspondence memory 116. Thereafter, the value of the setting target counter in the control RAM 114 is incremented by 1 (step S605).

[0217] If a negative determination is made in step S603, or if the processing of step S605 is executed, it is determined (step S606) whether or not an identification end command has been received from the main CPU 63. If an identification end command has not been received (step S606: NO), the process returns to step S603, and the processing of steps S604 and S605 is executed again on the condition that a new type identification command is received from the main CPU 63 (step S603: YES).

[0218] If an identification end command has been received from the main CPU 63 (step S606: YES), the processes of steps S607 and S608 are repeatedly executed. In step S607, details of which will be described later, a history setting process is executed to store history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S608, details of which will be described later, an external output process is executed to output the history information stored in the history memory 117 to the reading terminal 102.

[0219] Fig. 19 is a time chart showing how information on the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o is stored in the correspondence memory 116. Fig. 19(a) shows a period during which commands are output from the main CPU 63 to the control CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Fig. 19(b) shows a period during which the output state of the ninth signal is at HI level, Fig. 19(c) shows an execution period of an identification state during which processing is executed to identify the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o, and Fig. 19(d) shows the timing at which the correspondence setting process (step S604) is executed by the control CPU 112.

[0220] When the supply of operating power to the primary CPU 63 and the control CPU 112 begins, output of the identification start command using the first to eighth signals begins at time t1, as shown in FIG. 19(a). Also, at time t1, the output state of the ninth signal changes from low to high, as shown in FIG. 19(b). Thereafter, at time t2, while the output of the identification start command is continuing, the output state of the ninth signal changes from high to low, as shown in FIG. 19(b). The control CPU 112 determines that a command has been sent from the primary CPU 63 by confirming that the output state of the ninth signal has changed from high to low, and determines the content of the command received from the primary CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification start command has been received, the control CPU 112 makes a positive determination in step S601 of the control process (FIG. 18) and enters the identification state. Then, at time t3, output of the identification start command is stopped, as shown in FIG. 19(a).

[0221] Then, at timing t4, as shown in FIG. 19(a), output of the first type identification command using signals 1 to 8 begins. Also, at timing t4, as shown in FIG. 19(b), the output state of signal 9 changes from LOW to HI at timing t4. Then, at timing t5, while the type identification command continues to be output, the output state of signal 9 changes from HI to LOW at timing t5, as shown in FIG. 19(b). The management CPU 112 determines that a command has been sent from the main CPU 63 by confirming that the output state of signal 9 has changed from HI to LOW, and identifies the content of the command received from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command has been received, the management CPU 112 executes a correspondence setting process at timing t5, as shown in FIG. 19(d). In this correspondence setting process, information indicating the general winning slot 31 and the number of prize balls therein are stored in the first correspondence area 123a of the correspondence memory 116. After that, at timing t6, the output of the type identification command is stopped as shown in FIG. 19(a).

[0222] Thereafter, from timing t7 to timing t9, from timing t10 ​​to timing t12, from timing t13 to timing t15, and from timing t16 to timing t18, similar to timing t4 to timing t6, the correspondence setting process corresponding to the type identification command output from the main CPU 63 is executed by the management CPU 112. In this case, from timing t16 to timing t18, the correspondence setting process corresponding to the 15th type identification command is completed.

[0223] Then, at timing t19, output of the identification end command using the first to eighth signals is started as shown in FIG. 19(a). Also, at timing t19, the output state of the ninth signal is changed from low to high as shown in FIG. 19(b). Then, at timing t20, while the output of the identification end command is continuing, the output state of the ninth signal is changed from high to low as shown in FIG. 19(b). The control side CPU 112 determines that a command has been sent from the primary side CPU 63 by confirming that the output state of the ninth signal has changed from high to low, and determines the content of the command received from the primary side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification end command has been received, the identification state of the control side CPU 112 ends at timing t20 as shown in FIG. 19(c). Then, at timing t21, output of the identification end command is stopped as shown in FIG. 19(a).

[0224] As described above, the configuration allows the management CPU 112 to recognize whether a command is being output using the 9th signal, so that the management CPU 112 can clearly recognize that a command is being output even when the command is output using the 1st to 8th signals (i.e., the 1st to 8th signal paths) used to instruct the management CPU 112 when to store history information.

[0225] Next, a description will be given of a processing configuration for storing history information in the history memory 117. Fig. 20 is a flowchart showing the management output processing executed by the main CPU 63. The management output processing is executed in step S219 in the timer interrupt processing (Fig. 8).

[0226] First, "10" is set to the management target counter provided in the main RAM 65 (step S701). The management target counter is a counter that allows the main CPU 63 to determine whether there are any management targets that have not been identified as targets for determining whether or not the signal output status to the management CPU 112 should be changed in this management output process, and to identify which management targets the signal output status to the management CPU 112 should be changed for. In one management output process, the management targets for which the main CPU 63 identifies whether or not the signal output status to the management CPU 112 should be changed are the seven ball entry detection sensors 42a-48a, whether or not the open / close execution mode is being executed, whether or not the high frequency support mode is being executed, and whether or not the front door frame 14 is open / closed, a total of 10 targets. Therefore, the management target counter is initially set to "10".

[0227] Then, it is determined whether the signal output state to the management side CPU 112 for the management object corresponding to the current value of the management object counter is at HI level (step S702). If it is not at HI level (step S702: NO), it is determined whether the value of the management object counter is 4 or more, thereby identifying which of the seven ball entry detection sensors 42a to 48a is the management object corresponding to the value of the management object counter (step S703).

[0228] If the determination in step S703 is affirmative, it is determined whether or not "1" is set in the output flag of the main RAM 65 corresponding to the value of the managed counter (step S704). Specifically, if the value of the managed counter is "10" and corresponds to the first winning opening detection sensor 42a, it is determined whether or not "1" is set in the first output flag, if the value of the managed counter is "9" and corresponds to the second winning opening detection sensor 43a, it is determined whether or not "1" is set in the second output flag, if the value of the managed counter is "8" and corresponds to the third winning opening detection sensor 44a, it is determined whether or not "1" is set in the third output flag, if the value of the managed counter is "7" and corresponds to the special power detection sensor 45a If the value of the managed counter is "6" and corresponds to the first actuation port detection sensor 46a, it determines whether the fifth output flag is set to "1" or not; if the value of the managed counter is "5" and corresponds to the second actuation port detection sensor 47a, it determines whether the sixth output flag is set to "1" or not; and if the value of the managed counter is "4" and corresponds to the outlet 24a, it determines whether the seventh output flag is set to "1" or not. As already explained, these first to seventh output flags are set to "1" in the ball entry detection process (Figure 10).

[0229] If the output flag corresponding to the value of the managed counter is set to "1" (step S704: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HI level (step S705), and then the output flag corresponding to the value of the managed counter is cleared to "0" (step S706).

[0230] If a negative determination is made in step S703, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed counter to HI level (step S707). Specifically, if the value of the managed counter is "3", it is determined whether a transition to the open / close execution mode has occurred, if the value of the managed counter is "2", it is determined whether a transition to the high frequency support mode has occurred, and if the value of the managed counter is "1", it is determined whether the front door frame 14 has entered the open state. If a positive determination is made in step S707, the output state of the signal corresponding to the value of the managed counter is set to HI level (step S708).

[0231] If the determination in step S702 is affirmative, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to a low level (step S709). Specifically, if the value of the counter to be managed is 4 or greater and the current managed object is one of the ball entry detection sensors 42a-48a, it is determined whether a HI output duration (specifically, 10 msec) has elapsed since the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals was switched from a low level to a high level. This HI output duration is set in the management-side CPU 112 to a period longer than the longest processing interval of the history setting process (step S607) of the management process (FIG. 18), and is a period that allows the management-side CPU 112 to reliably identify the output state of the signal that switched from a low level to a high level. Furthermore, if the value of the management target counter is "3" and the current management target is in the open / close execution mode, it is determined whether the open / close execution mode has ended, if the value of the management target counter is "2" and the current management target is in the high-frequency support mode, it is determined whether the high-frequency support mode has ended, and if the value of the management target counter is "1" and the current management target is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. If an opportunity has occurred to switch the output state of the signal corresponding to the value of the management target counter to a LOW level (step S709: YES), the output state of the signal corresponding to the value of the management target counter is set to a LOW level (step S710).

[0232] If a negative determination is made in step S704, if the processing of step S706 is executed, if a negative determination is made in step S707, if the processing of step S708 is executed, if a negative determination is made in step S709, or if the processing of step S710 is executed, the value of the managed object counter in the main RAM 65 is decremented by 1 (step S711). Then, it is determined whether the value of the managed object counter after the decrement by 1 is "0" (step S712). If the value of the managed object counter is 1 or greater (step S712: NO), the processing from step S702 onwards is executed for the managed object corresponding to the new value of the managed object counter.

[0233] Next, the history setting process executed by the management-side CPU 112 will be described with reference to the flowchart of Fig. 21. The history setting process is executed in step S607 of the management process (Fig. 18).

[0234] First, the number of buffers to be checked by the management CPU 112 among the first to fifteenth buffers 122a to 122o is set in a confirmation target counter provided in the management RAM 114 (step S801). Specifically, the number of correspondence relationship areas in which information other than information indicating that the correspondence relationship areas are blank is identified among the first to fifteenth correspondence relationship areas 123a to 123o in the correspondence relationship memory 116 is stored, and the information of the identified number is set in the confirmation target counter. As already explained, in this pachinko machine 10, information other than information indicating that the correspondence relationship areas are blank is stored in the first to tenth correspondence relationship areas 123a to 123j, and therefore, in step S801, "10" is set in the confirmation target counter.

[0235] Thereafter, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current value of the counter to be checked, among the first to fifteenth buffers 122a to 122o, has been switched from LOW to HIGH (step S802) by checking whether the numerical information stored in that buffer has changed from "0" to "1." Note that if the value of the counter to be checked is "n," the nth buffers 122a to 122o are the target for checking the numerical information. For example, if the value of the counter to be checked is "10," the tenth buffer 122j is the target for checking the numerical information, and if the value of the counter to be checked is "5," the fifth buffer 122e is the target for checking the numerical information.

[0236] If the determination in step S802 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S803). Then, a write process to the history memory 117 is executed (step S804). In this write process, the pointer information in the history area 124 currently being written is identified by referencing the pointer area 126 of the history memory 117, and the RTC information read in step S803 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written. Furthermore, correspondence information is read from the correspondence areas 123a to 123o corresponding to the current counter value to be checked, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information being written. Furthermore, if the correspondence information is any of information indicating the open / close execution mode, information indicating the high-frequency support mode, and information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information being written. If the value of the counter to be checked is "n," the n-th correspondence area 123a to 123o is the target for reading the correspondence information. For example, if the value of the counter to be checked is "10," the tenth correspondence area 123j is the target for reading the correspondence information, and if the value of the counter to be checked is "5," the fifth correspondence area 123e is the target for reading the correspondence information.

[0237] By executing the write process as described above, if the value of the counter to be checked is any of the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34, the history information storage area 125 corresponding to the pointer information to be written stores as history information a combination of RTC information and correspondence information indicating that it is any of the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34. Also, if the value of the counter to be checked is any of the opening / closing execution mode, high frequency support mode, and front door frame 14, the history information storage area 125 corresponding to the pointer information to be written stores as history information a combination of RTC information, correspondence information indicating that it is any of the opening / closing execution mode, high frequency support mode, and front door frame 14, and start information.

[0238] Thereafter, the target pointer is updated (step S805). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after incrementing by one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

[0239] If a negative determination is made in step S802, or if the processing of step S805 is executed, it is determined whether or not correspondence information for which it should be confirmed whether the signal output has been switched to a LOW level is stored in the correspondence areas 123a to 123o corresponding to the current value of the counter to be confirmed (step S806). Specifically, if the current value of the counter to be confirmed is "8" to "10", any of information indicating the opening / closing execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14 is stored in the corresponding correspondence areas 123h to 123j, and therefore a positive determination is made in step S806.

[0240] If the determination in step S806 is affirmative, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current counter value to be checked among the first to fifteenth buffers 122a to 122o has been switched from HI level to LOW level by checking whether the numerical information stored in that buffer has changed from "1" to "0" (step S807). If the determination in step S807 is affirmative, RTC information is read (step S808) as in step S803, and a write process to the history memory 117 is executed (step S809). In this write process, the RTC information read in step S808 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, correspondence information is read from the correspondence areas 123a to 123o corresponding to the current counter value to be checked, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. In addition, not only the correspondence information but also the termination information is written to the history information storage area 125 corresponding to the pointer information to be written. By executing the write process in this manner, when the value of the counter to be checked is either the open / close execution mode, the high frequency support mode, or the front door frame 14, a combination of the RTC information, the correspondence information indicating either the open / close execution mode, the high frequency support mode, or the front door frame 14, and the termination information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Thereafter, the target pointer update process is executed in the same manner as in step S805 (step S810).

[0241] If a negative determination is made in step S806, if a negative determination is made in step S807, or if the processing of step S810 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S811). Then, it is determined whether the value of the confirmation target counter after decrementing by 1 is "0" (step S812). If the value of the confirmation target counter is 1 or greater (step S812: NO), the processing of step S802 and subsequent steps is executed for the confirmation target corresponding to the new value of the confirmation target counter.

[0242] Next, the manner in which history information is stored in history memory 117 will be described with reference to the time chart of Fig. 22. Fig. 22(a) shows a period in which a HI level signal is input to any of the first to seventh buffers 122a to 122g, Fig. 22(b) shows a period in which a HI level signal is input to the eighth buffer 122h, Fig. 22(c) shows a period in which a HI level signal is input to the ninth buffer 122i, Fig. 22(d) shows a period in which a HI level signal is input to the tenth buffer 122j, and Fig. 22(e) shows the timing of writing history information to history memory 117.

[0243] At time t1, the output state of a signal input to one of the first to seventh buffers 122a to 122g is switched from LOW to HI at time t1, as shown in FIG. 22(a). Therefore, at time t1, history information is written to history memory 117, as shown in FIG. 22(e). Thereafter, at time t2, the signal that was switched to HI at time t1, as shown in FIG. 22(a), is switched to LOW at time t2. However, since this signal is input to one of the first to seventh buffers 122a to 122g and the switching to LOW does not result in history information being stored, writing of history information is not executed at time t2, as shown in FIG. 22(e).

[0244] Thereafter, at times t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to any of the first to seventh buffers 122a to 122g is switched from LOW level to HIGH level, as shown in Fig. 22(a). Therefore, at each of these times, history information is written as shown in Fig. 22(e).

[0245] As shown in FIG. 22(b), the output state of the signal input to the eighth buffer 122h is HI level from time t4 to time t7. This eighth buffer 122h corresponds to whether or not the open / close execution mode is occurring. Therefore, as shown in FIG. 22(e), history information is written at time t4, when the output state of the signal input to the eighth buffer 122h switches to HI level, and at time t7, when the output state of the signal switches to LOW level. In this case, the history information written at time t4 includes start information, and the history information written at time t7 includes end information. This makes it possible to determine the execution period of the open / close execution mode by checking the history information in the history memory 117.

[0246] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is during the opening / closing execution mode. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is during the opening / closing execution mode by comparing the RTC information.

[0247] As shown in FIG. 22(c), the output state of the signal input to the ninth buffer 122i is HI level from time t8 to time t11. This ninth buffer 122i corresponds to whether or not the high frequency support mode is active. Therefore, as shown in FIG. 22(e), history information is written at time t8, when the output state of the signal input to the ninth buffer 122i switches to HI level, and at time t11, when the output state of the signal switches to LOW level. In this case, the history information written at time t8 includes start information, and the history information written at time t11 includes end information. This makes it possible to determine the execution period of the high frequency support mode by checking the history information in the history memory 117.

[0248] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 is from the high frequency support mode. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 is from the high frequency support mode by comparing the RTC information.

[0249] As shown in FIG. 22(d), the output state of the signal input to the tenth buffer 122j is HI level from time t12 to time t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in FIG. 22(e), history information is written at time t12, when the output state of the signal input to the tenth buffer 122j switches to HI level, and at time t15, when the output state of the signal switches to LOW level. In this case, the history information written at time t12 includes start information, and the history information written at time t15 includes end information. This makes it possible to determine the period during which the front door frame 14 is open by checking the history information in the history memory 117.

[0250] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open by comparing the RTC information.

[0251] Next, a description will be given of a processing configuration for outputting history information stored in the history memory 117 to a reading device electrically connected to the reading terminal 102 of the MPU 62. Fig. 23 is a flowchart showing the data output processing executed by the main CPU 63. The data output processing is executed in step S111 of the main processing (Fig. 7).

[0252] In the data output process, first, it is determined whether or not a connection signal indicating that the reading device is electrically connected to the reading terminal 102 has been received from the reading terminal 102 (step S901). The reading device is configured to output a connection signal when electrically connected to the reading terminal 102, and if the connection signal has been received through the reading terminal 102, a positive determination is made in step S901.

[0253] If a negative determination is made in step S901, the data output process is terminated. In this case, the supply of operating power to the MPU 62 must be restarted in order for the data output process to be executed. Therefore, in order for the history information to be output externally, the supply of operating power to the MPU 62 must be started with a reading device electrically connected to the reading terminal 102. A power control unit for stopping and starting the supply of operating power to the MPU 62 is provided on the back of the back pack unit 15. Therefore, in order to perform these stopping and starting operations, the gaming machine main body 12 must be opened relative to the outer frame 11 to expose the back of the back pack unit 15. Under these circumstances, by configuring the system so that the supply of operating power to the MPU 62 must be started with a reading device electrically connected to the reading terminal 102 in order for the history information to be output externally, it becomes difficult for anyone other than the gaming hall manager to read the history information.

[0254] If the determination in step S901 is affirmative, the process determines whether a control information confirmation signal has been received from the read terminal 102, thereby determining whether the current connection of the reading device to the read terminal 102 corresponds to confirmation of the control information (programs and data) in the main ROM 64 (step S902). The reading device is configured to be able to confirm both the control information and the history information. If control information confirmation is selected by manual operation of the reading device, the reading device transmits a control information confirmation signal. If history information confirmation is selected by manual operation of the reading device, the reading device transmits a history confirmation signal. Note that this is not limited to this, and a reading device for control information confirmation and a reading device for history confirmation may be separate. In this case, if a reading device for control information confirmation is electrically connected to the read terminal 102, the reading device transmits a control information confirmation signal. If a reading device for history confirmation is electrically connected to the read terminal 102, the reading device transmits a history confirmation signal.

[0255] If the determination in step S902 is affirmative, an output process for confirming the control information is executed (step S903). In this output process, a program and data are read from the main ROM 64 as control information, and the read control information is output to the read terminal 102. This makes it possible to read the control information in a reading device electrically connected to the read terminal 102, and to confirm whether the control information is authentic or normal.

[0256] If a negative determination is made in step S902, an output instruction signal is sent to the management CPU 112 (step S904). Specifically, the output state of the output instruction signal is switched from a low level to a high level. This high level output state continues for a specific period of time. This specific period is long enough for the management CPU 112 to determine that a high level output instruction signal has been input to the sixteenth buffer 122p. When the output state of the output instruction signal is switched to a high level, processing for outputting history information is executed in the management CPU 112. This processing will be described in detail later.

[0257] When the process of step S903 is executed or when the process of step S904 is executed, it is determined whether the electrical connection of the reading device to the reading terminal 102 continues (step S905). If it continues (step S905: YES), the process waits in step S905. This makes it possible to prevent a process set in the execution order after the data output process from being executed until the electrical connection of the reading device to the reading terminal 102 is released. When the electrical connection of the reading device to the reading terminal 102 is released (step S905: NO), the data output process is terminated.

[0258] Next, the external output process executed by the management-side CPU 112 will be described with reference to the flowchart of Fig. 24. The external output process is executed in step S608 of the management process (Fig. 18).

[0259] When the output state of the output instruction signal received from the main CPU 63 is switched from LOW level to HI level (step S1001: YES), processing for outputting history information from step S1002 onwards is executed. Specifically, first, the number of history information storage areas 125 in which correspondence relationship information indicating the outlet 24a is stored in the history area 124 of the history memory 117 is counted to calculate the number of balls that have entered the outlet 24a (step S1002). In addition, the number of history information storage areas 125 in which correspondence relationship information indicating the general winning port 31 is stored in the history area 124 of the history memory 117 is counted to calculate the number of balls that have entered the general winning port 31 (step S1003). In addition, the number of history information storage areas 125 in which correspondence relationship information indicating the special winning device 32 is stored in the history area 124 of the history memory 117 is counted to calculate the number of balls that have entered the special winning device 32 (step S1004). The number of balls that have entered the first operating port 33 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the first operating port 33 is stored in the history area 124 of the history memory 117 (step S1005). The number of balls that have entered the second operating port 34 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the second operating port 34 is stored in the history area 124 of the history memory 117 (step S1006).

[0260] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating that it is the front door frame 14 in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating that it is the front door frame 14, the number of balls that entered each of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state is calculated (step S1007). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating that it is the front door frame 14 in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating that it is the front door frame 14 is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire consecutive pointer information, if there are multiple sections between the history information storage area 125 in which correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which correspondence information and end information indicating that it is the front door frame 14 are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which correspondence information and start information indicating that it is the front door frame 14 are stored, but the history information storage area 125 in which RTC information corresponding to a time later than that history information storage area 125 is stored does not store correspondence information and start information indicating that it is the front door frame 14, all of the history information in the history information storage area 125 in which RTC information corresponding to a time later than that of the history information storage area 125 in which correspondence information and start information indicating that it is the front door frame 14 is stored is treated as if the front door frame 14 is in an open state.

[0261] After that, various parameters are calculated using the calculation results of steps S1002 to S1007 (step S1008). Specifically, first, the number of balls that entered the room while the front door frame 14 was open, calculated in step S1007, is subtracted from the number of balls that entered the room calculated in steps S1002 to S1006. Then, the following parameters are calculated using the number of balls entered after this subtraction: The difference between the number of balls entering the out port 24a calculated in step S1007 and the number of balls entering the port calculated in step S1002 is designated as the number of balls entering the port K1, the difference between the number of balls entering the general winning port 31 calculated in step S1007 and the number of balls entering the port S1003 is designated as the number of balls entering the port K2, the difference between the number of balls entering the special electric winning device 32 calculated in step S1007 and the number of balls entering the port S1004 is designated as the number of balls entering the port K3, the difference between the number of balls entering the first operating port 33 calculated in step S1007 and the number of balls entering the port S1005 is designated as the number of balls entering the port K4, and the difference between the number of balls entering the second operating port 34 calculated in step S1007 and the number of balls entering the port S1006 is designated as the number of balls entering the port K5. First parameter: Total number of game balls dispensed (K2 x "Number of prize balls for winning at the general winning port 31" + K3 x "Number of prize balls for winning at the special winning device 32" + K4 x "Number of prize balls for winning at the first operating port 33" + K5 x "Number of prize balls for winning at the second operating port 34") / Ratio of the total number of game balls dispensed from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D1"). Second parameter: The ratio of the total number of game balls entering the general winning slot 31 (K2) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) Third parameter: The ratio of the total number of game balls entering the special winning device 32 (K3) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) Fourth parameter: The ratio of the total number of game balls entering the first operating port 33 (K4) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D2") Fifth parameter: The ratio of the total number of game balls entering the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D3") Sixth parameter: D1 - (D2 x "Number of winning balls for winning into the first operating port 33" + D3 x "Number of winning balls for winning into the second operating port 34") Seventh parameter: (K3 × "Number of prize balls for winning at the special electric winning device 32" + K5 × "Number of prize balls for winning at the second operating port 34") / Total number of game balls paid out (K2 × "Number of prize balls for winning at the general winning port 31" + K3 × "Number of prize balls for winning at the special electric winning device 32" + K4 × "Number of prize balls for winning at the first operating port 33" + K5 × "Number of prize balls for winning at the second operating port 34") ratio Eighth parameter: K3 × "Number of prize balls for winning the special electric winning device 32" / Total number of game balls paid out (K2 × "Number of prize balls for winning the general winning port 31" + K3 × "Number of prize balls for winning the special electric winning device 32" + K4 × "Number of prize balls for winning the first operating port 33" + K5 × "Number of prize balls for winning the second operating port 34") ratio Thereafter, the oldest RTC information and the newest RTC information in the history area 124 of the history memory 117 are used to calculate the total time required for all of the history information currently being calculated to be extracted (step S1009). Then, a first output process is executed (step S1010). In the first output process, all of the history information stored in the history area 124 of the history memory 117 is sequentially output to the reading terminal 102. Furthermore, the various parameters calculated in step S1008 are sequentially output to the reading terminal 102, and the total time calculated in step S1009 is output to the reading terminal 102. As a result, the information to be output in the first output process is read by a reading device electrically connected to the reading terminal 102.

[0262] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the opening and closing execution mode, the number of balls entering each of the outlet 24a, the general winning port 31, the special power winning device 32, the first operating port 33, and the second operating port 34 that occurred in the opening and closing execution mode is calculated (step S1011). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the opening and closing execution mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections within the entire set of consecutive pointer information between history information storage area 125 storing correspondence relationship information and start information indicating the opening and closing execution mode and history information storage area 125 storing correspondence relationship information and end information indicating the opening and closing execution mode, the total number of balls entered for each section is calculated. Furthermore, if there is a history information storage area 125 storing correspondence relationship information and start information indicating the opening and closing execution mode, but the history information storage area 125 storing RTC information corresponding to a time later than that of the history information storage area 125 does not store correspondence relationship information and start information indicating the opening and closing execution mode, all history information in history information storage area 125 storing RTC information corresponding to a time later than that of the history information storage area 125 storing correspondence relationship information and start information indicating the opening and closing execution mode is treated as being in the opening and closing execution mode.

[0263] Thereafter, the number of balls that entered each of the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state during the period of the opening / closing execution mode specified in step S1011 is calculated (step S1012). The method for calculating these numbers of balls is the same as in step S1007, except that it is based on the period of the opening / closing execution mode specified in step S1011.

[0264] Thereafter, various parameters are calculated using the calculation results of steps S1011 and S1012 (step S1013). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1012, is subtracted from the number of balls that entered the outlet 24a calculated in step S1011. Then, the following parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1011 and the number of balls that entered the outlet 24a calculated in step S1012 is set as the number of balls that entered the outlet 24a, K11; the difference between the number of balls that entered the general winning port 31 calculated in step S1011 and the number of balls that entered the general winning port 31 calculated in step S1012 is set as the number of balls that entered the outlet 24a, K12; and the difference between the number of balls that entered the special winning device 32 calculated in step S1011 and the number of balls that entered the special winning device 32 calculated in step S1012 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1012 is designated as the number of balls that enter K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1011 and the number of balls that enter the first operating port 33 calculated in step S1012 is designated as the number of balls that enter K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1011 and the number of balls that enter the second operating port 34 calculated in step S1012 is designated as the number of balls that enter K15. 11th parameter: Total number of game balls paid out (K12 × "number of prize balls for winning at the general winning port 31" + K13 × "number of prize balls for winning at the special winning device 32" + K14 × "number of prize balls for winning at the first operating port 33" + K15 × "number of prize balls for winning at the second operating port 34") / ratio of the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D11"). 12th parameter: The ratio of the total number of game balls entering the general winning slot 31 (K12) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 13th parameter: The ratio of the total number of game balls entering the special winning device 32 (K13) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 14th parameter: The ratio of the total number of game balls entering the first operating port 33 (K14) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D12") 15th parameter: The ratio of the total number of game balls entering the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13") 16th parameter: D11 - (D12 x "Number of winning balls for winning into the first operating port 33" + D13 x "Number of winning balls for winning into the second operating port 34") 17th parameter: (K13 × "Number of prize balls for winning the special electric winning device 32" + K15 × "Number of prize balls for winning the second operating port 34") / Total number of game balls paid out (K12 × "Number of prize balls for winning the general winning port 31" + K13 × "Number of prize balls for winning the special electric winning device 32" + K14 × "Number of prize balls for winning the first operating port 33" + K15 × "Number of prize balls for winning the second operating port 34") ratio 18th parameter: K13 × "Number of prize balls for winning the special electric winning device 32" / Total number of game balls paid out (K12 × "Number of prize balls for winning the general winning port 31" + K13 × "Number of prize balls for winning the special electric winning device 32" + K14 × "Number of prize balls for winning the first operating port 33" + K15 × "Number of prize balls for winning the second operating port 34") ratio Thereafter, a second output process is executed (step S1014). In the second output process, the various parameters calculated in step S1013 are sequentially output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads each piece of information to be output in the second output process.

[0265] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high frequency support mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the high frequency support mode, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, and the second operating hole 34 that occurred in the high frequency support mode situation is calculated (step S1015). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high frequency support mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the high frequency support mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections within the entire set of consecutive pointer information between history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode and history information storage area 125 storing correspondence relationship information and end information indicating the high frequency support mode, the total number of balls scored for each section is calculated. Furthermore, if there is a history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode, but the history information storage area 125 storing RTC information corresponding to a time later than that of the history information storage area 125 does not store correspondence relationship information and start information indicating the high frequency support mode, all history information in history information storage area 125 storing RTC information corresponding to a time later than that of the history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode is treated as being in the high frequency support mode.

[0266] Thereafter, the number of balls that entered each of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state during the period of the high frequency support mode identified in step S1015 is calculated (step S1016). The method for calculating these numbers of balls is the same as in step S1007, except that it is based on the period of the high frequency support mode identified in step S1015.

[0267] Thereafter, various parameters are calculated using the calculation results of steps S1015 and S1016 (step S1017). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1016, is subtracted from the number of balls that entered the outlet 24a calculated in step S1015. Then, the following parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1015 and the number of balls that entered the outlet 24a calculated in step S1016 is set as the number of balls that entered the outlet 24a, the difference between the number of balls that entered the general winning port 31 calculated in step S1015 and the number of balls that entered the general winning port 31 calculated in step S1016 is set as the number of balls that entered the outlet 24a, and the difference between the number of balls that entered the general winning port 31 calculated in step S1015 and the number of balls that entered the special winning device 32 calculated in step S1016 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1016 is designated as the number of balls that enter K23, the difference in the number of balls that enter the first operating port 33 calculated in step S1015 and the number of balls that enter the first operating port 33 calculated in step S1016 is designated as the number of balls that enter K24, and the difference in the number of balls that enter the second operating port 34 calculated in step S1015 and the number of balls that enter the second operating port 34 calculated in step S1016 is designated as the number of balls that enter K25. 21st parameter: Total number of game balls paid out (K22 × "Number of prize balls for winning at the general winning port 31" + K23 × "Number of prize balls for winning at the special winning device 32" + K24 × "Number of prize balls for winning at the first operating port 33" + K25 × "Number of prize balls for winning at the second operating port 34") / Ratio of the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D11"). 22nd parameter: The ratio of the total number of game balls entering the general winning slot 31 (K22) to the total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) 23rd parameter: The ratio of the total number of game balls entering the special winning device 32 (K23) to the total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) 24th parameter: The ratio of the total number of game balls entering the first operating port 33 (K24) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D22") 25th parameter: The ratio of the total number of game balls entering the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D23") 26th parameter: D21 - (D22 x "Number of winning balls for winning into the first operating port 33" + D23 x "Number of winning balls for winning into the second operating port 34") Thereafter, a third output process is executed (step S1018). In the third output process, the various parameters calculated in step S1017 are sequentially output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads each piece of information to be output in the third output process. Thereafter, a clear process is executed (step S1019). In the clear process, the history information storage area 125 of the history memory 117 is all cleared to "0", and the pointer area 126 is also cleared to "0". As a result, the history area 124 is initialized.

[0268] According to the present embodiment described above in detail, the following excellent effects are achieved.

[0269] When a gaming ball enters any of the general winning slot 31, the special winning device 32, the first actuation slot 33, and the second actuation slot 34, the gaming ball is paid out. Therefore, players play in the hope that a gaming ball will enter one of these slots. In this configuration, when a gaming ball enters any of the outlet slot 24a, the general winning slot 31, the special winning device 32, the first actuation slot 33, and the second actuation slot 34 (hereinafter referred to as the history-targeted ball entry slots), the corresponding history information is stored in the history memory 117 of the management IC 66. This allows the pachinko machine 10 to store and retain information for managing the number and frequency of gaming balls entering each history-targeted ball entry slot. Using this managed information, it is possible to appropriately manage the manner in which gaming balls enter each history-targeted ball entry slot. Furthermore, since the history information is stored and retained within the pachinko machine 10 itself, unauthorized access to or unauthorized modification of the history information can be prevented.

[0270] All ball entry sections that eject game balls from the game area PA are subject to the execution of the history information storage process and are subject to management using the history information. This makes it possible to manage the ball entry frequency for any history target ball entry section using the history information. Also, it becomes possible to manage the ratio of the number of game balls that enter each history target ball entry section to the number of game balls that are ejected from the game area PA using the history information.

[0271] The history information includes RTC information, which is information corresponding to the timing when the game ball entered the history target ball entry area that triggered the storage of the history information. By using the history information, it is possible to grasp the history of game balls entering the history target ball entry area in detail.

[0272] The history memory 117 stores not only history information corresponding to game balls entering the history target ball entry portion, but also history information indicating whether the opening / closing execution mode is in effect, history information indicating whether the high frequency support mode is in effect, and history information indicating whether the front door frame 14 is open or not. This makes it possible to distinguish between these situations and manage the manner in which game balls enter the history target ball entry portion.

[0273] The history information stored in the history memory 117 can be output to a reading device that is an external device to the pachinko machine 10. This makes it possible to read the history information with the reading device and use the read history information to analyze the manner in which game balls enter the history target ball entry portion.

[0274] The MPU 62 is provided with a read terminal 102, and a reading device electrically connected to the read terminal 102 can read out the program from the main ROM 64. This makes it possible to check whether the program is normal. In this configuration, the read terminal 102, which is used to output the program externally, is used to output the history information stored in the history memory 117 to the outside. This makes it possible to output the history information to the outside without complicating the configuration.

[0275] It is determined whether the information to be output from the read terminal 102 is a program or history information, and the information corresponding to the determination result is output to the outside through the read terminal 102. As a result, in a configuration in which history information is output to the outside using the read terminal 102 for externally outputting a program, it is determined on the pachinko machine 10 side whether the information to be externally output is a program or history information, and the determined information is output to the outside. Therefore, even in a configuration in which the read terminal 102 is used for both purposes, it is possible to read out only the necessary information.

[0276] Based on information received from a reading device electrically connected to the reading terminal 102, it is determined whether the information to be output from the reading terminal 102 is a program or history information. This makes it possible to prevent the configuration for selecting information to be output from becoming complicated.

[0277] The MPU 62, which has a main ROM 64 that stores a program in advance, has a management IC 66 and a read terminal 102. This makes it possible to consolidate the signal path to the read terminal 102 within the MPU 62. This makes it possible to achieve the excellent effects already described while making it difficult to make unauthorized access to the signal path to the read terminal 102.

[0278] A management CPU 112 is provided separately from the main CPU 63, which executes processing to have game balls paid out based on the game balls entering any of the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34, and the management CPU 112 executes processing to have history information stored in the history memory 117. This makes it possible to manage the game ball entry patterns into each history target ball entry port while preventing the processing load on the main CPU 63 from increasing excessively.

[0279] The main CPU 63 and the control CPU 112 are provided on the same chip as the MPU 62. This makes it possible to prevent unauthorized access to the communication path between the main CPU 63 and the control CPU 112.

[0280] The main CPU 63 transmits information corresponding to the detection results of each of the ball entry detection sensors 42a-48a to each of the buffers 122a-122g of the input port 121 of the management IC 66, using the signal paths corresponding to each of the ball entry detection sensors 42a-48a. This results in a correspondence between the type of information transmitted from the main CPU 63 and each of the buffers 122a-122g (i.e., each signal path), making it possible to simplify the configuration for distinguishing each type of information in the management CPU 112.

[0281] The main CPU 63 transmits information corresponding to whether the door is in the open / close execution mode, information corresponding to whether the door is in the high frequency support mode, and information corresponding to whether the front door frame 14 is open to each of the buffers 122h-122j of the input port 121 of the management IC 66, using the signal paths corresponding to each of these situations. This allows the type of information corresponding to each of these situations to correspond to each of the buffers 122h-122j (i.e., each signal path), making it possible to simplify the configuration for distinguishing between each type of information in the management CPU 112.

[0282] The main CPU 63 transmits correspondence information indicating which type of information each of the buffers 122a-122j (i.e., each of the signal paths 118a-118j) corresponds to to the management CPU 112. This eliminates the need to store the correspondence information in advance in the management IC 66. This makes it possible to improve the versatility of the management IC 66.

[0283] When the supply of operating power to the main CPU 63 is started, the main CPU 63 transmits correspondence information to the management IC 66. As a result, in a situation where a game ball may enter the history target ball entry section, it becomes possible for the management IC 66 to identify the correspondence between the information transmitted from the main CPU 63 and the history target ball entry section.

[0284] The correspondence information is transmitted from the main CPU 63 to the management IC 66 using signal paths 118a to 118g for transmitting information indicating whether or not a gaming ball has entered the history target entry portion. This simplifies the communication configuration compared to a configuration in which a dedicated signal path is provided for transmitting the correspondence information.

[0285] The management IC 66 is provided with a correspondence memory 116, and the correspondence information transmitted from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. This eliminates the need to provide information that enables the management IC 66 to identify the history target goal location corresponding to the information to be transmitted each time the main CPU 63 transmits information on the detection results of each goal detection sensor 42a-48a. This makes it possible to reduce the amount of information on the detection results of each goal detection sensor 42a-48a transmitted from the main CPU 63.

[0286] When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from LOW level to HI level, information is output from the management IC 66 to the read terminal 102. In this case, the management CPU 112 can identify that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal without receiving correspondence relationship information from the main CPU 63. This makes it possible to prevent the configuration for transmitting correspondence relationship information from becoming extremely complicated.

[0287] The management IC 66 is provided with buffers 122a to 122p capable of receiving information from the main CPU 63, the number of which is greater than the number of types of information that need to be transmitted from the main CPU 63 to the management IC 66. This makes it possible to accommodate an increase or decrease in the number of types of information depending on the model of the pachinko machine 10 without changing the configuration of the buffers 122a to 122p. This makes it possible to increase the versatility of the management IC 66.

[0288] When history information is transmitted from the management IC 66 to the reading terminal 102, the history information contains correspondence information indicating the type of history target ball entry portion that corresponds to the history information. This makes it possible to identify the manner in which game balls entered each history target ball entry portion using the read history information.

[0289] In the management IC 66, various parameters (parameters 1 to 8, 11 to 18, and 21 to 26) corresponding to the ball entry patterns of the game balls in the game area PA during a predetermined period are calculated by using the history information stored in the history memory 117. This makes it possible to externally output the various parameters calculated using the history information.

[0290] Various parameters are calculated with the historical information corresponding to the situation where the front door frame 14 is open excluded. This makes it possible to derive various parameters for the normal situation where the front door frame 14 is closed. In addition, various parameters corresponding to the situation where the opening / closing execution mode is active and the situation where the high frequency support mode is active are calculated. This makes it possible for the manager of the amusement hall to grasp the manner in which game balls enter the machine depending on each situation.

[0291] When various parameters have been calculated, a process for clearing the history memory 117 is executed to initialize the history memory 117. This makes it possible to prevent the occurrence of an event in which history information that exceeds the storage capacity of the history memory 117 is stored in the history memory 117, resulting in the history information that should have been stored and retained being erased by overwriting.

[0292] When various parameters are output to the read terminal 102, the history information stored in the history memory 117 is also output to the read terminal 102. This makes it possible to refer to not only the various parameters but also the history information that is the basis for calculating the various parameters when reading out various parameters to analyze the manner in which game balls enter the game area PA.

[0293] The control CPU 112 calculates various parameters when a reading device is electrically connected to the reading terminal 102. This makes it possible to reduce the frequency of calculating various parameters.

[0294] When the main CPU 63 identifies that a reading device is electrically connected to the reading terminal 102 and the main CPU 63 transmits output instruction information, various parameters are calculated in the management IC 66, and the various parameters resulting from the calculation are output to the reading terminal 102. This makes it possible to output various parameters to a reading device outside the pachinko machine 10 based on instructions from the main CPU 63.

[0295] The process executed by the main CPU 63 when the supply of operating power starts determines whether or not a reading device is electrically connected to the reading terminal 102, and when it is determined that a reading device is electrically connected, output instruction information is transmitted from the main CPU 63 to the management IC 66. As a result, while the process when the supply of operating power starts is being executed by the main CPU 63, i.e., before the main CPU 63 starts normal processing for progressing a game, the calculation of various parameters and the external output of the calculation results are completed. Therefore, it is possible to prevent the calculation of various parameters and the external output of the calculation results from being performed in a situation where a gaming ball may enter the history target ball entry section, and it is possible to reduce the processing load on the management IC 66.

[0296] In a configuration in which when a gaming ball enters the first actuation port 33 or the second actuation port 34, a corresponding external output is made through the external terminal board 97, and history information is stored in the history memory 117. This makes it possible to easily grasp the number and frequency of gaming balls entering the first actuation port 33 or the second actuation port 34 by using the information outputted externally through the external terminal board 97, and to accurately grasp the number and frequency of gaming balls entering the history target entry portion by using the history information stored in the history memory 117.

[0297] <Second embodiment> In this embodiment, the type of buffers for which the type of input signal is determined at the design stage of the management IC 66 among the first to sixteenth buffers 122a to 122p of the input port 121 in the management I / F 111 differs from that of the first embodiment. Also, the processing configuration executed by the main CPU 63 to cause the management CPU 112 to identify the type of input signal differs from that of the first embodiment. The following describes the configuration that differs from the first embodiment. Note that a description of the same configuration as the first embodiment will basically be omitted.

[0298] FIG. 25 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111 in this embodiment.

[0299] The first to seventh buffers 122a to 122g and the sixteenth buffer 122p receive the same types of signals as those in the first embodiment. In detail, a first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a, a second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b, a third signal corresponding to the detection result of the third winning port detection sensor 44a is input to the third buffer 122c, a fourth signal corresponding to the detection result of the special electric current detection sensor 45a is input to the fourth buffer 122d, a fifth signal corresponding to the detection result of the first operating port detection sensor 46a is input to the fifth buffer 122e, a sixth signal corresponding to the detection result of the second operating port detection sensor 47a is input to the sixth buffer 122f, a seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g, and an output instruction signal is input to the sixteenth buffer 122p.

[0300] On the other hand, in the first embodiment, the signal corresponding to the opening / closing execution mode is input as the eighth signal to the eighth buffer 122h, the signal corresponding to the high frequency support mode is input as the ninth signal to the ninth buffer 122i, and the signal corresponding to the front door frame 14 is input as the tenth signal to the tenth buffer 122j, but in this embodiment, the buffers to which these signals are input are different. Specifically, the signal corresponding to the opening / closing execution mode is input as an opening / closing execution mode signal to the thirteenth buffer 122m, the signal corresponding to the high frequency support mode is input as a high frequency support mode signal to the fourteenth buffer 122n, and the signal corresponding to the front door frame 14 is input as a door open signal to the fifteenth buffer 122o.

[0301] The input of an open / close execution mode signal to the thirteenth buffer 122m, the input of a high-frequency support mode signal to the fourteenth buffer 122n, the input of a door open signal to the fifteenth buffer 122o, and the input of an output instruction signal to the sixteenth buffer 122p were determined during the design stage of the management IC 66, and the management CPU 112 can determine that the corresponding signals will be input to the thirteenth to sixteenth buffers 122m to 122p without receiving an instruction from the main CPU 63. Meanwhile, the types of signals to be input to the first to twelfth buffers 122a to 122l were not determined during the design stage of the management IC 66, and the types of these signals are determined by the management CPU 112 upon receiving an instruction from the main CPU 63. The process for determining the type of signal is executed when the supply of operating power to the main CPU 63 and the management CPU 112 is initiated, as in the first embodiment.

[0302] Fig. 26 is a flowchart showing the recognition process of this embodiment executed by the main CPU 63. The recognition process is executed in step S110 of the main process (Fig. 7) in the same manner as in the first embodiment.

[0303] First, the recognition output counter in the main RAM 65 is set to "12," which is the number of the first to twelfth buffers 122a to 122l that are to be recognized for signal type (step S1101). Then, an identification start signal output process is executed (step S1102). In this output process, the output states of the first signal input to the first buffer 122a, the open / close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to a HI level, thereby starting output of the identification start signal. The periods during which these signals are maintained at a HI level are set long enough for the management CPU 112 to recognize the output states of these signals.

[0304] Thereafter, information on the number of outputs corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64, and the read information on the number of outputs is set in the output number counter provided in the main RAM 65 (step S1103). The output number counter is a counter for the main CPU 63 to specify the number of times the type identification signal has been output.

[0305] In this embodiment, when the management CPU 112 is made to recognize the type of signal input to the first buffer 122a to the twelfth buffer 122l, the type identification signal is output the same number of times as the number of prize balls set for the ball entry section corresponding to that type of signal. The management CPU 112 stores information corresponding to the number of times the type identification signal has been received for each of the first buffer 122a to the twelfth buffer 122l in the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116. In other words, the type of signal input to the first buffer 122a to the twelfth buffer 122l is understood as the number of prize balls set for the ball entry section corresponding to that signal type.

[0306] In step S1103, if the value of the recognition output counter is any of "12," "11," and "10," the output count counter is set to "10," which corresponds to the number of prize balls in the general winning port 31. If the value of the recognition output counter is "9," the output count counter is set to "15," which corresponds to the number of prize balls in the special winning device 32. If the value of the recognition output counter is "8," the output count counter is set to "1," which corresponds to the number of prize balls in the first operating port 33. If the value of the recognition output counter is "7," the output count counter is set to "1," which corresponds to the number of prize balls in the second operating port 34. If the value of the recognition output counter is "6," the output count counter corresponds to the outlet 24a, but even if a game ball enters the outlet 24a, the payout of the game ball is not executed, so the output count counter is set to "0." Also, if the value of the recognition output counter is any one of "5" to "1", there is no corresponding ball entry section and it is blank, so the output number counter is set to "0".

[0307] Thereafter, a process of outputting a start trigger signal is executed (step S1104). In this output process, the output state of the first signal input to the first buffer 122a is set to a HI level, thereby starting output of the start trigger signal. The period during which the first signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the first signal.

[0308] Thereafter, on the condition that the value of the output count counter in the main RAM 65 is not "0" (step S1105: YES), that is, on the condition that a value of 1 or greater was set in the output count counter in step S1103, the process proceeds to step S1106. In step S1106, output processing of a type identification signal is executed. In this output processing, the output state of the second signal input to the second buffer 122b is set to a HI level, thereby starting output of the type identification signal. The period for which the second signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the second signal.

[0309] Thereafter, the value of the output counter in the main RAM 65 is decremented by 1 (step S1107), and it is determined whether the value of the output counter after decrementing by 1 is "0" (step S1108). If the value of the output counter is 1 or more (step S1108: NO), the process returns to step S1106.

[0310] If the determination in step S1105 is affirmative, or if the determination in step S1108 is affirmative, output processing of a termination trigger signal is executed (step S1109). In this output processing, the output state of the third signal input to the third buffer 122c is set to a HI level, thereby starting output of the termination trigger signal. The period during which the third signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the third signal.

[0311] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S1110), and it is determined whether the value of the recognition output counter after decrementing by 1 is "0" (step S1111). If the value of the recognition output counter is 1 or greater (step S1111: NO), the process returns to step S1103, and processing is performed to recognize the type of signal corresponding to the value of the recognition output counter after decrementing by 1.

[0312] On the other hand, if the value of the recognition output counter is "0" (step S1111: YES), an identification end signal output process is executed (step S1112). In this output process, the output states of the third signal input to the third buffer 122c, the open / close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to a HI level, thereby starting output of the identification end signal. The period for which these signals are maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

[0313] Next, the management process in this embodiment executed by the management-side CPU 112 will be described with reference to the flowchart in Fig. 27. The management process starts when the supply of operating power to the management-side CPU 112 starts, similar to the first embodiment.

[0314] When reception of the identification start signal from the main CPU 63 has ended (step S1201: YES), the value of the setting target counter in the control RAM 114 is cleared to "0" (step S1202). Thereafter, on the condition that a start trigger signal has been received from the main CPU 63 (step S1203: YES), the process proceeds to step S1204. In step S1204, it is determined whether or not a type identification signal has been received from the main CPU 63. When a type identification signal has been received (step S1204: YES), the value of a reception count counter provided in the control RAM 114 is incremented by 1 (step S1205). The reception count counter is a counter used by the control CPU 112 to identify the number of times a type identification signal has been received from the main CPU 63. The value of the reception count counter is cleared to "0" when a positive determination is made in step S1203.

[0315] If a negative determination is made in step S1204, or if the processing of step S1205 is executed, it is determined whether or not a termination trigger signal has been received from the main CPU 63 (step S1206). If a termination trigger signal has not been received (step S1206: NO), the process returns to step S1204, and if a termination trigger signal has been received (step S1206: YES), a correspondence setting process is executed (step S1207). In the correspondence setting process, the value set in the reception count counter is stored in the correspondence area corresponding to the current value of the setting target counter in the management RAM 114, among the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116. In this case, the first correspondence area 123a, the second correspondence area 123b, and the third correspondence area 123c are set to "10," which corresponds to the number of prize balls in the general winning port 31; the fourth correspondence area 123d is set to "15," which corresponds to the number of prize balls in the special winning device 32; the fifth correspondence area 123e is set to "1," which corresponds to the number of prize balls in the first operating port 33; and the sixth correspondence area 123f is set to "1," which corresponds to the number of prize balls in the second operating port 34. Furthermore, "0" is set in the seventh to twelfth correspondence areas 123g to 123l. After that, the value of the setting target counter in the management-side RAM 114 is incremented by 1 (step S1208).

[0316] If a negative determination is made in step S1203, or if the processing of step S1208 is executed, it is determined whether or not reception of the identification end signal from the main CPU 63 has finished (step S1209). If reception of the identification end signal has not finished (step S1209: NO), the process returns to step S1203, and, on the condition that a start trigger signal is received from the main CPU 63 (step S1203: YES), the processing of step S1204 and thereafter is executed. If reception of the identification end signal from the main CPU 63 has finished (step S1209: YES), the history setting processing of step S1210 and the external output processing of step S1211 are repeatedly executed.

[0317] FIG. 28 is a time chart showing how information on the correspondence between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l is stored in the correspondence memory 116. In FIG. Figure 28(a) shows the period when the output state of the first signal is at HI level, Figure 28(b) shows the period when the output state of the second signal is at HI level, Figure 28(c) shows the period when the output state of the third signal is at HI level, Figure 28(d) shows the period when the output state of the open / close execution mode signal is at HI level, Figure 28(e) shows the period when the output state of the high frequency support mode signal is at HI level, Figure 28(f) shows the execution period of the identification state in which processing is executed to identify the correspondence between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l, Figure 28(g) shows the timing when the value of the reception count counter in the management side RAM 114 is incremented by 1, and Figure 28(h) shows the timing when the correspondence setting processing (step S1207) is executed by the management side CPU 112.

[0318] When the supply of operating power to the main CPU 63 and the control CPU 112 is started, at timing t1, the output states of the first signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from LOW level to HI level, as shown in Figures 28(a), 28(d), and 28(e). This causes output of an identification start signal from the main CPU 63 to the control CPU 112 to begin. Thereafter, at timing t2, the output states of the first signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from HI level to LOW level. This causes output of the identification start signal from the main CPU 63 to the control CPU 112 to stop. At timing t2, the control CPU 112 makes a positive determination in step S1201 of the control process (Figure 27), thereby entering the identification state as shown in Figure 28(f).

[0319] Thereafter, the output state of the first signal is maintained at a HI level from time t3 to time t4, as shown in Figure 28(a). As a result, a start trigger signal is output to the control CPU 112. Then, the output state of the second signal is maintained at a HI level from time t5 to time t7, as shown in Figure 28(b). As a result, a type identification signal is output once to the control CPU 112. In this case, at time t6, the value of the reception count counter in the control RAM 114 is incremented by 1, as shown in Figure 28(g).

[0320] Thereafter, the output state of the third signal is maintained at HI level from timing t8 to timing t10 ​​as shown in Figure 28(c). As a result, a state is created in which a termination trigger signal is output to the control CPU 112. In this case, at timing t9, the control CPU 112 executes a correspondence setting process as shown in Figure 28(h). Since the value of the reception count counter is "1" when the correspondence setting process is executed, the information of "1" is stored as the correspondence information in the correspondence areas 123a to 123l to be set this time in the correspondence memory 116.

[0321] Thereafter, the output state of the first signal is maintained at a HI level from timing t11 to timing t12, as shown in FIG. 28(a). As a result, a start trigger signal is output to the control CPU 112. Then, as shown in FIG. 28(b), the output state of the second signal is maintained at a HI level from timing t13 to timing t15, from timing t16 to timing t18, from timing t19 to timing t21, and from timing t22 to timing t24. As a result, a type identification signal is output once to the control CPU 112. In this case, the value of the reception count counter in the control RAM 114 is incremented by 1 at each of timings t14, t17, t20, and t23, as shown in FIG. 28(g).

[0322] Thereafter, the output state of the third signal is maintained at HI level from timing t25 to timing t27 as shown in Figure 28(c). As a result, a state is created in which a termination trigger signal is output to the control CPU 112. In this case, at timing t26, as shown in Figure 28(h), the control CPU 112 executes a correspondence setting process. Since the value of the reception count counter is "10" when the correspondence setting process is executed, the information of "10" is stored as the correspondence information in the correspondence areas 123a to 123l to be set this time in the correspondence memory 116.

[0323] After that, at timing t28, as shown in Figures 28(c), 28(d), and 28(e), the output states of the third signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from LOW level to HI level. This causes output of an identification end signal from the main CPU 63 to the control CPU 112 to begin. After that, at timing t29, the output states of the third signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from HI level to LOW level. This causes output of the identification end signal from the main CPU 63 to the control CPU 112 to stop. At timing t29, the control CPU 112 makes a positive determination in step S1209 of the control process (Figure 27), and the identification state is released as shown in Figure 28(f).

[0324] In this embodiment, since information on the number of prize balls is stored as the correspondence information, the history information stored in the history memory 117 also includes, as correspondence information, information on the number of prize balls corresponding to the ball entry section that triggered the storage of the history information. In this configuration, if there are multiple types of ball entry sections with the same number of prize balls, these ball entry sections cannot be distinguished from each other in the history information. Specifically, since the first actuation port 33 and the second actuation port 34 both have a single prize ball, the first actuation port 33 and the second actuation port 34 cannot be distinguished from each other in the history information. In such circumstances, the number of prize balls for the first actuation port 33 and the second actuation port 34 may be made different. This makes it possible to distinguish between the first actuation port 33 and the second actuation port 34 in the history information, even in a configuration in which history information is stored as in the second embodiment.

[0325] In this embodiment, in step S801 of the history setting process, the confirmation target counter in the management RAM 114 is set to "15." As a result, all of the first to fifteenth buffers 122a to 122o become targets for confirmation.

[0326] According to the embodiment described above, the control CPU 112 can identify the signal paths corresponding to not only the output instruction signal but also information corresponding to whether the machine is in the open / close execution mode, information corresponding to whether the machine is in the high-frequency support mode, and information corresponding to whether the front door frame 14 is open, without receiving correspondence information from the main CPU 63. In this case, only the information corresponding to the detection results of each ball entry detection sensor 42a-48a is the information that the main CPU 63 needs to have the control CPU 112 recognize the correspondence between each piece of information and each signal path 118a-118g. When the control CPU 112 recognizes the correspondence information, the main CPU 63 outputs a number of pulse signals equal to the number of winning balls corresponding to each ball entry detection sensor 42a-48a to the control CPU 112 using the second signal. This simplifies the configuration for transmitting the correspondence information.

[0327] <Third embodiment> In this embodiment, the trigger for executing calculation of various parameters using history information is different from that of the first embodiment. The following describes the configuration that is different from the first embodiment. Note that the description of the same configuration as the first embodiment will basically be omitted.

[0328] 29 is a block diagram for explaining the electrical configuration of the management IC 66 in this embodiment. As in the first embodiment, the management IC 66 is provided with a management I / F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, and a history memory 117. These functions are the same as in the first embodiment.

[0329] In addition to the above, the management IC 66 is also provided with a calculation result memory 131. In this embodiment, as will be described in detail later, when a calculation trigger occurs, various parameters are calculated in the management side CPU 112 using the history information stored in the history memory 117 at that time. The calculated various parameters are then sequentially stored in the calculation result memory 131. The various parameters stored in the calculation result memory 131 are output to a reading device electrically connected to the reading terminal 102.

[0330] The timing for calculating various parameters occurs before the reading device is electrically connected to the reading terminal 102. This makes it possible to differentiate the timing for calculating various parameters from the timing for externally outputting the parameters to the reading device, thereby distributing the processing load.

[0331] Furthermore, by providing a calculation result memory 131 for storing the calculation results of various parameters, it is possible to store not only the various parameters for one calculation trigger, but also the various parameters for multiple calculation triggers all together, thereby shortening the time required to calculate the various parameters at each calculation trigger.

[0332] FIG. 30 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111 in this embodiment.

[0333] The first to tenth buffers 122a to 122j and the sixteenth buffer 122p are input with the same types of signals as in the first embodiment. In detail, the first buffer 122a receives a first signal corresponding to the detection result of the first winning opening detection sensor 42a, the second buffer 122b receives a second signal corresponding to the detection result of the second winning opening detection sensor 43a, the third buffer 122c receives a third signal corresponding to the detection result of the third winning opening detection sensor 44a, the fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a, and the fifth buffer 122e receives a fifth signal corresponding to the detection result of the first operation opening detection sensor 46a. A signal corresponding to the detection result of the second operating port detection sensor 47a is input to the sixth buffer 122f, a sixth signal corresponding to the detection result of the second operating port detection sensor 47a is input to the seventh buffer 122g, a signal corresponding to the opening / closing execution mode is input to the eighth buffer 122h, a signal corresponding to the high frequency support mode is input to the ninth buffer 122i, a signal corresponding to the front door frame 14 is input to the tenth buffer 122j, and an output instruction signal is input to the sixteenth buffer 122p.

[0334] In this embodiment, in addition to the various signals described above, a calculation instruction signal is input to the fifteenth buffer 122o. The calculation instruction signal is a signal output from the primary CPU 63 to provide the management CPU 112 with an opportunity to calculate various parameters. The input of the calculation instruction signal to the fifteenth buffer 122o, like the input of the output instruction signal to the sixteenth buffer 122p, was determined during the design phase of the management IC 66. Therefore, the management CPU 112 can determine that the corresponding signals described above will be input to the fifteenth to sixteenth buffers 122o to 122p without receiving an instruction from the primary CPU 63. Meanwhile, the types of signals input to the first to fourteenth buffers 122a to 122n were not determined during the design phase of the management IC 66. The types of signals are identified by the management CPU 112 upon receiving an instruction from the primary CPU 63. As in the first embodiment, the process for identifying the type of signal is executed when the supply of operating power to the primary CPU 63 and the management CPU 112 is initiated.

[0335] Next, a description will be given of a processing configuration for causing the management CPU 112 to calculate various parameters in response to the occurrence of a calculation trigger. Fig. 31 is a flowchart showing the power outage information storage processing executed by the main CPU 63. The power outage information storage processing is executed in step S201 of the timer interrupt processing (Fig. 8).

[0336] In the power outage information storage process, if a power outage signal corresponding to a power outage has been received from the power outage monitoring board 67 (step S1301: YES), output processing of a calculation instruction signal is executed (step S1302). In this output processing, the output state of the calculation instruction signal input to the 15th buffer 122o of the input port 121 of the management side I / F 111 is maintained at HI level for a specific period. This specific period is long enough for the management side CPU 112 to recognize that the output state of the calculation instruction signal is HI level. After that, after executing power outage processing in step S1303, an infinite loop is executed, and the process waits until the supply of operating power to the main side CPU 63 is completely stopped. In the power outage processing, the power outage flag in the main side RAM 65 is set to "1," and a checksum is calculated and stored.

[0337] Fig. 32 is a flowchart showing the power failure response process executed by the management CPU 112. The power failure response process is configured to be executed after the external output process in the management process (Fig. 18), and after receiving an identification end command from the main CPU 63 in the management process (step S606: YES), the history setting process in step S607, the external output process in step S608, and the power failure response process are repeatedly executed in this order.

[0338] In the power outage response processing, when the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1401: YES), in steps S1402 to S1406, the number of balls that have entered each of the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34 is calculated, similar to steps S1002 to S1006 of the external output processing (Fig. 24) in the first embodiment described above. Also, in step S1407, the number of balls that have entered each type when the front door frame 14 is open is calculated, similar to step S1007 of the external output processing (Fig. 24) in the first embodiment described above. Furthermore, in step S1408, various parameters are calculated, similar to step S1008 of the external output processing (FIG. 24) in the first embodiment, and in step S1409, a total time is calculated, similar to step S1009 of the external output processing (FIG. 24) in the first embodiment. Then, the calculation result information of step S1408 and the calculation result information of step S1409 are written to the calculation result memory 131 (step S1410). In this case, if other calculation result information is already stored in the calculation result memory 131, the calculation result information is written so as not to overwrite the already stored calculation result information. Furthermore, the current date and time information is read from the RTC 115, and the read date and time information are attached to the calculation result information written this time. This makes it possible to identify the timing to which the calculation result information written this time corresponds.

[0339] Then, in step S1411, similar to step S1011 of the external output processing (FIG. 24) in the first embodiment, the number of balls entering the various types during the opening / closing execution mode is calculated. In step S1412, similar to step S1012 of the external output processing (FIG. 24) in the first embodiment, the number of balls entering the various types during the opening / closing execution mode when the front door frame 14 is open is calculated. Also, in step S1413, similar to step S1013 of the external output processing (FIG. 24) in the first embodiment, various parameters are calculated. Then, the information of the calculation result in step S1414 is written to the calculation result memory 131 (step S1414). In this case, the calculation result information is written so as not to overwrite other calculation result information already stored in the calculation result memory 131. Also, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to identify the timing to which the information on the calculation result written this time corresponds.

[0340] Then, in step S1415, similar to step S1015 of the external output processing (FIG. 24) in the first embodiment, the number of balls entering the game during the high-frequency support mode is calculated. In step S1416, similar to step S1016 of the external output processing (FIG. 24) in the first embodiment, the number of balls entering the game during the high-frequency support mode when the front door frame 14 is open is calculated. Also, in step S1417, similar to step S1017 of the external output processing (FIG. 24) in the first embodiment, various parameters are calculated. Then, the information of the calculation result in step S1417 is written to the calculation result memory 131 (step S1418). In this case, the calculation result information is written so as not to overwrite other calculation result information already stored in the calculation result memory 131. Also, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to identify the timing of the calculation result information written this time. After that, an infinite loop is entered, and the control CPU 112 waits until the supply of operating power to the control CPU 112 is completely stopped.

[0341] 33 is a flowchart showing the external output process executed by the management CPU 112. The external output process is executed in step S608 of the management process (FIG. 18).

[0342] When the output state of the output instruction signal from the main CPU 63 becomes HI level (step S1501: YES), an output process of the calculation results is executed (step S1502). In this output process, the various calculation results stored in the calculation result memory 131 are output to the reading terminal 102. As a result, the various calculation results stored in the calculation result memory 131 are read by a reading device electrically connected to the reading terminal 102. In this case, if the calculation result memory 131 only stores various calculation results corresponding to the occurrence of a single calculation trigger, only the various calculation results corresponding to the occurrence of that single calculation trigger are read by the reading device, and if the calculation result memory 131 stores various calculation results corresponding to the occurrence of multiple calculation triggers, the various calculation results corresponding to those multiple calculation triggers are read by the reading device.

[0343] Thereafter, a process for outputting history information is executed (step S1503). In this output process, all of the history information stored in the history area 124 of the history memory 117 is sequentially output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads the various pieces of history information stored in the history area 124. By outputting not only the various calculation results but also the history information in this way, the worker using the reading device can perform a detailed analysis of the various calculation results.

[0344] Thereafter, a clearing process is executed (step S1504). In the clearing process, all of the history information storage area 125 of the history memory 117 is cleared to "0", and the pointer area 126 is also cleared to "0". As a result, the history area 124 is initialized. Furthermore, in the clearing process, all of the areas of the calculation result memory 131 are cleared to "0". As a result, the calculation result memory 131 is initialized.

[0345] According to the present embodiment described above in detail, the following excellent effects are achieved.

[0346] When the supply of operating power to the main CPU 63 is stopped, various parameters are calculated by the control CPU 112. This makes it possible to manage various parameters on a business day basis.

[0347] When the main CPU 63 determines that the supply of operating power is to be stopped, the output state of the calculation instruction signal is changed to HI level, causing the control CPU 112 to calculate various parameters. This makes it possible for the control CPU 112 to calculate various parameters based on instructions from the main CPU 63.

[0348] The various parameters calculated by the management CPU 112 are sequentially written to the calculation result memory 131. This allows the various parameters to be accumulated in the management IC 66, and when the various parameters are read by a reading device, it becomes possible to read out the various parameters for multiple business days all at once.

[0349] When various parameters are written to the calculation result memory 131, information that enables identification of the time when the various parameters were calculated is attached to the various parameters and written to the calculation result memory 131. This makes it possible to analyze various parameter information while knowing the time when the various parameters were calculated.

[0350] Note that the history memory 117 may be configured to be cleared to "0" when a calculation trigger occurs and the calculation results of various parameters for that trigger are written to the calculation result memory 131. This makes it less likely that new history information will be written to the history memory 117 when the maximum number of pieces of history information that can be stored in the history memory 117 has already been stored.

[0351] Also, the information to be output to the reading device may be only the information of various parameters stored in the calculation result memory 131, and the history information stored in the history memory 117 may not be output to the outside. This makes it possible to reduce the amount of information to be output to the outside.

[0352] <Fourth embodiment> In this embodiment, the processing configuration of the power outage response processing executed by the management CPU 112 is different from that of the third embodiment. The configuration that differs from the third embodiment will be described below. Note that the description of the same configuration as the third embodiment will basically be omitted.

[0353] FIG. 34 is a flowchart showing the power outage response process executed by the control CPU 112 in this embodiment.

[0354] When the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1601: YES), various calculation processes are executed (step S1602). In the various calculation processes, the processes of steps S1402 to S1409, steps S1411 to S1413, and steps S1415 to S1417 of the power outage response process (FIG. 32) in the third embodiment are executed.

[0355] Thereafter, it is determined whether or not a predetermined parameter among the various parameters calculated in step S1602 is within a reference range (step S1603). Seventh parameter: (K3 × "Number of prize balls for winning at the special electric winning device 32" + K5 × "Number of prize balls for winning at the second operating port 34") / Total number of game balls paid out (K2 × "Number of prize balls for winning at the general winning port 31" + K3 × "Number of prize balls for winning at the special electric winning device 32" + K4 × "Number of prize balls for winning at the first operating port 33" + K5 × "Number of prize balls for winning at the second operating port 34") ratio Eighth parameter: K3 × "Number of prize balls for winning the special electric winning device 32" / Total number of game balls paid out (K2 × "Number of prize balls for winning the general winning port 31" + K3 × "Number of prize balls for winning the special electric winning device 32" + K4 × "Number of prize balls for winning the first operating port 33" + K5 × "Number of prize balls for winning the second operating port 34") ratio These two parameters are set as parameters to be determined as to whether they are within the reference range. If the value of the seventh parameter is 0.7 or less and the value of the eighth parameter is 0.6 or less, it is determined that the predetermined parameters are within the reference range and a positive determination is made in step S1603.

[0356] The predetermined parameters are not limited to the seventh and eighth parameters, and other parameters may be set as the predetermined parameters instead of or in addition to the seventh and eighth parameters. For example, Second parameter: The ratio of the total number of game balls entering the general winning slot 31 (K2) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) may be set as the predetermined parameter. In this case, for example, if the value of the second parameter is equal to or greater than 0.1 and equal to or less than 0.2, the predetermined parameter may be determined to be within the reference range. Also, only the predetermined parameter to be determined in step S1603 may be calculated in the various calculation processes in step S1602.

[0357] If the predetermined parameters are not within the reference range (step S1603: NO), the various parameters calculated in step S1602 are written to the calculation result memory 131 (step S1604). In this case, if other calculation result information is already stored in the calculation result memory 131, the calculation result information is written so as not to overwrite the already stored calculation result information. In addition, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to identify the timing to which the calculation result information written this time corresponds.

[0358] On the other hand, if the predetermined parameter is within the reference range (step S1603: YES), the process of step S1604 is not executed. As a result, only the various parameters when the predetermined parameter is not within the reference range are written to the calculation result memory 131. Therefore, if an abnormal situation occurs, the history of that situation is left in the calculation result memory 131, while making it possible to reduce the storage capacity required for the calculation result memory 131.

[0359] If a positive determination is made in step S1603, or if the processing of step S1604 is executed, a process of clearing the history memory 117 is executed (step S1605). In this clearing process, all of the history information storage area 125 of the history memory 117 are cleared to "0", and the pointer area 126 is also cleared to "0". This causes the history area 124 to be initialized. After the processing of step S1605 is executed, an infinite loop is entered, and the process waits until the supply of operating power to the control-side CPU 112 is completely stopped.

[0360] According to the present embodiment described above in detail, it is determined whether the contents of the various calculated parameters fall within a reference range, and only the various parameters that are determined to fall within the reference range are written to the calculation result memory 131. This makes it possible to reduce the amount of various parameters to be stored in the calculation result memory 131, and also makes it possible to reduce the storage capacity required for the calculation result memory 131.

[0361] <Fifth embodiment> In this embodiment, the content of the calculation trigger that causes the management CPU 112 to calculate various parameters differs from that of the third embodiment. The following describes the configuration that differs from the third embodiment. Note that the description of the same configuration as the third embodiment will basically be omitted.

[0362] 35(a) is a flowchart showing the trigger identification process executed by the main CPU 63. The trigger identification process is executed when a positive determination is made in step S712 in the management output process (FIG. 20).

[0363] It is determined whether or not a game ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 (step S1701). If a positive determination is made in step S1701, an increment process is executed on the ball entry counter provided in the main RAM 65 (step S1702). In this increment process, the number of game balls that have entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 is determined based on the number of times step S705 has been executed in the management output process (FIG. 20) for this processing round. Then, the determined number of game balls is added to the ball entry counter.

[0364] Then, it is determined whether the value of the ball entry counter is equal to or greater than the trigger reference number of "500" (step S1703). If it is equal to or greater than "500" (step S1703: YES), a subtraction process is performed on the ball entry counter in the main RAM 65 (step S1704). In this subtraction process, the value of the ball entry counter is subtracted by "500". Then, an output process of the calculation instruction signal is performed (step S1705). In this output process, the output state of the calculation instruction signal input to the 15th buffer 122o in the input port 121 of the management side I / F 111 is maintained at a HI level for a specific period of time. This specific period is sufficient for the management side CPU 112 to recognize that the output state of the calculation instruction signal is at a HI level.

[0365] Fig. 35(b) is a flowchart showing the arithmetic processing executed by the management-side CPU 112. Note that the arithmetic processing is a processing executed in place of the power outage response processing in the third embodiment. Therefore, the arithmetic processing is configured to be executed after the external output processing in the management processing (Fig. 18), and in the management processing, after receiving an identification end command from the main-side CPU 63 (step S606: YES), the history setting processing in step S607, the external output processing in step S608, and the arithmetic processing are repeatedly executed in this order.

[0366] When the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1801: YES), various calculation processes are executed (step S1802). In the various calculation processes, the same processes as steps S1402 to S1418 of the power failure response process (FIG. 32) in the third embodiment are executed.

[0367] According to the present embodiment described above in detail, each time the total number of game balls discharged from the game area PA exceeds the trigger reference number, various parameters are calculated by the management CPU 112. In this case, since various parameters are calculated each time a calculation trigger occurs, which occurs repeatedly while operating power is being supplied to the main CPU 63, it becomes possible to precisely manage the manner in which game balls enter the game area PA within one business day.

[0368] Furthermore, since the various parameters are calculated based on whether the total number of game balls discharged from the game area PA is equal to or greater than the trigger reference number, the various parameters are calculated on the condition that the game is being played. This makes it possible to prevent the various parameters from being calculated meaninglessly when the game is not being played continuously.

[0369] Sixth Embodiment In this embodiment, the content of the calculation trigger that causes the management CPU 112 to calculate various parameters differs from that of the fifth embodiment. The following describes the configuration that differs from the fifth embodiment. Note that the description of the same configuration as the fifth embodiment will basically be omitted.

[0370] Fig. 36 is a flowchart showing the trigger identification process executed by the main CPU 63. The trigger identification process is executed when a positive determination is made in step S712 in the management output process (Fig. 20).

[0371] It is determined whether or not a gaming ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 (step S1901). If a negative determination is made in step S1901, the value of a continuation counter provided in the main RAM 65 is incremented by 1 (step S1902). The continuation counter is a counter used by the main CPU 63 to identify the period during which no gaming ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34.

[0372] If the value of the continuation counter after incrementing by one is equal to or greater than the stop reference value (step S1903: YES), the time measurement flag provided in the main RAM 65 is cleared to "0" (step S1904). The stop reference value is set so that a positive determination is made in step S1903 if a state in which no gaming ball enters any of the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, and second operating port 34 continues for 5 seconds. The time measurement flag is a flag used by the main CPU 63 to determine whether or not to measure time to determine the timing for switching the output state of the calculation instruction signal to the HI level. If the value of the time measurement flag is "0," the time measurement is not made, and if the value of the time measurement flag is "1," the time measurement is made. If a positive determination is made in step S1901, the time measurement flag is set to "1" (step S1905).

[0373] If a negative determination is made in step S1903, if the processing of step S1904 is executed, or if the processing of step S1905 is executed, the value of a measurement counter provided in the main RAM 65 is incremented by 1 (step S1907) on the condition that the time measurement flag in the main RAM 65 is set to "1" (step S1906: YES). The measurement counter is a counter used to measure the time required to determine the timing for switching the output state of the calculation instruction signal to HI level.

[0374] It is determined whether the value of the measurement counter after incrementing by 1 is equal to or greater than the indication reference value (step S1908). The indication reference value is set so that a positive determination is made in step S1908 when the time measured by the measurement counter reaches 10 hours. If a positive determination is made in step S1908, the value of the measurement counter is cleared to "0" (step S1909), and output processing of a calculation instruction signal is executed (step S1910). In this output processing, the output state of the calculation instruction signal input to the 15...

Claims

[Claim 1] A predetermined storage execution means for executing a predetermined storage process so that when a predetermined event occurs as a result of a game, information corresponding to the event is stored in the predetermined storage means, thereby causing predetermined information to be stored in the predetermined storage means; an information calculation means for calculating, each time a predetermined calculation trigger occurs, behavior information corresponding to a game result during a predetermined period using the predetermined information; a result storage execution means for sequentially storing the aspect information obtained by the calculation by the information calculation means in a calculation result storage means; Equipped with the result storage execution means includes means for causing the mode information to be stored among the mode information obtained by the calculation by the information calculation means to be stored in the calculation result storage means; the state information obtained by the calculation by the information calculation means, which is not a storage target, is not stored in the calculation result storage means; This gaming machine is A predetermined control means capable of executing a predetermined progress process for progressing a game; A means for generating a specific advantageous period when a specific opportunity occurs; a notification means capable of notifying the user of the content corresponding to the aspect information stored in the calculation result storage means; Equipped with When a specific event occurs that stops the game progress control, the predetermined storage process is not executed by the predetermined storage execution means. A gaming machine characterized in that the information calculation means calculates the status information corresponding to the results of the game during the specified period using the specified information during the specific advantageous period.

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