Semiconductor Module

Abstract

This semiconductor module comprises at least one substrate and a plurality of semiconductor switching elements. The substrate has a first electrode pattern, a second electrode pattern, and a third electrode pattern, the first electrode pattern being positioned between the second electrode pattern and the third electrode pattern in plan view. The semiconductor switching elements each have a first surface joined to the first electrode pattern, and a second surface facing in the opposite direction to the first surface. A control electrode, a control wiring connected to the control electrode, and a main electrode having a plurality of regions separated by the control wiring are provided to the second surface. Each of the plurality of regions is electrically connected to the second electrode pattern via a first wire and is electrically connected to the third electrode pattern via a second wire. The second electrode pattern is a pattern for a main current. The third electrode pattern is used as an auxiliary pattern for control.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] 2. Description of the Related Art Semiconductor modules, such as power semiconductor modules, may employ a configuration in which a plurality of semiconductor switching elements are connected in parallel.

[0003] For example, in the semiconductor module described in Patent Document 1, a drain pattern, a source pattern, a source control pattern, and a gate control pattern are provided on an insulating substrate on which a plurality of semiconductor switching elements are mounted, and the drain pads of the semiconductor switching elements are bonded to the drain pattern. The source pads of the semiconductor switching elements are electrically connected to the source pattern by wires. The source pads of the semiconductor switching elements are electrically connected to the source control pattern by wires. The gate pads of the semiconductor switching elements are electrically connected to the gate control pattern by wires. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2019 / 044748 Summary of the Invention [Problem to be solved by the invention]

[0005] In the configuration described in Patent Document 1, the wire for electrically connecting the source pad to the source control pattern is bonded to a biased position within the surface of the source pad, which causes an imbalance in current within the source pad, resulting in a problem of reduced switching characteristics.

[0006] In consideration of the above circumstances, one aspect of the present disclosure aims to improve the switching characteristics of a semiconductor module. [Means for solving the problem]

[0007] In order to solve the above problems, a semiconductor module according to a preferred embodiment of the present disclosure comprises: at least one substrate having a first electrode pattern, a second electrode pattern, and a third electrode pattern, wherein the first electrode pattern is located between the second electrode pattern and the third electrode pattern in a planar view; and a plurality of semiconductor switching elements each having a first surface bonded to the first electrode pattern and a second surface facing in the opposite direction to the first surface, wherein the second surface is provided with a control electrode, control wiring connected to the control electrode, and a main electrode having a plurality of regions separated by the control wiring, each of the plurality of regions being electrically connected to the second electrode pattern via a first wire and electrically connected to the third electrode pattern via a second wire, wherein the second electrode pattern is a pattern for a main current, and the third electrode pattern is used as an auxiliary pattern for control. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor module according to an embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor module according to the embodiment, with a portion thereof omitted. [Figure 3] FIG. 2 is a circuit diagram of an upper arm of the semiconductor module. [Figure 4] FIG. 10 is a circuit diagram of an upper arm of a semiconductor module having a configuration in which an auxiliary control terminal is connected to a main current path. [Figure 5] FIG. 10 is a side view illustrating a semiconductor switching element and a semiconductor element on a substrate for an upper arm. [Figure 6] FIG. 10 is a plan view showing the configuration on the substrate for the upper arm. [Figure 7] FIG. 10 is a plan view showing the configuration on the substrate for the lower arm. [Figure 8]FIG. 2 is a plan view showing a configuration example of a control terminal. [Figure 9] FIG. 10 is a plan view showing the configuration on a substrate for an upper arm in Modification 1. [Figure 10] FIG. 10 is a plan view showing the configuration on a substrate for a lower arm in Modification 1. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present disclosure will be described below with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual dimensions and are shown schematically to facilitate understanding. Furthermore, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0010] 1. Embodiment 1-1. Overall configuration of semiconductor module FIG. 1 is a cross-sectional view of a semiconductor module 10 according to an embodiment. FIG. 2 is a partially omitted plan view of the semiconductor module 10 according to an embodiment. Note that, for ease of viewing, FIG. 1 omits wires 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, and 95 (described below) and indicates the outlines of a case 50 and a lid 60 (described below) by a two-dot chain line. In FIG. 2, for ease of explanation, the case 50, the lid 60, main terminals 71, 72, and 73, and control terminals 81, 82, 83, and 84 (described below) are omitted.

[0011] The semiconductor module 10 is a power module such as an IGBT (Insulated Gate Bipolar Transistor) module, and is used for power control in devices such as inverters or rectifiers mounted on equipment such as industrial equipment, railway vehicles, automobiles, and household electrical machines.

[0012] As shown in Figures 1 and 2, the semiconductor module 10 includes two substrates 20a, two substrates 20b, eight semiconductor switching elements 31a, eight semiconductor switching elements 31b, eight semiconductor elements 32a, eight semiconductor elements 32b, a base 40, a case 50, a lid 60, main terminals 71, 72, 73, control terminals 81, 82, 83, 84, and wires 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, 95.

[0013] Here, each of the control terminals 82 and 84 is an example of a "first control terminal." Each of the control terminals 81 and 83 is an example of a "second control terminal." Each of the wires 91a and 91b is an example of a "first wire." Each of the wires 92a and 92b is an example of a "second wire." Each of the wires 93a and 93b is an example of a "third wire." Each of the wires 94a and 94b is an example of a "fourth wire."

[0014] Eight semiconductor switching elements 31a and eight semiconductor elements 32a are mounted separately on two substrates 20a and electrically connected in parallel by wires 91a, 92a, 93a, and 94a to form the upper arm of the inverter circuit. Meanwhile, eight semiconductor switching elements 31b and eight semiconductor elements 32b are mounted separately on two substrates 20b and electrically connected in parallel by wires 91b, 92b, 93b, and 94b to form the lower arm of the inverter circuit. The upper and lower arms are electrically connected by wire 95.

[0015] First, the outline of each part of the semiconductor module 10 will be sequentially explained with reference to FIGS. 1 and 2. Hereinafter, for convenience of explanation, the mutually orthogonal X-axis, Y-axis, and Z-axis will be appropriately used. The Z-axis is an axis parallel to the thickness direction or height direction of the semiconductor module 10. Hereinafter, one direction along the X-axis is the X1 direction, and the direction opposite to the X1 direction is the X2 direction. One direction along the Y-axis is the Y1 direction, and the direction opposite to the Y1 direction is the Y2 direction. One direction along the Z-axis is the Z1 direction, and the direction opposite to the Z1 direction is the Z2 direction. The relationship between these directions and the vertical direction is not particularly limited and is arbitrary. Hereinafter, viewing in the direction along the Z-axis may be referred to as a "planar view."

[0016] Each of the two boards 20a is housed in the case 50 and is a board on which four semiconductor switching elements 31a and four semiconductor elements 32a are mounted. Similarly, each of the two boards 20b is housed in the case 50 and is a board on which four semiconductor switching elements 31b and four semiconductor elements 32b are mounted.

[0017] 1 and 2, two substrates 20a are aligned in the direction along the Y axis, and two substrates 20b are aligned in the direction along the Y axis at a position in the X2 direction relative to the two substrates 20a. Here, one of the two substrates 20a is disposed in a position in the X1 direction relative to one of the two substrates 20b, and the other substrate 20b is disposed in a position in the X1 direction relative to the other substrate 20b.

[0018] Each of the substrates 20a and 20b is a laminated substrate such as a DCB (Direct Copper Bonding) substrate or a DBA (Direct Bonded Aluminum) substrate. Specifically, as shown in Fig. 2, the substrate 20a has an insulating plate 21a, a wiring layer 22a, and a heat dissipation layer 23a. Similarly, the substrate 20b has an insulating plate 21b, a wiring layer 22b, and a heat dissipation layer 23b.

[0019] Each of insulating plate 21a and insulating plate 21b is an insulating plate-shaped member and is made of ceramics such as aluminum nitride, aluminum oxide, or silicon nitride. A wiring layer 22a is provided on one surface of insulating plate 21a, and a heat dissipation layer 23a is provided on the other surface. Similarly, a wiring layer 22b is provided on one surface of insulating plate 21b, and a heat dissipation layer 23b is provided on the other surface. Each of wiring layers 22a, 22b and heat dissipation layers 23a, 23b is made of metal such as copper or aluminum.

[0020] The wiring layer 22a is a conductive layer for mounting the semiconductor switching element 31a and the semiconductor element 32a. The main terminal 71 and the control terminals 81 and 82 are joined to the wiring layer 22a with a conductive bonding material such as solder. The heat dissipation layer 23a is a thermally conductive layer for dissipating heat from the semiconductor switching element 31a and the semiconductor element 32a to the base 40, and is joined to the base 40 with a conductive bonding material such as solder.

[0021] Similarly, wiring layer 22b is a conductive layer for mounting semiconductor switching element 31b and semiconductor element 32b. Main terminals 72 and 73 and control terminals 83 and 84 are joined to wiring layer 22b with a conductive bonding material such as solder. Heat dissipation layer 23b is a thermally conductive layer for dissipating heat from semiconductor switching element 31b and semiconductor element 32b to base 40, and is joined to base 40 with a conductive bonding material such as solder.

[0022] 2, the wiring layer 22a has electrode patterns 22a1, 22a2, 22a3, and 22a4 that are spaced apart from one another. Similarly, the wiring layer 22b has electrode patterns 22b1, 22b2, 22b3, and 22b4 that are spaced apart from one another.

[0023] Here, electrode pattern 22a1 and electrode pattern 22b1 are each an example of a "first electrode pattern." Electrode pattern 22a2 and electrode pattern 22b2 are each an example of a "second electrode pattern." Electrode patterns 22a1, 22b1, 22a2, and 22b2 are each a pattern for a main current. The main current is the maximum current flowing through semiconductor switching element 31a or semiconductor switching element 31b, such as the current flowing between the emitter electrode and the collector electrode or the current flowing between the source electrode and the drain electrode. Electrode pattern 22a3 and electrode pattern 22b3 are each an example of a "third electrode pattern" and are used as auxiliary control patterns. Electrode pattern 22a4 and electrode pattern 22b4 are each an example of a "fourth electrode pattern" and are used as main control patterns. Details of these electrode patterns will be described later with reference to FIGS. 5 to 7.

[0024] The back surfaces of the semiconductor switching element 31a and the semiconductor element 32a are joined to the electrode pattern 22a1 of the wiring layer 22a with a conductive bonding material such as solder. Similarly, the back surfaces of the semiconductor switching element 31b and the semiconductor element 32b are joined to the electrode pattern 22b1 of the wiring layer 22b with a conductive bonding material such as solder.

[0025] In Figure 2, the main terminals 71, 72, 73 and the control terminals 81, 82, 83, 84 are not shown, but areas CTa, CTb, CTc, CTd, CTe, CTf, and CTg for connecting these terminals to the wiring layers 22a and 22b with a conductive bonding material such as solder are shown.

[0026] The region CTa is a region for joining the main terminal 71 and is provided in the electrode pattern 22a1 of the wiring layer 22a. The region CTb is a region for joining the control terminal 82 and is provided in the electrode pattern 22a3 of the wiring layer 22a. The region CTc is a region for joining the control terminal 81 and is provided in the electrode pattern 22a4 of the wiring layer 22a. The region CTd is a region for joining the main terminal 73 and is provided in the electrode pattern 22b1 of the wiring layer 22b. The region CTe is a region for joining the main terminal 72 and is provided in the electrode pattern 22b2 of the wiring layer 22b. The region CTf is a region for joining the control terminal 84 and is provided in the electrode pattern 22b3 of the wiring layer 22b. The region CTg is a region for joining the control terminal 83 and is provided in the electrode pattern 22b4 of the wiring layer 22b.

[0027] Each of the semiconductor switching elements 31a and 31b is a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). An input electrode is provided on the back surface (first surface) of each of the semiconductor switching elements 31a and 31b. The input electrode is a drain electrode or a collector electrode. Meanwhile, an output electrode (main electrode) and a control electrode are provided on the front surface (second surface) of each of the semiconductor switching elements 31a and 31b. The output electrode is a source electrode or an emitter electrode. The control electrode is a gate electrode. Details of the front surfaces will be described with reference to FIGS. 6 and 7.

[0028] Each of the semiconductor elements 32a and 32b is a free wheeling diode (FWD). An output electrode is provided on the rear surface (third surface) of each of the semiconductor elements 32a and 32b. The output electrode is a cathode electrode. Meanwhile, an input electrode is provided on the front surface (fourth surface) of each of the semiconductor elements 32a and 32b. The input electrode is an anode electrode.

[0029] The base 40 is a plate-like member for heat dissipation and constitutes the bottom plate of the semiconductor module 10. The two substrates 20a and two substrates 20b described above are bonded to the upper surface of the base 40. Meanwhile, a heat dissipation member such as a heat dissipation fin (not shown) may be disposed on the lower surface of the base 40. The base 40 is a metal plate made of, for example, copper, a copper alloy, aluminum, or an aluminum alloy. The base 40 has thermal conductivity and dissipates heat from the semiconductor switching elements 31a, 31b and the semiconductor elements 32a, 32b. The base 40 also has conductivity and may be electrically connected to a reference potential such as a ground potential.

[0030] In the example shown in FIG. 2, the thickness direction of the base 40 is along the Z-axis. When viewed in the direction along the Z-axis, the base 40 has a shape having a pair of long sides extending in the direction along the X-axis and a pair of short sides extending in the direction along the Y-axis. Mounting holes 41 are provided in the base 40 near each corner. The mounting holes 41 are, for example, through holes used to screw a heat dissipation member such as a heat dissipation fin (not shown) to the base 40. The planar shape of the base 40 is not limited to the example shown in FIG. 2 and can be any shape. The mounting holes 41 may be provided as needed or may be omitted.

[0031] Case 50 is a frame-shaped member that defines an internal space that houses semiconductor switching elements 31a, 31b and semiconductor elements 32a, 32b. Case 50 is essentially an insulator and is made of a resin material such as PPS (Polyphenylene Sulfide) or PBT (Polybutylene Terephthalate), and is obtained by injection molding or the like. Case 50 may be integrally formed with main terminals 71, 72, 73 and control terminals 81, 82, 83, 84 by insert molding or the like. The resin material may contain inorganic fibers such as glass fibers or inorganic fillers such as alumina or silica to improve the mechanical strength or thermal conductivity of case 50.

[0032] The case 50 may be filled with a sealing resin. The sealing resin is a potting material that covers the semiconductor switching elements 31a, 31b and the semiconductor elements 32a, 32b, and is made of a thermosetting resin such as an epoxy resin or a silicone resin. The sealing resin preferably contains an inorganic filler such as silica or alumina to enhance thermal conductivity. The sealing resin may also be in a gel form.

[0033] Although not shown, the internal space of the case 50 is open in both the Z1 and Z2 directions. The base 40 is bonded to the case 50 with an adhesive or the like so as to close the opening of the case 50 facing the Z2 direction. The lid 60 is also bonded to the case 50 with an adhesive or the like so as to close the opening of the case 50 facing the Z1 direction.

[0034] The lid 60 is a member that closes an opening of the case 50 facing the Z1 direction. Like the case 50, the lid 60 is made of a resin material such as PPS (Polyphenylene Sulfide) or PBT (Polybutylene Terephthalate). In the example shown in FIG. 1, the lid 60 has a function of supporting a portion of the main terminals 71, 72, and 73. Here, the lid 60 may be a nut case for screwing the main terminals 71, 72, and 73 to a bus bar (not shown).

[0035] Each of the main terminals 71, 72, and 73 is a terminal for connecting a bus bar (not shown) to the semiconductor module 10, and has a portion exposed to the outside of the semiconductor module 10. In the example shown in FIG. 1 , the main terminals 71, 72, and 73 penetrate the lid 60, and a portion of the main terminals 71, 72, and 73 is exposed to the outside of the semiconductor module 10.

[0036] The main terminal 71 is a high-potential terminal and is joined to the aforementioned region CTa. The main terminal 72 is a low-potential terminal and is joined to the aforementioned region CTe. The main terminal 73 is an output terminal and is joined to the aforementioned region CTd. Each of the main terminals 71, 72, and 73 is made of a metal such as copper, copper alloy, aluminum, aluminum alloy, or iron alloy, and is obtained by bending a metal plate, for example.

[0037] Each of the control terminals 81 and 82 is a terminal for connecting the semiconductor module 10 to a control circuit (not shown) that controls the operation of the semiconductor switching element 31a. The control circuit is installed outside the semiconductor module 10. The control terminal 81 has a terminal portion 81a exposed to the outside of the semiconductor module 10. A signal for controlling the operation of the semiconductor switching element 31a is supplied to the control terminal 81 from the control circuit. The control terminal 82 has a terminal portion 82a exposed to the outside of the semiconductor module 10. A constant potential that serves as a reference for the signal is supplied to the control terminal 82 from the control circuit.

[0038] Similarly, each of the control terminals 83 and 84 is a terminal for connecting a control circuit (not shown) that controls the operation of the semiconductor switching element 31b to the semiconductor module 10. The control circuit is installed outside the semiconductor module 10. Here, the control terminal 83 has a terminal portion 83a exposed to the outside of the semiconductor module 10. A signal for controlling the operation of the semiconductor switching element 31b is supplied to the control terminal 83 from the control circuit. The control terminal 84 has a terminal portion 84a exposed to the outside of the semiconductor module 10. A constant potential that serves as a reference for the signal is supplied to the control terminal 84 from the control circuit.

[0039] Like the main terminals 71, 72, and 73, the control terminals 81, 82, 83, and 84 are each made of a metal such as copper, copper alloy, aluminum, aluminum alloy, or iron alloy, and are obtained by bending a metal plate.

[0040] Each of the wires 91a, 91b, 92a, 92b, 93a, 93b, 94a, 94b, and 95 is a conductive wire or a group of wires that is made up of at least one bonding wire.

[0041] Wire 91a is bonded to electrode pattern 22a2 of wiring layer 22a and to the output electrode of semiconductor switching element 31a. This bonding electrically connects electrode pattern 22a2 and the output electrode of semiconductor switching element 31a via wire 91a. Similarly, wire 91b is bonded to electrode pattern 22b2 of wiring layer 22b and to the output electrode of semiconductor switching element 31b. This bonding electrically connects electrode pattern 22b2 and the output electrode of semiconductor switching element 31b via wire 91b.

[0042] Wire 92a is bonded to each of the output electrodes of semiconductor switching element 31a, semiconductor element 32a, and electrode pattern 22a3 of wiring layer 22a. This bonding electrically connects the output electrodes of semiconductor switching element 31a, semiconductor element 32a, and electrode pattern 22a3 via wire 92a. Similarly, wire 92b is bonded to each of the output electrodes of semiconductor switching element 31b, semiconductor element 32b, and electrode pattern 22b3 of wiring layer 22b. This bonding electrically connects the output electrodes of semiconductor switching element 31b, semiconductor element 32b, and electrode pattern 22b3 via wire 92b.

[0043] Wire 93a is bonded to electrode pattern 22a4 of wiring layer 22a and to the control electrode of semiconductor switching element 31a. This bonding electrically connects electrode pattern 22a4 and the control electrode of semiconductor switching element 31a via wire 93a. Similarly, wire 93b is bonded to electrode pattern 22b4 of wiring layer 22b and to the control electrode of semiconductor switching element 31b. This bonding electrically connects electrode pattern 22b4 and the control electrode of semiconductor switching element 31b via wire 93b.

[0044] The wire 94a is bonded to the electrode patterns 22a4 of the two substrates 20a. As a result of this bonding, the electrode patterns 22a4 of the two substrates 20a are electrically connected to each other via the wire 94a. Similarly, the wire 94b is bonded to the electrode patterns 22b4 of the two substrates 20b. As a result of this bonding, the electrode patterns 22b4 of the two substrates 20b are electrically connected to each other via the wire 94b.

[0045] Wire 95 is bonded to electrode pattern 22a2 and electrode pattern 22b1 of substrate 20a and substrate 20b adjacent to each other in the direction along the X-axis. By this bonding, electrode pattern 22a2 and electrode pattern 22b1 of substrate 20a and substrate 20b adjacent to each other in the direction along the X-axis are electrically connected via wire 95.

[0046] As described above, electrode pattern 22a2 is electrically connected to the output electrode of semiconductor switching element 31a. In contrast, electrode pattern 22b1 is electrically connected to the input electrode of semiconductor switching element 31b. Therefore, for substrates 20a and 20b adjacent to each other in the direction along the X-axis, semiconductor switching elements 31a and 31b are electrically connected in series with each other.

[0047] In the semiconductor module 10, as described above, in the upper arm, the electrode pattern 22a3 used as an auxiliary control pattern is separate from the electrode pattern 22a2, so the control terminal 82 is electrically connected to the output electrode of the semiconductor switching element 31a without passing through the main current path. Therefore, the current path for controlling the drive of the semiconductor switching element 31a is less susceptible to current fluctuations in the main current path, thereby improving the switching characteristics of the semiconductor switching element 31a. Similarly, in the lower arm, the electrode pattern 22b3 used as an auxiliary control pattern is separate from the electrode pattern 22b2, so the control terminal 84 is electrically connected to the output electrode of the semiconductor switching element 31b without passing through the main current path. Therefore, the current path for controlling the drive of the semiconductor switching element 31b is less susceptible to current fluctuations in the main current path, thereby improving the switching characteristics of the semiconductor switching element 31b. This point will be described in detail below, taking an example of the upper arm as a representative example, with reference to FIGS. 3 and 4.

[0048] Fig. 3 is a circuit diagram of the upper arm of the semiconductor module 10. Fig. 3 shows the electrical connection configuration of four semiconductor switching elements 31a and four semiconductor elements 32a mounted on one substrate 20a.

[0049] In the example shown in Fig. 3, the semiconductor switching elements 31a are MOSFETs. As shown in Fig. 3, in the upper arm, the control terminal 82 is electrically connected to the sources of the four semiconductor switching elements 31a via the electrode pattern 22a3 without passing through the main current path. Therefore, the main current path does not intervene in the current path for controlling the driving of the semiconductor switching elements 31a. Therefore, the current path for controlling the driving of the semiconductor switching elements 31a is less susceptible to the influence of current fluctuations in the main current path.

[0050] Here, the path length of the main current path differs for each semiconductor switching element 31a. Therefore, the main current path has a different parasitic inductance L for each semiconductor switching element 31a. As a result, when a fluctuation in the main current occurs, a back electromotive force of a different magnitude is generated in the parasitic inductance L for each semiconductor switching element 31a.

[0051] However, in the semiconductor module 10, as described above, the main current path is not interposed in the current path for controlling the operation of the semiconductor switching elements 31a, so the current path for controlling the operation of the semiconductor switching elements 31a is not affected by the back electromotive force. This reduces current exchange and imbalance between the gates of the four semiconductor switching elements 31a, which are electrically connected in parallel, thereby preventing oscillation due to repeated charging and discharging. Furthermore, by arranging the current paths for controlling the operation of the semiconductor switching elements 31a close to each other among the four semiconductor switching elements 31a, the loop formed by the current paths can be reduced. As a result, electromagnetic radiation noise from peripheral circuits is less likely to be interlinked, reducing the risk of false firing and other problems. Furthermore, the above-mentioned effects also have the advantage of eliminating the need for wires to bridge the sources of the semiconductor switching elements 31a.

[0052] 4 is a circuit diagram of the upper arm of a semiconductor module 10X having a configuration in which an auxiliary control terminal 82X is connected to the main current path. The semiconductor module 10X has the same configuration as the semiconductor module 10, except that it has a control terminal 82X instead of the control terminal 82.

[0053] 4, in the upper arm of the semiconductor module 10X, the control terminal 82X is electrically connected to the sources of the four semiconductor switching elements 31a via the main current path, so that a parasitic inductance L of the main current path is present in the current path for controlling the driving of the semiconductor switching elements 31a.

[0054] Therefore, in the semiconductor module 10X, when a back electromotive force is generated in the parasitic inductance L due to fluctuations in the main current, current flows and an imbalance occurs between the gates of the four semiconductor switching elements 31a electrically connected in parallel, as indicated by the dashed arrows in Fig. 4. Therefore, in the semiconductor module 10X, oscillation caused by repeated charging and discharging increases the risk of false firing and element damage.

[0055] 1-2. Electrode pattern and wire details Fig. 5 is a side view illustrating semiconductor switching element 31a and semiconductor element 32a on upper arm substrate 20a. Fig. 6 is a plan view showing the configuration on upper arm substrate 20a. Note that wires 91a, 92a, 93a, 94a, and 95 are omitted from Fig. 5 for ease of viewing.

[0056] As shown in FIGS. 5 and 6, the electrode pattern 22a2, the electrode pattern 22a1, the electrode pattern 22a3, and the electrode pattern 22a4 are arranged in this order in the X1 direction.

[0057] 6, electrode pattern 22a3 and electrode pattern 22a4 each have an elongated shape extending in the direction along the Y-axis. Furthermore, both ends of electrode pattern 22a2, electrode pattern 22a1, electrode pattern 22a3, and electrode pattern 22a4 in the direction along the Y-axis are aligned. Therefore, electrode patterns 22a2, electrode pattern 22a1, electrode pattern 22a3, and electrode pattern 22a4 have the same length in the direction along the Y-axis. Furthermore, any one of electrode patterns 22a2, electrode pattern 22a1, electrode pattern 22a3, and electrode pattern 22a4 is provided across the entire area of ​​any other electrode pattern in the direction along the Y-axis.

[0058] The shapes of electrode pattern 22a1, electrode pattern 22a2, electrode pattern 22a3, and electrode pattern 22a4 are not limited to the example shown in Fig. 6. For example, electrode pattern 22a2, electrode pattern 22a1, electrode pattern 22a3, and electrode pattern 22a4 may have different lengths in the direction along the Y axis.

[0059] A plurality of semiconductor switching elements 31a and a plurality of semiconductor elements 32a are joined to the electrode pattern 22a1 via a conductive bonding material such as solder. In the example shown in Fig. 6, four semiconductor switching elements 31a are aligned in the direction along the Y axis, and four semiconductor elements 32a are aligned in the direction X1 relative to the four semiconductor switching elements 31a in the direction along the Y axis.

[0060] The semiconductor switching element 31a has a first surface F1 and a second surface F2. The first surface F1 is the surface of the semiconductor switching element 31a that is bonded to the electrode pattern 22a1. In the example shown in FIG. 5, the first surface F1 faces the Z2 direction. Although not shown, as described above, an input electrode that is a drain electrode or a collector electrode is provided on the first surface F1. The second surface F2 is the surface of the semiconductor switching element 31a that faces in the opposite direction to the first surface F1. As shown in FIG. 6, a control electrode 311, a control wiring 312, and a main electrode 313 are provided on the second surface F2.

[0061] The control electrode 311 is a gate electrode. A control voltage is input to the control electrode 311 from a control circuit (not shown). The control electrode 311 is made of a metal such as aluminum. In the example shown in FIG. 6, the control electrode 311 is disposed at the end of the second surface F2 in the Y1 direction or the Y2 direction. The shape and arrangement of the control electrode 311 are not limited to the example shown in FIG. 6. For example, the control electrode 311 may be disposed at the end of the second surface F2 in the X1 direction or the X2 direction.

[0062] The control electrode 311 is electrically connected to the electrode pattern 22a4 via a wire 93a. Here, the wire 93a has one end joined to the electrode pattern 22a4 and the other end joined to the control electrode 311. In the example shown in Fig. 6, the wire 93a is configured by one wire for each control electrode 311. Note that the number of wires configuring the wire 93a for each control electrode 311 may be two or more.

[0063] The control wiring 312 is a wiring connected to the control electrode 311. The control wiring 312 is, for example, a laminate of a gate runner made of a semiconductor such as impurity-doped polysilicon and a gate metal layer made of a metal such as aluminum provided on the gate runner. In the example shown in FIG. 6, the control wiring 312 extends in the Y1 direction or the Y2 direction from the control electrode 311. The shape of the control wiring 312 in a planar view is determined depending on the number and shape of regions RE (described later), and is not limited to the example shown in FIG. 6. For example, the control wiring 312 may have a portion that follows the outer edge of the main electrode 313 in a planar view.

[0064] The main electrode 313 is a source electrode or emitter electrode, and outputs a main current when the semiconductor switching element 31a is in an on state. The main electrode 313 is made of a metal such as aluminum, an aluminum alloy, titanium, or a titanium alloy. The main electrode 313 is divided by control wiring 312 in a plan view and has a plurality of regions RE_1 and RE_2. Hereinafter, the regions RE_1 and RE_2 may each be referred to as a region RE.

[0065] 6 illustrates an example in which the main electrode 313 is divided into two regions RE, but the present invention is not limited to this example. For example, the main electrode 313 may have three or more regions RE. That is, the number of divisions of the main electrode 313 is not limited to two, and may be three or more.

[0066] In the example shown in FIG. 6, regions RE_1 and RE_2 are arranged in this order in the X1 direction. Regions RE_1 and RE_2 each extend in the direction along the Y axis. Regions RE_1 and RE_2 have the same shape in a planar view. Regions RE_1 and RE_2 each form a rectangle in a planar view. Note that the shape of regions RE_1 and RE_2 in a planar view is not limited to the example shown in FIG. 6, and for example, regions RE_1 and RE_2 may have different shapes in a planar view. Regions RE_1 and RE_2 may also extend in the direction along the X axis.

[0067] Although not shown, the semiconductor switching element 31a includes a plurality of transistor units constituting transistors such as IGBTs or power MOSFETs corresponding to the plurality of regions RE. Each region RE is electrically connected to the source region or emitter region of the corresponding transistor unit. The plurality of regions RE are electrically insulated from one another on the second face F2 and output main currents independently of one another. Furthermore, the gates of the plurality of transistor units are electrically connected to a control wiring 312. As a result, the gates are electrically connected to the control electrode 311 via the control wiring 312. Note that the semiconductor switching element 31a may be provided with a diode unit such as an FWD in addition to the transistor unit for each region RE.

[0068] Each of the region RE_1 and the region RE_2 is electrically connected to the electrode pattern 22a2 via a wire 91a, and is also electrically connected to the electrode pattern 22a3 via a wire 92a.

[0069] Here, the wire 91a has one end joined to the electrode pattern 22a2 and the other end joined to the region RE. In the example shown in Fig. 6, the wire 91a is configured with two wires for each region RE. Note that the number of wires constituting the wire 91a for each region RE may be one, or may be three or more.

[0070] The wire 92a has one end joined to the electrode pattern 22a3 and the other end joined to the region RE. In the example shown in Fig. 6, the wire 92a is configured with two wires for each region RE. Note that the number of wires constituting the wire 92a for each region RE may be one, or may be three or more.

[0071] Here, the wire 92a is joined at a midpoint to the semiconductor element 32a by stitch bonding. The midpoint of the wire 92a refers to any position between one end and the other end of the wire 92a. As shown in FIG. 5, the semiconductor element 32a has a third surface F3 and a fourth surface F4. The third surface F3 is the surface of the semiconductor element 32a that is joined to the electrode pattern 22a1. In the example shown in FIG. 5, the third surface F3 faces the Z2 direction. As described above, an output electrode serving as a cathode electrode (not shown) is provided on the third surface F3. The fourth surface F4 is the surface of the semiconductor element 32a that faces the opposite direction from the third surface F3. As described above, an input electrode serving as an anode electrode (not shown) is provided on the fourth surface F4, and the wire 92a is joined at a midpoint.

[0072] Although not shown in Fig. 6, the electrode patterns 22a1 of the two substrates 20a are electrically connected to each other via the main terminals 71. In Fig. 6, the region CTa for joining the main terminals 71 is shown shaded. In the example shown in Fig. 6, the region CTa is located at the center of the electrode pattern 22a1 in the direction along the Y axis. Note that the position of the region CTa is not limited to the example shown in Fig. 6, and may be, for example, a position shifted from the center of the electrode pattern 22a1 in the direction along the Y axis.

[0073] Although not shown in Fig. 6, the electrode patterns 22a3 of the two substrates 20a are electrically connected to each other via the control terminals 82. In Fig. 6, a region CTb for joining the control terminals 82 is shown shaded. In the example shown in Fig. 6, the region CTb is located at the center of the electrode pattern 22a3 in the direction along the Y axis. Note that the position of the region CTb is not limited to the example shown in Fig. 6, and may be, for example, a position shifted from the center of the electrode pattern 22a3 in the direction along the Y axis.

[0074] In this embodiment, the electrode patterns 22a3 of the two substrates 20a are electrically connected to each other not only via the control terminals 82 but also via a wire 94a, which is an example of a "fourth wire." The wire 94a has one end joined to the electrode pattern 22a3 of one of the two substrates 20a, and the other end joined to the electrode pattern 22a3 of the other substrate 20a. In the example shown in FIG. 6, the wire 94a is composed of a single wire. Note that the number of wires constituting the wire 94a may be two or more.

[0075] Furthermore, although not shown in Fig. 6, the electrode patterns 22a4 of the two substrates 20a are electrically connected to each other via the control terminals 81. In Fig. 6, a region CTc for joining the control terminals 81 is shown shaded. In the example shown in Fig. 6, the region CTc is located at the center of the electrode pattern 22a4 in the direction along the Y axis. Note that the position of the region CTc is not limited to the example shown in Fig. 6, and may be, for example, a position shifted from the center of the electrode pattern 22a4 in the direction along the Y axis.

[0076] Furthermore, electrode pattern 22a2 of substrate 20a is electrically connected to electrode pattern 22b1 of substrate 20b (described later) via wire 95. Wire 95 has one end joined to electrode pattern 22a2 of substrate 20a and the other end joined to electrode pattern 22b1 of substrate 20b. In the example shown in FIG. 6, wire 95 is made up of multiple wires. Note that the number and arrangement of wires constituting wire 95 are not limited to the example shown in FIG. 6 and are arbitrary.

[0077] Fig. 7 is a plan view showing the configuration on the substrate 20b for the lower arm. As shown in Fig. 7, the electrode pattern 22b2, the electrode pattern 22b1, the electrode pattern 22b3, and the electrode pattern 22b4 are arranged in this order in the X2 direction.

[0078] In the example shown in FIG. 7, electrode patterns 22b3 and 22b4 each have an elongated shape extending in the direction along the Y-axis. Furthermore, both ends of electrode patterns 22b1, 22b3, and 22b4 in the direction along the Y-axis are aligned. Therefore, electrode patterns 22b1, 22b3, and 22b4 have the same length in the direction along the Y-axis. Any one of electrode patterns 22b1, 22b3, and 22b4 is provided over the entire area of ​​any other electrode pattern in the direction along the Y-axis. Furthermore, the length of electrode patterns 22b1, 22b3, and 22b4 in the direction along the Y-axis is longer than the length of electrode pattern 22b2 in the direction along the Y-axis. Furthermore, the ends of electrode patterns 22b1 and 22b2 in the X1 direction are aligned.

[0079] The shapes of the electrode pattern 22b1, the electrode pattern 22b2, the electrode pattern 22b3, and the electrode pattern 22b4 are not limited to the example shown in Fig. 7. For example, the lengths of the electrode pattern 22b1, the electrode pattern 22b3, and the electrode pattern 22b4 in the direction along the Y axis may be different from one another.

[0080] A plurality of semiconductor switching elements 31b and a plurality of semiconductor elements 32b are joined to the electrode pattern 22b1 via a conductive bonding material such as solder. In the example shown in Fig. 7, four semiconductor switching elements 31b are aligned in the direction along the Y axis, and four semiconductor elements 32b are aligned in the direction X2 relative to the four semiconductor switching elements 31b in the direction along the Y axis.

[0081] Although not shown, the semiconductor switching element 31b has a first surface F1 and a second surface F2, similar to the semiconductor switching element 31a.

[0082] Each of the regions RE_1 and RE_2 of the semiconductor switching element 31b is electrically connected to the electrode pattern 22b2 via a wire 91b, and is also electrically connected to the electrode pattern 22b3 via a wire 92b.

[0083] Here, the wire 91b has one end joined to the electrode pattern 22b2 and the other end joined to the region RE. As a result, the electrode pattern 22b2 and each region RE are electrically connected via the wire 91b. In the example shown in Fig. 7, the wire 91b is configured by two wires for each region RE. Note that the number of wires constituting the wire 91b for each region RE may be one, or may be three or more.

[0084] The wire 92b has one end joined to the electrode pattern 22b3 and the other end joined to the region RE. This electrically connects the electrode pattern 22b3 to each region RE via the wire 92b. In the example shown in Fig. 7, the wire 92b is configured with two wires for each region RE. Note that the number of wires constituting the wire 92b for each region RE may be one, or may be three or more.

[0085] Here, the middle of the wire 92b is joined to the semiconductor element 32b by stitch bonding. The middle of the wire 92b refers to any position between one end and the other end of the wire 92b. Although not shown, the semiconductor element 32b has a third face F3 and a fourth face F4, similar to the semiconductor element 32a. The middle of the wire 92b is joined to the fourth face F4 of the semiconductor element 32b.

[0086] Although not shown in Fig. 7, the electrode patterns 22b1 of the two substrates 20b are electrically connected to each other via the main terminals 73. In Fig. 7, a region CTd for joining the main terminals 73 is shown shaded. In the example shown in Fig. 7, the region CTd is located at the center of the electrode pattern 22b1 in the direction along the Y axis. Note that the position of the region CTd is not limited to the example shown in Fig. 7, and may be, for example, a position shifted from the center of the electrode pattern 22b1 in the direction along the Y axis.

[0087] Although not shown in Fig. 7, the electrode patterns 22b2 of the two substrates 20b are electrically connected to each other via the main terminals 72. In Fig. 7, the region CTe for joining the main terminals 72 is shown shaded. In the example shown in Fig. 7, the region CTe is located at the center of the electrode pattern 22b1 in the direction along the Y axis. Note that the position of the region CTe is not limited to the example shown in Fig. 7, and may be, for example, a position shifted from the center of the electrode pattern 22b1 in the direction along the Y axis.

[0088] Furthermore, although not shown in Fig. 7, the electrode patterns 22b3 of the two substrates 20b are electrically connected to each other via the control terminal 84. In Fig. 7, the region CTf for joining the control terminal 84 is shown shaded. In the example shown in Fig. 7, the region CTf is located at the center of the electrode pattern 22b3 in the direction along the Y axis. Note that the position of the region CTf is not limited to the example shown in Fig. 7, and may be, for example, a position shifted from the center of the electrode pattern 22b3 in the direction along the Y axis.

[0089] In this embodiment, the electrode patterns 22b3 of the two substrates 20b are electrically connected to each other not only via the control terminal 84 but also via a wire 94b, which is an example of a "fourth wire." The wire 94b has one end joined to the electrode pattern 22b3 of one of the two substrates 20b, and the other end joined to the electrode pattern 22b3 of the other substrate 20b. In the example shown in FIG. 7, the wire 94b is composed of a single wire. Note that the number of wires constituting the wire 94b may be two or more.

[0090] Furthermore, although not shown in Fig. 7, the electrode patterns 22b4 of the two substrates 20b are electrically connected to each other via the control terminal 83. In Fig. 7, a region CTg for joining the control terminal 83 is shown shaded. In the example shown in Fig. 7, the region CTg is located at the center of the electrode pattern 22b4 in the direction along the Y axis. Note that the position of the region CTg is not limited to the example shown in Fig. 7, and may be, for example, a position shifted from the center of the electrode pattern 22b4 in the direction along the Y axis.

[0091] Fig. 8 is a plan view showing an example of the configuration of control terminals 81, 82, 83, and 84. In Fig. 8, for ease of viewing, the control terminals 81, 83 and the control terminals 82, 84 are displayed in gray scales of different densities.

[0092] 8, control terminal 81 is bonded to region CTc of electrode pattern 22a4 of each of the two substrates 20a. Similarly, control terminal 82 is bonded to region CTb of electrode pattern 22a3 of each of the two substrates 20a. Control terminal 83 is bonded to region CTg of electrode pattern 22b4 of each of the two substrates 20b. Control terminal 84 is bonded to region CTf of electrode pattern 22b3 of each of the two substrates 20b.

[0093] As described above, the semiconductor module 10 includes at least one substrate 20a and a plurality of semiconductor switching elements 31a in the upper arm. Similarly, the semiconductor module 10 includes at least one substrate 20b and a plurality of semiconductor switching elements 31b in the lower arm.

[0094] In the upper arm, the at least one substrate 20a has an electrode pattern 22a1 which is an example of a "first electrode pattern," an electrode pattern 22a2 which is an example of a "second electrode pattern," and an electrode pattern 22a3 which is an example of a "third electrode pattern." In a plan view, electrode pattern 22a1 is located between electrode pattern 22a2 and electrode pattern 22a3. Similarly, in the lower arm, the at least one substrate 20b has an electrode pattern 22b1 which is an example of a "first electrode pattern," an electrode pattern 22b2 which is an example of a "second electrode pattern," and an electrode pattern 22b3 which is an example of a "third electrode pattern." In a plan view, electrode pattern 22b1 is located between electrode pattern 22b2 and electrode pattern 22b3.

[0095] In the upper arm, each of the semiconductor switching elements 31a has a first surface F1 bonded to the electrode pattern 22a1 and a second surface F2 facing in the opposite direction from the first surface F1. Similarly, in the lower arm, each of the semiconductor switching elements 31b has a first surface F1 bonded to the electrode pattern 22b1 and a second surface F2 facing in the opposite direction from the first surface F1. The second surface F2 is provided with a control electrode 311, a control wiring 312 connected to the control electrode 311, and a main electrode 313 having a plurality of regions RE separated by the control wiring 312.

[0096] Furthermore, in the upper arm, each of the multiple regions RE is electrically connected to electrode pattern 22a2 via wire 91a, which is an example of a "first wire," and is electrically connected to electrode pattern 22a3 via wire 92a, which is an example of a "second wire." Electrode pattern 22a2 is a pattern for a main current. Electrode pattern 22a3 is used as an auxiliary pattern for control. Similarly, in the lower arm, each of the multiple regions RE is electrically connected to electrode pattern 22b2 via wire 91b, which is an example of a "first wire," and is electrically connected to electrode pattern 22b3 via wire 92b, which is an example of a "second wire." Electrode pattern 22b2 is a pattern for a main current. Electrode pattern 22b3 is used as an auxiliary pattern for control.

[0097] In the above-described semiconductor module 10, the electrode patterns 22a3 and 22b3 electrically connected to the main electrode 313 via a path separate from the main current path are used as auxiliary patterns for control, thereby reducing degradation of switching characteristics due to variations in the parasitic inductance L of the main current path and back electromotive force, etc. Moreover, each of the multiple regions RE of the main electrode 313 is electrically connected to the electrode patterns 22a3 and 22b3 via the wires 92a and 92b, thereby reducing current imbalance within the main electrode 313. As a result, the switching characteristics can be improved.

[0098] As described above, the semiconductor module 10 of this embodiment further includes control terminals 82 and 84, which are examples of "first control terminals." The control terminal 82 is bonded to the electrode pattern 22a3. This has the advantage of making it easier to equalize the currents in the main electrodes 313 among the multiple semiconductor switching elements 31a, compared to a configuration in which the control terminal 82 is electrically connected to the substrate 20a via a pattern other than the electrode pattern 22a3. This advantage contributes to improved switching characteristics. Bonding the control terminal 82 to the electrode pattern 22a3 also has the advantage of simplifying the wiring for the control terminal 82. Bonding the control terminal 84 to the electrode pattern 22b3 also provides the same advantages as bonding the control terminal 82 to the electrode pattern 22a3. Furthermore, using the control terminals 82 and 84 reduces the wiring area on the substrates 20a and 20b, thereby making it easier to secure the area required for mounting semiconductor chips and the like on the substrates 20a and 20b.

[0099] As described above, the electrode pattern 22a3 is elongated. The control terminal 82 is bonded to a portion of the electrode pattern 22a3 closer to the center than to the ends in the longitudinal direction. That is, the distance between the bonded portion of the electrode pattern 22a3 and the control terminal 82 and the center of the electrode pattern 22a3 in the longitudinal direction is smaller than the distance between the bonded portion of the electrode pattern 22a3 and the control terminal 82 and the ends in the longitudinal direction of the electrode pattern 22a3. This has the advantage of easily reducing current imbalance within the electrode pattern 22a3. This advantage contributes to improving switching characteristics. Similarly, the electrode pattern 22b3 is elongated, and the control terminal 84 is bonded to a portion of the electrode pattern 22b3 closer to the center than to the ends in the longitudinal direction. This also reduces current imbalance within the electrode pattern 22b3.

[0100] Furthermore, as described above, the semiconductor module 10 further includes control terminals 81 and 83, which are an example of a "second control terminal." The at least one substrate 20a further includes an electrode pattern 22a4, which is an example of a "fourth electrode pattern." The electrode pattern 22a4 is electrically connected to the control electrode 311 via a wire 93a, which is an example of a "third wire." The control terminal 81 is joined to the electrode pattern 22a4. The electrode pattern 22a3 is located between the electrode patterns 22a1 and 22a4 in a plan view. This allows the electrode patterns 22a3 and 22a4 to be spaced apart from the electrode pattern 22a2 for the main current. As a result, the electrode patterns 22a3 and 22a4 are less susceptible to reactor effects due to fluctuations in the main current, thereby reducing current imbalance and preventing false firing. Furthermore, by placing electrode pattern 22a3 closer to electrode pattern 22a1 than electrode pattern 22a4, wire 93a can be easily formed even if the number of wires constituting wire 92a is large, which facilitates mounting. Furthermore, the length of wire 92a can be shortened compared to a configuration in which electrode pattern 22a4 is located between electrode pattern 22a3 and electrode pattern 22a1 in a plan view. As a result, current imbalances among the main electrodes 313 of multiple semiconductor switching elements 31a can be reduced.

[0101] Similarly, the at least one substrate 20b further includes an electrode pattern 22b4, which is an example of a “fourth electrode pattern.” The electrode pattern 22b4 is electrically connected to the control electrode 311 via a wire 93b, which is an example of a “third wire.” The control terminal 83 is joined to the electrode pattern 22b4. The electrode pattern 22b3 is located between the electrode patterns 22b1 and 22b4 in a plan view. This allows the electrode patterns 22b3 and 22b4 to be spaced apart from the electrode pattern 22b2 for the main current. This reduces the reactor influence caused by fluctuations in the main current in the electrode patterns 22b3 and 22b4, thereby reducing current imbalance and preventing false firing. By locating the electrode pattern 22b3 closer to the electrode pattern 22b1 than the electrode pattern 22b4, the wire 92b can be easily formed even if the number of wires constituting the wire 92b is large, thereby facilitating implementation. Furthermore, the length of the wire 92b can be made shorter than in a configuration in which the electrode pattern 22b4 is located between the electrode pattern 22b3 and the electrode pattern 22b1 in plan view, thereby reducing the imbalance in current between the main electrodes 313 of the multiple semiconductor switching elements 31b.

[0102] As described above, the at least one substrate 20a is made up of a plurality of substrates 20a each having an electrode pattern 22a1, an electrode pattern 22a2, and an electrode pattern 22a3. The control terminal 82 is bonded to the electrode pattern 22a3 of each of the plurality of substrates 20a. This reduces the imbalance in current between the electrode patterns 22a3 of the plurality of substrates 20a.

[0103] Similarly, the at least one substrate 20b is made up of a plurality of substrates 20b each having an electrode pattern 22b1, an electrode pattern 22b2, and an electrode pattern 22b3. The control terminal 84 is bonded to the electrode pattern 22b3 of each of the plurality of substrates 20b. This reduces the imbalance in current among the electrode patterns 22b3 of the plurality of substrates 20b.

[0104] Furthermore, as described above, the semiconductor module 10 further includes wires 94a and 94b, which are an example of a "fourth wire." The wire 94a electrically connects the electrode patterns 22a3 of the multiple substrates 20a to each other. This makes it possible to reduce current imbalances among the electrode patterns 22a3 of the multiple substrates 20a. Similarly, the wire 94b electrically connects the electrode patterns 22b3 of the multiple substrates 20b to each other. This makes it possible to reduce current imbalances among the electrode patterns 22b3 of the multiple substrates 20b.

[0105] As described above, the semiconductor switching elements 31a are electrically connected in parallel. Similarly, the semiconductor switching elements 31b are electrically connected in parallel. In this case, the aforementioned effect of reducing the degradation of switching characteristics due to variations in the parasitic inductance L of the main current path and back electromotive force can be significantly achieved.

[0106] Furthermore, as described above, the wire 92a is formed of a plurality of wires for each of the plurality of regions RE. This makes it possible to effectively reduce current imbalance in the main electrode 313 of the semiconductor switching element 31a. Similarly, the wire 92b is formed of a plurality of wires for each of the plurality of regions RE. This makes it possible to effectively reduce current imbalance in the main electrode 313 of the semiconductor switching element 31b.

[0107] As described above, the semiconductor module 10 further includes a plurality of semiconductor elements 32a in the upper arm. Each of the plurality of semiconductor elements 32a has a third surface F3 bonded to the electrode pattern 22a1 and a fourth surface F4 facing in the opposite direction from the third surface F3. The wire 92a is bonded to the fourth surface F4 at its midpoint. Therefore, even in a configuration including a semiconductor element 32a separate from the semiconductor switching element 31a, it is possible to effectively reduce current imbalance within the main electrode 313 of the semiconductor switching element 31a.

[0108] Similarly, the semiconductor module 10 further includes a plurality of semiconductor elements 32b in the lower arm. Each of the plurality of semiconductor elements 32b has a third surface F3 bonded to the electrode pattern 22b1 and a fourth surface F4 facing in the opposite direction from the third surface F3. The wire 92b is bonded to the fourth surface F4 at its midpoint. Therefore, even in a configuration including the semiconductor element 32b separate from the semiconductor switching element 31b, it is possible to effectively reduce current imbalance within the main electrode 313 of the semiconductor switching element 31b.

[0109] 2. Variations The present disclosure is not limited to the above-described embodiments, and various modifications are possible as described below. In addition, the embodiments and modifications may be combined as appropriate.

[0110] 2-1. Variation 1 Fig. 9 is a plan view showing the configuration on the upper arm substrate 20a in Modification 1. Fig. 10 is a plan view showing the configuration on the lower arm substrate 20b in Modification 1.

[0111] Modification 1 is similar to the above-described embodiment except that the arrangement of electrode patterns 22a3 and 22a4 is reversed and the arrangement of electrode patterns 22b3 and 22b4 is reversed.

[0112] The above-described first modification also improves switching characteristics, similar to the above-described embodiment. In the first modification, as described above, the electrode pattern 22a4, which is an example of a “fourth electrode pattern,” is located between the electrode pattern 22a1, which is an example of a “first electrode pattern,” and the electrode pattern 22a3, which is an example of a “third electrode pattern,” in a plan view. This allows the electrode patterns 22a3 and 22a4 to be spaced apart from the electrode pattern 22a2 for the main current. This reduces the reactor influence caused by fluctuations in the main current in the electrode patterns 22a3 and 22a4, thereby reducing current imbalance and preventing false ignition. Furthermore, by locating the electrode pattern 22a3 farther from the electrode pattern 22a1 than the electrode pattern 22a4, the wire 92a can be easily joined to the electrode pattern 22a3, even if the diameter of the wire constituting the wire 92a exceeds 400 μm. Moreover, the area between the electrode pattern 22a1 and the electrode pattern 22a3 is effectively utilized by the electrode pattern 22a4, which allows the board 20a to be made smaller.

[0113] Similarly, as described above, electrode pattern 22b4, an example of a “fourth electrode pattern,” is located between electrode pattern 22b1, an example of a “first electrode pattern,” and electrode pattern 22b3, an example of a “third electrode pattern,” in a plan view. Therefore, electrode pattern 22b3 and electrode pattern 22b4 can be located farther away from electrode pattern 22b2 for the main current. As a result, electrode patterns 22b3 and 22b4 are less susceptible to reactor effects due to fluctuations in the main current, thereby reducing current imbalance and preventing false arcing. Furthermore, by locating electrode pattern 22b3 farther away from electrode pattern 22b1 than electrode pattern 22b4, wire 92b can be easily joined to electrode pattern 22b3 even if the diameter of the wire constituting wire 92b exceeds 400 μm. Furthermore, electrode pattern 22b4 effectively utilizes the area between electrode pattern 22b1 and electrode pattern 22b3, thereby enabling the board 20b to be miniaturized.

[0114] 2-2. Variation 2 In the above-described embodiment, the number of semiconductor switching elements 31a or semiconductor elements 32a mounted on the substrate 20a is four, but the number may be one to three, or five or more. Similarly, the number of semiconductor switching elements 31b or semiconductor elements 32b mounted on the substrate 20b is four, but the number may be one to three, or five or more.

[0115] 2-3. Variation 3 In the above-described embodiment, the number of substrates 20a or 20b is two, but the number may be one or three or more. Furthermore, substrates 20a and 20b may be integrally configured. Furthermore, in the above-described embodiment, substrates 20a and 20b have different configurations, but this is not limiting, and substrates 20a and 20b may have the same configuration.

[0116] 2-4. Variation 4 In each of the above-described embodiments, a configuration is exemplified in which the base 40 is provided separately from the heat dissipation layers 23a and 23b of the substrates 20a and 20b, but the present invention is not limited to this configuration. For example, the base 40 may also serve as the heat dissipation layers 23a and 23b. In this case, the base 40 can be said to be part of the substrates 20a and 20b. [Explanation of symbols]

[0117] 10...semiconductor module, 10X...semiconductor module, 20a...substrate, 20b...substrate, 21a...insulating plate, 21b...insulating plate, 22a...wiring layer, 22a1...electrode pattern (first electrode pattern), 22a2...electrode pattern (second electrode pattern), 22a3...electrode pattern (third electrode pattern), 22a4...electrode pattern (fourth electrode pattern), 22b...wiring layer, 22b1...electrode pattern (first electrode pattern ), 22b2...electrode pattern (second electrode pattern), 22b3...electrode pattern (third electrode pattern), 22b4...electrode pattern (fourth electrode pattern), 23a...heat dissipation layer, 23b...heat dissipation layer, 31a...semiconductor switching element, 31b...semiconductor switching element, 32a...semiconductor element, 32b...semiconductor element, 40...base, 41...mounting hole, 50...case, 60...lid, 71...main terminal, 72...main terminal, 73... Main terminal, 81...control terminal, 81a...terminal portion, 82...control terminal, 82X...control terminal, 82a...terminal portion, 83...control terminal, 83a...terminal portion, 84...control terminal, 84a...terminal portion, 91a...wire (first wire), 91b...wire (first wire), 92a...wire (second wire), 92b...wire (second wire), 93a...wire (third wire), 93b...wire (third wire), 94a...wire (fourth wire), 94b...wire (fourth wire), 95...wire, 311...control electrode, 312...control wiring, 313...main electrode, CTa...region, CTb...region, CTc...region, CTd...region, CTe...region, CTf...region, CTg...region, F1...first surface, F2...second surface, F3...third surface, F4...fourth surface, L...parasitic inductance, RE...region, RE_1...region, RE_2...region.

Claims

1. at least one substrate having a first electrode pattern, a second electrode pattern, and a third electrode pattern, the first electrode pattern being located between the second electrode pattern and the third electrode pattern in a plan view; a plurality of semiconductor switching elements each having a first surface bonded to the first electrode pattern and a second surface facing in a direction opposite to the first surface; a plurality of semiconductor elements each having a third surface bonded to the first electrode pattern and a fourth surface facing in a direction opposite to the third surface; a control electrode, a control wiring connected to the control electrode, and a main electrode having a plurality of regions separated by the control wiring are provided on the second surface; each of the plurality of regions is electrically connected to the second electrode pattern via a first wire and is electrically connected to the third electrode pattern via a second wire; a middle portion of the second wire is joined to the fourth surface; the second electrode pattern is a pattern for a main current, The third electrode pattern is used as an auxiliary pattern for control. Semiconductor module.

2. a first control terminal bonded to the third electrode pattern; The semiconductor module according to claim 1 .

3. the third electrode pattern has an elongated shape, The distance between the joint portion between the third electrode pattern and the first control terminal and the center of the third electrode pattern in the longitudinal direction is the distance is smaller than the distance between a junction between the third electrode pattern and the first control terminal and an end of the third electrode pattern in the longitudinal direction. The semiconductor module according to claim 2 .

4. Further comprising a second control terminal; the at least one substrate further includes a fourth electrode pattern electrically connected to the control electrode via a third wire; the second control terminal is bonded to the fourth electrode pattern; the third electrode pattern is located between the first electrode pattern and the fourth electrode pattern in a plan view; The semiconductor module according to claim 2 .

5. Further comprising a second control terminal; the at least one substrate further includes a fourth electrode pattern electrically connected to the control electrode via a third wire; the second control terminal is bonded to the fourth electrode pattern; the fourth electrode pattern is located between the first electrode pattern and the third electrode pattern in a plan view; The semiconductor module according to claim 2 .

6. the at least one substrate includes a plurality of substrates each having the first electrode pattern, the second electrode pattern, and the third electrode pattern; the first control terminal is bonded to the third electrode pattern of each of the plurality of substrates; The semiconductor module according to claim 2 .

7. a fourth wire electrically connecting the third electrode patterns of the plurality of substrates to each other; The semiconductor module according to claim 6 .

8. the plurality of semiconductor switching elements are electrically connected in parallel; The semiconductor module according to claim 1 .

9. The second wire is configured with a plurality of wires for each of the plurality of regions. The semiconductor module according to claim 1 .

10. In each of the plurality of regions, one end of the first wire and one end of the second wire are joined at the same position. The semiconductor module according to claim 1 .

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