Offset Recessed Ground Plane Cutout

Abstract

Techniques are presented for creating an offset embedded ground plane cutout for a qubit device to facilitate frequency tuning of the qubit device. The qubit device may include a first substrate and a second substrate in a flip chip assembly. The qubit chip assembly may include a qubit component fabricated on the first substrate. The qubit component may include a Josephson junction (JJ) circuit, which may be offset from a center point of the qubit component. The qubit chip assembly may include an embedded ground plane located on a surface of the qubit chip assembly. A cutout may be formed in the ground plane and positioned above the JJ circuit. The cutout may allow access of an optical signal or a magnetic flux to the JJ circuit. The qubit component may be frequency tuned based on application of the optical signal or magnetic flux to the JJ circuit.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to quantum circuitry, and more particularly to offset embedded ground plane cutouts. Summary of the Invention

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the disclosed subject matter. This summary is not intended to identify key or critical elements or to delineate the scope of any particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. One or more embodiments described herein present systems, devices, structures, methods, apparatus, and / or computer program products that can facilitate the creation, design, and / or utilization of offset circuitry and embedded ground plane cutouts for qubit devices to facilitate frequency tuning of the qubit devices.

[0003] According to certain embodiments, a system can include a qubit chip assembly. The qubit chip assembly can include a qubit component fabricated on a substrate, the qubit component including a Josephson junction circuit offset a specified distance from a center point of the qubit component. The qubit chip assembly can also include a ground plane located on a surface of the qubit chip assembly, where a cutout is formed in the ground plane, defined by a remainder of the ground plane, and positioned above the Josephson junction circuit.

[0004] Another embodiment relates to a method that can include forming a qubit component including Josephson junction circuitry on a substrate, wherein the Josephson junction circuitry is offset a defined distance from a center point of the qubit component. The method can also include forming a ground plane located on a surface of a qubit chip package that includes the qubit component, wherein a cutout is formed in the ground plane, defined by a remainder of the ground plane, and positioned above the Josephson junction circuitry.

[0005] Further embodiments relate to qubit devices that can include a qubit chip package. The qubit chip package can include a qubit component formed on a substrate component, where the qubit component includes a Josephson junction component offset from a central region of the qubit component by a specified amount. The qubit chip package can also include a ground plane component located on a surface of the qubit chip package, where a cutout portion is formed in the ground plane component and defined by a remainder of the ground plane component and located above the Josephson junction component.

[0006] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0007] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0008] [Figure 1]FIG. 10 shows a diagram of an exemplary, non-limiting device that can include offset circuitry and offset ground plane cutouts to facilitate tuning the frequency of one or more qubits of the device, according to various aspects and embodiments of the disclosed subject matter.

[0009] [Figure 2] 1A-1D illustrate top and side view diagrams of an exemplary portion of a first chip (e.g., a qubit chip) that may include a qubit component having offset cutouts in a buried ground plane and offset Josephson junction circuitry to facilitate laser tuning of the Josephson junction circuitry of the qubit component, in accordance with various aspects and embodiments of the disclosed subject matter.

[0010] [Figure 3] 1A-1D illustrate top and side view diagrams of an exemplary portion of a first chip (e.g., a qubit chip) that may include a qubit component having offset Josephson junction circuitry including offset cutouts in a buried ground plane and superconducting quantum interference (SQUID) components to facilitate flux tuning of the qubit component, in accordance with various aspects and embodiments of the disclosed subject matter.

[0011] [Figure 4] FIG. 10 illustrates a diagram of a top view of an exemplary portion of a first chip (e.g., a qubit chip) in which a flux coil may be placed above an offset cutout in a buried ground plane of the qubit chip to facilitate flux tuning of the qubit components, according to various aspects and embodiments of the disclosed subject matter.

[0012] [Figure 5]FIG. 1 shows a diagram of an exemplary, non-limiting device that can include offset Josephson junction circuitry, offset buried ground plane cutouts, and interposer ground plane cutouts that can increase mutual inductance from magnetic fields generated by coil components in association with and to facilitate desired tuning of the frequency of one or more flux-tunable qubits of the device, according to various aspects and embodiments of the disclosed subject matter.

[0013] [Figure 6] FIG. 1 shows a diagram of an example X-mon qubit component that may include offset Josephson junction circuitry and may be associated with offset ground plane cutouts to facilitate desired tuning of qubits in a qubit device in accordance with various aspects and embodiments of the disclosed subject matter.

[0014] [Figure 7] FIG. 1 shows a diagram of an example transmon qubit component that may include offset Josephson junction circuitry and may be associated with an offset ground plane cutout to facilitate desired tuning of a qubit in a qubit device in accordance with various aspects and embodiments of the disclosed subject matter.

[0015] [Figure 8] 1 presents a diagram of an example graph of handler coupling dependency in relation to ground plane cutout offset, in accordance with various aspects and embodiments of the disclosed subject matter.

[0016] [Figure 9] 10A-10C show diagrams of example graphs that can illustrate magnetic field and qubit handler transfer dependencies, according to various aspects and embodiments of the disclosed subject matter.

[0017] [Figure 10] 10 shows a diagram of an example graph of frequency dependence of handler coupling with respect to ground plane cutout offset, in accordance with various aspects and embodiments of the disclosed subject matter.

[0018] [Figure 11] 1 illustrates a diagram of an example graph of qubit crosstalk versus ground plane cutout offset, in accordance with various aspects and embodiments of the disclosed subject matter.

[0019] [Figure 12] 1 illustrates a diagram of an exemplary graph transfer S21 (e.g., crosstalk between qubits) as a function of frequency, according to various aspects and embodiments of the disclosed subject matter.

[0020] [Figure 13] FIG. 1 illustrates a block diagram of an exemplary system that may be utilized to create, form, or design a qubit device including offset Josephson junction circuitry, offset buried ground plane cutouts, and / or offset interposer ground plane cutouts, in accordance with various aspects and embodiments of the disclosed subject matter.

[0021] [Figure 14] FIG. 1 shows a flow diagram of an example, non-limiting method by which offset circuitry and ground plane cutouts can be formed to facilitate tuning the frequency of one or more qubits of a qubit device, according to various aspects and embodiments of the disclosed subject matter.

[0022] [Figure 15] FIG. 10 shows a flow diagram of another exemplary, non-limiting method by which offset circuitry and ground plane cutouts can be formed to facilitate tuning the frequency of one or more qubits of a qubit device, in accordance with various aspects and embodiments of the disclosed subject matter.

[0023] [Figure 16] FIG. 1 shows a flow diagram of an example, non-limiting method by which the frequency of a qubit component of a qubit device can be tuned, where the qubit device includes an offset cutout in a buried ground plane and / or the qubit component includes offset Josephson junction circuitry, according to various aspects and embodiments of the disclosed subject matter.

[0024] [Figure 17] FIG. 1 illustrates a block diagram of an exemplary non-limiting operating environment that can facilitate one or more embodiments described herein.

[0025] [Figure 18] 1 shows a diagram of an exemplary qubit device that can include a multi-layer package, in accordance with various aspects and embodiments of the disclosed subject matter. DETAILED DESCRIPTION OF THE INVENTION

[0026] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments, nor is it intended to be bound by any expressed or implied information presented in the Background or Summary sections above or in the Detailed Description section.

[0027] One or more embodiments will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various cases one or more embodiments may be practiced without these specific details.

[0028] Frequency-tunable qubit devices may be useful and desirable in many quantum computing architectures. They may be used, for example, for parametric computation or as tunable coupling devices. Frequency-tunable qubit devices may exist based on Josephson junction circuitry, where the qubit device may be tuned by applying an optical signal (e.g., a laser signal) to the Josephson junction circuitry of the qubit device. Frequency-tunable qubit devices may also exist based on superconducting quantum interferometers (SQUIDs), where the qubit device may be tuned by applying a magnetic flux to the SQUID loop of the qubit device.

[0029] Multi-layer packaging can be used to scale up multi-qubit devices (e.g., devices including multiple qubit components). The multi-layer packaging can include chips that can include multiple qubits and associated circuitry that can be inserted into a larger assembly (e.g., a qubit chip assembly), where the qubit chips and interposer chips include grounded through-silicon vias (TSVs) for desirable chip mode suppression. Referring to FIG. 18 , FIG. 18 is a diagram of an example qubit device 1800 that can include a multi-layer package according to various aspects and embodiments of the disclosed subject matter. The example qubit device 1800 can include a qubit chip 1802 and an interposer chip 1804. The qubit chip 1802 and the interposer chip 1804 can each have desired dimensions (e.g., length, width, and height). A handler wafer 1806 can be associated with the qubit chip 1802, and the handler wafer 1806 can have desired dimensions. Another handler wafer 1808 may be associated with the interposer chip 1804, and the handler wafer 1808 may have any desired dimensions.

[0030] Qubit chip 1802 may include a buried ground plane 1810 that may be associated with (e.g., adjacent to or attached to) handler wafer 1806, and buried ground plane 1810 may be formed of a desired conductive material, such as, for example, a desired superconducting material. A metallization layer 1812 (e.g., qubit metallization) may be formed or deposited on an outer or top surface of qubit chip 1802, and metallization layer 1812 may include a conductive material, such as, for example, a desired superconducting material. Metallization layer 1812 may be processed (e.g., chemically etched) to form qubits, such as qubit 1814 and qubit 1816, and ground plane 1818 (e.g., qubit ground plane). A set of TSVs, such as TSV 1820 and TSV 1822, may be formed within qubit chip 1802 (e.g., may be formed within the qubit chip structural material of qubit chip 1802, which may be located between buried ground plane 1810 and ground plane 1818 and qubits 1814 and 1816).

[0031] Further with respect to interposer chip 1804, interposer chip 1804 can include a buried ground plane 1824 that can be associated with (e.g., adjacent to or attached to) handler wafer 1808, and buried ground plane 1824 can be formed of a desired conductive material, such as, for example, a desired superconducting material. A ground plane 1826 (e.g., interposer ground plane) can be formed or deposited on an outer or top surface of interposer chip 1804, and ground plane 1826 can include a conductive material, such as, for example, a desired superconducting material. A set of TSVs, such as TSV 1828 and TSV 1830, can be formed in interposer chip 1804 (e.g., can be formed in the interposer chip structural material of interposer chip 1804, which can be located between buried ground plane 1824 and ground plane 1826).

[0032] A set of bump bonds, such as bump bonds 1832 and 1834, may be formed between ground plane 1818 of qubit chip 1802 and ground plane 1826 of interposer chip 1804, for example, proximate the location of the TSVs. The set of bump bonds may connect components on qubit chip 1802 to components on interposer chip 1804.

[0033] To avoid undesired frequency collisions that may adversely affect the performance of a quantum computer, it may be desirable to tune (e.g., adjust) the frequencies of the qubits (e.g., qubit frequencies) of a qubit device. Tuning the frequencies of the qubits may typically be performed after fabrication of the qubit device. Techniques for tuning the qubit frequencies may include laser tuning or flux tuning. With laser tuning, a laser device may apply optical pulses (e.g., laser light pulses) to Josephson junctions of the qubit device to tune the frequency of the qubits. With flux tuning, a coil device (e.g., an electric coil) may generate a magnetic field, and the magnetic flux generated by the magnetic field may be applied to a SQUID loop associated with a qubit of the flux frequency tunable qubit device to tune the frequency of the qubit.

[0034] With multi-layer packaging using a flip-chip structure, in which a handler wafer associated with the qubit chip and interposer chip of a qubit device can be located in an outer region of the qubit device, and the qubits can be located in an inner region of the qubit device, it may be infeasible, impractical, or impossible to adjust the frequency of the qubits using laser tuning or flux tuning techniques due to the presence of a continuous ground plane on top of the qubit chip. A continuous ground plane (e.g., a continuous superconducting ground plane) can prevent or inhibit optical signals or magnetic flux from penetrating the ground plane and reaching the qubits to enable tuning of the qubits.

[0035] It may be desirable to have a frequency tunable device that does not suffer from these and / or other drawbacks. For example, it may be desirable to create, realize, or develop a frequency tunable qubit device that can be tuned (e.g., tuned after fabrication) in an efficient, practical, and useful manner that does not undesirably (e.g., adversely or excessively) affect the performance of the qubit device.

[0036] To that end, various embodiments described herein relate to techniques for designing, creating, and / or utilizing offset circuitry and buried ground plane cutouts for qubit devices to facilitate frequency tuning of the qubit devices. The qubit devices may include a first substrate component (e.g., a first handler wafer) and a second substrate component (e.g., a second handler wafer) in a flip-chip assembly. The qubit chip assembly may include qubit components formed (e.g., fabricated) on the first substrate component (e.g., on the first substrate component of the qubit chip). The qubit components may include Josephson junction circuits that may be offset a specified distance from a center point of the qubit component. In some embodiments, the Josephson junction circuits may include a SQUID loop. The qubit chip assembly may also include a buried ground plane that may be located on a surface of the qubit chip assembly, and the buried ground plane may be on the opposite side of the qubit chip from the qubit ground plane, and the buried ground plane may be associated with, formed on, or located on the first substrate component (e.g., the handler wafer component of the qubit chip). A cutout may be formed in the buried ground plane and may be positioned at least partially above or above the Josephson junction circuit. The cutout may have a desired shape and size as described herein. In some embodiments, the cutout may allow access of an optical signal (e.g., an optical signal including a laser light pulse) to the Josephson junction circuit, an optical signal generator device may generate the optical signal, and a qubit component may be frequency tuned (e.g., laser tuned) based at least in part on application of the optical signal to the Josephson junction circuit.In other embodiments, the cutout portion can allow magnetic flux access to the Josephson junction circuit, the coil device can generate a magnetic field to generate magnetic flux, and the frequency of the qubit component can be tuned (e.g., flux tuned) based at least in part on application of the magnetic flux to the Josephson junction circuit including the SQUID loop.

[0037] These and other aspects and embodiments of the disclosed subject matter will now be described with reference to the drawings.

[0038] 1 illustrates a diagram of an exemplary, non-limiting device 100 that may include offset circuitry and offset ground plane cutouts to facilitate tuning the frequency of one or more qubits of device 100, according to various aspects and embodiments of the disclosed subject matter. Device 100 may include a system of various components and circuitry that may be arranged to perform one or more desired functions. In some embodiments, device 100 may be or include a qubit device (e.g., a frequency-tunable qubit device). In particular embodiments, device 100 may be a transmon qubit device.

[0039] Device 100 may include a first chip 102 (e.g., a qubit chip) and a second chip 104 (e.g., an interposer chip). In some embodiments, first chip 102 and second chip 104 may be arranged in relation to one another to form a multi-layer flip-chip package, and second chip 104 may be flipped (e.g., turned upside down) so that its top surface on which various components and circuitry are formed faces and is relatively close to the top surface of first chip 102 on which various other components and circuitry may be formed. First chip 102 and second chip 104 may each have desired dimensions (e.g., length, width, and height), and at least some of the dimensions (e.g., length, width, and / or height) of second chip 104 may be the same as or correspond to at least some of the dimensions (e.g., length, width, and / or height) of first chip 102. Device 100 (e.g., a qubit device or multi-qubit device or package) can have dimensions that can vary, with the length of device 100 ranging, for example, from the order of millimeters to tens of millimeters, the width of device 100 ranging, for example, from the order of millimeters to tens of millimeters, and the thickness ranging, for example, from about 1 millimeter (mm) to about 3 mm. It should be appreciated and understood that these dimensions of device 100 are exemplary, and that according to other embodiments, device 100 can have dimensions that differ (e.g., smaller or larger) than the exemplary dimensions described herein.

[0040] A first substrate component 106 (also referred to herein as a first handler wafer) may be associated with the first chip 102, and the first substrate component 106 may have desired dimensions, and at least some of the dimensions (e.g., length and / or width) of the first substrate component 106 may be the same as or correspond to at least some of the dimensions (e.g., length and / or width) of the first chip 102. The first substrate component 106 may provide physical support for the first chip 102 and may provide an area or surface on which various components and circuitry of the first chip 102, as described herein, may be formed. A second substrate component 108 (also referred to herein as a second handler wafer) may be associated with the second chip 104, and the second substrate component 108 may have desired dimensions, and at least some of the dimensions (e.g., length and / or width) of the second substrate component 108 may be the same as or correspond to at least some of the dimensions (e.g., length and / or width) of the second chip 104. The second substrate component 108 may provide physical support for the second chip 104 and may provide an area or surface upon which various components and circuitry, as described herein, of the second chip 104 may be formed. The first substrate component 106 and the second substrate component 108 may be constructed of any desired silicon-based material (e.g., a silicon-based dielectric substrate).

[0041] The first chip 102 can include a buried ground plane 110 that can be associated with (e.g., adjacent to or attached to) and / or formed on the first substrate component 106, which can be formed of a desired conductive material, such as a desired superconducting material (e.g., a niobium-based superconducting material or other superconducting material). The first chip 102 and / or the first substrate component 106 can have dimensions that can vary, with the length of the first chip 102 and / or the first substrate component 106 ranging, for example, from the order of millimeters to tens of millimeters, the width ranging, for example, from the order of millimeters to tens of millimeters, and the thickness ranging, for example, from about 100 micrometers (μm) to about 1000 μm. It should be appreciated and understood that these dimensions of first chip 102 and / or first substrate component 106 are exemplary, and that according to other embodiments, first chip 102 and / or first substrate component 106 can have dimensions that differ (e.g., smaller or larger) than the exemplary dimensions described herein. A metallization layer 112 (e.g., qubit metallization) may be formed or deposited on an outer or top surface of first chip 102, and metallization layer 112 may include, for example, a conductive material, such as a desired superconducting material. As described more fully herein, metallization layer 112 may be processed (e.g., chemically etched) to form, for example, a set of qubit components including qubit component 114 and qubit component 116, and ground plane 118 (e.g., qubit ground plane).The qubit component (e.g., 114 or 116) can have dimensions that can vary, and the length of the qubit component can range, for example, from about 50 μm to about 500 μm, the width of the qubit component can range, for example, from about 50 μm to about 500 μm, and the thickness of the qubit component can range, for example, from about 50 nanometers (nm) to about 500 nm. It should be appreciated and understood that these dimensions of the qubit component (e.g., 114 or 116) are exemplary, and that according to other embodiments, the qubit component can have dimensions that differ (e.g., smaller or larger) than the exemplary dimensions described herein.

[0042] A first set of TSVs including TSV 120 and TSV 122 may be formed in the first chip 102. For example, the first set of TSVs (e.g., 120, 122) may be formed in a structural material (e.g., qubit chip structural material) of the first chip 102, which may be located between the buried ground planes 110 and 118 and the qubits 114 and 116, and portions of the structural material remaining after the formation of the TSVs (e.g., 120, 122) may surround and define the shape and size of the TSVs, which may have desired dimensions (e.g., width and / or height). According to various embodiments, the structural material of the first chip 102 may be or include the same or similar material as the substrate material of the first substrate component 106. The first set of TSVs (e.g., 120, 122) may be useful for suppressing or facilitating the suppression of chip modes in the first chip 102. Each qubit component (eg, 114, 116) may generally be positioned between each TSV (eg, 120, 122).

[0043] Further, with respect to the second chip 104, the second chip 104 can include a buried ground plane 124 that can be associated with (e.g., adjacent to or attached to) and / or formed on the second substrate component 108, and the buried ground plane 124 can be formed of a desired conductive material, such as a desired superconducting material. The second chip 104 and / or the second substrate component 108 can have dimensions that can vary, with the length of the second chip 104 and / or the second substrate component 108 ranging, for example, from the order of millimeters to tens of millimeters, the width ranging, for example, from the order of millimeters to tens of millimeters, and the thickness ranging, for example, from approximately 100 μm to approximately 1000 μm. It should be appreciated and understood that these dimensions of the second chip 104 and / or the second substrate component 108 are exemplary, and that according to other embodiments, the second chip 104 and / or the second substrate component 108 can have dimensions that differ (e.g., smaller or larger) than the exemplary dimensions described herein. A ground plane 126 (e.g., an interposer ground plane) may be formed or deposited on an outer or top surface of the second chip 104, and the ground plane 126 may include a conductive material, such as a desired superconducting material.

[0044] A second set of TSVs, including TSV 128 and TSV 130, may be formed in the second chip 104. For example, the second set of TSVs (e.g., 128, 130) may be formed in a structural material (e.g., interposer chip structural material) of the second chip 104, which may be located between the buried ground plane 124 and the ground plane 126, and portions of the structural material remaining after the formation of the TSVs (e.g., 128, 130) may surround and define the shape and size of the TSVs, which may have desired dimensions (e.g., width and / or height). According to various embodiments, the structural material of the second chip 104 may be or include the same or similar material as the substrate material of the second substrate component 108. The second set of TSVs (e.g., 128, 130) may be useful for suppressing or facilitating the suppression of chip modes in the second chip 104.

[0045] In some embodiments, a set of bump bond components (BB) including, for example, bump bond component 132 and bump bond component 134 may be formed between ground plane 118 of first chip 102 and ground plane 126 of second chip 104, for example, proximate to the locations of each of the first set of TSVs (e.g., TSV 120, TSV 122, and / or other TSVs) and the second set of TSVs (e.g., TSV 128, TSV 130, and / or other TSVs). The set of bump bond components (e.g., 132, 134) may connect or facilitate connection of components on first chip 102 to components on second chip 104.

[0046] It may be desirable to tune (e.g., adjust or modify) the frequency of device 100. It may be desirable to be able to tune a qubit component of a qubit device after fabrication of the qubit device. In some embodiments, laser tuning may be performed by causing a laser device to apply an optical signal (e.g., a laser, or an optical signal including a laser or optical pulse) of a desired wavelength to Josephson junction circuitry (e.g., a Josephson junction component) of a qubit component of the qubit device, and the frequency of the qubit component may be tuned (e.g., adjusted or modified) to a desired frequency based at least in part on the application of the optical signal to the Josephson junction circuitry of the qubit component. For example, the optical signal may include an infrared or other non-visible laser or optical pulse that may have a wavelength within the infrared or non-visible light spectrum. In other embodiments, the Josephson junction circuitry of a qubit component (e.g., a flux-tunable qubit) of a qubit device may include a SQUID component (e.g., a SQUID loop) of a coupler component (e.g., a qubit / coupler device). A flux coil can apply a desired amount of magnetic flux to the SQUID component, and the frequency of the qubit component can be tuned (e.g., adjusted or modified) based at least in part on the amount of magnetic flux applied to the SQUID component. Laser tuning or flux tuning of the qubit device can desirably reduce frequency collisions in packaged multi-qubit devices and can relax precision constraints (e.g., specifications or requirements) for targeting qubit frequencies, which can be particularly difficult to meet (e.g., meet) as the number of qubits on a multi-qubit device is scaled up.In conventional multi-layer qubit packaging structures, the qubits cannot be frequency tuned, or at least not desirably (e.g., suitably, sufficiently, or optimally), by either laser tuning or flux tuning techniques due to the presence of a continuous ground plane (e.g., a buried ground plane) on top of the qubit chip (e.g., a continuous superconducting ground plane can prevent optical signals or magnetic flux from penetrating such ground plane, allowing for the application of optical signals or magnetic flux to Josephson junction circuitry of the qubit).

[0047] According to various embodiments, the disclosed subject matter (e.g., using device-forming components as described herein) can form cutouts (e.g., openings or areas) in the buried ground plane 110 of the first chip 102 (e.g., by removing a portion of the conductive material of the buried ground plane 110) to allow (e.g., permit) optical access of optical signals or penetration of magnetic flux to Josephson junction circuitry of the qubit components (e.g., 114, 116) of the device 100 to facilitate tuning (e.g., laser tuning or flux tuning) of the qubit components of the device 100. However, if the cutouts in the buried ground plane 110 and other features of the qubit device are not properly structured, forming cutouts in the buried ground plane of the qubit chip can potentially undesirably provide another path for energy to undesirably leak from the qubits to the handler wafer and / or can result in undesirable crosstalk between qubits of the device (e.g., a multi-qubit device). The transfer of electromagnetic energy (e.g., S 21) may be undesirably enhanced (e.g., increased) at frequencies that can correspond to chip modes in the handler wafer of the qubit chip, may increase as the cutout size of the cutout in the buried ground plane increases, and may saturate at cutout sizes above about 200 μm. Reducing the size of the cutout in the buried ground plane below 200 μm may attenuate qubit-to-handler transmission, but reducing the cutout size may undesirably reduce the optical access efficiency of application of optical signals to the qubit Josephson junction circuitry and may undesirably reduce the mutual inductance of flux coils to the qubit device.

[0048] According to various embodiments, the disclosed subject matter can desirably (e.g., appropriately, suitably, or optimally) form and structure cutouts (e.g., offset cutouts) such as cutout 136 and cutout 138 within buried ground plane 110 and other features of the qubit device to enable desired tuning of the qubit components (e.g., 114, 116) of the qubit device while mitigating (e.g., reducing or minimizing) undesired transfer of electromagnetic energy from the qubit to the handler wafer and undesired crosstalk between qubits. The disclosed subject matter can also offset the Josephson junction circuit configurations (e.g., Josephson junction components or SQUID components (e.g., SQUID loops)) of the qubit components (e.g., 114, 116), which, together with cutout portions (e.g., 136, 138) positioned above the offset Josephson junction circuit configuration for each qubit component (e.g., 114, 116), can enable desired tuning of the qubit components (e.g., 114, 116) of device 100 while mitigating (e.g., reducing or minimizing) undesired transfer of electromagnetic energy from the qubits to the handler wafer and undesired crosstalk between qubits, as described more fully herein.

[0049] It should be appreciated and understood that although device 100 shows only two cutouts, including cutouts 136 and 138, formed in buried ground plane 110, the disclosed subject matter is not so limited and, according to various embodiments, device 100 can include any desired number of cutouts formed in buried ground plane 110, e.g., corresponding to and respectively associated with respective qubit components formed on device 100.

[0050] Referring to Figure 2 (in conjunction with Figure 1), Figure 2 illustrates a top view (e.g., horizontal cross section) and a side view (e.g., vertical cross section) diagram of an exemplary portion of a first chip 200 (e.g., a qubit chip) that may include a qubit component having offset cutouts in a buried ground plane and offset Josephson junction circuitry to facilitate laser tuning of the Josephson junction circuitry of the qubit component, in accordance with various aspects and embodiments of the disclosed subject matter. For brevity and clarity, only certain components and features of the qubit chip and qubit component are shown in Figure 2. Figure 2 presents a top view 202 of the portion of first chip 200 and a side view 204 of the portion of first chip 200.

[0051] First chip 200 (e.g., a portion of first chip 200) may include qubit component 206, which may be formed in ground plane pocket 208, which may be formed in ground plane 210 (e.g., a portion of the qubit ground plane) of first chip 200. Qubit component 206, ground plane pocket 208, and ground plane 210 may be formed on and / or from metallization layers, which may be formed and processed (e.g., etched) on a first substrate component 212 (e.g., a first handler wafer) of or associated with first chip 200. The metallization layers, and qubit component 206 (a portion) and ground plane 210, may be formed of a desired conductive material, such as, for example, a desired superconducting material. First substrate component 212 may be composed of a desired silicon-based material. Ground plane pocket 208 may have desired dimensions (e.g., length, width, and / or depth), may span an area on the order of micrometers, may be larger than the size of qubit component 206, and may surround qubit component 206 to facilitate desired shaping of the components of qubit component 206 and desired isolation of qubit component 206 from other components of the qubit device. First chip 200 may be substantially the same as first chip 102 of FIG. 1 except as described and modified herein to desirably enable tuning (e.g., laser tuning) of the qubits (e.g., qubit component 206) of the qubit device.

[0052] Qubit component 206 may include a capacitor component (C) 214 (e.g., a qubit capacitor) that may include or be associated with capacitor paddle components 216 and 218, which may have desired dimensions (e.g., length, width, and height). Capacitor paddle component 216 and capacitor paddle component 218 may be separated from one another with a desired amount of space (e.g., on the order of micrometers) between them. Qubit component 206 may also include Josephson junction circuitry that may include Josephson junction component 220, whose ends (e.g., respective terminals) may be associated (e.g., electrically connected) with capacitor paddle components 216 and 218, respectively. Conventionally, the Josephson junction may be located (e.g., positioned) in a central area of ​​the capacitor paddle of the qubit capacitor (e.g., the Josephson junction may be located midway along the length of the capacitor paddle). In some embodiments, the disclosed subject matter (e.g., using device-forming components) can form a Josephson junction circuit configuration including Josephson junction component 220 that is desirably offset by a specified distance (d) from the center of capacitor paddle components 216 and 218 such that the Josephson junction circuit configuration including Josephson junction component 220 can be positioned (e.g., positioned) at or near the end of capacitor paddle components 216 and 218 on one side of capacitor paddle components 216 and 218 in accordance with specified qubit device formation criteria. According to various embodiments, the specified offset distance (d) can range, for example, from about 200 μm to about 800 μm. For example, the desired specified offset distance (d) can be about 300 μm. In particular embodiments, the Josephson junction circuit configuration can be a capacitively shunted Josephson junction circuit configuration.The disclosed subject matter allows the Josephson junction circuitry, including Josephson junction component 220, to be desirably located further away from capacitor component 214 and other components of qubit component 206 in accordance with defined qubit device formation criteria by offsetting the Josephson junction circuitry, including Josephson junction component 220, along the length of capacitor paddle components 216 and 218 by a desired distance from the center of qubit component 206 (e.g., qubit center) and the centers of capacitor paddle components 216 and 218.

[0053] First chip 200 may also include a buried ground plane 222 that may be associated with (e.g., adjacent to or attached to) and / or formed on first substrate component 212, and buried ground plane 222 may be formed of a desired conductive material, such as a desired superconducting material. Buried ground plane 222 may be a surface (e.g., a buried surface) of a qubit chip assembly (also called a qubit chip package) of a qubit device. Qubit components, including qubit component 206 and ground plane 210 formed from metallization layers, may be positioned on opposing sides of the qubit chip assembly. Structural material 224 (e.g., qubit chip structural material), which may include the same or similar material as first substrate component 212, may be located between buried ground plane 222 and qubit component 206, ground plane pocket 208, and ground plane 210. Thus, buried ground plane 222 may be located (e.g., embedded) between structural material 224 and first substrate component 212.

[0054] In certain embodiments, the disclosed subject matter (e.g., using device-forming components) can form cutout 226 in buried ground plane 222, and cutout 226 can have desired dimensions (e.g., length and width) according to defined qubit device formation criteria. In some embodiments, the disclosed subject matter (e.g., using device-forming components) can form cutout 226 according to defined qubit device formation criteria to have a desired length that can be greater than about 200 μm. When forming cutout 226, the disclosed subject matter (e.g., using device-forming components) can desirably offset cutout 226 by a desired distance relative to the position of qubit component 206, and particularly relative to the position of capacitor component 214, such that cutout 226 can be positioned above (e.g., positioned above at least a portion of) an offset Josephson junction circuit configuration including Josephson junction component 220. For example, the disclosed subject matter may offset the location of cutout 226 in buried ground plane 222, and may offset the location of Josephson junction circuitry including Josephson junction component 220 relative to the location of qubit component 206, particularly relative to the location of capacitor component 214, such that exposure of capacitor component 214, capacitor paddle components 216 and 218, and / or other components of qubit component 206 to cutout 226 and first substrate component 212 (e.g., a first handler wafer) may be desirably reduced or minimized, thereby reducing or minimizing the amount of energy leaking from qubit component 206 to first substrate component 212 and / or reducing or minimizing crosstalk between qubit component 206 and another qubit component (not shown in FIG. 2) of a qubit device (e.g., a multi-qubit device).For example, the remaining portion of buried ground plane 222 may be positioned above and / or cover a desired portion (e.g., a majority) of capacitor component 214, including a desired portion (e.g., a majority) of capacitor paddle components 216 and 218, thereby desirably reducing or minimizing the amount of energy leaking from qubit component 206 to first substrate component 212 and / or reducing or minimizing crosstalk between qubit component 206 and another qubit component of the qubit device. Accordingly, qubit handler coupling may be desirably suppressed (e.g., reduced or minimized). Also, crosstalk between qubit components (e.g., qubit component 206 and an adjacent qubit component) may be desirably suppressed (e.g., reduced or minimized) to substantially the same level as when no cutout is present (e.g., when there is a continuous buried ground plane). In some embodiments, cutout portion 226 may be offset with respect to the Josephson junction circuitry, including being offset with respect to Josephson junction component 220, such that a portion of cutout portion 226 near a side (e.g., an edge) of cutout portion 226 is positioned above the Josephson junction circuitry (e.g., Josephson junction component 220), and another portion (e.g., a relatively larger portion) of cutout portion 226 is positioned above ground plane pocket 208 adjacent to qubit component 206.

[0055] In certain embodiments, a laser device 228 may be utilized to facilitate tuning the frequency of qubit component 206. Laser device 228 may generate and emit optical signal 230 (e.g., a laser, or an optical signal including laser or optical pulses) that may have a desired wavelength as described herein. Laser device 228 may apply optical signal 230 to a Josephson junction circuit configuration including Josephson junction component 220 via optical access that may be available through cutout 226 in buried ground plane 222. For example, optical signal 230 may pass through first substrate component 212, cutout 226 in buried ground plane 222, and structural material 224 between buried ground plane 222 and ground plane 210, and may be applied to a Josephson junction circuit configuration including Josephson junction component 220. The frequency of qubit component 206 may be desirably (e.g., preferably or optimally) tuned or adjusted based at least in part on application of optical signal 230 to a Josephson junction circuit configuration including Josephson junction component 220.

[0056] Referring to FIG. 3 (in conjunction with FIG. 1 ), FIG. 3 illustrates a top view (e.g., horizontal cross section) and a side view (e.g., vertical cross section) diagram of an exemplary portion of a first chip 300 (e.g., a qubit chip) that may include a qubit component having offset Josephson junction circuitry, including offset cutouts in a buried ground plane and SQUID components, to facilitate flux tuning of the qubit component, in accordance with various aspects and embodiments of the disclosed subject matter. For brevity and clarity, only certain components and features of the qubit chip and qubit component are shown in FIG. 3 . FIG. 3 presents a top view 302 of the portion of first chip 300 and a side view 304 of the portion of first chip 300.

[0057] First chip 300 (e.g., a portion of first chip 300) may include qubit component 306, which may be formed in ground plane pocket 308, which may be formed in ground plane 310 (e.g., a portion of the qubit ground plane) of first chip 300. Qubit component 306, ground plane pocket 308, and ground plane 310 may be formed on and / or from metallization layers, which may be formed and processed (e.g., chemically etched) on a first substrate component 312 (e.g., a first handler wafer) of or associated with first chip 300. The metallization layers, and qubit component 306 (a portion) and ground plane 310, may be formed of a desired conductive material, such as, for example, a desired superconducting material. First substrate component 312 may be composed of a desired silicon-based material. Ground plane pocket 308 may have desired dimensions (e.g., length, width, and / or depth), may span an area on the order of micrometers, may be larger than the size of qubit component 306, and may surround qubit component 306 to promote desired isolation of qubit component 306 from other components of the qubit device. Exemplary portions of first chip 300 may be substantially the same as portions of first chip 102 of FIG. 1 and first chip 200 of FIG. 2 except as described and modified herein, including, for example, that portions of first chip 300 may include SQUID components (e.g., SQUID loops) and may desirably enable tuning (e.g., flux tuning) of qubits (e.g., qubit component 306) of the qubit device.

[0058] Qubit component 306 may include capacitor component 314 (e.g., qubit capacitor), which may include or be associated with capacitor paddle components 316 and 318, which may have desired dimensions (e.g., length, width, and height). Capacitor paddle component 316 and capacitor paddle component 318 may be separated from one another with a desired amount of space (e.g., on the order of micrometers) between them. Qubit component 306 may also include Josephson junction circuitry, which may include SQUID component (S) 320 (e.g., a SQUID loop), which may include at least two Josephson junction components, including Josephson junction component (JJ) 322 and Josephson junction component 324, and ends (e.g., respective terminals) of SQUID component 320 may be associated (e.g., electrically connected) with capacitor paddle components 316 and 318, respectively. Conventionally, a Josephson junction circuit configuration including a SQUID loop can be located (e.g., positioned) in a central area of ​​a capacitor paddle of a qubit capacitor (e.g., the SQUID loop can be located midway along the length of the capacitor paddle). In some embodiments, the disclosed subject matter (e.g., using device-forming components) can form a Josephson junction circuit configuration including a SQUID component 320 that is desirably offset by a specified distance (d) from the center of capacitor paddle components 316 and 318, such that the Josephson junction circuit configuration including the SQUID component 320 can be located (e.g., positioned) at or near an end of capacitor paddle components 316 and 318 on one side of capacitor paddle components 316 and 318 in accordance with specified qubit device-forming criteria.The disclosed subject matter allows the Josephson junction circuitry, including SQUID component 320, to be desirably located further away from capacitor component 314 and other components of qubit component 306 in accordance with defined qubit device formation criteria by offsetting the Josephson junction circuitry, including SQUID component 320, along the length of capacitor paddle components 316 and 318 by a desired distance from the center of qubit component 306 (e.g., qubit center) and the centers of capacitor paddle components 316 and 318.

[0059] First chip 300 may also include a buried ground plane 326 that may be associated with (e.g., adjacent to or attached to) and / or formed on first substrate component 312, and buried ground plane 326 may be formed of a desired conductive material, such as a desired superconducting material. Buried ground plane 326 may be a surface (e.g., a buried surface) of a qubit chip assembly or qubit chip package of a qubit device. Qubit components, including qubit component 306 and ground plane 310 formed from metallization layers, may be positioned on the opposite side of the qubit chip assembly or qubit chip package. Structural material 328 (e.g., qubit chip structural material), which may include the same or similar material as first substrate component 312, may be located between buried ground plane 326 and qubit component 306, ground plane pocket 308, and ground plane 310. Thus, buried ground plane 326 may be located (e.g., embedded) between structural material 328 and first substrate component 312.

[0060] In certain embodiments, the disclosed subject matter (e.g., using device-forming components) can form cutout portion 330 in buried ground plane 326, and cutout portion 330 can have desired dimensions (e.g., length and width) according to defined qubit device formation criteria. In some embodiments, the disclosed subject matter (e.g., using device-forming components) can form cutout portion 330 according to defined qubit device formation criteria to have a desired length that can be greater than about 200 μm. When forming cutout portion 330, the disclosed subject matter (e.g., using device-forming components) can desirably offset cutout portion 330 by a desired distance relative to the position of qubit component 306, and particularly relative to the position of capacitor component 314, such that cutout portion 330 can be positioned above (e.g., centered or substantially centered above) the offset Josephson junction circuitry including SQUID component 320. For example, the disclosed subject matter may offset the location of cutout 330 in buried ground plane 326, and may offset the location of Josephson junction circuitry including SQUID component 320 relative to the location of qubit component 306 (e.g., relative to a central region of qubit component 306), particularly relative to the location of capacitor component 314, such that exposure of capacitor component 314, capacitor paddle components 316 and 318, and / or other components of qubit component 306 to cutout 330 and first substrate component 312 (e.g., a first handler wafer) may be desirably reduced or minimized, which may reduce or minimize the amount of energy leaking from qubit component 306 to first substrate component 312 and / or reduce or minimize crosstalk between qubit component 306 and another qubit component (not shown in FIG. 3 ) of a qubit device (e.g., a multi-qubit device).For example, the remaining portion of embedded ground plane 326 may be positioned above and / or cover a desired portion (e.g., a majority) of capacitor component 314, including a desired portion (e.g., a majority) of capacitor paddle components 316 and 318, thereby desirably reducing or minimizing the amount of energy leaking from qubit component 306 to first substrate component 312 and / or reducing or minimizing crosstalk between qubit component 306 and another qubit component of the qubit device. Accordingly, qubit handler coupling may be desirably suppressed (e.g., reduced or minimized). Also, crosstalk between qubit components (e.g., qubit component 306 and an adjacent qubit component) may be desirably suppressed (e.g., reduced or minimized) to substantially the same level as when no cutout is present (e.g., when there is a continuous embedded ground plane). In some embodiments, the cutout portion 330 formed in the buried ground plane 326 may be offset with respect to (e.g., relative to) the Josephson junction circuitry, including being offset with respect to the SQUID component 320, such that a portion of the cutout portion 330 near a side (e.g., an edge) of the cutout portion 330 is positioned above the Josephson junction circuitry (e.g., the SQUID component 320), and another portion (e.g., a relatively larger portion) of the cutout portion 330 may be positioned above the ground plane pocket 308 adjacent the qubit component 306.

[0061] In certain embodiments, a coil component 332 (e.g., a flux coil) may be utilized to facilitate tuning the frequency of qubit component 306. Coil component 332 may generate and radiate a desired amount of magnetic flux 334. Coil component 332 may apply magnetic flux 334 to the Josephson junction circuitry including SQUID component 320 via flux access, which may be available through cutout 330 formed in buried ground plane 326. For example, magnetic flux 334 may pass through (e.g., penetrate) first substrate component 312, cutout 330 formed in buried ground plane 326, and structural material 328 between buried ground plane 326 and ground plane 310, thereby being applied to the Josephson junction circuitry including SQUID component 320. The frequency of qubit component 306 may be desirably (e.g., preferably or optimally) tuned or adjusted based at least in part on the application of magnetic flux 334 to the Josephson junction circuitry including SQUID component 320.

[0062] Referring to Figure 4 (in conjunction with Figures 1 and 3), Figure 4 shows a diagram of a top view 400 (e.g., a horizontal cross section) of an exemplary portion of a first chip 300 (e.g., a qubit chip) in which a flux coil may be installed above an offset cutout in the buried ground plane of the qubit chip to facilitate flux tuning of the qubit component, in accordance with various aspects and embodiments of the disclosed subject matter. For simplicity and clarity, only certain components and features of the qubit chip and qubit component are shown in Figure 4.

[0063] In some embodiments, the coil component 332 (e.g., an external coil component) can include a flux coil 402 that can be centered over a cutout 330 formed in the buried ground plane 326. For example, the flux coil 402 can be a concentric flux coil that can be concentric with the cutout 330 formed in the buried ground plane 326, and the coil component 332 can generate a desired magnetic flux 334 and apply the magnetic flux 334 to the SQUID component 320 (e.g., a SQUID loop). By using a flux coil 402 that can be concentric with the cutout 330 formed in the buried ground plane 326 and positioned over the SQUID component 320 (e.g., an offset SQUID loop), the flux coil 402 can generate a desired (e.g., enhanced, optimal, or maximum) mutual inductance with the SQUID component 320.

[0064] Referring to FIG. 5 , FIG. 5 illustrates a diagram of an exemplary, non-limiting device 500 that can include offset Josephson junction circuitry, offset embedded ground plane cutouts, and interposer ground plane cutouts that can increase mutual inductance from magnetic fields generated by coil components in association with and to facilitate desired tuning of the frequency of one or more flux-tunable qubits of the device 500, according to various aspects and embodiments of the disclosed subject matter. Device 500 can include a system of various components and circuitry that can be arranged to perform one or more desired functions. In some embodiments, device 500 can be or include a qubit device (e.g., a frequency-tunable qubit device). Device 500 can be substantially similar to (e.g., can be of substantially the same structure as) device 100, except as described and modified herein (e.g., to include an interposer ground plane cutout).

[0065] The device 500 may include a first chip 502 (e.g., a qubit chip) and a second chip 504 (e.g., an interposer chip) that may be arranged in association with one another to form a multi-layer flip-chip package, and the second chip 504 may be flipped (e.g., turned upside down) so that its top surface on which various components and circuitry are formed faces and is relatively close to the top surface of the first chip 502 on which various other components and circuitry may be formed. The device 500 may include a first substrate component 506 (also referred to herein as a first handler wafer) that may be associated with the first chip 502, and a second substrate component 508 (also referred to herein as a second handler wafer) that may be associated with the second chip 504. The first chip 502 may include a buried ground plane 510 that may be associated with (e.g., adjacent to or attached to) and / or formed on the first substrate component 506. A metallization layer 512 (e.g., qubit metallization) may be formed or deposited on an outer or top surface of first chip 502, and may include, for example, a conductive material such as a desired superconducting material. Metallization layer 512 may be processed (e.g., chemically etched) to form, for example, a set of qubit components including qubit component 514 and qubit component 516, and ground plane 518 (e.g., qubit ground plane). A first set of TSVs including TSV 520 and TSV 522 may be formed in first chip 502. For example, a first set of TSVs (e.g., 520, 522) may be formed in the structural material (e.g., qubit chip structural material) of the first chip 502, where the structural material may be located between the buried ground plane 510 and the ground plane 518 and the qubits 514 and 516, and the portion of the structural material remaining after the formation of the TSVs (e.g., 520, 522) may surround the TSVs and define their shape and size, and the TSVs may have desired dimensions (e.g., width and / or height).According to various embodiments, the structural material may be or include the same or similar material as the substrate material of the first substrate component 506 .

[0066] Further with respect to second chip 504, second chip 504 may include an embedded ground plane 524 that may be associated with (e.g., adjacent to or attached to) and / or formed on second substrate component 508. A ground plane 526 (e.g., an interposer ground plane) may be formed or deposited on an outer or top surface of second chip 504, and ground plane 526 may include a conductive material, such as, for example, a desired superconducting material. A second set of TSVs, including TSV 528 and TSV 530, may be formed in second chip 504. For example, the second set of TSVs (e.g., 528, 530) may be formed in the structural material (e.g., interposer chip structural material) of the second chip 504, which may be located between the buried ground plane 524 and the ground plane 526, and the portions of such structural material remaining after the formation of the TSVs (e.g., 528, 530) may surround and define the shape and size of the TSVs, which may have desired dimensions (e.g., width and / or height). According to various embodiments, the structural material of the second chip 504 may be or include the same or similar material as the substrate material of the second substrate component 508.

[0067] In some embodiments, a set of bump bond components, including, for example, bump bond component 532 and bump bond component 534, may be formed between ground plane 518 of first chip 502 and ground plane 526 of second chip 504, proximate to the locations of each of the first set of TSVs (e.g., TSV 520, TSV 522, and / or other TSVs) and the second set of TSVs (e.g., TSV 528, TSV 530, and / or other TSVs). The set of bump bond components (e.g., 532, 534) may connect or facilitate connection of components on first chip 502 to components on second chip 504.

[0068] In particular embodiments, the disclosed subject matter can desirably (e.g., appropriately, suitably, or optimally) form and structure cutouts (e.g., offset cutouts), such as cutout 536, in buried ground plane 510 and other features of device 500 to enable desired tuning of qubit components (e.g., qubit component 514) of device 500 while mitigating (e.g., reducing or minimizing) undesired transfer of electromagnetic energy from the qubit to the handler wafer and undesired crosstalk between qubits. The disclosed subject matter can also offset Josephson junction circuitry (e.g., SQUID components (e.g., SQUID loops)) of qubit components (e.g., 514), which, together with cutouts (e.g., 536) positioned above the offset Josephson junction circuitry, can enable desired tuning of qubit components (e.g., 514) of device 500 while mitigating (e.g., reducing or minimizing) undesired transfer of electromagnetic energy from the qubit to the handler wafer and undesired crosstalk between qubits, as described more fully herein.

[0069] In some embodiments, in addition to including an offset buried ground plane cutout (e.g., cutout 536) and offset Josephson junction circuitry (e.g., offset SQUID loop) formed in buried ground plane 510 on first chip 502 (e.g., qubit chip), there may also be an interposer ground plane cutout 538 formed in ground plane 526 (e.g., interposer ground plane) of second chip 504 (e.g., interposer chip) proximate to the offset Josephson junction circuitry (e.g., offset SQUID loop) of qubit component 514. A coil component 540 may apply a desired magnetic flux to the offset SQUID component of qubit component 514 through cutout 536 formed in buried ground plane 510, and the magnetic flux may also pass through (e.g., penetrate) the structural material (e.g., qubit chip structural material) between TSVs 520 and 522 and first substrate component 506. In particular embodiments, interposer ground plane cutout 538 may be offset a specified distance relative to the center (e.g., qubit center) of qubit component 514 and / or the associated offset SQUID component of qubit component 514 in the same or similar manner as cutout 536 formed in embedded ground plane 510 on first chip 502. Additional cutouts (e.g., interposer ground plane cutout 538) formed in ground plane 526 may enhance (e.g., increase or improve) the amount of mutual inductance generated from the magnetic field generated by coil component 540, thereby further enhancing and making the process of tuning the frequency of one or more flux-tunable qubits of device 500 more efficient.

[0070] It should be appreciated and understood that although device 500 shows only two cutouts, including cutout 536 formed in buried ground plane 510 and one cutout 538 formed in ground plane 526, the disclosed subject matter is not so limited and according to various embodiments, device 500 can include any desired number of cutouts formed in buried ground plane 510 and any desired number of cutouts formed in ground plane 526, for example, corresponding to and respectively associated with respective qubit components formed on device 500.

[0071] Further with respect to qubits and associated capacitors, in addition to the qubit and associated capacitor designs described herein with respect to Figures 1-5, the disclosed subject matter can use and implement offset Josephson junction circuitry and offset ground plane cutouts with various other types of qubits and associated capacitors in a manner similar to that described herein with respect to Figures 1-5. In that regard, referring briefly to Figure 6, Figure 6 illustrates a diagram of an exemplary X-Mon qubit component 600 that can include offset Josephson junction circuitry and associated with an offset ground plane cutout to facilitate desired tuning of a qubit of a qubit device in accordance with various aspects and embodiments of the disclosed subject matter. X-Mon qubit component 600 can include a cross-shaped qubit capacitor component 602 that can include a first electrode component 604 and a second electrode component 606 that can be structured in a shape resembling a cross.

[0072] Xmon qubit component 600 may include Josephson junction circuitry toward and / or near the end of one of the electrode components (e.g., first electrode component 604), which may be offset a desired distance from a center point of Xmon qubit component 600. In some embodiments, the Josephson junction circuitry may include a SQUID component 608 (as shown) (e.g., a SQUID loop), which may include at least two Josephson junction components, including Josephson junction components 610 and 612. In other embodiments, other types of Josephson junction circuitry may be used with Xmon qubit component 600. In particular embodiments, one of the electrode components, such as second electrode component 606, may be part of the ground plane (e.g., qubit ground plane) of the qubit device. First electrode component 604, second electrode component 606, and Josephson junction circuitry (e.g., SQUID component 608) may be formed of desired conductive materials, such as desired superconducting materials.

[0073] Cutout portion 614 may be formed in buried ground plane 616 of the qubit chip of the qubit device in the same or similar manner as described more fully herein. Cutout portion 614 may be formed in the buried ground plane such that it may be offset a desired distance from the center point of the qubit (e.g., a desired distance from the center or intersection point (e.g., cross point) of cross-shaped qubit capacitor component 602) and / or may be offset a desired distance from the center point of the Josephson junction circuitry (e.g., SQUID component 608), and at least a portion of cutout portion 614 may be positioned above the Josephson junction circuitry.

[0074] Referring briefly to Figure 7, Figure 7 illustrates a diagram of an exemplary transmon qubit component 700 that may include offset Josephson junction circuitry and may be associated with an offset ground plane cutout to facilitate desired tuning of a qubit in a qubit device, in accordance with various aspects and embodiments of the disclosed subject matter. The transmon qubit component 700 may include a capacitor component 702 that may include a first capacitor island component 704 and a second capacitor island component 706 that may be separated from one another by a desired gap 708 (e.g., space). In some embodiments, the first capacitor island component 704 and the second capacitor island component 706 may be shaped and positioned relative to one another such that the gap 708 may resemble a snake.

[0075] The transmon qubit component 700 may include Josephson junction circuitry toward and / or near the ends of the capacitor component 702 (e.g., near corresponding or associated ends of the first capacitor island component 704 and the second capacitor island component 706), which may be offset a desired distance from a center point of the transmon qubit component 700. In some embodiments, the Josephson junction circuitry may include a SQUID component 710 (as shown) (e.g., a SQUID loop), which may include at least two Josephson junction components, including Josephson junction components 712 and 714. In other embodiments, other types of Josephson junction circuitry may be used with the transmon qubit component 700. The first capacitor island component 704, the second capacitor island component 706, and the Josephson junction circuitry (e.g., the SQUID component 710) may be formed of a desired conductive material, such as a desired superconducting material.

[0076] A cutout 716 may be formed in a buried ground plane 718 of a qubit chip of a qubit device in the same or similar manner as described more fully herein. The cutout 716 may be formed in the buried ground plane 718 such that it may be offset a desired distance from the center point of the qubit (e.g., the center point of the transmon qubit component 700) and / or from the center point of the Josephson junction circuitry (e.g., the SQUID component 710), and at least a portion of the cutout 716 may be positioned above the Josephson junction circuitry.

[0077] The disclosed subject matter can enable desirable mitigation or reduction of frequency collisions in multi-qubit devices by enabling tuning of qubit frequencies after fabrication of the multilayer qubit device using either magnetic fields and / or laser tuning, preferably by offsetting Josephson junction circuitry, creating cutouts in the buried ground plane of the qubit chip, offsetting cutouts in the buried ground plane of the qubit chip, creating cutouts in the interposer ground plane of the interposer chip, and / or offsetting cutouts in the interposer ground plane of the interposer chip. The disclosed subject matter can also reduce challenges that may be faced during fabrication of multi-qubit devices with respect to achieving precise target qubit frequencies in multi-qubit devices. The disclosed subject matter may add to the knowledge base of device structures for mitigating crosstalk and chip mode coupling. The disclosed subject matter can also facilitate (e.g., enable) much more rapid production of larger multi-qubit devices.

[0078] 8, which presents a diagram of an example graph 800 of handler coupling dependence relative to ground plane cutout offset, according to various aspects and embodiments of the disclosed subject matter. The example graph 800 shows the transfer S (e.g., from the qubit to the handler wafer) measured at 2.5 gigahertz (GHz) (e.g., in the lowest frequency chip mode of the qubit device) as a function of ground plane cutout offset (μm). 21 Example graph 800 includes a graph 802 that can present the percent qubit electric field contribution at the handler wafer as a function of ground plane cutout offset (μm). In graphs 802 and 804, a cutout offset of 0 can correspond to the original case where the ground plane cutout, coil, and qubit ground plane pocket are all concentric. As can be observed in graphs 802 and 804, offsetting the ground plane cutout by 600 μm by 600 μm can desirably reduce the amount of coupling between the qubit and handler wafer, and can desirably reduce the percent qubit electric field contribution at the handler wafer.

[0079] 9 illustrates a diagram of an example graph 900 that can show magnetic field and qubit handler transfer dependence, according to various aspects and embodiments of the disclosed subject matter. The example graph 900 shows the transfer S (e.g., from the qubit to the handler wafer) measured at 2.5 GHz (e.g., in the lowest frequency chip mode of the qubit device) as a function of ground plane cutout offset (μm). 21The example graph 900 may include a graph 902 that may present the amount of mutual inductance (Φ / milliamps (mA)) as a function of the ground plane cutout times the displacement position (μm). With respect to the data presented in graphs 902 and 904, such data is based on the coil being concentric with the center of the ground plane cutout.

[0080] As can be observed in graphs 902 and 904, the maximum mutual inductance can occur when the coil, cutout, and SQUID are all centered and the ground plane cutout is offset by approximately 250 μm. As can be further observed in graphs 902 and 904, a ground plane cutout offset of 500 μm results in approximately 34 dB of attenuation (e.g., 50×S) with sufficient flux coupling (e.g., 0.22 Φ / mA). 21 As can be further observed in graphs 902 and 904, even when most of the qubit device is covered by a buried ground plane (e.g., a 600 μm ground plane cutout), an attenuation of about 56 dB (630×S 21 ) may be obtained and there may still be a mutual inductance of about 0.1Φ / mA.

[0081] 10, which illustrates a diagram of an exemplary graph 1000 of frequency dependence of handler coupling with respect to ground plane cutout offset, in accordance with various aspects and embodiments of the disclosed subject matter. Graph 1000 illustrates the transfer S (e.g., from a qubit to a handler wafer) as a function of frequency (f) (GHz) for no ground plane cutout offset (denoted by reference numeral 1002) and for a ground plane cutout offset of 500 μm (denoted by reference numeral 1004). 21As can be observed from graph 1000, which includes respective data points (e.g., respective graph lines) indicated by reference characters 1002 and 1004, the suppressed coupling of the qubit device to the handler wafer may be desirably broadband when there is an offset in the ground plane cutout, including at the handler mode frequency.

[0082] Referring briefly to FIGS. 11 and 12, FIG. 11 illustrates a diagram of an example graph 1100 of qubit crosstalk versus ground plane cutout offset, and FIG. 12 illustrates an example graph 1200 of transmission S as a function of frequency (f) (GHz), in accordance with various aspects and embodiments of the disclosed subject matter. 21 Graph 1100 shows a diagram of the transfer S (dB) as a function of the cutout offset (μm) of the ground plane cutout in the buried ground plane of the qubit device for crosstalk at a handler mode frequency of 2.5 GHz and a distance between qubits of 2 millimeters. 21 The transfer S (dB) when there is a closed buried ground plane in the qubit device (e.g., no cutouts in the buried ground plane) can be presented (as shown by the data points at 1102). 21 is indicated by reference numeral 1104.

[0083] Graph 1200 shows the transmission S as a function of frequency for a qubit device with no ground plane cutout offset (as shown by data point 1202), with a ground plane cutout offset (as shown by data point 1204), and with a closed buried ground plane (e.g., no cutout in the buried ground plane) (as shown by data point 1206). 21As can be observed in graphs 1100 and 1200, crosstalk between qubits (e.g., adjacent qubits) may be desirably suppressed when there is an offset of the ground plane cutout in the buried ground plane of the qubit device (e.g., |cutout offset| > 500 μm), and the amount of crosstalk between qubits when there is a cutout offset in the buried ground plane may be at substantially the same level as the amount of crosstalk between qubits when there is no cutout in the buried ground plane of the qubit device (e.g., when the qubits may be isolated from the handler wafer of the qubit device). Accordingly, the graph line labeled 1204 (e.g., for the cutout offset) substantially overlaps with the graph line labeled 1206 (for the closed buried ground plane).

[0084] 13 shows a block diagram of an example system 1300 that may be utilized to create, form, or design a qubit device including offset Josephson junction circuitry, offset embedded ground plane cutouts, and / or offset interposer ground plane cutouts in accordance with various aspects and embodiments of the disclosed subject matter. System 1300 may include device formation components 1302, processor components 1304, and data store 1306. Device formation components 1302 may be utilized to create, form, or design various components of or associated with qubit device 1308, and may tune the frequencies of the qubit components of qubit device 1308 (e.g., via laser tuning or flux tuning), as described more fully herein. For example, device formation components 1302 may be utilized to create, form, or design various components that may be formed or located on a first chip 1310 (e.g., a qubit chip) and various components that may be formed or located on a second chip 1312 (e.g., an interposer chip). The various components may include, for example, qubit components 1314, coupler components 1316 (which may include or be associated with capacitor components), Josephson junction (JJ) circuitry 1318 (e.g., offset Josephson junction circuitry) which, in some embodiments, may include a SQUID component (SQUID COMP.) 1320 (e.g., a SQUID loop), buried ground plane 1322, interposer ground plane 1324, cutouts 1326 (e.g., buried ground planes and / or offset cutouts in the interposer ground plane), TSVs 1328, bump bond components 1330, and associated circuitry 1332.Device formation component 1302 may also use and / or control the operation of a laser device or coil component to tune the frequency of qubit component 1314 of qubit device 1308 (e.g., after fabrication of qubit device 1308).

[0085] As part of and to facilitate the creation, formation, or design of various components of or associated with qubit device 1308, device formation component 1302 can form or process substrate components, such as a first substrate component that can be part of first chip 1310 and a second substrate component that can be part of second chip 1312. As part of and to facilitate the creation, formation, or design of various components of or associated with qubit device 1308, device formation component 1302 can also form, deposit, or process one or more metallization layers on the first and second substrate components, where the metallization layers may be formed of one or more desired metals or conductive materials that can be or include one or more desired superconducting materials (e.g., niobium-based superconducting materials), and the metallization layers can have a desired thickness or height. In some embodiments, device formation component 1302 can remove (e.g., selectively remove) respective portions of the metallization layers to facilitate the creation or formation of respective components or circuitry of qubit device 1308. For example, device formation component 1302 may use and / or control various processes, including microfabrication processes, nanofabrication processes, masking or photoresist processes, photolithography processes, chemical etching processes, other etching or removal processes, or other desired processes, to desirably process metallization layers and remove respective portions of metallization layers to facilitate the creation or formation of respective components or circuitry of qubit device 1308.

[0086] Processor component 1304 can operate in conjunction with other components (e.g., device formation component 1302, data store 1306, or another component) to facilitate the performance of various functions of system 1300. Processor component 1304 can employ one or more processors, microprocessors, or controllers capable of processing data such as information related to qubit devices, qubit components, coupler components, SQUID loops, Josephson junction components, capacitor components, inductor components, buried ground planes, interposer ground planes, cutouts in buried ground planes and / or interposer ground planes, TSVs, bump bond components, circuit design criteria, circuit design algorithms, traffic flows, policies, protocols, interfaces, tools, and / or other information to facilitate the operation of system 1300 and to control the flow of data between system 1300 and other components (e.g., computer components, computers, laptop computers, other computing or communication devices, or network devices) associated with (e.g., connected to) system 1300, as disclosed more fully herein.

[0087] Data store 1306 can store information related to data structures (e.g., user data, metadata), code structures (e.g., modules, objects, hashes, classes, procedures) or instructions, qubit devices, qubit components, coupler components, SQUID loops, Josephson junction components, capacitor components, inductor components, buried ground planes, interposer ground planes, cutouts in buried ground planes and / or interposer ground planes, TSVs, bump bond components, circuit design criteria, circuit design algorithms, traffic flows, policies, protocols, interfaces, tools, and / or other information to facilitate control of operations associated with system 1300. In an aspect, processor component 1304 can be operatively coupled to data store 1306 (e.g., via a memory bus) to store and retrieve information desired to operate and / or provide functionality, at least in part, to device formation component 1302, data store 1306, or other components, and / or virtually any other operating aspect of system 1300.

[0088] It should be appreciated that the data store 1306, as described herein, may include volatile and / or non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which may act as external cache memory. By way of example, and not limitation, RAM may come in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), sync link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The memory of the disclosed aspects is intended to include, without being limited to, these and other suitable types of memory.

[0089] Systems and / or devices have been described herein (or will be described) with respect to interactions between multiple components. It should be recognized that such systems and components may include those components or subcomponents identified therein, some of the identified components or subcomponents, and / or additional components. Subcomponents may be implemented as components communicatively coupled to other components rather than being included within a parent component. Furthermore, one or more components and / or subcomponents may be combined into a single component that provides aggregate functionality. Components may interact with one or more other components not specifically described herein for the sake of brevity, but known to those skilled in the art.

[0090] 14 shows a flow diagram of an exemplary, non-limiting method 1400 that can form offset circuitry and ground plane cutouts to facilitate tuning the frequency of one or more qubits of a qubit device, according to various aspects and embodiments of the disclosed subject matter. Method 1400 can be performed, for example, by a system (e.g., a computer system) that includes or is operatively coupled to device-forming components, a processor component, and memory. Repeated descriptions of similar elements used in other embodiments described herein may be omitted or omitted for the sake of brevity.

[0091] In 1402, a qubit component including Josephson junction circuitry can be formed on a substrate component. The Josephson junction circuitry can be offset a specified distance from a center point of the qubit component. A device formation component can form a qubit component including Josephson junction circuitry on a substrate component (e.g., a substrate component on a qubit chip), where the Josephson junction circuitry can be offset a specified distance from a center point of the qubit component.

[0092] At 1404, a ground plane can be formed. The ground plane can be located on a surface of the qubit chip package that includes the qubit components, and a cutout can be formed in the ground plane, defined by the remainder of the ground plane, and positioned above the Josephson junction circuitry. The device-forming components can form the ground plane (e.g., a buried ground plane on the qubit chip), and the ground plane can be located on a surface of the qubit chip package that can include the qubit components, and a cutout (e.g., an offset cutout) can be formed in the ground plane, defined by the remainder of the ground plane, and positioned above the Josephson junction circuitry.

[0093] 15 shows a flow diagram of another exemplary, non-limiting method 1500 that can form offset circuitry and ground plane cutouts to facilitate tuning the frequency of one or more qubits of a qubit device, according to various aspects and embodiments of the disclosed subject matter. Method 1500 can be performed, for example, by a system (e.g., a computer system) that includes or is operatively coupled to device forming components, a processor component, and memory. Repeated descriptions of similar elements used in other embodiments described herein may be omitted or omitted for the sake of brevity.

[0094] At 1502, a buried ground plane may be formed on a first substrate component. The buried ground plane may be located on a first surface of a qubit chip package that may be formed on the first substrate component. The device-forming component may form a buried ground plane on the first substrate component (e.g., a first substrate of a qubit chip or a handler wafer), and the buried ground plane may be located on a first surface of a qubit chip package that may be formed on the first substrate component.

[0095] At 1504, a qubit ground plane can be formed on a second surface of the qubit chip package. The device formation components can form a qubit ground plane on the second surface (e.g., a metallization layer) of the qubit chip package.

[0096] In 1506, a qubit component can be formed on a second surface of the qubit chip package. A device formation component can form the qubit component on the second surface (e.g., a metallization layer) of the qubit chip package.

[0097] In 1508, in connection with forming the qubit component, Josephson junction circuitry associated with the qubit component can be offset a prescribed distance from a center point of the qubit component. In connection with forming the qubit component, the device formation component can offset Josephson junction circuitry associated with the qubit component a prescribed distance from a center point of the qubit component. In some embodiments, the Josephson junction circuitry can include a SQUID loop, which can include two or more Josephson junction components.

[0098] At 1510, an interposer chip package including the interposer ground plane can be formed on a second substrate component. A device-forming component can form the interposer chip package including the interposer ground plane on a second substrate component (e.g., a second substrate of the interposer chip or a handler wafer).

[0099] At 1512, TSVs can be formed in the qubit chip package and the interposer chip package. Device forming components can form TSVs at desired locations in the qubit chip package (e.g., qubit chip assembly) and the interposer chip package (e.g., interposer chip assembly), as described more fully herein.

[0100] At 1514, bump bonding components can be formed to connect the qubit chip package to the interposer chip package. The device formation components can form bump bonding components to connect the qubit chip package to the interposer chip package (e.g., connect components of the qubit chip package to components of the interposer chip package).

[0101] At 1516, a capacitor component can be formed. The capacitor component can be associated with Josephson junction circuitry and can be part of a qubit component. The device forming components can form the capacitor component. The capacitor component can be associated with Josephson junction circuitry (e.g., offset Josephson junction circuitry) and can be part of a qubit component.

[0102] At 1518, an offset cutout may be formed in the buried ground plane. The offset cutout may be defined by a remaining portion of the buried ground plane and may be positioned above the Josephson junction circuitry, which may be positioned above a portion of the capacitor component. The device-forming component may form an offset cutout in the buried ground plane, which may be defined by a remaining portion of the buried ground plane and may be positioned above the Josephson junction circuitry, which may be positioned above a portion (e.g., a majority) of the capacitor component. In some embodiments, the device-forming component may form the offset cutout in the buried ground plane such that the cutout may be offset a desired distance relative to a center point of the qubit component and / or relative to a center point of the Josephson junction circuitry, as described more fully herein.

[0103] 16 shows a flow diagram of an exemplary, non-limiting method 1600 that can tune the frequency of a qubit component of a qubit device according to various aspects and embodiments of the disclosed subject matter, where the qubit device includes an offset cutout in a buried ground plane and / or the qubit component includes offset Josephson junction circuitry. Method 1600 can be performed, for example, by a system (e.g., a computer system) that includes or is operatively coupled to device-forming components, a processor component, and memory. Repeated descriptions of similar elements used in other embodiments described herein may be omitted or omitted for brevity.

[0104] In 1602, a determination may be made as to whether a qubit component of a qubit device is laser-tunable or flux-tunable. The qubit device includes an offset cutout in a buried ground plane, and / or the qubit component includes offset Josephson junction circuitry. In 1604, if it is determined that the qubit component is laser-tunable, an optical signal may be applied to the offset Josephson junction circuitry via the offset cutout in the buried ground plane of the qubit device. In 1606, a frequency of the qubit component may be adjusted (e.g., tuned) based at least in part on the application of the optical signal to the offset Josephson junction circuitry. If it is determined that the qubit component is laser-tunable, the device-forming components may generate an optical signal (e.g., a laser, or an optical signal including a laser or optical pulse) of a desired wavelength using a laser device and apply the optical signal to the offset Josephson junction circuitry via the offset cutout in the buried ground plane of the qubit device. A device forming component that uses or controls the laser device can adjust or tune the frequency of the qubit component based at least in part on application of an optical signal to the offset Josephson junction circuitry.

[0105] Referring again to reference numeral 1602, if it is determined in 1602 that the qubit component is flux-tunable, then in 1608, a magnetic flux may be applied to an offset Josephson junction circuit configuration (e.g., an offset SQUID loop) via an offset cutout in the buried ground plane of the qubit device. At 1610, the frequency of the qubit component may be adjusted (e.g., tuned) based at least in part on the application of the magnetic flux to the offset Josephson junction circuit configuration. If it is determined that the qubit component is flux-tunable, then the device forming components may generate the desired magnetic flux using a coil component (e.g., a flux coil), and apply the magnetic flux to the offset Josephson junction circuit configuration (e.g., an offset SQUID loop) via an offset cutout in the buried ground plane of the qubit device. The device forming components using or controlling the coil component may adjust or tune the frequency of the qubit component based at least in part on the application of the magnetic flux to the offset Josephson junction circuit configuration. It should be appreciated and understood that in some embodiments, laser tuning and flux tuning can be performed on Josephson junction circuitry (e.g., laser tuning and flux tuning can be performed on Josephson junction components of a SQUID loop) as needed and desired.

[0106] For ease of explanation, these methods and / or computer-implemented methods are illustrated and described as a series of acts. It is understood and appreciated that the disclosed subject matter is not limited by the illustrated acts and / or the order of acts; for example, acts may occur in various orders and / or simultaneously, with other acts not shown and described herein. Moreover, not all illustrated acts may be required to implement a computer-implemented method in accordance with the disclosed subject matter. Those skilled in the art will also understand and appreciate that a computer-implemented method can alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it is further appreciated that the computer-implemented methods disclosed hereinafter and throughout this specification can be stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methods to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0107] To provide a context for various aspects of the disclosed subject matter, FIG. 17 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 17 illustrates a block diagram of an exemplary, non-limiting operating environment that can facilitate one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein may be omitted or omitted for the sake of brevity. Referring to FIG. 17, a suitable operating environment 1700 for implementing various aspects of the present disclosure may include a computer 1712. The computer 1712 may also include a processing unit 1714, a system memory 1716, and a system bus 1718. The system bus 1718 couples system components, including, but not limited to, the system memory 1716, to the processing unit 1714. The processing unit 1714 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 1714. The system bus 1718 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any kind of available bus architecture, including, but not limited to, Industry Standard Architecture (ISA), MicroChannel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), CardBus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI). The system memory 1716 may also include volatile memory 1720 and nonvolatile memory 1722. The basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 1712, such as during start-up, is stored in the nonvolatile memory 1722.By way of example, and not limitation, non-volatile memory 1722 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 1720 may also include random access memory (RAM) that acts as external cache memory. By way of example, and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), sync link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0108] Computer 1712 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 17, for example, illustrates disk storage 1724. Disk storage 1724 may include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 1724 may also include storage media separately or in combination with other storage media, including, but not limited to, an optical disk drive, such as a compact disc read-only memory (CD-ROM), a CD-recordable drive (CD-R drive), a CD-rewriteable drive (CD-RW drive), or a digital versatile disc read-only memory (DVD-ROM) drive. A removable or non-removable interface, such as interface 1726, is typically used to facilitate connection of disk storage 1724 to system bus 1718. Figure 17 also illustrates software that acts as an intermediary between users and the basic computer resources described in preferred operating environment 1700. Such software may include, for example, operating system 1728. Operating system 1728, which may be stored on disk storage 1724, acts to control and allocate resources of the computer 1712. System applications 1730 take advantage of the management of resources by operating system 1728 through program modules 1732 and program data 1734, for example, stored either in system memory 1716 or on disk storage 1724. It should be appreciated that the present disclosure may be implemented with various operating systems or combinations of operating systems. A user enters commands or information into computer 1712 through input devices 1736.The input devices 1736 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, television tuner card, digital camera, digital video camera, webcam, and the like. These and other input devices connect to the processing unit 1714 through the system bus 1718 via interface ports 1738. Interface ports 1738 include, for example, serial ports, parallel ports, game ports, and universal serial buses (USB). The output devices 1740 use several of the same types of ports as the input devices 1736. Thus, for example, a USB port can be used to provide input to the computer 1712 and to output information from the computer 1712 to the output device 1740. An output adapter 1742 is provided to illustrate that some output devices 1740, such as monitors, speakers, and printers, among other output devices 1740, require special adapters. Output adapters 1742 include, by way of illustration and not limitation, video and sound cards that provide a method of connection between output device 1740 and the system bus 1718. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer(s) 1744.

[0109] The computer 1712 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1744. The remote computer 1744 may be a computer, a server, a router, a network PC, a workstation, a microprocessor-based appliance, a peer device or other common network node, and the like, and may typically include many or all of the elements described relative to the computer 1712. For purposes of simplicity, only a memory storage device 1746 is shown with the remote computer 1744. The remote computer 1744 is logically connected to the computer 1712 through a network interface 1748 and then physically connected via communication connection 1750. The network interface 1748 encompasses wired and / or wireless communication networks such as a local area network (LAN), a wide area network (WAN), a cellular network, and the like. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 1750 refers to the hardware / software used to connect network interface 1748 to system bus 1718. While communications connection(s) 1750 are shown internal to computer 1712 for clarity of illustration, they may also be external to computer 1712. The hardware / software for connecting to network interface 1748 may also include, by way of example only, internal and external technologies such as modems, including ordinary telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0110] One or more embodiments may be systems, methods, apparatus, and / or computer program products of any conceivable level of technical detail of integration. A computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to implement aspects of one or more embodiments. A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction-execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may include portable computer diskettes, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), SRAM, portable CD-ROMs, digital versatile disks (DVDs), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as ridge structures in grooves with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as being transitory signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

[0111] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage. The computer-readable program instructions for implementing operations of the disclosed subject matter may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for configuring an integrated circuit, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, or the like, and procedural programming languages ​​such as the “C” programming language or similar. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., over the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the disclosed subject matter.

[0112] Aspects of the disclosed subject matter are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create a method for implementing the function(s) / act(s) specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored thereon includes an article of manufacture containing instructions that implement aspects of the function(s) / act(s) specified in one or more blocks of the flowchart illustrations and / or block diagrams. The computer-readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational acts to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0113] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the disclosed subject matter. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or that implements a combination of dedicated hardware and computer instructions.

[0114] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one computer and / or multiple computers, those skilled in the art will recognize that the present disclosure may also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Those skilled in the art will also recognize that the computer-implemented methods disclosed herein may be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronic devices, and the like. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in local and remote memory storage devices.

[0115] As used herein, terms such as “component,” “system,” “platform,” and “interface” may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functionalities. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a server and the server may be a component. One or more components may reside within a process and / or thread of execution, and a component may be localized on one computer and / or distributed between two or more computers. In another example, each component may execute from various computer-readable media having various data structures stored thereon. Components may communicate via local and / or remote processes, such as according to signals comprising one or more data packets (e.g., data from one component interacting with another component in a local system, a distributed system, and / or a network, e.g., the Internet, with other systems via signals). As another example, a component may be a device having inherent functionality provided by mechanical parts operated by electrical or electronic circuitry operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component may be a device that provides inherent functionality without mechanical parts through electronic components, where the electronic components may include a processor or other means for executing software or firmware that at least partially provides the functionality of the electronic component. In some aspects, a component may emulate the electronic component, for example, via a virtual machine in a cloud computing system.

[0116] Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied under any of the aforementioned multiple examples. Additionally, the articles "a" and "an," as used in this specification and the accompanying drawings, should generally be construed to mean "one or more" unless otherwise specified or clear from the context that the singular form is intended. As used herein, the terms "example" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not meant to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0117] As used herein, the term "processor" may refer to virtually any computing processing unit or device, including, but not limited to, a single-core processor; a single processor with software multithreading execution capabilities; a multi-core processor; a multi-core processor with software multithreading execution capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space usage or enhance the performance of user equipment. A processor may be implemented as a combination of computing processing units. In this disclosure, terms such as “store,” “storage,” “data store,” “data storage,” “database,” and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a “memory” or “memory component” entity embodied in a component that includes memory. It should be recognized that memory and / or memory components described herein may be either volatile or nonvolatile memory, or may include both volatile and nonvolatile memory. By way of illustration and not limitation, nonvolatile memory may include ROM, PROM, EPROM, EEPROM, flash memory, or nonvolatile RAM (e.g., FeRAM). Volatile memory may include, for example, RAM, which may act as external cache memory.By way of example, and not limitation, RAM is available in many forms, including SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, DRRAM, DRDRAM, and RDRAM. Additionally, the memory components of computer-implemented methods or systems disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0118] The foregoing includes merely exemplary systems and computer-implemented methods. Naturally, for purposes of describing the present disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods; however, one skilled in the art will recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "comprises," "having," and "possessing" are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as "comprises" is interpreted when used as a transitional term in a claim. While the description of various embodiments has been presented for illustrative purposes, it is not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was selected to best explain the principles of the embodiments, practical applications of, or technical improvements to, commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A system comprising a qubit chip assembly, the qubit chip assembly comprising: a qubit component fabricated on a substrate, the qubit component including a Josephson junction circuit offset a specified distance from a center point of the qubit component; and a ground plane located on a surface of the qubit chip assembly, wherein a cutout is formed in the ground plane and defined by a remainder of the ground plane, the cutout being positioned above the Josephson junction circuit; and the cutout portion of the ground plane allows optical access for an optical signal to the Josephson junction circuit, and the frequency of the qubit component is tuned based on application of the optical signal to the Josephson junction circuit. system.

2. 10. The system of claim 1, wherein the cutout portion of the ground plane is positioned at least partially above the Josephson junction circuit and offset from the center point of the qubit component.

3. 3. The system of claim 1, wherein the Josephson junction circuit includes a superconducting quantum interferometer loop, the cutout portion of the ground plane allows magnetic flux access to the superconducting quantum interferometer loop, and the frequency of the qubit component is tuned based on application of the magnetic flux to the superconducting quantum interferometer loop.

4. a coil component concentric with the cutout portion of the ground plane, the coil component generating the magnetic flux and applying the magnetic flux to the superconducting quantum interference loop; The system of claim 3 further comprising:

5. 5. The system of claim 4, wherein the cutout portion of the ground plane is a first cutout portion of a first ground plane, a second ground plane is part of an interposer chip assembly associated with the qubit chip assembly, a second cutout portion is formed in the second ground plane and positioned proximate to the Josephson junction circuit, and the second cutout portion facilitates increasing the amount of mutual inductance due to a magnetic field generated by the coil component.

6. 5. The system of claim 1 , wherein the qubit component is associated with a first ground plane located on a first surface of the qubit chip assembly, the ground plane located on the surface of the qubit chip assembly being a second ground plane located on a second surface of the qubit chip assembly, the second ground plane being embedded in the substrate, and the second ground plane being on an opposite side of the qubit chip assembly from the first ground plane.

7. a capacitor component associated with the Josephson junction circuit and part of the qubit component, wherein the remaining portion of the second ground plane is positioned above at least a portion of the capacitor component. The system of claim 6 further comprising:

8. the substrate is a first substrate that provides physical support for the qubit chip assembly, the qubit chip assembly having a first set of through vias, and the system further comprises: an interposer component including a second set of through vias, wherein the interposer component is electrically connected to the qubit chip assembly via a set of bump bonds; and a second substrate that provides physical support for the interposer component; 8. The system according to claim 6 or 7, comprising:

9. forming a qubit component on a substrate, the qubit component including Josephson junction circuitry, the Josephson junction circuitry being offset a specified distance from a center point of the qubit component; and forming a ground plane overlying a surface of a qubit chip package containing the qubit component, wherein a cutout is formed in the ground plane, defined by a remainder of the ground plane, and positioned above the Josephson junction circuitry. Equipped with The method, wherein the cutout portion of the ground plane allows optical signal access to the Josephson junction circuitry, and wherein the frequency of the qubit component is tunable based on application of the optical signal to the Josephson junction circuitry.

10. forming the Josephson junction circuit configuration including a superconducting quantum interference loop, wherein the cutout portion of the ground plane allows magnetic flux access to the superconducting quantum interference loop, and wherein the frequency of the qubit component is tunable based on application of the magnetic flux to the superconducting quantum interference loop by a coil device. The method of claim 9 further comprising:

11. 11. The method of claim 9 or 10, wherein the qubit component is associated with a first ground plane located on a first surface of the qubit chip package, the ground plane located on the surface of the qubit chip package being a second ground plane located on a second surface of the qubit chip package, the second ground plane being embedded in the substrate, the second surface being on an opposite side of the qubit chip package from the first surface.

12. forming a capacitor component associated with the Josephson junction circuitry and part of the qubit component, wherein the remaining portion of the second ground plane is positioned above at least a portion of the capacitor component. The method of claim 11 further comprising:

13. The substrate is a first substrate that provides support for the qubit chip package, and the method further comprises: forming a first set of through vias in the qubit chip package; forming an interposer component including a second set of through vias, the interposer component being associated with a second substrate that provides support for the interposer component; and forming a set of bump bonds connecting the interposer component to the qubit chip package; 13. The method of claim 11 or 12, comprising:

14. 1. A qubit device comprising a qubit chip package, the qubit chip package comprising: a qubit component formed on a substrate component, the qubit component including a Josephson junction component offset from a central region of the qubit component by a specified amount; and a ground plane component located on a surface of the qubit chip package, wherein a cutout portion is formed in the ground plane component and defined by a remainder of the ground plane component, the cutout portion being located above the Josephson junction component; and the cutout portion of the ground plane component allows optical signal access to the Josephson junction component to facilitate tuning of a frequency of the qubit component based on application of the optical signal to the Josephson junction component. Qubit device.

15. 15. The qubit device of claim 14, wherein the Josephson junction component includes a superconducting quantum interferometer loop, and the cutout portion of the ground plane component allows magnetic flux access to the superconducting quantum interferometer loop to facilitate tuning of a frequency of the qubit component based on application of the magnetic flux to the superconducting quantum interferometer loop by a coil component.

16. 16. A qubit device as described in claim 14 or 15, wherein the qubit component is associated with a first ground plane component located on a first surface of the qubit chip package, the ground plane component located on the surface of the qubit chip package being a second ground plane component located on a second surface of the qubit chip package, the second ground plane component being embedded in the substrate component, the second surface being on the opposite side of the qubit chip package from the first surface.

17. the substrate component is a first handler component that provides support for the qubit chip package, the qubit chip package having a first set of through vias, and the qubit device further comprising: a capacitor component associated with the Josephson junction component and part of the qubit component, wherein the remaining portion of the second ground plane component is located above at least a portion of the capacitor component; an interposer component including a second set of through vias, wherein the interposer component is connected to the qubit chip package via a set of bump bond connectors; and a second handler component providing support to the interposer component; 17. The qubit device of claim 16, comprising:

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