Information processing apparatus, image forming apparatus, and method for controlling information processing apparatus

Abstract

To prevent wrong data from being written in a memory while power is cut off.SOLUTION: An information processing apparatus has: a capacitor that stores electric charges supplied from a power source; a first controller that operates by power supply voltage received via the capacitor; a memory that is accessed by the first controller; and a second controller that, when the supply from the power source is stopped for a predetermined time, inhibits a writing operation in the memory performed by the first controller.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an information processing apparatus and an image forming apparatus. and control method for information processing device Regarding. [Background technology]

[0002] In an image forming device, a technology has been disclosed that prevents the loss of the latest data by writing data to non-volatile memory when the zero-cross point of the AC voltage is not detected for a predetermined period of time due to a power outage or unplugging (see, for example, Patent Document 1). Summary of the Invention [Problem to be solved by the invention]

[0003] However, when data is written to the memory during a period when the power supply is cut off and the power supply voltage drops, there is a risk that incorrect data will be written to the memory.

[0004] In view of the above problems, an object of the present invention is to prevent erroneous data from being written to a memory when the power supply is cut off. [Means for solving the problem]

[0005] In order to solve the above technical problems, an information processing device according to one aspect of the present invention includes a capacitor that stores electric charge supplied from a power source, a first controller that operates using a power source voltage received via the capacitor, a memory that is accessed by the first controller, and a second controller that inhibits the first controller from performing a write operation on the memory when the supply of the power source is stopped for a predetermined period of time. The power supply circuit includes a first power-on reset circuit that resets the first controller when the power supply voltage is lower than a first voltage, and a second power-on reset circuit that resets the second controller when the power supply voltage is lower than a second voltage that is lower than the first voltage, and when the power supply voltage drops due to a power cutoff, the second controller is reset after the first controller is reset. It is characterized by: [Effects of the Invention]

[0006] This can prevent erroneous data from being written to the memory when the power is cut off. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating the overall configuration of an image forming apparatus according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing an outline of hardware of a main part of the image forming apparatus of FIG. 1. [Figure 3] 3 is a circuit block diagram showing an example of a controller control board of FIG. 2. FIG. [Figure 4] 4 is a flowchart showing an example of the operation of the controller control board of FIG. 3. [Figure 5] 4 is a sequence diagram showing an example of the operation of the controller control board of FIG. 3. [Figure 6] FIG. 10 is a circuit block diagram illustrating an example of a controller control board in an image forming apparatus according to a second embodiment of the present invention. [Figure 7] 7 is a sequence diagram showing an example of the operation of the controller control board of FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal value, a signal line, or a signal terminal. A symbol indicating a voltage is also used to indicate a voltage line or a voltage terminal to which a voltage is supplied.

[0009] FIG. 1 is a diagram illustrating the overall configuration of an image forming apparatus according to a first embodiment of the present invention. The image forming apparatus 1 illustrated in FIG. 1 is, for example, a digital multifunction peripheral (MFP: Multi-Function Printer) having copy, print, scanner, and facsimile functions. The image forming apparatus 1 can switch between operating modes that respectively realize the copy, print, scanner, and facsimile functions using an application switching key or the like on an operation unit (not shown). The image forming apparatus 1 enters copy mode when the copy function is selected, print mode when the print function is selected, scanner mode when the scanner function is selected, and facsimile mode when the facsimile function is selected. The image forming apparatus 1 may also be a copier with only a copy function, a printer with only a print function, or a facsimile with only a facsimile function.

[0010] Furthermore, the internal state of the image forming apparatus 1 switches to an operating mode (operating state), a standby mode (standby state), an energy saving mode (low power state), etc. depending on the state of the internal circuit. Hereinafter, the energy saving mode is also referred to as an energy saving mode.

[0011] For example, the operating mode includes a copy mode or a print mode in which images or text data are printed on paper media. The print mode includes an operation in facsimile mode in which received data is printed on paper media. The operating mode also includes a scanner mode in which an original document is scanned or a transmission / reception operation in facsimile mode. The state of the internal circuitry is switched by a user operating the operation unit or by control within the image forming apparatus 1.

[0012] For example, image forming apparatus 1 has an automatic document feeder (ADF) 2, an image reading device 3, a writing unit 4, a printer unit 5, a power supply device 20, and a control device 21. Printer unit 5 has a photosensitive drum 6, a developing device 7, a conveyor belt 8, a fixing device 9, and a storage space for a paper feed tray 10. Printer unit 5 creates a toner image to be transferred to a paper medium or the like based on image information. Printer unit 5 is an example of an image forming section that forms an image. Below, as an example of the flow of image formation in image forming apparatus 1, a case where the operating mode is set to copy mode will be briefly described.

[0013] In copy mode, multiple originals to be copied are set in automatic document feeder 2. When a start button on an operation unit (not shown) is pressed, automatic document feeder 2 feeds the originals one by one to image reading device 3. Image reading device 3 reads the image information of each original sent in order from automatic document feeder 2. The image information read by image reading device 3 is processed, for example, by an image processing unit mounted on control device 21.

[0014] The writing unit 4 converts the image information processed by the image processing unit into optical information. The photosensitive drum 6 is uniformly charged by a charger (not shown) and then exposed to laser light containing the optical information converted by the writing unit 4. An electrostatic latent image is formed on the photosensitive drum 6 through exposure. The developing device 7 develops the electrostatic latent image on the photosensitive drum 6, forming a toner image on the photosensitive drum 6. The conveyor belt 8 transfers the toner image to a paper medium or the like. The fixing device 9 fixes the toner image to the paper medium or the like. The transfer paper on which the image of the original has been copied is then discharged from the discharge section.

[0015] For example, the standby mode described above is the state in copy mode until the start button is pressed, and the operating mode is the state from when the start button is pressed until paper media or the like is ejected, in which loads such as motors are operating. After the operating mode ends, the image forming apparatus 1 returns to the standby mode, and if the standby mode continues for a predetermined time, it enters the energy saving mode. Then, if the operation unit is operated during the energy saving mode, the image forming apparatus 1 returns to the standby mode.

[0016] The power supply device 20 converts an AC voltage supplied from an AC power supply 30, such as a commercial power supply, into multiple types of DC voltages (for example, a first DC voltage and a second DC voltage). The power supply device 20 supplies the converted first DC voltage to various loads, such as the printer unit 5 of the image forming apparatus 1. For example, the loads include various motors, a charger that charges the photosensitive drum 6, and a developing roller of the developing device 7. The power supply device 20 supplies the converted second DC voltage to the control device 21.

[0017] The second DC voltage supplied to the control device 21 is used as an operating power source for a CPU (Central Processing Unit), memory, and the like mounted on the control device 21. The control device 21 controls the overall operation of the image forming apparatus 1 by causing a controller such as a built-in CPU to execute a control program. In this way, the image forming apparatus 1 operates by receiving power from a commercial power source. The control device 21 is an example of an information processing device that executes a control program to perform a control method for forming an image, etc.

[0018] Fig. 2 is a block diagram showing an example of a hardware configuration of the main parts of the image forming apparatus 1 shown in Fig. 1. The image forming apparatus 1 has an AC (Alternating Current) / DC (Direct Current) converter 40, a printer 50, a scanner 60, a facsimile 70, an operation unit 80, an engine control board 100, and a controller control board 200.

[0019] The AC / DC converter 40 converts the AC voltage supplied from the AC power supply 30 into a second DC voltage, which is then supplied to the engine control board 100. The AC / DC converter 40 corresponds to the power supply device 20 in FIG. 1. The second DC voltage supplied to the engine control board 100 is then supplied via the engine control board 100 to the control units of the printer 50, the scanner 60, the facsimile 70, and the operation unit 80, and to the controller control board 200.

[0020] 1. The scanner 60 corresponds to the image reading device 3. For example, the facsimile 70, the engine control board 100, and the controller control board 200 correspond to the control device 21 in FIG.

[0021] Fig. 3 is a circuit block diagram showing an example of the controller control board 200 of Fig. 2. The controller control board 200 has a microcomputer 210, a main CPU 220, a power control switch 230, a memory 240, power-on reset circuits 250 and 260, a switch DCSW, an AND circuit AND, and capacitors C1 and C2.

[0022] When AC power supply 30 is connected to image forming apparatus 1 via an AC cable or the like, AC / DC converter 40 outputs a zero-cross signal voltage indicating that power is being supplied while receiving power from AC power supply 30. Zero-cross signal ZCRS is a signal whose logical value is inverted when the AC voltage received from AC power supply 30 crosses 0 V, and is, for example, a pulse signal having the same period as the AC voltage. In this way, AC / DC converter 40 functions as a power supply detector that detects the supply of power.

[0023] The microcomputer 210 operates by receiving a power supply voltage VCCA (second DC voltage). The microcomputer 210 has a function of controlling the power supply of the image forming apparatus 1. For example, the microcomputer 210 controls the supply of the power supply voltage VCCA supplied to the controller control board 200 to the power supply line VCCB.

[0024] Furthermore, the microcomputer 210 can determine whether or not the AC power supply 30 is connected to the image forming apparatus 1 by monitoring the zero-cross signal ZCRS output from the AC / DC converter 40. The microcomputer 210 can control the write protect function of the memory 240 in accordance with the zero-cross signal ZCRS. The control program executed by the microcomputer 210 may be stored in the memory 240 or in an internal memory. The microcomputer 210 is an example of a second controller.

[0025] The main CPU 220 operates by receiving a power supply voltage VCCB (second DC voltage). The main CPU 220 has a function of controlling operations such as printer operation and scanner operation of the image forming apparatus 1. For example, the main CPU 220 accesses the memory 240 to execute a control program that operates the image forming apparatus 1, and reads and writes data and various parameters used for operation to the memory 240. The main CPU 220 is an example of a first controller.

[0026] Power supply control switch 230 controls the connection between power supply line VCCA and power supply line VCCB in response to a control signal from microcomputer 210. For example, when image forming apparatus 1 is set to a normal mode in which it performs operations such as printer operation and scanner operation, power supply control switch 230 connects power supply line VCCA to power supply line VCCB. Also, for example, when image forming apparatus 1 is set to an energy-saving mode, power supply control switch 230 cuts off the connection between power supply line VCCA and power supply line VCCB.

[0027] The memory 240 is an electrically rewritable nonvolatile memory such as a flash memory or MRAM (Magnetoresistive Random Access Memory), and operates by receiving a power supply voltage VCCB. The memory 240 executes a read operation or a write operation in response to a clock signal CLK and a memory access signal (such as an address signal and an access control signal) (not shown) from the main CPU 220. During a write operation, the memory 240 writes a data input signal DI received from the main CPU 220 together with the memory access signal into a memory cell. During a read operation, the memory 240 outputs data read from the memory cell to the main CPU 220 as a data output signal DO.

[0028] The memory 240 prohibits write operations while the write protect terminal / WP receives a write protect signal / WPc output from the main CPU 220 or a write protect signal / WPm output from the microcomputer 210. The write protect signals / WPc, / WPm, and / WP are negative logic signals, with a low level indicating a write-protected state and a high level indicating a write-permitted state. The memory 240 prohibits write operations when the write protect signal / WP is low level, and permits write operations when the write protect signal / WP is high level.

[0029] The write protect signals / WPc and / WPm are supplied to the write protect terminal / WP via an AND circuit AND (a negative logic OR circuit). The AND circuit AND receives the write protect signal / WPc at one input and the write protect signal / WPm at the other input, and outputs the write protect signal / WP to the write protect terminal / WP.

[0030] This allows the write protect of the memory 240 to be controlled not only by the main CPU 220 but also by the microcomputer 210. In other words, even if the main CPU 220 is executing a program that write-accesses the memory 240 when the power is cut off, the microcomputer 210 can mask the high-level write protect signal / WPc output by the main CPU 220. The AND circuit AND is an example of a mask circuit that masks the high-level write protect signal / WPc output by the main CPU 220.

[0031] The two input terminals and one output terminal of the AND circuit AND are each pulled down, which makes it possible to prohibit write access to the memory 240 when any of the write protect signal lines / WPm, / WPc, and / WP is in a floating state, thereby preventing erroneous writing of data to the memory 240.

[0032] Furthermore, the transition time of the write protect signal lines / WPm, / WPc, and / WP from high to low can be made faster compared to when they are not pulled down, which makes it possible to quickly prohibit write access to the memory 240 when the write protect signal / WPm from the microcomputer 210 or the write protect signal / WPc from the main CPU 220 changes to low.

[0033] If memory 240 is a volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), data stored in memory 240 will be lost when power is cut off. On the other hand, memory 240 such as flash memory continues to store data even after power is cut off. For this reason, if there is a risk of erroneous data being written, it is necessary to prohibit write access to memory 240 and prevent malfunction after restarting image forming apparatus 1.

[0034] The power-on reset circuit 250 supplies a high-level reset signal / RSTm to the microcomputer 210 while receiving the power supply voltage VCCA at the power supply terminal, thereby setting the microcomputer 210 to an operable state. When the power supply voltage VCCA drops below a threshold voltage VT2 shown in Fig. 5, the power-on reset circuit 250 sets the reset signal / RSTm to a low level, thereby setting the microcomputer 210 to a reset state. The power-on reset circuit 250 is an example of a second power-on reset circuit.

[0035] The power-on reset circuit 260 supplies a high-level reset signal / RSTc to the main CPU 220 while receiving the power supply voltage VCCB at its power terminal, thereby setting the main CPU 220 to an operable state. When the power supply voltage VCCB drops below the threshold voltage VT1 shown in Fig. 5, the power-on reset circuit 260 sets the reset signal / RSTc to a low level, thereby setting the main CPU 220 to a reset state. The power-on reset circuit 260 is an example of a first power-on reset circuit.

[0036] For example, the threshold voltage VT1 is higher than the threshold voltage VT2. Therefore, when the power supply voltages VCCA and VCCB drop, the reset signal / RSTc changes to low level earlier than the reset signal / RSTm. The threshold voltage VT1 is an example of a first voltage, and the threshold voltage VT2 is an example of a second voltage.

[0037] The switch DCSW is a push-button switch operated by, for example, a serviceman performing maintenance or repairs on the image forming apparatus 1. When the switch DCSW is pressed, the charge accumulated in the capacitors C1 and C2 is discharged to the ground line VSS via the power supply voltage terminal VCCA of the microcomputer 210 and the switch DCSW. This prevents the microcomputer 210 and the main CPU 220 from continuing to operate after the power is turned off until the charge accumulated in the capacitors C1 and C2 is naturally discharged.

[0038] For example, when the service technician performs maintenance or repairs on the image forming apparatus 1, he or she turns off the power, presses the switch DCSW, and then removes the controller control board 200 from the image forming apparatus 1. This shortens the time it takes for the charge accumulated in the capacitors C1 and C2 to be discharged, improving workability. Furthermore, pressing the switch DCSW ensures that the charge is discharged from the capacitors C1 and C2. Therefore, removing the controller control board 200 from the image forming apparatus 1 while charge remains in the capacitors C1 and C2 can prevent damage to the electronic components mounted on the controller control board.

[0039] Capacitor C1 has a function of smoothing power supply voltage VCCA and a function of storing charge supplied from AC / DC converter 40. Capacitor C2 has a function of smoothing power supply voltage VCCB and a function of storing charge supplied from power supply control switch 230.

[0040] Fig. 4 is a flow diagram showing an example of the operation of controller control board 200 of Fig. 3. That is, Fig. 4 shows an example of a control method executed by image forming apparatus 1, and an example of a control program executed by image forming apparatus 1. Fig. 4 also shows an example of a control method executed by an information processing device mounted on image forming apparatus 1, and an example of a control program executed by the information processing device mounted on image forming apparatus 1. The control program may be stored in a recording medium detachably mounted on image forming apparatus 1, and transferred from the recording medium to memory 240, an internal memory of microcomputer 210, or the like.

[0041] First, in step S10, when the AC cable of image forming apparatus 1 is connected to AC power supply 30, AC / DC converter 40 starts generating power supply voltage VCCA. As a result, charge is accumulated in capacitor C1, and power supply voltage VCCA is supplied to microcomputer 210 and power-on reset circuit 250.

[0042] Next, in step S12, the power-on reset circuit 250 sets the reset signal / RSTm from low level to high level (reset release state) in response to the rise in the power supply voltage VCCA, and starts up the microcomputer 210.

[0043] Next, in step S14, the started-up microcomputer 210 turns on the power supply control switch 230 to connect the power supply line VCCA to the power supply line VCCB, thereby storing charge in the capacitor C2.

[0044] Next, in step S16, the microcomputer 210 changes the write protect signal / WEm from low level to high level (H). As a result, the input level of the write protect terminal / WP of the memory 240 also changes from low level to high level (H), and write access to the memory 240 by the main CPU 220 is permitted. After the write protect signal / WPm is set to high level, the main CPU 220 sets the write protect signal / WPc to low level, thereby changing the input level of the write protect terminal / WP to low level. As a result, write access to the memory 240 can be prohibited.

[0045] In step S18, the microcomputer 210 polls the logic level of the zero-cross signal ZCRS. Next, in step S20, the microcomputer 210 determines whether the time during which the logic level of the zero-cross signal ZCRS does not change is equal to or longer than time T1 (a predetermined time). If the logic level of the zero-cross signal ZCRS changes before time T1 has elapsed, the microcomputer 210 returns the process to step S18 and continues polling the zero-cross signal ZCRS. If the period during which the logic level of the zero-cross signal ZCRS does not change is equal to or longer than time T1, the microcomputer 210 proceeds to step S22.

[0046] Although not particularly limited, time T1 may be, for example, 50 ms (milliseconds). This allows microcomputer 210 to detect interruptions of AC power supply 30 while excluding momentary interruptions of AC power supply 30 that do not affect the operation of image forming apparatus 1 from the detection target. Here, the duration of a momentary interruption that does not affect the operation of image forming apparatus 1 is determined depending on the amount of charge that can be stored in capacitors C1 and C2, and time T1 is set based on the determined duration. For example, an interruption of AC power supply 30 occurs due to incorrect unplugging of the AC cable, a power outage, or the like.

[0047] In step S22, the microcomputer 210 changes the write protect signal / WEm from high to low, which also changes the input level of the write protect terminal / WP of the memory 240 from high to low, prohibiting write access to the memory 240 by the main CPU 220.

[0048] Therefore, even if the main CPU 220 can access the memory 240 after the AC power supply 30 is shut off and before the charge accumulated in the capacitors C1 and C2 is discharged, write access to the memory 240 is prohibited. As a result, the write access is stopped midway, and data corruption caused by incorrect data being written to the memory 240 can be prevented. Furthermore, after the image forming apparatus 1 is restarted, malfunction of the image forming apparatus 1 due to the memory 240 holding incorrect data can be prevented.

[0049] Next, in step S24, after the microcomputer 210 prohibits write access to the memory 240, the discharge of the capacitors C1 and C2 is completed, and the operations of the microcomputer 210 and the main CPU 220 are stopped.

[0050] Fig. 5 is a sequence diagram showing an example of the operation of the controller control board of Fig. 3. In Fig. 5, the symbol ON indicates a state in which power is supplied or a state in which the zero-cross signal ZCRS is generated, and the symbol OFF indicates a state in which power supply is stopped or a state in which the generation of the zero-cross signal ZCRS is stopped.

[0051] First, when an AC cable is connected to the AC power supply 30, the AC / DC converter 40 periodically outputs a pulsed zero-cross signal ZCRS to generate a power supply voltage VCCA (FIGS. 5(a) and 5(b)). The capacitor C1 receives the power supply voltage VCCA and accumulates charge.

[0052] When the power supply voltage VCCA becomes equal to or higher than the threshold voltage VT2, the power-on reset circuit 250 changes the reset signal / RSTm to high level (FIG. 5(c)). As a result, the microcomputer 210 starts operation, sets the write protect signal / WPm to high level, and the memory 240 becomes write-accessible (FIG. 5(d)).

[0053] Furthermore, when the microcomputer 210 turns on the power supply control switch 230, the power supply line VCCA is connected to the power supply line VCCB, and the power supply voltage VCCB rises (FIG. 5(e)). The capacitor C2 receives the power supply voltage VCCB and stores charge.

[0054] When the power supply voltage VCCB becomes equal to or higher than the threshold voltage VT1, the power-on reset circuit 260 changes the reset signal / RSTc to high level (FIG. 5(f)). As a result, the main CPU 220 starts operation and starts accessing the memory 240, although this is not shown.

[0055] The microcomputer 210 continues to poll the zero-cross signal ZCRS while receiving the power supply voltage VCCA and operating (FIG. 5(g)). If the microcomputer 210 does not detect a transition edge of the zero-cross signal ZCRS for a time period T1 or longer, it detects that a power supply abnormality such as a cutoff of the AC power supply 30 has occurred, and changes the write protect signal / WPm to low level (FIGS. 5(h) and 5(i)).

[0056] The low-level write protect signal / WPm is supplied to the write protect terminal / WP of the memory 240 via the AND circuit AND, so that the main CPU 220 cannot write access the memory 240. This prevents the main CPU 220 from erroneously writing data to the memory 240 when the power is cut off (FIG. 5(j)). As a result, it is possible to prevent the image forming apparatus 1 from malfunctioning after restarting.

[0057] While the write protect signal / WPm is at a low level, the main CPU 220 can perform read access to the memory 240. The clock CLK in the figure indicates that the main CPU 220 is performing read access to the memory 240, and the data output signal DO in the figure indicates that the data is output from the memory 240 in response to the read access (FIGS. 5(k) and (l)).

[0058] When the AC / DC converter 40 stops generating the power supply voltage VCCA due to the interruption of the AC power supply 30, the charge accumulated in the capacitors C1 and C2 is gradually discharged. When the power supply voltage VCCA becomes lower than the threshold voltage VT2, the power-on reset circuit 250 changes the reset signal / RSTm to low level (FIG. 5(m)). This causes the microcomputer 210 to enter a reset state and stop operating.

[0059] When the power supply voltage VCCB becomes lower than the threshold voltage VT1, the power-on reset circuit 260 changes the reset signal / RSTc to low level (FIG. 5(n)). This causes the main CPU 220 to enter a reset state and stop operation (FIG. 5(o)). Note that even if the main CPU 220 stops operation during a read access by the main CPU 220, the data stored in the memory 240 is retained without being lost. The power supply voltages VCCA and VCCB gradually decrease until the discharge of the capacitors C1 and C2 is completed (FIGS. 5(p) and (q)).

[0060] Because the threshold voltage VT1 is set higher than the threshold voltage VT2, the reset signal / RSTc transitions to low level earlier than the reset signal / RSTm. This allows the main CPU 220 to be stopped before the microcomputer 210 that controls the power supply is stopped. Therefore, even if the write protect signal / WPm temporarily goes high when the microcomputer 210 is stopped, it is possible to prevent the main CPU 220 from performing write access to the memory 240. Since erroneous writing of data can be prevented, it is possible to prevent malfunctions after restarting the image forming apparatus 1.

[0061] As described above, in this embodiment, when the microcomputer 210 detects the occurrence of a power supply abnormality such as a cutoff of the AC power supply 30, it sets the write protect signal / WP to a low level and prohibits write access to the memory 240. This makes it possible to prevent the main CPU 220 from erroneously writing data to the memory 240 when the power is cut off, and to prevent malfunctions after restarting the image forming apparatus 1.

[0062] By transitioning the reset signal / RSTc to low level earlier than the reset signal / RSTm when the power is cut off, the main CPU 220 can be stopped before the microcomputer 210 is stopped. This makes it possible to prevent the main CPU 220 from erroneously writing data to the memory 240, even if the write protect signal / WPm temporarily goes high level when the microcomputer 210 is stopped, and prevents malfunction of the image forming apparatus 1.

[0063] For example, if the memory 240 is a non-volatile memory, it continues to store data even after power is cut off. In this embodiment, the microcomputer 210 prohibits write access to the memory 240 when power is cut off, thereby preventing erroneous data from being written to the memory 240 when power is cut off. This prevents malfunction of the image forming apparatus 1 after restart due to erroneous data being stored in the memory 240.

[0064] When power is cut off, the microcomputer 210 sets the write protect signal / WPm to low level and forcibly outputs the low-level write protect signal / WP to the memory 240 via the AND circuit AND. This makes it possible to mask the output of the high-level write protect signal / WPc output by the main CPU 220 to the memory 240 even if the main CPU 220 is executing a program that write-accesses the memory 240 when power is cut off. As a result, it is possible to prevent erroneous writing of data to the memory 240 when power is cut off.

[0065] Figure 6 is a circuit block diagram showing an example of a controller control board in an image forming apparatus according to a second embodiment of the present invention. Elements similar to those in Figures 1 to 3 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The controller control board 200A of this embodiment is configured by adding a battery BAT and diodes D1 and D2 to the controller control board 200 of Figure 3.

[0066] For example, the controller control board 200A may be mounted on the control device 21 in Fig. 1 to function as an image processing unit of the image forming apparatus 1. The hardware overview of the image forming apparatus 1 mounted with the controller control board 200A is the same as that shown in Fig. 2.

[0067] The power supply terminal VCCA of the microcomputer 210 and a power supply terminal (not shown) of the power-on reset circuit 250 are connected to the power supply line VCCA via a diode D2, and are also connected to the battery BAT via a diode D2. The microcomputer 210 operates on the power supply voltage VCCA or the voltage supplied from the battery BAT. Note that the diode D1 prevents the capacitor C1 from being charged by the voltage output by the battery BAT.

[0068] While the battery BAT is outputting a voltage, the power-on reset circuit 250 outputs a high-level reset signal / RSTm. Therefore, the power-on reset circuit 250 sets the reset signal / RSTm to a low level or a high level according to the power supply voltage VCCA generated by the AC / DC converter 40 only when the battery BAT is depleted.

[0069] In this embodiment, the microcomputer 210 can operate using power from the battery BAT even when the power supply is abnormally interrupted. Therefore, even when the power supply voltage VCCA generated by the AC / DC converter 40 drops due to an abnormal power supply interruption, it is possible to prevent a voltage lower than the guaranteed input voltage of the microcomputer 210 from being supplied to the power supply terminal VCCA of the microcomputer 210. Therefore, the microcomputer 210 can operate normally even when the power supply is interrupted, and can change the write protect signal / WPm to low level if it does not detect a transition edge of the zero-cross signal ZCRS for time T1 or longer.

[0070] Fig. 7 is a sequence diagram showing an example of the operation of the controller control board 200A of Fig. 6. Detailed description of the same operations as those in Fig. 5 will be omitted. The operation flow of the controller control board 200A is the same as that in Fig. 4.

[0071] The waveforms of the AC power supply 30, the zero-cross signal ZCRS, the power supply voltage VCCA output by the AC / DC converter 40, the clock signal CLK of the memory 240, and the data output signal DO of the memory 240 are the same as those in Figure 5. The waveforms of the power supply voltage VCCB and the reset signal / RSTc are the same as those in Figure 5, except that their rising timings are earlier than those in Figure 5. The waveform of the write protect signal / WPm is the same as that in Figure 5, except that it is set to a high level when the AC cable is connected.

[0072] The dashed dotted lines shown for the power supply terminal VCCA of the microcomputer 210, the reset signal / RSTm, and the write protect signal / WPm indicate waveforms when the battery BAT is depleted, and are similar to the waveforms in FIG.

[0073] In this embodiment, the power supply terminal VCCA of the microcomputer 210 receives the power supply voltage supplied from the battery BAT regardless of whether there is a supply from the AC power supply 30, and is therefore maintained at a constant voltage output from the battery BAT (FIG. 7(a)). Similarly, the power-on reset circuit 250 receives the power supply voltage supplied from the battery BAT regardless of whether there is a supply from the AC power supply 30, and therefore fixes the reset signal / RSTm to a high level (FIG. 7(b)).

[0074] Because the reset signal / RSTm is fixed at a high level, the microcomputer 210 keeps the power supply control switch 230 on at all times. The power supply line VCCB is always connected to the power supply line VCCA. Therefore, the power supply voltage VCCB rises together with the power supply voltage VCCA output from the AC / DC converter 40 (FIG. 7(c)).

[0075] When the power supply voltage VCCB becomes equal to or higher than the threshold voltage VT1, the power-on reset circuit 260 changes the reset signal / RSTc to high level (FIG. 7(d)). This causes the main CPU 220 to start operating and begin accessing the memory 240.

[0076] As in FIG. 5, when the microcomputer 210 does not detect a transition edge of the zero-cross signal ZCRS for a period of time T1 or longer, it changes the write protect signal / WPm to low level (FIGS. 7(e) and (f)).

[0077] When the generation of the power supply voltage VCCA by the AC / DC converter 40 is stopped due to interruption of the AC power supply 30, the charge accumulated in the capacitors C1 and C2 is gradually discharged. The power supply terminal VCCA of the microcomputer 210 receives the power supply voltage supplied from the battery BAT regardless of whether or not there is a supply from the AC power supply 30, and is therefore maintained at a constant voltage (FIG. 7(g)). Similarly, the power-on reset circuit 250 receives the power supply voltage supplied from the battery BAT regardless of whether or not there is a supply from the AC power supply 30, and therefore fixes the reset signal / RSTm to a high level (FIG. 7(h)). The operation of the power-on reset circuit 260 (the waveform of the reset signal / RSTc) is the same as that shown in FIG. 5.

[0078] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, when a power supply abnormality occurs, such as when AC power supply 30 is interrupted, microcomputer 210 prohibits write access to memory 240, thereby preventing erroneous writing of data to memory 240 when power is interrupted and preventing malfunction after restarting image forming apparatus 1.

[0079] Furthermore, in this embodiment, the microcomputer 210 can operate using power from the battery BAT even when the power supply is abnormally cut off, so it can operate normally and monitor the zero-cross signal ZCRS even when the power supply is cut off. If the microcomputer 210 does not detect a transition edge of the zero-cross signal ZCRS for time T1 or longer, it changes the write protect signal / WPm to low level, thereby reliably prohibiting write access to the memory 240.

[0080] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0081] 1. Image forming device 2 Automatic document feeder 3. Image reading device 4 writing units 5 Printer unit 6 Photosensitive drum 7. Developing device 8 conveyor belt 9 Fixing device 10 Paper tray 20 Power supply 21 Control device 30 AC power supply 40 AC / DC converter 50 printers 60 Scanner 70 Facsimile 80 Control section 100 Engine control board 200, 200A controller control board 210 Microcomputer 220 Main CPU 230 Power Control Switch 240 memory 250, 260 Power-on reset circuit AND circuit BAT Battery C1 and C2 capacitors CLK Clock signal D1, D2 diodes DCSW switch DI Data Input Signal DO Data output signal / RSTc, / RSTm Reset signal VCCA, VCCB power supply voltage / WPc, / WPm Write protect signal ZCRS Zero Cross Signal [Prior art documents] [Patent documents]

[0082] [Patent Document 1] Japanese Patent Application Publication No. 10-185965

Claims

1. a capacitor that stores charge supplied from a power supply; a first controller that operates using a power supply voltage received via the capacitor; a memory accessed by the first controller; a second controller that inhibits the first controller from performing a write operation on the memory when the supply of power is stopped for a predetermined period of time; a first power-on reset circuit that resets the first controller when the power supply voltage is lower than a first voltage; a second power-on reset circuit that resets the second controller when the power supply voltage is lower than a second voltage that is lower than the first voltage; When the power supply voltage drops due to a power cutoff, the second controller is reset after the first controller is reset. An information processing device characterized by:

2. a capacitor that stores charge supplied from a power supply; a first controller that operates using a power supply voltage received via the capacitor; a memory accessed by the first controller; a second controller that inhibits the first controller from performing a write operation on the memory when the supply of power is stopped for a predetermined period of time; a mask circuit that masks a write permission state due to a write protect signal output by the first controller to the memory in response to a write protect signal output by the second controller when the supply of the power supply is stopped for a predetermined time; An information processing device comprising:

3. a battery connected to a power supply terminal of the second controller; The second controller operates on a power supply voltage supplied from the capacitor or a power supply voltage supplied from the battery, and when the supply of the power supply is stopped for a predetermined time, prohibits the first controller from performing a write operation on the memory.

3. The information processing device according to claim 1, wherein:

4. The memory is an electrically rewritable non-volatile memory.

4. The information processing device according to claim 1, wherein:

5. a mask circuit for masking a write permission state due to a write protect signal output by the first controller to the memory in response to the write protect signal output by the second controller when the supply of the power supply is stopped for a predetermined time; 2. The information processing device according to claim 1,

6. an image forming unit that forms an image; a capacitor that stores charge supplied from a power supply; a first controller that operates using a power supply voltage received via the capacitor; a memory accessed by the first controller; a second controller that inhibits the first controller from performing a write operation on the memory when the supply of power is stopped for a predetermined period of time; a first power-on reset circuit that resets the first controller when the power supply voltage is lower than a first voltage; a second power-on reset circuit that resets the second controller when the power supply voltage is lower than a second voltage that is lower than the first voltage; When the power supply voltage drops due to a power cutoff, the second controller is reset after the first controller is reset. An image forming apparatus comprising:

7. an image forming unit that forms an image; a capacitor that stores charge supplied from a power supply; a first controller that operates using a power supply voltage received via the capacitor; a memory accessed by the first controller; a second controller that inhibits the first controller from performing a write operation on the memory when the supply of power is stopped for a predetermined period of time; a mask circuit that masks a write permission state due to a write protect signal output by the first controller to the memory in response to a write protect signal output by the second controller when the supply of the power supply is stopped for a predetermined time; An image forming apparatus comprising:

8. A control method for an information processing device having a capacitor that stores electric charges supplied from a power supply, a first controller that operates by a power supply voltage received via the capacitor, a memory that is accessed by the first controller, a second controller that inhibits a write operation of the first controller to the memory when the supply of the power supply is stopped for a predetermined time, a first power-on reset circuit that resets the first controller when the power supply voltage is lower than a first voltage, and a second power-on reset circuit that resets the second controller when the power supply voltage is lower than a second voltage that is lower than the first voltage, prohibiting the first controller from performing a write operation on the memory when the supply of power is stopped for a predetermined period of time; When the power supply voltage drops due to a power cutoff, the second controller is reset after the first controller is reset. A method for controlling an information processing device, comprising:

9. A control method for an information processing device having a capacitor that stores electric charge supplied from a power supply, a first controller that operates by a power supply voltage received via the capacitor, a memory that is accessed by the first controller, and a second controller that inhibits a write operation of the first controller to the memory when the supply of the power supply is stopped for a predetermined period of time, comprising: prohibiting the first controller from performing a write operation on the memory when the supply of power is stopped for a predetermined period of time; masking a write permission state due to a write protect signal output by the first controller to the memory in response to a write protect signal output by the second controller when the supply of the power supply is stopped for a predetermined time; A method for controlling an information processing device, comprising:

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