Power Conversion Device

Abstract

To provide a power converter of which inductance is reduced.SOLUTION: An inverter circuit is a 3-level inverter circuit. The inverter circuit includes: a P bus bar 71 connected to a higher potential side terminal of a battery; an N bus bar 72 connected to a lower potential side terminal of the battery; and an M bus bar 73 as a potential between the P bus bar 71 and the N bus bar 72. The inverter circuit includes: a PM capacitor 30 connected to the P bus bar and the M bus bar; an MN capacitor 40 connected to the N bus bar and the M bus bar; and a semiconductor device 20 connected to the M bus bar. The M bus bar includes: a semiconductor device 20; and a base part 73a as a part between the PM capacitor and the MN capacitor, the base part being arranged between the P bus bar and the N bas bar and facing the P bus bar and the N bus bar.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] One example of a conventional multilevel inverter is a three-level inverter disclosed in Patent Document 1. The three-level inverter includes a cooling fin base, a first switching function element, a first diode, a second switching function element, a fourth switching function element, a second diode, a third switching function element, and a connection plate. The three-level inverter also includes a first switching function element, a first diode, a second switching function element, a fourth switching function element, a second diode, and a third switching function element, each arranged on both sides of the cooling fin base with their back surfaces facing each other. In the three-level inverter, each switching function element and each diode are connected by connection plates provided to face the three sides of the cooling fin base. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-201249 Summary of the Invention [Problem to be solved by the invention]

[0004] In a three-level inverter, the midpoint wiring is divided into two parts by a cooling fin base. This causes a problem of large inductance between the high-potential wiring and the low-potential wiring. Furthermore, further improvements are required for power conversion devices in the above and other aspects not mentioned above.

[0005] One disclosed object is to provide a power converter with reduced inductance. [Means for solving the problem]

[0006] The power conversion device disclosed herein comprises: A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, a high-potential wiring (71) connected to the positive electrode of the power supply; a low potential wiring (72) connected to the negative terminal of the power supply; At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to a high-potential wiring, a low-potential wiring, and an output wiring; a first capacitor (30) having a high potential side electrode connected to the high potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring; At least one midpoint wiring is a part between the second power module and the first capacitor and the second capacitor, and is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring. Crate , The first capacitor and the second capacitor are arranged such that the first midpoint electrode and the second midpoint electrode face each other, The midpoint wiring is sandwiched between the first capacitor and the second capacitor, and has a connection portion (73c) connected to the first midpoint electrode and the second midpoint electrode. It is characterized by:

[0007] In the power conversion device disclosed herein, a midpoint wiring is disposed between a high-potential wiring and a low-potential wiring, and has an opposing portion opposing the high-potential wiring and the low-potential wiring. Therefore, the power conversion device can cancel out magnetic fields between the high-potential wiring and the opposing portion of the midpoint wiring, and between the opposing portion of the midpoint wiring and the low-potential wiring. Therefore, the power conversion device can reduce inductance. Further, the power conversion device disclosed herein is A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, a high-potential wiring (71) connected to the positive electrode of the power supply; a low potential wiring (72) connected to the negative terminal of the power supply; At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to a high-potential wiring, a low-potential wiring, and an output wiring; a first capacitor (30) having a high potential side electrode connected to the high potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring; At least one midpoint wiring is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring. 、 The midpoint wiring has a connection portion (73c) connected to the first midpoint electrode and the second midpoint electrode, and a portion protruding from the connection portion and sandwiched between the first capacitor and the second capacitor. Further, the power conversion device disclosed herein is A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, a high-potential wiring (71) connected to the positive electrode of the power supply; a low potential wiring (72) connected to the negative terminal of the power supply; At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to a high-potential wiring, a low-potential wiring, and an output wiring; a first capacitor (30) having a high potential side electrode connected to the high potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring; at least one midpoint wiring is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing portion (73a) opposing the high potential wiring and the low potential wiring; the first capacitor and the second capacitor are arranged such that a side surface connected to the first midpoint electrode and the high potential side electrode faces a side surface connected to the second midpoint electrode and the low potential side electrode; The midpoint wiring has two connection parts (73c) connected to the first midpoint electrode and the second midpoint electrode, and the part connecting the two connection parts is disposed between the first capacitor and the second capacitor. Further, the power conversion device disclosed herein is A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, a high-potential wiring (71) connected to the positive electrode of the power supply; a low potential wiring (72) connected to the negative terminal of the power supply; At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to a high-potential wiring, a low-potential wiring, and an output wiring; a first capacitor (30) having a high potential side electrode connected to the high potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring; at least one midpoint wiring is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing portion (73a) opposing the high potential wiring and the low potential wiring; The first capacitor and the second capacitor are arranged such that the first midpoint electrode and the low potential side electrode or the second midpoint electrode and the high potential side electrode face each other, the midpoint wiring has two connection portions (73c) connected to the first midpoint electrode and the second midpoint electrode, One of the connection portions is disposed in a region where the first capacitor and the second capacitor face each other. Further, the power conversion device disclosed herein is A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, a high-potential wiring (71) connected to the positive electrode of the power supply; a low potential wiring (72) connected to the negative terminal of the power supply; At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to a high-potential wiring, a low-potential wiring, and an output wiring; a first capacitor (30) having a high potential side electrode connected to the high potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring; At least one midpoint wiring is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring. , the first capacitor and the second capacitor are arranged such that a side surface connected to the first midpoint electrode and the high potential side electrode faces a side surface connected to the second midpoint electrode and the low potential side electrode; The midpoint wiring has two connection parts (73c) connected to the first midpoint electrode and the second midpoint electrode, and the part connecting the two connection parts is arranged along the arrangement direction of the first capacitor and the second capacitor.

[0008] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a schematic configuration of an inverter circuit in a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a schematic configuration of an inverter circuit. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 4 is a plan view seen from the direction of arrow IV in FIG. [Figure 5] FIG. 2 is a perspective view showing a schematic configuration of an inverter circuit. [Figure 6] FIG. 6 is a cross-sectional view showing a schematic configuration of a capacitor device according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a schematic configuration of a capacitor device according to a third embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a schematic configuration of a capacitor device according to a fourth embodiment. [Figure 9] FIG. 10 is a plan view showing a schematic configuration of a capacitor device according to a fifth embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. [Figure 11]FIG. 10 is a cross-sectional view taken along line XI-XI in FIG. 9. [Figure 12] FIG. 10 is a plan view showing a schematic configuration of a capacitor device according to a sixth embodiment. [Figure 13] FIG. 13 is a circuit diagram showing a schematic configuration of an inverter circuit according to a seventh embodiment. [Figure 14] FIG. 2 is a cross-sectional view showing a schematic configuration of an inverter circuit. [Figure 15] FIG. 2 is a perspective view showing the arrangement of a capacitor device. [Figure 16] FIG. 13 is a perspective view showing the arrangement of a capacitor device according to an eighth embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a ninth embodiment. [Figure 18] FIG. 22 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a tenth embodiment. [Figure 19] FIG. 22 is a cross-sectional view showing a schematic configuration of an inverter circuit according to an eleventh embodiment. [Figure 20] FIG. 23 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a twelfth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several embodiments for carrying out the present disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in the preceding embodiment may be assigned the same reference numerals, and duplicated explanations may be omitted. In each embodiment, when only a part of the configuration is described, the other parts of the configuration may be applied by referring to the other embodiment described previously.

[0011] (First embodiment) An inverter circuit 100 of a first embodiment will be described with reference to FIGS. 1 to 5. The inverter circuit 100 is configured to divide an input DC voltage into a plurality of values ​​and to be able to output voltages at a plurality of levels. The inverter circuit 100 is a so-called multilevel inverter. Whereas a two-level inverter can output voltages at two levels other than 0, namely +E, -E, and 0, where E is the voltage of a battery 200, a multilevel inverter can output voltages at three or more levels. In this embodiment, a three-level inverter circuit 100 is used as an example.

[0012] The inverter circuit 100 can be mounted on a mobile object such as a vehicle or an aircraft. As shown in FIG. 1, the inverter circuit 100 is electrically connected to a battery 200 and a motor 300. The motor 300 is a three-phase motor including a U-phase coil 301, a V-phase coil 302, and a W-phase coil 303. For example, a motor generator can be used as the motor 300. The inverter circuit 100 converts DC power output by the battery 200 into three-phase AC power and supplies the three-phase AC power to the motor 300. The inverter circuit 100 corresponds to a power conversion device.

[0013] <Circuit configuration of inverter circuit 100> The circuit configuration of the inverter circuit 100 will be described with reference to Fig. 1. The inverter circuit 100 includes switching elements 11 to 16, a U-phase middle section 21, a V-phase middle section 22, a W-phase middle section 23, and a capacitor device 60. Note that Fig. 1 illustrates a PM capacitor 30 and an MN capacitor 40 included in the capacitor device 60.

[0014] The switching elements 11 to 16 may be MOSFETs, IGBTs, or the like. Furthermore, the switching elements 11 to 16 may be configured primarily from wide bandgap semiconductors such as Si or SiC. The gate electrodes of the switching elements 11 to 16 are connected to an electronic control device (not shown). The switching elements 11 to 16 are controlled and driven by the electronic control device.

[0015] Switching elements 11 to 16 include U-phase upper arm element 11, U-phase lower arm element 12, V-phase upper arm element 13, V-phase lower arm element 14, W-phase upper arm element 15, and W-phase lower arm element 16.

[0016] U-phase upper arm element 11 and U-phase lower arm element 12 are connected in series between a high potential side terminal (P) and a low potential side terminal (N) of battery 200. A source terminal of U-phase upper arm element 11 and a drain terminal of U-phase lower arm element 12 are connected to U-phase coil 301. U-phase upper arm element 11 and U-phase lower arm element 12 can be collectively referred to as a U-phase arm.

[0017] V-phase upper arm element 13 and V-phase lower arm element 14 are connected in series between the high potential terminal and the low potential terminal of battery 200. The source terminal of V-phase upper arm element 13 and the drain terminal of V-phase lower arm element 14 are connected to V-phase coil 302. V-phase upper arm element 13 and V-phase lower arm element 14 can be collectively referred to as a V-phase arm.

[0018] W-phase upper arm element 15 and W-phase lower arm element 16 are connected in series between the high potential terminal and the low potential terminal of battery 200. The source terminal of W-phase upper arm element 15 and the drain terminal of W-phase lower arm element 16 are connected to W-phase coil 303. W-phase upper arm element 15 and W-phase lower arm element 16 can be collectively referred to as a V-phase arm.

[0019] In this way, each arm is connected in series between a P bus bar 71 and an N bus bar 72, which will be described later. With regard to the structure of the switching elements 11 to 16, a battery 200, which will be described later, corresponds to the power source. The high potential side terminal corresponds to the positive electrode. The low potential side terminal corresponds to the negative electrode.

[0020] The U-phase middle section 21, V-phase middle section 22, and W-phase middle section 23 are connected to each arm and a midpoint (neutral point) M between the high potential and the low potential. Each of the middle sections 21 to 23 includes two switching elements. The switching elements can be the same as the switching elements 11 to 16 described above. The switching elements have their gate electrodes connected to an electronic control device. The switching elements are driven and controlled by the electronic control device. The midpoint M can be considered to be a location of an intermediate potential between the high potential and the low potential. The midpoint M is also located between the PM capacitor 30 and the MN capacitor 40.

[0021] The U-phase middle section 21 includes a first U-phase middle element 21a and a second U-phase middle element 21b as switching elements. The first U-phase middle element 21a has a drain terminal connected to midpoint M and a source terminal connected to a source terminal of the second U-phase middle element 21b. The drain terminal of the second U-phase middle element 21b is connected to the source terminal of the U-phase upper arm element 11 and the drain terminal of the U-phase lower arm element 12.

[0022] The V-phase middle section 22 includes a first V-phase middle element 22a and a second V-phase middle element 22b as switching elements. The first V-phase middle element 22a has a drain terminal connected to the midpoint M and a source terminal connected to the source terminal of the second V-phase middle element 22b. The drain terminal of the second V-phase middle element 22b is connected to the source terminal of the V-phase upper arm element 13 and the drain terminal of the V-phase lower arm element 14.

[0023] The W-phase middle section 23 includes a first W-phase middle element 23a and a second W-phase middle element 23b as switching elements. The drain terminal of the first W-phase middle element 23a is connected to the midpoint M, and the source terminal is connected to the source terminal of the second W-phase middle element 23b. The drain terminal of the second W-phase middle element 23b is connected to the source terminal of the W-phase upper arm element 15 and the drain terminal of the W-phase lower arm element 16. The structures of the U-phase middle section 21, V-phase middle section 22, and W-phase middle section 23 will be described later.

[0024] The capacitor device 60 includes, as smoothing capacitors, a PM capacitor 30 and an MN capacitor 40. The PM capacitor 30 is connected between the high potential side terminal and a midpoint M. The MN capacitor 40 is connected between the midpoint M and a low potential side terminal. Therefore, the PM capacitor 30 and the MN capacitor 40 are connected in series.

[0025] The PM capacitor 30 and the MN capacitor 40 are provided mainly for voltage stabilization and current ripple absorption. In other words, the PM capacitor 30 and the MN capacitor 40 are provided to suppress the allowable voltage fluctuation at the midpoint M and to reduce the current ripple that flows out of the inverter circuit 100. The PM capacitor 30 corresponds to the first capacitor. The MN capacitor 40 corresponds to the second capacitor.

[0026] The present disclosure can also be applied to a diode-clamped (T-type) inverter circuit 100. The present disclosure can also be used in an inverter circuit 100 with N levels (N=4) or more. In this case, the intermediate potential is N-2.

[0027] <Structure of inverter circuit 100> 2 to 5, the structure of the inverter circuit 100 will be described. In the inverter circuit 100, a capacitor device 60 and a structure in which the semiconductor devices 10, 20 and a cooler 90 are integrally assembled are arranged side by side. In the drawings, the direction in which the capacitor device 60 and the structure are arranged is indicated by an arrow AD.

[0028] As shown in FIGS. 2 to 5, the inverter circuit 100 includes bus bars 71 to 74 that connect the capacitors 30 to 50 with the semiconductor devices 10 and 20. The bus bars 71 to 74 are conductive members whose main component is copper or the like. The bus bars 71 to 74 are flat-plate-shaped members. Each of the bus bars 71 to 74 is made of a single flat-plate-shaped member. It can also be said that each of the bus bars 71 to 74 is formed by bending a single metal plate, for example.

[0029] The P bus bar 71 is connected to a high-potential side terminal. A terminal connected to the high-potential side terminal is connected to the P bus bar 71. The P bus bar 71 corresponds to a high-potential wiring.

[0030] 2 and 4, the P bus bar 71 has a base portion 71a, a switch-side connection portion 71b connected to the base portion 71a, and a capacitor-side connection portion 71c connected to the base portion 71a. The base portion 71a is a base portion connected to the switch-side connection portion 71b and the capacitor-side connection portion 71c. The switch-side connection portion 71b is connected to a P terminal 1 of the semiconductor device 10, which will be described later. The capacitor-side connection portion 71c is connected to a first PM terminal 31 of a PM capacitor 30, which will be described later.

[0031] The N bus bar 72 is connected to a low potential side terminal. A terminal connected to the low potential side terminal is connected to the N bus bar 72. The N bus bar 72 corresponds to a low potential wiring.

[0032] 2 and 4, the N bus bar 72 has a base portion 72a, a switch-side connection portion 72b connected to the base portion 72a, and a capacitor-side connection portion 72c connected to the base portion 72a. The base portion 72a is a base portion connected to the switch-side connection portion 72b and the capacitor-side connection portion 72c. The switch-side connection portion 72b is connected to the N terminal 2 of the semiconductor device 10. The capacitor-side connection portion 72c is connected to the second MN terminal 42 of the MN capacitor 40, which will be described later.

[0033] Furthermore, as shown in Fig. 5, the N bus bar 72 has an extension portion 72d. The extension portion 72d is a portion that is continuous with the base portion 72a and that extends up to above the O bus bar 74. The extension portion 72d is disposed opposite the O bus bar 74. Note that in Fig. 4, the extension portion 72d is not shown to simplify the drawing. The N bus bar 72 does not necessarily have to have the extension portion 72d.

[0034] The M bus bar 73 forms the midpoint M. The M bus bar 73 has a potential between the P bus bar 71 and the N bus bar 72. The M bus bar 73 is connected to the PM capacitor 30 and the MN capacitor 40. The terminal connected to the midpoint M is connected to the M bus bar 73. The M bus bar 73 corresponds to midpoint wiring. In this embodiment, a configuration including one M bus bar 73 is adopted. However, the present disclosure is not limited to this. It is sufficient to include at least one M bus bar 73. The number of M bus bars 73 varies depending on the number of output levels of the inverter circuit 100.

[0035] 2 and 4, the M bus bar 73 has a base portion 73a, a switch-side connection portion 73b connected to the base portion 73a, and a capacitor-side connection portion 73c connected to the base portion 73a. The base portion 73a is a base portion connected to the switch-side connection portion 73b and the capacitor-side connection portion 73c. ​​The switch-side connection portion 73b is connected to an M terminal 4 of the semiconductor device 20, which will be described later.

[0036] The capacitor side connection portion 73c is connected to the second PM terminal 32 of the PM capacitor 30 and the first MN terminal 41 of the MN capacitor 40. In other words, one surface of the capacitor side connection portion 73c is connected to the second PM terminal 32, and the other surface is connected to the first MN terminal 41. The capacitor side connection portion 73c is commonly connected to the PM capacitor 30 and the MN capacitor 40. As such, in this embodiment, as an example, an M bus bar 73 provided with only one capacitor side connection portion 73c is employed. The positional relationship between the bus bars 71 to 73 will be described in detail later.

[0037] The O bus bar 74 is connected to the O terminal 3 of the semiconductor device 10. It is an output wiring. The inverter circuit 100 includes an O bus bar 74 connected to each of the U-phase coil 301, the V-phase coil 302, and the W-phase coil 303. The O bus bar 74 corresponds to the output wiring.

[0038] In this embodiment, as an example, an example is adopted in which insulating members 80 are provided to electrically insulate the components from one another. The insulating members 80 are provided between the P bus bar 71 and the M bus bar 73, and between each bus bar 71, 73 and the PM capacitor 30. The insulating members 80 are also provided between the M bus bar 73 and the N bus bar 72, and between each bus bar 72, 73 and the MN capacitor 40. However, if electrical insulation is possible, there is no need to provide the insulating members 80.

[0039] The semiconductor devices 10 and 20 are, for example, two bare-chip switching elements connected together and covered with an electrically insulating sealing resin. As shown in FIGS. 2 and 4, the semiconductor devices 10 and 20 have terminals 1 to 5 with their tips protruding from the sealing resin. The inverter circuit 100 includes a plurality of semiconductor devices 10 and a plurality of semiconductor devices 20. The semiconductor devices 10 and 20 are arranged side by side and attached to a cooler 90. Note that the cooler 90 is omitted from FIG. 4 to simplify the drawing.

[0040] The inverter circuit 100 includes three semiconductor devices 10 that configure each arm. The semiconductor device 10 of the U-phase arm includes a U-phase upper arm element 11 and a U-phase lower arm element 12. The semiconductor device 10 of the V-phase arm includes a V-phase upper arm element 13 and a V-phase lower arm element 14. The semiconductor device 10 of the W-phase arm includes a W-phase upper arm element 15 and a W-phase lower arm element 16. Each semiconductor device 10 also includes a P terminal 1, an N terminal 2, an O terminal 3, and a signal terminal 5. The semiconductor device 10 can also be referred to as an arm device. The semiconductor device 10 corresponds to a first power module.

[0041] The inverter circuit 100 includes three semiconductor devices 20 constituting each of the middle sections 21 to 23. The semiconductor device 20 of the U-phase middle section 21 includes a first U-phase middle element 21a and a second U-phase middle element 21b. The semiconductor device 20 of the V-phase middle section 22 includes a first V-phase middle element 22a and a second V-phase middle element 22b. The semiconductor device 20 of the W-phase middle section 23 includes a first W-phase middle element 23a and a second W-phase middle element 23b. Each semiconductor device 20 also includes an O terminal 3, an M terminal 4, and a signal terminal 5. The semiconductor device 20 can also be referred to as a middle device. The semiconductor device 20 corresponds to a second power module.

[0042] As shown in FIG. 4, P terminal 1 is connected to P bus bar 71. N terminal 2 is connected to N bus bar 72. O terminal 3 is connected to O bus bar 74. M terminal 4 is connected to M bus bar 73. As shown in FIG. 2, signal terminal 5 is connected to wiring board 110. Note that wiring board 110 is a board in which conductive wiring is provided on an insulating base material such as resin. Wiring board 110 is connected to an electronic control device.

[0043] The cooler 90 is configured to circulate a coolant such as water in order to cool the semiconductor devices 10 and 20. The cooler 90 sandwiches the semiconductor devices 10 and 20 between the portions through which the coolant flows.

[0044] Therefore, the switch-side connection portions 71b to 73b of the bus bars 71 to 74, which are connection portions with the terminals 1 to 4, are arranged near the cooler 90. Furthermore, the bus bars 71 to 74 are connected to the terminals 1 to 4 of the semiconductor devices 10 and 20, which are cooled by the cooler 90, as described above. Therefore, the bus bars 71 to 74 are cooled by the cooler 90 together with the semiconductor devices 10 and 20. It can also be said that one end of the bus bars 71 to 73 is connected to the structure, and the other end is connected to the capacitor device 60.

[0045] As shown in Figures 2 and 3, the capacitor device 60 includes the capacitors 30, 40, a capacitor case 61, and a sealing resin part 63. The capacitor case 61 houses the capacitors 30, 40 and is a case with an opening 62 provided in a portion thereof. The capacitor case 61 is provided with the sealing resin part 63 while housing the capacitors 30, 40. In other words, the capacitor case 61 has the capacitors 30, 40 and the sealing resin part 63 provided in the housing space. The capacitors 30, 40 are sealed with the sealing resin part 63.

[0046] Furthermore, a portion of the P bus bar 71, the N bus bar 72, and the M bus bar 73 are arranged inside the capacitor case 61 to connect to the capacitors 30 and 40. The portions of the P bus bar 71, the N bus bar 72, and the M bus bar 73 arranged inside the capacitor case 61 are sealed with a sealing resin portion 63. Furthermore, as shown in FIG. 3 , the P bus bar 71, the N bus bar 72, and the M bus bar 73 protrude from the opening 62.

[0047] In this way, the capacitor device 60 has two capacitors 30 and 40 held together. The capacitor device 60 can also be called a capacitor structure. The capacitors 30 and 40 may each be composed of a single capacitor element, or may each be composed of multiple capacitor elements. The capacitor element here is a film capacitor.

[0048] As shown in Fig. 2, the PM capacitor 30 includes a first PM terminal 31 and a second PM terminal 32. The first PM terminal 31 is connected to a P bus bar 71. The second PM terminal 32 is connected to an M bus bar 73. The PM capacitor 30 corresponds to a first capacitor. The first PM terminal 31 corresponds to a high-potential electrode. The second PM terminal 32 corresponds to a first midpoint electrode.

[0049] The MN capacitor 40 has a first MN terminal 41 and a second MN terminal 42. The first MN terminal 41 is connected to the M bus bar 73. The second MN terminal 42 is connected to the N bus bar 72. The MN capacitor 40 corresponds to the second capacitor. The first MN terminal 41 corresponds to the second midpoint electrode. The second MN terminal 42 corresponds to the low potential side electrode.

[0050] 2 and 5, the PM capacitor 30 and the MN capacitor 40 are stacked in a direction intersecting the alignment direction AD. In the present embodiment, as an example, the PM capacitor 30 and the MN capacitor 40 are stacked in a direction perpendicular to the alignment direction AD.

[0051] More specifically, the PM capacitor 30 and the MN capacitor 40 are stacked so that the second PM terminal 32 of the PM capacitor 30 faces the first MN terminal 41 of the MN capacitor 40. In other words, the second PM terminal 32 and the first MN terminal 41 are arranged opposite each other.

[0052] A capacitor-side connection portion 73c, which is a part of the M bus bar 73, is arranged between the PM capacitor 30 and the MN capacitor 40. The capacitor-side connection portion 73c is sandwiched between the PM capacitor 30 and the MN capacitor 40. The capacitor-side connection portion 73c is connected to the second PM terminal 32 and the first MN terminal 41. In other words, the second PM terminal 32 and the first MN terminal 41 are connected to the same M bus bar 73. The capacitor-side connection portion 73c corresponds to a connection portion.

[0053] 2, the M bus bar 73 has a capacitor-side connection portion 73c that runs parallel to the PM capacitor 30 and the MN capacitor 40. In other words, the capacitor-side connection portion 73c is disposed opposite the PM capacitor 30 and the MN capacitor 40. The capacitor-side connection portion 73c is also connected to the PM capacitor 30 and the MN capacitor 40. Therefore, it can be said that the capacitor-side connection portion 73c and the PM capacitor 30, and the capacitor-side connection portion 73c and the MN capacitor 40 are disposed in positions that allow magnetic fields to be canceled out. This allows the inverter circuit 100 to reduce the inductance between the second PM terminal 32 and the first MN terminal 41.

[0054] For this reason, the inverter circuit 100 can be made smaller in size along the arrangement direction AD than a configuration in which the PM capacitor 30 and the MN capacitor 40 are arranged along the arrangement direction AD. It can also be said that the inverter circuit 100 can be made smaller in size in a direction perpendicular to the stacking direction of the PM capacitor 30 and the MN capacitor 40. It can also be said that the PM capacitor 30 and the MN capacitor 40 are stacked in the thickness direction of both capacitors 30, 40. It can also be said that the PM capacitor 30 and the MN capacitor 40 are simply stacked.

[0055] The thickness direction is a direction perpendicular to the connection surfaces of terminals 31, 32 with bus bars 71, 73. The thickness direction is also a direction perpendicular to the connection surfaces of terminals 41, 42 with bus bars 72, 73.

[0056] <Positional relationship of bus bars 71 to 73> 2, 3, and 5, the base portion 73a of the M bus bar 73 is disposed between the semiconductor device 20 and the capacitors 30, 40. A portion of the base portion 73a is disposed between the P bus bar 71 and the N bus bar 72, and faces the P bus bar 71 and the N bus bar 72. The base portion 73a also includes a portion facing the base portion 71a of the P bus bar 71 and the base portion 72a of the N bus bar 72. A portion of the base portion 73a is disposed opposite the base portion 71a and the base portion 72a outside the sealing resin portion 63. Furthermore, a portion of the base portion 73a is also disposed opposite the base portion 71a and the base portion 72a inside the sealing resin portion 63.

[0057] It can also be said that a portion of the base portion 73a runs parallel to a portion of the P bus bar 71 and a portion of the N bus bar 72. It can also be said that the base portion 73a is stacked with the base portions 71a and 72a with the insulating member 80 interposed therebetween. The base portion 73a is stacked (facing) at a short distance from the base portions 71a and 72a. A short distance means a distance at which magnetic fields can be canceled out. A portion of the base portion 73a can be considered to correspond to the facing portion. Furthermore, the portion of the base portion 73a that corresponds to the facing portion can be considered to be a portion that faces the base portions 71a and 72a within a short distance.

[0058] <Effects> As shown by the two-dot chain line in FIG. 2 , the inverter circuit 100 has an M bus bar 73 disposed between the P bus bar 71 and the N bus bar 72, and has a base portion 73a facing the P bus bar 71 and the N bus bar 72. Therefore, the inverter circuit 100 can cancel out magnetic fields between the P bus bar 71 and the base portion 73a of the M bus bar 73, and between the base portion 73a and the N bus bar 72. Therefore, the inverter circuit 100 can reduce inductance. That is, the inverter circuit 100 can reduce inductance between the P bus bar 71 and the M bus bar 73, and between the M bus bar 73 and the N bus bar 72. Furthermore, because the inverter circuit 100 can reduce inductance, it can suppress surge voltages. Therefore, the inverter circuit 100 can reduce losses.

[0059] Note that, similarly to the other embodiments, a portion of the base portion 73a is disposed between the P bus bar 71 and the N bus bar 72 and faces the P bus bar 71 and the N bus bar 72. Therefore, in the other embodiments, similar to the present embodiment, the inductance can be reduced.

[0060] The preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the present disclosure. Below, the second to twelfth embodiments will be described as other aspects of the present disclosure. The above embodiments and the second to twelfth embodiments can be implemented independently, or can be implemented in appropriate combinations. The present disclosure is not limited to the combinations shown in the embodiments, and can be implemented in various combinations.

[0061] The following embodiments will mainly be described with respect to differences from the previously described embodiments. The second to sixth embodiments differ from the first embodiment mainly in the positional relationship between the PM capacitor 30 and the MN capacitor 40 and the configuration of the bus bars 71 to 73. The seventh embodiment differs from the first embodiment mainly in that it includes a PN capacitor 50.

[0062] (Second embodiment) An inverter circuit 100 according to the second embodiment will be described with reference to Fig. 6. Note that Fig. 6 only partially illustrates bus bars 71 to 73. This also applies to the third to sixth embodiments described later.

[0063] The PM capacitor 30 and the MN capacitor 40 are stacked in a direction perpendicular to the arrangement direction AD. The PM capacitor 30 and the MN capacitor 40 are also arranged so that their side walls face each other. The side walls of the PM capacitor 30 are wall surfaces that connect to the first PM terminal 31 and the second PM terminal 32. The MN capacitor 40 is a wall surface that connects to the first MN terminal 41 and the second MN terminal 42.

[0064] The second PM terminal 32 and the first MN terminal 41 are arranged along an imaginary plane perpendicular to the arrangement direction AD. Similarly, the first PM terminal 31 and the second MN terminal 42 are arranged along another imaginary plane perpendicular to the arrangement direction AD. The second PM terminal 32 and the first MN terminal 41 are arranged closer to the bottom of the capacitor case 61 than the first PM terminal 31 and the second MN terminal 42. The bottom of the capacitor case 61 is the portion facing the opening 62.

[0065] The P bus bar 71 is bent from one end of the base portion 71a to provide a capacitor-side connection portion 71c. The capacitor-side connection portion 71c is connected to the first PM terminal 31. The capacitor-side connection portion 71c and the first PM terminal 31 are connected by welding or the like.

[0066] The N bus bar 72 is bent from one end of the base portion 72a to provide a capacitor-side connection portion 72c. The capacitor-side connection portion 72c is connected to the second MN terminal 42. The capacitor-side connection portion 72c and the second MN terminal 42 are connected by welding or the like.

[0067] A portion of the base portion 73a of the M bus bar 73 is arranged along the arrangement direction AD. The M bus bar 73 has a capacitor-side connection portion 73c at the tip of the base portion 73a. The M bus bar 73 has a capacitor-side connection portion 73c connected to the second PM terminal 32 and a capacitor-side connection portion 73c connected to the first MN terminal 41. In other words, the M bus bar 73 has two capacitor-side connection portions 73c. ​​The two capacitor-side connection portions 73c are arranged perpendicular to the arrangement direction AD. The capacitor-side connection portion 73c is connected to the second PM terminal 32 and the first MN terminal 41 by welding.

[0068] The base portion 73a is provided to protrude from between the two capacitor-side connecting portions 73c. ​​The base portion 73a has a portion sandwiched between the PM capacitor 30 and the MN capacitor 40. In other words, a portion of the base portion 73a is disposed between the side wall of the PM capacitor 30 and the side wall of the MN capacitor 40. Note that the base portion 73a does not contact these side walls.

[0069] In the inverter circuit 100, the terminals 31, 32 of the PM capacitor 30 and the terminals 41, 42 of the MN capacitor 40 are not arranged opposite to each other. Therefore, in the inverter circuit 100, it is easy to connect the terminals 31, 32, 41, 42 to the capacitor-side connecting portions 71c to 73c.

[0070] (Third embodiment) An inverter circuit 100 of the third embodiment will be described with reference to FIG. 7. The PM capacitor 30 and the MN capacitor 40 are arranged side by side along the arrangement direction AD. The PM capacitor 30 and the MN capacitor 40 are arranged so that their side walls face each other. The second PM terminal 32 and the second MN terminal 42 are arranged along the arrangement direction AD. Similarly, the first PM terminal 31 and the first MN terminal 41 are arranged along the arrangement direction AD. In other words, the second PM terminal 32 and the second MN terminal 42 are arranged on the same imaginary plane along the arrangement direction AD. The first PM terminal 31 and the first MN terminal 41 are arranged on the same imaginary plane along the arrangement direction AD. The two imaginary planes are at different positions in the direction perpendicular to the arrangement direction AD. The MN capacitor 40 is arranged closer to the bottom of the capacitor case 61 than the PM capacitor 30.

[0071] The M bus bar 73 has a capacitor-side connection portion 73c connected to the second PM terminal 32 and a capacitor-side connection portion 73c connected to the first MN terminal 41. In other words, the M bus bar 73 has two capacitor-side connection portions 73c. ​​The M bus bar 73 has one capacitor-side connection portion 73c, and the other capacitor-side connection portion 73c is provided via a bent portion. The M bus bar 73 has a portion (connecting portion) that connects the two capacitor-side connection portions 73c. ​​The connecting portion is located between the PM capacitor 30 and the MN capacitor 40. The two capacitor-side connection portions 73c are different portions of a single metal plate. Therefore, the connecting portion can also be considered an intermediate portion between the two capacitor-side connection portions 73c.

[0072] 7, the inverter circuit 100 can arrange the base portion 72a and the capacitor-side connecting portion 73c opposite each other on the PM capacitor 30. Therefore, the inverter circuit 100 can further reduce the inductance between the N bus bar 72 and the M bus bar 73.

[0073] Furthermore, the inverter circuit 100 has the PM capacitors 30 and the MN capacitors 40 arranged along the arrangement direction AD, which allows the inverter circuit 100 to have a low profile in the direction perpendicular to the arrangement direction AD.

[0074] (Fourth embodiment) An inverter circuit 100 of the fourth embodiment will be described with reference to Fig. 8. The PM capacitor 30 and the MN capacitor 40 are stacked in a direction perpendicular to the arrangement direction AD. The PM capacitor 30 and the MN capacitor 40 are stacked so that the first PM terminal 31 and the first MN terminal 41 face each other.

[0075] The M bus bar 73 has a capacitor-side connection portion 73c connected to the second PM terminal 32 and a capacitor-side connection portion 73c connected to the first MN terminal 41. The M bus bar 73 has a portion (coupling portion) that connects the two capacitor-side connection portions 73c. ​​The capacitor-side connection portion 73c connected to the first MN terminal 41 is located in an area where the PM capacitor 30 and the MN capacitor 40 face each other. The coupling portion and the base portion 72a are located between the capacitors 30, 40 and the bottom of the capacitor case 61.

[0076] 8, the inverter circuit 100 can arrange the capacitor-side connection portion 71c and the capacitor-side connection portion 73c opposite each other between the capacitors 30 and 40. Therefore, the inverter circuit 100 can further reduce the inductance between the P bus bar 71 and the M bus bar 73.

[0077] Furthermore, the inverter circuit 100 can arrange the base portion 72a of the N bus bar 72 and the connecting portion of the M bus bar 73 to face each other between the capacitors 30, 40 and the bottom of the capacitor case 61. Therefore, the inverter circuit 100 can further reduce the inductance between the N bus bar 72 and the M bus bar 73. Note that the inverter circuit 100 can achieve the same effect even if the PM capacitor 30 and the MN capacitor 40 are stacked and arranged so that the second PM terminal 32 and the second MN terminal 42 face each other.

[0078] (Fifth embodiment) An inverter circuit 100 according to the sixth embodiment will be described with reference to Figures 9 to 11. In Figure 9, the capacitor case 61 and the sealing resin part 63 are not shown in order to simplify the drawing.

[0079] As shown in Figure 9, the PM capacitor 30 and the MN capacitor 40 are arranged side by side in a direction perpendicular to the arrangement direction AD. The PM capacitor 30 and the MN capacitor 40 are arranged so that their side walls face each other. The second PM terminal 32 and the second MN terminal 42 are arranged along the perpendicular direction. Similarly, the first PM terminal 31 and the first MN terminal 41 are arranged along the perpendicular direction. The PM capacitor 30 and the MN capacitor 40 are arranged at the same position in the depth direction of the capacitor case 61.

[0080] 10 and 11, the M bus bar 73 has a capacitor-side connection portion 73c connected to the second PM terminal 32 and a capacitor-side connection portion 73c connected to the first MN terminal 41. The M bus bar 73 has a portion (connecting portion) that connects the two capacitor-side connection portions 73c. ​​The connecting portion is arranged along the arrangement direction of the PM capacitor 30 and the MN capacitor 40. The inverter circuit 100 can be made smaller than that of the first embodiment.

[0081] (Sixth embodiment) An inverter circuit 100 according to a sixth embodiment will be described with reference to FIG. 12. In this embodiment, a four-level inverter circuit 100 is employed. The inverter circuit 100 includes an MM capacitor 40a in addition to a PM capacitor 30 and an MN capacitor 40. The MM capacitor 40a is connected in series with the PM capacitor 30 and the MN capacitor 40. The MM capacitor 40a includes a first MM terminal 41a and a second MM terminal 42a. The first MM terminal 41a is disposed opposite the second PM terminal 32. The second MM terminal 42a is disposed opposite the first MN terminal 41.

[0082] The inverter circuit 100 includes two M bus bars 73. One M bus bar 73 has a capacitor-side connection portion 73c connected to the second PM terminal 32 and the first MM terminal 41a. The other M bus bar 73 has a capacitor-side connection portion 73c connected to the first MN terminal 41 and the second MM terminal 42a.

[0083] The base portions 73a of the two M bus bars 73 are arranged between the semiconductor device 20 and the capacitors 30, 40. A portion of the base portion 73a is arranged between the P bus bar 71 and the N bus bar 72, and faces the P bus bar 71 and the N bus bar 72. Therefore, it can be said that the two M bus bars 73 each have an opposing portion. The inverter circuit 100 can also be applied to a multilevel inverter with four or more levels.

[0084] Seventh embodiment The structure of an inverter circuit 100a according to the seventh embodiment will be described with reference to Figures 13 to 15. The inverter circuit 100a differs from the inverter circuit 100 in that it includes a PN capacitor 50. Note that bus bars 71 to 73, insulating member 80, etc. are not shown in Figure 15. The same applies to Figure 16, which will be described later.

[0085] As shown in FIGS. 13 and 14, the inverter circuit 100a has a PN capacitor 50 connected between the P bus bar 71 and the N bus bar 72. The PN capacitor 50 is connected to the high-potential terminal and the low-potential terminal. Therefore, the PN capacitor 50 is connected in parallel to the PM capacitor 30 and the MN capacitor 40. The PN capacitor 50 is provided to absorb current ripple. In other words, the PN capacitor 50 is provided to reduce current ripple flowing out of the inverter circuit 100a. The PN capacitor 50 corresponds to a third capacitor.

[0086] In the inverter circuit 100a, a small capacitor capacity is required to suppress the allowable voltage fluctuation at the midpoint M, while a large capacitor capacity is required to reduce the current ripple that flows out to the outside. Therefore, the inverter circuit 100a is provided with a PN capacitor 50. This PN capacitor 50 is connected in parallel with the PM capacitor 30 and the MN capacitor 40 as described above. This allows the inverter circuit 100a to reduce the total capacitance of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50. Therefore, the inverter circuit 100a allows the physical sizes of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 to be reduced.

[0087] As shown in Fig. 14, the capacitor device 60 includes a PN capacitor 50 in addition to a PM capacitor 30, an MN capacitor 40, a capacitor case 61, and a sealing resin part 63. The PN capacitor 50 is housed in the capacitor case 61 together with the PM capacitor 30 and the MN capacitor 40. The PN capacitor 50 is sealed with the sealing resin part 63. Furthermore, as shown in Figs. 14 and 15, the PN capacitor 50 is arranged in the arrangement direction AD with respect to the PM capacitor 30 and the MN capacitor 40.

[0088] The PN capacitor 50 includes a first PN terminal 51 and a second PN terminal 52. The first PN terminal 51 is connected to a P bus bar 71. The second PN terminal 52 is connected to an N bus bar 72.

[0089] The PM condenser 30 and the MN condenser 40 are disposed closer to the cooler 90 than the PN condenser 50. In the present embodiment, as an example, they are arranged in the following order along the arrangement direction AD: the cooler 90, the PM condenser 30, the MN condenser 40, and the PN condenser 50. For this reason, the PM condenser 30 and the MN condenser 40 are more easily cooled by the cooler 90 than the PN condenser 50. It can be said that in the inverter circuit 100a, the PM condenser 30 and the MN condenser 40 have stronger cooling power than the PN condenser 50.

[0090] Furthermore, the length of the P bus bar 71 from the connection point with the structure to the connection point with the PM condenser 30 is shorter than the length from the connection point with the structure to the connection point with the PN condenser 50. Therefore, the PM condenser 30 is more easily cooled by the P bus bar 71 cooled by the cooler 90 than the PN condenser 50.

[0091] On the other hand, the length of the N bus bar 72 from the connection point with the structure to the connection point with the MN capacitor 40 is shorter than the length from the connection point with the structure to the connection point with the PN capacitor 50. Therefore, the MN capacitor 40 is more easily cooled by the N bus bar 72 cooled by the cooler 90 than the PN condenser 50.

[0092] Incidentally, the ripple current caused by heat generation is larger in the PM capacitor 30 and the MN capacitor 40 than in the PN capacitor 50. Therefore, in the present disclosure, the PM capacitor 30 and the MN capacitor 40 are arranged closer to the cooler 90 than the PN capacitor 50. As a result, the inverter circuit 100a can suppress heat generation in the PM capacitor 30 and the MN capacitor 40. Therefore, the inverter circuit 100a can increase the allowable current of the PM capacitor 30 and the MN capacitor 40. In other words, the inverter circuit 100a can increase the allowable current compared to a configuration in which the PN capacitor 50 is closer to the cooler 90 than the PM capacitor 30 and the MN capacitor 40. Note that the positional relationship between the cooler 90 and each of the capacitors 30 to 50 described above can also be applied to other embodiments.

[0093] The P bus bar 71 and the N bus bar 72 may have a higher thermal conductivity at the portions connected to the PM capacitor 30 and the MN capacitor 40 than at the portions connected to the PN capacitor 50. For example, the portions connected to the PN capacitor 50 may be made primarily of copper. On the other hand, the portions connected to the PM capacitor 30 and the MN capacitor 40 may be made primarily of silver. This also allows the inverter circuit 100a to increase the allowable current of the PM capacitor 30 and the MN capacitor 40.

[0094] In the following embodiment, differences from the seventh embodiment will be mainly described.

[0095] (Eighth embodiment) An inverter circuit 100a of the eighth embodiment will be described with reference to Fig. 16. This embodiment differs from the seventh embodiment in the positional relationship between the PM capacitor 30 and the MN capacitor 40.

[0096] The PM capacitor 30 and the MN capacitor 40 are arranged in parallel. The first PM terminal 31 and the first MN terminal 41 of the PM capacitor 30 and the MN capacitor 40 are arranged on the same imaginary plane. The second PM terminal 32 and the second MN terminal 42 of the PM capacitor 30 and the MN capacitor 40 are arranged on another imaginary plane.

[0097] Therefore, the inverter circuit 100a can be made smaller in size in the direction perpendicular to the capacitor arrangement direction of the PM capacitor 30 and the MN capacitor 40 than a configuration in which both capacitors 30, 40 are stacked. Also, like the first embodiment, the inverter circuit 100a can make each of the capacitors 30 to 50 smaller in size. Note that the PN capacitor 50 is arranged in parallel with both the PM capacitor 30 and the MN capacitor 40. The first PN terminal 51 is arranged on the same imaginary plane as the first PM terminal 31 and the first MN terminal 41. The second PN terminal 52 is arranged on the same imaginary plane as the second PM terminal 32 and the second MN terminal 42.

[0098] (Ninth embodiment) An inverter circuit 100a of the ninth embodiment will be described using Figure 17. This embodiment differs from the first embodiment in the positional relationship between the PM capacitor 30 and the MN capacitor 40. The PM capacitor 30 and the MN capacitor 40 are arranged with a shift in the arrangement direction AD. As with the seventh embodiment, the inverter circuit 100a allows the physical size of each of the capacitors 30 to 50 to be reduced.

[0099] (Tenth embodiment) An inverter circuit 100a of the tenth embodiment will be described with reference to Fig. 18. In this embodiment, differences from the eighth embodiment will be mainly described. This embodiment differs from the eighth embodiment in the positional relationship of the PN capacitor 50 with respect to the PM capacitor 30 and the MN capacitor 40.

[0100] The PN capacitor 50 is arranged in parallel with the PM capacitor 30 and the MN capacitor 40. In other words, the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 are arranged in a straight line.

[0101] Therefore, the inverter circuit 100a can be made smaller in size in the direction perpendicular to the capacitor arrangement direction of the capacitors 30 to 50 than a configuration in which the capacitors 30 to 50 are arranged in a stacked manner. Also, in the inverter circuit 100a, the size of each of the capacitors 30 to 50 can be made smaller, similar to the seventh embodiment.

[0102] (Eleventh embodiment) An inverter circuit 100a of the eleventh embodiment will be described with reference to Fig. 19. This embodiment differs from the seventh embodiment in the positional relationship of the PN capacitor 50 with respect to the PM capacitor 30 and the MN capacitor 40.

[0103] The PN capacitor 50 is arranged in a stack together with the PM capacitor 30 and the MN capacitor 40. The capacitors 30 to 50 are arranged so that their terminals do not face each other. The first PN terminal 51 is arranged parallel to the same imaginary plane as the first PM terminal 31 and the first MN terminal 41. The second PN terminal 52 is arranged parallel to the same imaginary plane as the second PM terminal 32 and the second MN terminal 42. The inverter circuit 100a can be made smaller in size in a direction perpendicular to the capacitor arrangement direction of the capacitors 30 to 50 than a configuration in which the capacitors 30 to 50 are arranged in parallel. Furthermore, as with the seventh embodiment, the inverter circuit 100a can make the size of each of the capacitors 30 to 50 smaller.

[0104] (Twelfth embodiment) An inverter circuit 100a of the twelfth embodiment will be described with reference to Fig. 20. This embodiment differs from the seventh embodiment in the configurations of the P bus bar 71 and the N bus bar 72.

[0105] The P bus bar 71 includes a PM bus bar portion 71m connected to the PM capacitor 30 and a PN bus bar portion 71p connected to the PN capacitor 50. The N bus bar 72 includes an MN bus bar portion 72m connected to the MN capacitor 40 and a PN bus bar portion 72p connected to the PN capacitor 50. The PM bus bar portion 71m has a larger cross-sectional area than the PN bus bar portion 71p. The MN bus bar portion 72m has a larger cross-sectional area than the PN bus bar portion 72p.

[0106] This also enables the inverter circuit 100a to increase the allowable current of the PM capacitor 30 and the MN capacitor 40. Furthermore, the inverter circuit 100a allows the size of each of the capacitors 30 to 50 to be reduced in size, similar to the seventh embodiment.

[0107] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, although various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more, or less than one element are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0108] 100... inverter circuit, 1... P terminal, 2... N terminal, 3... O terminal, 4... M terminal, 5... signal terminal, 10, 20... semiconductor device, 11 to 16... switching elements, 11... U-phase upper arm element, 12... U-phase lower arm element, 13... V-phase upper arm element, 14... V-phase lower arm element, 15... W-phase upper arm element, 16... W-phase lower arm element, 21... U-phase middle section, 22... V-phase middle section, 23... W-phase middle section, 21a... first U-phase middle element, 21b... second U-phase middle element, 22a... first V-phase middle element, 22b... second V-phase middle element, 23a... first W-phase middle element, 23b... second W-phase middle element, 30... PM capacitor, 31...first PM terminal, 32...second PM terminal, 40...MN capacitor, 41...first MN terminal, 42...second MN terminal, 50...PN capacitor, 51...first PN terminal, 52...second PN terminal, 60...capacitor device, 61...capacitor case, 62...opening, 63...sealing resin portion, 71...P bus bar, 71m...PM bus bar portion, 71p...PN bus bar portion, 72...N bus bar, 72m...MN bus bar portion, 72p...PN bus bar portion, 73...M bus bar, 74...O bus bar, 80...insulating member, 90...cooler, 110...wiring board, 200...battery, 300...motor, 301...U-phase coil, 302...V-phase coil, 303...W-phase coil

Claims

1. A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, A high potential wiring (71) connected to the positive electrode of the power supply; A low potential wiring (72) connected to the negative electrode of the power supply; At least one midpoint wiring (73) that has a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to the high potential wiring, the low potential wiring, and the output wiring; a first capacitor (30) having a high potential side electrode connected to the high potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring, at least one of the midpoint wirings is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring; The first capacitor and the second capacitor are arranged such that the first midpoint electrode and the second midpoint electrode face each other, The power conversion device, wherein the midpoint wiring is sandwiched between the first capacitor and the second capacitor and has a connection portion (73c) connected to the first midpoint electrode and the second midpoint electrode.

2. A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, A high potential wiring (71) connected to the positive electrode of the power supply; A low potential wiring (72) connected to the negative electrode of the power supply; At least one midpoint wiring (73) that has a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to the high potential wiring, the low potential wiring, and the output wiring; a first capacitor (30) having a high-potential electrode connected to the high-potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring, at least one of the midpoint wirings is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring; the midpoint wiring has a connection portion (73c) connected to the first midpoint electrode and the second midpoint electrode, and a portion protruding from the connection portion and sandwiched between the first capacitor and the second capacitor.

3. A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, A high potential wiring (71) connected to the positive electrode of the power supply; A low potential wiring (72) connected to the negative electrode of the power supply; At least one midpoint wiring (73) that has a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to the high potential wiring, the low potential wiring, and the output wiring; a first capacitor (30) having a high-potential electrode connected to the high-potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring, at least one of the midpoint wirings is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring; the first capacitor and the second capacitor are arranged such that a side surface connected to the first midpoint electrode and the high potential side electrode faces a side surface connected to the second midpoint electrode and the low potential side electrode, the midpoint wiring has two connection portions (73c) connected to the first midpoint electrode and the second midpoint electrode, and a portion connecting the two connection portions is disposed between the first capacitor and the second capacitor.

4. A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, A high potential wiring (71) connected to the positive electrode of the power supply; A low potential wiring (72) connected to the negative electrode of the power supply; At least one midpoint wiring (73) that has a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to the high potential wiring, the low potential wiring, and the output wiring; a first capacitor (30) having a high-potential electrode connected to the high-potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring, at least one of the midpoint wirings is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring; the first capacitor and the second capacitor are arranged such that the first midpoint electrode and the low potential side electrode or the second midpoint electrode and the high potential side electrode face each other, the midpoint wiring has two connection portions (73c) connected to the first midpoint electrode and the second midpoint electrode, One of the connection portions is disposed in an area where the first capacitor and the second capacitor face each other.

5. A power conversion device capable of dividing an input DC voltage into a plurality of values ​​and outputting a plurality of voltage levels via an output wiring, A high potential wiring (71) connected to the positive electrode of the power supply; A low potential wiring (72) connected to the negative electrode of the power supply; At least one midpoint wiring (73) that has a potential between the high potential wiring and the low potential wiring; a first power module (10) connected to the high potential wiring, the low potential wiring, and the output wiring; a first capacitor (30) having a high-potential electrode connected to the high-potential wiring and a first midpoint electrode connected to the midpoint wiring; a second capacitor (40) having a low potential side electrode connected to the low potential wiring and a second midpoint electrode connected to the midpoint wiring; a second power module (20) connected to the midpoint wiring and the output wiring, at least one of the midpoint wirings is a part between the second power module and the first capacitor and the second capacitor, is disposed between the high potential wiring and the low potential wiring, and has an opposing part (73a) opposing the high potential wiring and the low potential wiring; the first capacitor and the second capacitor are arranged such that a side surface connected to the first midpoint electrode and the high potential side electrode faces a side surface connected to the second midpoint electrode and the low potential side electrode, the midpoint wiring has two connection portions (73c) connected to the first midpoint electrode and the second midpoint electrode, and a portion connecting the two connection portions is arranged along an arrangement direction of the first capacitor and the second capacitor.

6. The power conversion device according to any one of claims 1 to 5, wherein the two or more midpoint wirings each have the opposing portion (73a).

7. The power conversion device according to any one of claims 1 to 5, further comprising at least one third capacitor (50) connected to the high-potential wiring and the low-potential wiring.

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