gaming machines

Abstract

To provide a game machine capable of making a configuration concerning a setting value suitable.SOLUTION: When power of a Pachinko machine is turned on in a state in which a setting key insertion part 68a is turned on and a reset button 68c is pressed, a main-side CPU 63 executes setting value update processing. In the setting value update processing, processing for selecting a setting value for determining a degree of advantage of the Pachinko machine from among a plurality of stages on the basis of operation of a manager in a game hall. When the setting value update processing is executed, a predetermined area differing from an area for storing information of a setting value in a main-side Ram 65 is initialized. When the setting value update processing is executed, notification is performed after clearing in a display light emission part 53 and a speaker part 54. A degree of execution priority of notification is set higher for the notification after clearing concerned than body closing notification executed when a game machine body is closed.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Known gaming machines include pachinko machines and slot machines. For example, a pachinko machine has a tray storage section on the front of the machine that stores gaming balls given to a player. The gaming balls stored in the tray storage section are guided to a gaming ball launcher and launched toward a gaming area in response to a player's launch operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, the gaming ball is paid out to the tray storage section from, for example, a payout device. Also known in pachinko machines is a configuration in which the tray storage section includes an upper tray storage section and a lower tray storage section. In this case, gaming balls stored in the upper tray storage section are guided to the gaming ball launcher, and surplus gaming balls in the upper tray storage section are discharged to the lower tray storage section (see, for example, Patent Document 1).

[0003] In addition, in a slot machine, when a start lever is operated to start a new game while medals have been bet, a lottery process is executed by the control means. When the lottery process is executed, the control means executes a rotation start control to start the reels, and when a stop button is operated during the rotation of the reels, the control means executes a rotation stop control to stop the rotation of the reels. If the result of the reels stopping after the rotation stops corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-23329 Summary of the Invention [Problem to be solved by the invention]

[0005] Here, in gaming machines such as those exemplified above, it is necessary to appropriately manage the gaming machines, and there is still room for improvement in this regard.

[0006] The present invention has been made in consideration of the circumstances exemplified above, and has as its object to provide a gaming machine that allows for suitable management of the gaming machine. [Means for solving the problem]

[0007] In order to solve the above problem, the invention described in claim 1 comprises a history storage execution means for storing game history information corresponding to a predetermined event that occurs when a game is executed, in a history storage means; information deriving means for deriving behavior information corresponding to a game result by utilizing the history information stored in the history storage means; a behavior information storage means for storing the behavior information derived by the information derivation means; a mode information display control means for controlling the display of the mode information stored in the mode information storage means on the information display means; occurs before a new display corresponding to the aspect information is started. Before a new display corresponding to the mode information is started based on the occurrence of a predetermined display trigger. , corresponding to the occurrence of the predetermined display opportunity a predetermined correspondence display control means for controlling the information display means to display a predetermined correspondence display; a setting means for setting a set value corresponding to the advantage of a player; a situation generating means for generating a setting possible situation in which the setting means can set the setting value; Equipped with the aspect information storage means includes a plurality of specific storage areas so as to be able to store each of the plurality of aspect information, the aspect information display control means controls the information display means to sequentially execute displays corresponding to the plurality of aspect information stored in the plurality of specific storage areas in accordance with a predetermined display order, and when the information display means is caused to execute displays corresponding to the aspect information after the predetermined corresponding displays have been executed by the information display means, the information display means starts with a display corresponding to the aspect information corresponding to the first order in the predetermined display order, The gaming machine is equipped with a control means for executing various processes, The control means an intra-area processing execution means for executing intra-area processing, which is processing using a program stored in a storage area within a predetermined address range in the program storage means; an out-of-area processing execution means for executing out-of-area processing, which is processing using a program stored in a storage area in an address range outside the predetermined address range in the program storage means; Equipped with the intra-area processing execution means includes means for executing, as the intra-area processing, a process that can identify whether the setting value set as an object to be used is normal or not; This gaming machine is an intra-area corresponding storage area into which information can be written and read when the intra-area process is executed, and into which information can be read but not written when the extra-area process is executed; an outside-area corresponding storage area into which information can be written and read when the outside-area processing is executed, and into which information can be read but not written when the inside-area processing is executed; Equipped with the in-area process execution means is configured to be able to clear predetermined information in the in-area corresponding storage area when the setting possible state is reached, the intra-area corresponding storage area has a work area for intra-area processing and a stack area for intra-area processing, The area for storing information about the setting values ​​set by the setting means is provided in a work area for processing within the area. [Effects of the Invention]

[0008] According to the present invention, it is possible to appropriately manage gaming machines. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a pachinko machine according to a first embodiment. [Figure 2] FIG. 1 is an exploded perspective view showing the main components of a pachinko machine. [Figure 3] FIG. 2 is a front view showing the configuration of the game board. [Figure 4] FIG. 10 is an explanatory diagram for explaining the configuration for discharging game balls that have flowed down the game area. [Figure 5] FIG. 2 is a front view of the main control device. [Figure 6] FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. [Figure 7] This is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. [Figure 8] FIG. 2 is an explanatory diagram for explaining various tables stored in the main ROM. [Figure 9] 10 is a flowchart showing a main process executed by a main CPU. [Figure 10] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 11] 10 is a flowchart showing a timer interrupt process executed by the main CPU. [Figure 12] 10 is a flowchart showing a special chart special power control process executed by the main CPU. [Figure 13] This is a flowchart showing the special chart change start processing executed by the main CPU. [Figure 14]This is an explanatory diagram to explain the configuration in which the detection results of the ball entry detection sensor are input to the main CPU. [Figure 15] This is a flowchart showing the ball entry detection process executed by the main CPU. [Figure 16] A block diagram for explaining the electrical configuration of a dispensing control device and various devices that communicate with the dispensing control device. [Figure 17] 10 is a flowchart showing the timer interrupt processing executed by the dispensing CPU. [Figure 18] FIG. 2 is a block diagram for explaining the electrical configuration of a management IC. [Figure 19] FIG. 10 is an explanatory diagram illustrating the configuration of an input port of a management side I / F. [Figure 20] FIG. 2 is an explanatory diagram for explaining the configuration of a correspondence relationship memory; [Figure 21] FIG. 2 is an explanatory diagram illustrating the configuration of a history memory. [Figure 22] 10 is a flowchart showing a recognition process executed by a main CPU. [Figure 23] 10 is a flowchart showing a management process executed by a management-side CPU. [Figure 24] 10(a) to 10(d) are time charts showing how information on the correspondence between the first to fifteenth buffers and the types of signals is stored in the correspondence memory. [Figure 25] 10 is a flowchart showing a management output process executed by the main CPU. [Figure 26] 10 is a flowchart showing a history setting process executed by a management-side CPU. [Figure 27] 10(a) to 10(e) are time charts showing how history information is stored in a history memory. [Figure 28] 10 is a flowchart showing a process of outputting a set value update signal executed by a main CPU. [Figure 29] 10 is a flowchart showing a setting update recognition process executed by a management CPU. [Figure 30]10 is a flowchart showing a display output process executed by a management CPU. [Figure 31] 10 is a flowchart showing a display process executed by a management CPU. [Figure 32] 10A is a flowchart showing a data output process executed by the main CPU, and FIG. 10B is a flowchart showing an external output process executed by the control CPU. [Figure 33] FIG. 10 is an explanatory diagram for explaining various tables stored in a main ROM in the second embodiment. [Figure 34] FIG. 11 is an explanatory diagram for explaining the configuration of a separate storage memory in the third embodiment. [Figure 35] 10 is a flowchart showing a setting update recognition process executed by a management CPU. [Figure 36] 10 is a flowchart showing a process of monitoring a repeated change executed by a management CPU. [Figure 37] 13 is a flowchart showing a process of monitoring a repeated change executed by a main CPU in the fourth embodiment. [Figure 38] 13 is a flowchart showing a setting update recognition process executed by a management-side CPU in the fifth embodiment. [Figure 39] FIG. 20 is an explanatory diagram illustrating the configuration of a history memory in the sixth embodiment. [Figure 40] 10 is a flowchart showing a history setting process executed by a management-side CPU. [Figure 41] 10 is a flowchart showing a setting update recognition process executed by a management CPU. [Figure 42] FIG. 20 is an explanatory diagram illustrating the configuration of a history memory in the seventh embodiment. [Figure 43] 10 is a flowchart showing a setting update recognition process executed by a management CPU. [Figure 44] FIG. 20 is an explanatory diagram for explaining the configuration of a history memory in the eighth embodiment. [Figure 45]10 is a flowchart showing a setting update recognition process executed by a management CPU. [Figure 46] 10 is a flowchart showing a history setting process executed by a management-side CPU. [Figure 47] 10 is a flowchart showing a display output process executed by a management CPU. [Figure 48] FIG. 20 is an explanatory diagram illustrating the configuration of an input port of a management side I / F in the ninth embodiment. [Figure 49] 10 is a flowchart showing a recognition process executed by a main CPU. [Figure 50] 10 is a flowchart showing a management process executed by a management-side CPU. [Figure 51] 10(a) to 10(h) are time charts showing how information on the correspondence between the first to twelfth buffers and the types of signals is stored in the correspondence memory. [Figure 52] This is a block diagram to explain the configuration of the signal path that transmits the detection results of each ball entry detection sensor to the main CPU and management IC in the 10th embodiment. [Figure 53] FIG. 22 is a front view of the main control device in the eleventh embodiment. [Figure 54] FIG. 4 is a block diagram for explaining an electrical configuration for performing various displays on the first to fourth notification display devices under the control of an MPU. [Figure 55] 10 is a flowchart showing a display process executed by a management CPU. [Figure 56] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 57] (a) An explanatory diagram for explaining the display mode of the first to fourth notification display devices when the results of game history management are displayed, and (b) an explanatory diagram for explaining the display mode of the first to fourth notification display devices when the setting state of the pachinko machine is changed. [Figure 58] 10(a) to 10(h) are time charts showing how the first to fourth notification display devices change to display states. [Figure 59] FIG. 22(a) is an explanatory diagram for explaining the configuration of a first notification display device in the twelfth embodiment, and FIG. 22(b) is an explanatory diagram for explaining the configuration of a second notification display device. [Figure 60] This is an explanatory diagram for explaining the display contents of the first and second alarm display devices when the first to fourth alarm display devices display the results of game history management and when they display that the setting state of the pachinko machine is in a changeable state where it is possible to change it. [Figure 61] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 62] FIG. 23 is an explanatory diagram for explaining the configuration of an abnormality display area in the thirteenth embodiment. [Figure 63] 10 is a flowchart showing an abnormality setting process executed by the main CPU. [Figure 64] 10 is a flowchart showing an abnormality display process executed by the main CPU. [Figure 65] 23 is a flowchart showing an output process for management executed by a main CPU in the fourteenth embodiment. [Figure 66] 10 is a flowchart showing main processing executed by a main CPU in another embodiment. [Figure 67] FIG. 22 is an explanatory diagram for explaining the setting mode of programs and data in the main ROM in the fifteenth embodiment. [Figure 68] FIG. 10 is an explanatory diagram for explaining the setting mode of each area in the main RAM. [Figure 69] 10 is a flowchart showing a timer interrupt process executed by the main CPU. [Figure 70] 10 is a flowchart showing a management process executed by a main CPU. [Figure 71] 10 is a flowchart showing a management execution process executed by a main CPU. [Figure 72] FIG. 10 is an explanatory diagram illustrating various areas of a work area for non-specific control used to manage game history. [Figure 73] 10 is a flowchart showing a check process executed by a main CPU. [Figure 74] This is a flowchart showing the normal goal entry management processing executed by the main CPU. [Figure 75] 10 is a flowchart showing a result calculation process executed by the main CPU. [Figure 76] 10 is a flowchart showing a display process executed by the main CPU. [Figure 77] 20 is a flowchart showing a management process executed by a main CPU in the sixteenth embodiment. [Figure 78] 23 is a flowchart showing a management execution process executed by a main CPU in the seventeenth embodiment. [Figure 79] 22 is a flowchart showing a management execution process executed by a main CPU in the eighteenth embodiment. [Figure 80] 22 is a flowchart showing a management execution process executed by a main CPU in the nineteenth embodiment. [Figure 81] 13 is a flowchart showing a management process executed by a main CPU in the twentieth embodiment. [Figure 82] 10 is a flowchart showing a management execution process executed by a main CPU. [Figure 83] FIG. 21 is an explanatory diagram for explaining the electrical configuration in the twenty-first embodiment. [Figure 84] 22 is a flowchart showing a main process executed by a main CPU in the 22nd embodiment. [Figure 85] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 86] 10 is a flowchart showing a timer interrupt process executed by the main CPU. [Figure 87] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 88] 10 is a flowchart showing a RAM monitoring process executed by the main CPU. [Figure 89] 10 is a flowchart showing main processing executed by a main CPU in another embodiment. [Figure 90] 10 is a flowchart showing a setting value update process executed by the main CPU in another embodiment. [Figure 91] 23 is a flowchart showing a main process executed by a main CPU in the 23rd embodiment. [Figure 92] 24 is a flowchart showing a RAM monitoring process executed by a main CPU in the 24th embodiment. [Figure 93] 25 is a flowchart showing a RAM monitoring process executed by a main CPU in the 25th embodiment. [Figure 94] 10 is a flowchart showing a management execution process executed by a main CPU. [Figure 95] 10 is a flowchart showing another monitoring process executed by the main CPU. [Figure 96] 26 is a flowchart showing a management process executed by a main CPU in the 26th embodiment. [Figure 97] 27 is a flowchart showing a management process executed by a main CPU in the 27th embodiment. [Figure 98] 28 is a flowchart showing a management process executed by a main CPU in the 28th embodiment. [Figure 99] 29 is a flowchart showing a management process executed by a main CPU in the 29th embodiment. [Figure 100] 13 is a flowchart showing a main process executed by a main CPU in the 30th embodiment. [Figure 101] 10 is a flowchart showing a power outage information storage process executed by a main CPU. [Figure 102] FIG. 10A is a block diagram illustrating the configuration of an MPU, and FIG. 10B is a time chart illustrating the output of a reset signal by a reset signal output unit. [Figure 103] 10 is a flowchart showing a timer interrupt process executed by the main CPU. [Figure 104] 10 is a flowchart showing a setting monitoring process executed by a main CPU. [Figure 105] 10 is a flowchart showing a management process executed by a main CPU. [Figure 106] 10 is a flowchart showing a management execution process executed by a main CPU. [Figure 107] 10 is a flowchart showing another monitoring process executed by the main CPU. [Figure 108] 13 is a flowchart showing a main process executed by a main CPU in the thirty-first embodiment. [Figure 109] 10 is a flowchart showing a clearing process executed by the main CPU when an abnormality occurs. [Figure 110] 10 is a flowchart showing a clearing process for non-specific control executed by the main CPU. [Figure 111] 13 is a flowchart showing a power outage information storage process executed by the main CPU in the 32nd embodiment. [Figure 112] 10 is a flowchart showing a checksum monitoring process executed by the main CPU. [Figure 113] 10 is a flowchart showing a clearing process for non-specific control executed by the main CPU. [Figure 114] 13 is a flowchart showing a main process executed by the main CPU in the thirty-third embodiment. [Figure 115] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 116] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 117] 10 is a flowchart showing a first timer interrupt process executed by the main CPU. [Figure 118] 10 is a flowchart showing a setting monitoring process executed by a main CPU. [Figure 119] FIG. 10 is a block diagram for explaining a configuration for controlling the display of various display circuits by a main CPU. [Figure 120] (a) An explanatory diagram for explaining various buffers provided in a work area for specific control, and (b) an explanatory diagram for explaining various memory areas provided in a work area for non-specific control. [Figure 121] FIG. 2 is an explanatory diagram for explaining the electrical configuration of a display IC. [Figure 122] 10(a) to 10(g) are time charts showing how type data and display data are transmitted from the main CPU to the display IC and how the display data transmitted from the display IC is received by the first display circuit or the second display circuit. [Figure 123] 10 is a flowchart showing a second timer interrupt process executed by the main CPU. [Figure 124] (a) An explanatory diagram for explaining the display contents of the first to fourth notification display devices when the setting value is updated, and (b) an explanatory diagram for explaining the display contents of the first to fourth notification display devices when the setting value is confirmed. [Figure 125] 13 is a flowchart showing a setting value update process executed by the main CPU in the thirty-fourth embodiment. [Figure 126] FIG. 22 is an explanatory diagram for explaining the electrical configuration of a calculation result storage area in the thirty-fifth embodiment. [Figure 127] 5(a) to 5(d) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. [Figure 128] 5(a) to 5(c) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. [Figure 129] 10(a) to 10(e) are time charts showing how the base values ​​of various areas are notified by the first to fourth notification display devices. [Figure 130] 10 is a flowchart showing a result calculation process executed by the main CPU. [Figure 131] 10 is a flowchart showing a display process executed by the main CPU. [Figure 132] 10 is a flowchart showing a main process executed by a main CPU. [Figure 133] 10 is a flowchart showing a first timer interrupt process executed by the main CPU. [Figure 134] 10 is a flowchart showing a second timer interrupt process executed by the main CPU. [Figure 135] 10 is a flowchart showing a setting process during normal operation executed by the main CPU. [Figure 136] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 137] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 138] 10(a) to 10(f) are time charts for explaining the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. [Figure 139] 13 is a flowchart showing a main process executed by the main CPU in the 36th embodiment. [Figure 140] 13 is a flowchart showing a main process executed by the main CPU in the 37th embodiment. [Figure 141] 13 is a flowchart showing a normal setting process executed by the main CPU in the 38th embodiment. [Figure 142] 13(a) to 13(d) are explanatory diagrams for explaining a setting correspondence storage area provided in a main ROM in the thirty-ninth embodiment. [Figure 143] This is a flowchart showing the process of reading the win / lose table executed by the main CPU. [Figure 144] 10 is a flowchart showing a setting process to the fifth display data buffer during setting update executed by the main CPU. [Figure 145] 13(a) to 13(c) are explanatory diagrams for explaining a setting correspondence storage area provided in a main ROM in the fortieth embodiment. [Figure 146](a) An explanatory diagram for explaining the various display units provided in an area visible from the front of the pachinko machine through the window panel in the 41st embodiment, and (b) an explanatory diagram for explaining the display content of the round display unit. [Figure 147] 10 is a flowchart showing a main process executed by the main CPU in the 42nd embodiment. [Figure 148] 10 is a flowchart showing a first timer interrupt process executed by the main CPU. [Figure 149] 13 is a flowchart showing a result calculation process executed by the main CPU in the 43rd embodiment. [Figure 150] 10 is a flowchart showing a display process executed by the main CPU. [Figure 151] 10(a) to 10(g) are time charts showing how the base values ​​of various areas are notified by the first to fourth notification display devices. [Figure 152] 10(a) to 10(g) are time charts showing how the base values ​​of various areas are notified by the first to fourth notification display devices in the 44th embodiment. [Figure 153] 10 is a flowchart showing a main process executed by the main CPU in the 45th embodiment. [Fig. 154] 10 is an explanatory diagram for explaining the contents of a storage area related to setting values ​​provided in a work area for specific control. FIG. [Figure 155] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 156] 10 is a flowchart showing a setting process to the fifth display data buffer during setting confirmation executed by the main CPU. [Figure 157] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 158] 10 is a flowchart showing a setting process to the fifth display data buffer during setting update executed by the main CPU. [Figure 159]FIG. 10 is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. [Figure 160] 10(a) to 10(e) are time charts showing the end timings of the setting value update process and the setting confirmation process in relation to the operation state of the setting key insertion section. [Figure 161] 10 is a flowchart showing a main process executed by the main CPU in the 46th embodiment. [Figure 162] FIG. 10 is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. [Figure 163] This is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or setting confirmation processing is being executed in the 47th embodiment. [Fig. 164] This is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or setting confirmation processing is being executed in the 48th embodiment. [Figure 165] 10 is a flowchart showing main processing executed by the main CPU in the 49th embodiment. [Figure 166] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 167] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 168] 10(a) to 10(h) are time charts showing how first timer interrupt processing and second timer interrupt processing are permitted when processing is being executed at the start of supply of operating power. [Figure 169]10(a) to 10(g) are time charts showing how processing proceeds when an abnormality occurs in the power outage flag, checksum, or set value. [Figure 170] 10(a) to 10(g) are time charts showing the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. [Figure 171] FIG. 10 is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. [Fig. 172] FIG. 2 is an explanatory diagram for explaining the electrical configuration of the audio and light emission control device. [Figure 173] 10 is a flowchart showing the performance control process executed by the sound and light side CPU. [Fig. 174] 10 is an explanatory diagram for explaining the action corresponding to the content of the processing executed in the processing at the start of the supply of operating power in the main CPU. FIG. [Figure 175] A flowchart showing the performance control processing executed by the sound and light side CPU in the 50th embodiment. [Figure 176] 10 is an explanatory diagram for explaining the action corresponding to the content of the processing executed in the processing at the start of the supply of operating power in the main CPU. FIG. [Figure 177] 10 is a flowchart showing a main process executed by the main CPU in the 51st embodiment. [Figure 178] 10 is a flowchart showing a main process executed by the main CPU in the 52nd embodiment. [Figure 179] 10 is a flowchart showing a main process executed by the main CPU in the 53rd embodiment. [Figure 180] 10(a) to 10(g) are time charts showing the state of subsequent processing when the supply of operating power to the main CPU is stopped while the setting value update processing is being executed. [Figure 181] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 182] FIG. 10 is an explanatory diagram for explaining the contents of a storage area provided in a work area for specific control. [Figure 183] 10(a) to 10(f) are time charts showing how the setting values ​​to be updated are updated. [Figure 184] 10 is a flowchart showing a main process executed by the main CPU in the 54th embodiment. [Figure 185] 10 is a flowchart showing main processing executed by the main CPU in the 55th embodiment. [Figure 186] FIG. 10 is an explanatory diagram for explaining a clear target area and a non-clear target area set in a work area for specific control. [Figure 187] 10 is a flowchart showing a display start process executed by the main CPU. [Figure 188] 10 is a flowchart showing a second timer interrupt process executed by the main CPU. [Figure 189] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation when the supply of operating power begins. [Figure 190] FIG. 10 is an explanatory diagram for explaining each area provided in the clear target area of ​​the work area for specific control in the 56th embodiment. [Figure 191] 10 is a flowchart showing a display start process executed by the main CPU. [Figure 192] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation when the supply of operating power begins. [Figure 193] 13 is a flowchart showing a display start process executed by the main CPU in the 57th embodiment. [Figure 194] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation when the supply of operating power begins. [Figure 195] FIG. 10 is an explanatory diagram for explaining each area set in the clear target area and the clear non-target area of ​​the work area for specific control in the 58th embodiment. [Figure 196] 10 is a flowchart showing a first timer interrupt process executed by the main CPU. [Figure 197] 10 is a flowchart showing a display start process executed by the main CPU. [Figure 198] (a) is an explanatory diagram for explaining the lottery table for displaying the loss of a special drawing, and (b) is an explanatory diagram for explaining the lottery table for displaying the loss of a regular drawing. [Figure 199] 13 is a flowchart showing a display start process executed by the main CPU in the 59th embodiment. [Figure 200] (a) is an explanatory diagram for explaining the initial display lottery table for special drawings, and (b) is an explanatory diagram for explaining the initial display lottery table for regular drawings. [Figure 201] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation when the supply of operating power begins. [Figure 202] 10 is a flowchart showing a display start process executed by the main CPU in the 60th embodiment. [Figure 203] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation when the supply of operating power begins. [Figure 204] 10 is a flowchart showing a display start process executed by the main CPU in the 61st embodiment. [Figure 205] 10 is a flowchart showing a setting value update process executed by the main CPU in the 62nd embodiment. [Figure 206] 10 is a flowchart showing a display start process executed by the main CPU. [Figure 207] (a) An explanatory diagram for explaining the first display allocation table for special drawings, (b) An explanatory diagram for explaining the second display allocation table for special drawings, (c) An explanatory diagram for explaining the first display allocation table for regular drawings, and (d) An explanatory diagram for explaining the second display allocation table for regular drawings. [Figure 208] 10 is a flowchart showing a display start process executed by the main CPU in the 63rd embodiment. [Figure 209] A front view of the game board in the 64th embodiment. [Figure 210] 1A is a longitudinal cross-sectional view of a second actuation part in a non-guiding state, and FIG. 1B is a longitudinal cross-sectional view of the second actuation part in a guiding state. [Figure 211] 10A and 10B are explanatory diagrams for explaining the display contents of the symbol display device when a game round is executed. [Figure 212] (a) to (j) are explanatory diagrams for explaining the main and sub-patterns that are variably displayed in each pattern row. [Figure 213] A vertical cross-sectional view to explain the internal structure of the prize distribution device. [Figure 214] 10 is an explanatory diagram for explaining the electrical configuration for performing various lotteries in the main CPU. FIG. [Figure 215] (a) An explanatory diagram for explaining the win / loss table of the first special chart, and (b) an explanatory diagram for explaining the win / loss table of the second special chart. [Figure 216] (a) An explanatory diagram for explaining the type table for big wins, (b) An explanatory diagram for explaining the contents of each of the multiple types of big win results, (c) An explanatory diagram for explaining the type table for small wins, and (d) An explanatory diagram for explaining the contents of each of the multiple types of small win results. [Figure 217] 10 is a flowchart showing a general-purpose power control process executed by the main CPU. [Figure 218] 10 is a flowchart showing a special chart special power control process executed by the main CPU. [Figure 219] This is a flowchart showing the special chart change start processing executed by the main CPU. [Figure 220] This is a flowchart showing the processing during special chart determination executed by the main CPU. [Figure 221] 10 is a flowchart showing a distribution process executed by a main CPU. [Figure 222] 10 is a flowchart showing a special call termination process executed by the main CPU. [Figure 223] FIG. 10 is an explanatory diagram for explaining each area set in the clear target area of ​​the work area for specific control. [Figure 224] 10 is a flowchart showing a second timer interrupt process executed by the main CPU. [Figure 225] (a) is a flowchart showing the setting process for the first display data buffer during setting update executed by the main CPU, and (b) is a flowchart showing the setting process for the sixth display data buffer during setting confirmation executed by the main CPU. [Figure 226] 10(a) to 10(g) are time charts showing how the display contents of the first special symbol display section, the second special symbol display section, and the special display section change depending on the state of the pachinko machine. [Figure 227] 10 is a flowchart showing the second timer interrupt processing executed by the main CPU in the 65th embodiment. [Figure 228] A flowchart showing the second timer interrupt processing executed by the main CPU in the 66th embodiment. [Figure 229] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 230] 10 is a flowchart showing second timer interrupt processing executed by the main CPU in the 67th embodiment. [Figure 231] (a) An explanatory diagram for explaining the configuration of the special display unit in the 68th embodiment, and (b) a time chart showing the display contents of the 15R display unit, 6R display unit, and small win display unit when the setting value update process or setting confirmation process is being executed. [Figure 232] A front view of the game board in the 69th embodiment. [Figure 233] 10 is an explanatory diagram for explaining the electrical configuration for performing various lotteries in the main CPU. FIG. [Figure 234](a) An explanatory diagram for explaining the first correct / incorrect table when the probability is low, (b) An explanatory diagram for explaining the first correct / incorrect table when the probability is high, (c) An explanatory diagram for explaining the second correct / incorrect table when the probability is low, and (d) An explanatory diagram for explaining the second correct / incorrect table when the probability is high. [Figure 235] (a) An explanatory diagram for explaining the type table, (b) An explanatory diagram for explaining the contents of each of multiple types of jackpot results and the contents of one type of small jackpot result, and (c) An explanatory diagram for explaining the contents of the support mode. [Figure 236] FIG. 10 is an explanatory diagram for explaining the setting mode of the display duration of a game round. [Figure 237] 10 is a flowchart showing a first special symbol special power control process executed by the main CPU. [Figure 238] 10 is a flowchart showing a second special symbol special power control process executed by the main CPU. [Figure 239] This is a flowchart showing the special chart change start processing executed by the main CPU. [Figure 240] This is a flowchart showing the processing during special chart determination executed by the main CPU. [Figure 241] (a) An explanatory diagram for explaining the first correct / incorrect table at low probability in the 70th embodiment, (b) An explanatory diagram for explaining the first correct / incorrect table at high probability, (c) An explanatory diagram for explaining the second correct / incorrect table at low probability, and (d) An explanatory diagram for explaining the second correct / incorrect table at high probability. [Figure 242] (a) An explanatory diagram for explaining the first correct / incorrect table at low probability in the 71st embodiment, (b) An explanatory diagram for explaining the first correct / incorrect table at high probability, (c) An explanatory diagram for explaining the second correct / incorrect table at low probability, and (d) An explanatory diagram for explaining the second correct / incorrect table at high probability. [Figure 243] A front view of the game board in the 72nd embodiment. [Figure 244] FIG. 2 is an explanatory diagram for explaining the electrical configuration of the main control device and the audio and light emission control device. [Figure 245] 10 is a flowchart showing a main process executed by a main CPU. [Figure 246] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 247] 10 is a flowchart showing a set value update process executed by a main CPU. [Figure 248] FIG. 10 is an explanatory diagram for explaining the setting mode of each area in the main RAM. [Figure 249] FIG. 10A is an explanatory diagram illustrating the contents of an address counter, and FIGS. 10B to 10E are explanatory diagrams illustrating how the carry flag is set to "1" as a result of the target address being updated. [Figure 250] 10 is a flowchart showing a RAM clearing process executed by the main CPU. [Figure 251] 10 is a flowchart showing the target address addition process executed by the main CPU. [Figure 252] 10 is a flowchart showing a clearing process for non-specific control executed by the main CPU. [Figure 253] 10 is a flowchart showing a checksum calculation process executed by a main CPU. [Figure 254] 10 is a flowchart showing the performance control process executed by the sound and light side CPU. [Figure 255] (a) to (f) are time charts showing how, when the supply of operating power to the main CPU and the sound / light CPU is started, check displays are executed on the first to fourth alarm display devices and initial operations are performed by the movable body. [Figure 256] A flowchart showing the performance control processing executed by the sound and light side CPU in the 73rd embodiment. [Figure 257] 10 is a flowchart showing a main process executed by the main CPU in the 74th embodiment. [Figure 258] 10 is a flowchart showing a setting confirmation process executed by the main CPU. [Figure 259]10 is a flowchart showing a set value update process executed by a main CPU. [Figure 260] 10 is a flowchart showing a RAM clearing process executed by the main CPU. [Figure 261] 10 is a flowchart showing an open / close monitoring process executed by a main CPU. [Figure 262] FIG. 2 is an explanatory diagram for explaining the electrical configuration of the audio and light emission control device. [Figure 263] FIG. 10 is an explanatory diagram for explaining the contents of a post-confirmation notification table. [Figure 264] 10 is an explanatory diagram for explaining the relationship between various notification tables and the types of execution areas to be read out. FIG. [Figure 265] 10(a) to 10(h) are time charts showing the relationship between post-confirmation notification and main body closure notification, and the relationship between post-clear notification and main body closure notification. [Figure 266] 10 is a flowchart showing the performance control process executed by the sound and light side CPU. [Figure 267] 10 is a flowchart showing task processing executed by the sound and light side CPU. DETAILED DESCRIPTION OF THE INVENTION

[0010] First Embodiment A first embodiment of a pachinko machine 10, which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a perspective view of the pachinko machine 10, and Fig. 2 is an exploded perspective view showing the main components of the pachinko machine 10. For convenience, Fig. 2 omits the components within the gaming area PA of the pachinko machine 10.

[0011] As shown in Figure 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so that it can rotate forward. The outer frame 11 is made up of wooden boards connected at all four sides, forming a rectangular frame. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and the outer frame 11 may be attached to island equipment in the amusement hall.

[0012] 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 can be rotated forward with the left side as the base end of rotation and the right side as the tip end of rotation when viewed from the front.

[0013] A front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side being the base end and the right side being the tip end when viewed from the front. A back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated rearward with the left side being the base end and the right side being the tip end when viewed from the front.

[0014] The gaming machine main body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine main body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states can be released by using an unlocking key to unlock the cylinder lock 17, which is exposed on the front of the pachinko machine 10.

[0015] Next, the configuration of the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 in the resin base 21.

[0017] Here, the configuration of the game board 24 will be described with reference to Fig. 3. Fig. 3 is a front view of the game board 24.

[0018] An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and these inner rail section 25 and outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0019] The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeding device 27b that supplies game balls stored in an upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c that is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. When a launching operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0020] A plurality of large and small openings are formed in the game board 24, penetrating in the front-to-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a general symbol unit 38. There are four general winning openings 31 in total, and one of each of the others.

[0021] Even if a ball enters the through gate 35, no game balls will be paid out. On the other hand, if balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls will be paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball will be paid out; when one game ball enters the general winning opening 31, ten prize balls will be paid out; and when one game ball enters the special electric winning device 32, fifteen prize balls will be paid out.

[0022] The number of prize balls is arbitrary, and for example, the second actuation port 34 may be configured to have fewer prize balls than the first actuation port 33, or the second actuation port 34 may be configured to have more prize balls than the first actuation port 33.

[0023] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes etc. are discharged from the game area PA through the outlet 24a. Also, on the game board 24, a large number of nails 24b are planted to appropriately distribute and adjust the falling direction of the game balls, and various components such as windmills are also arranged.

[0024] Here, "entering" means that a gaming ball passes through a predetermined opening, and includes not only the case where the gaming ball passes through the opening and is discharged from the gaming area PA, but also the case where the gaming ball continues to flow down the gaming area PA without being discharged from the gaming area PA after passing through the opening. However, in the following explanation, in order to clearly distinguish from the gaming ball entering the outlet 24a, the gaming ball entering the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the through gate 35 will also be referred to as "winning."

[0025] The first actuation port 33 and the second actuation port 34 are united as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 open upward. Furthermore, the first actuation port 33 is at the top, and both actuation ports 33, 34 are aligned vertically. The second actuation port 34 is provided with a normal power device 34a serving as a guide piece made up of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

[0026] A through gate 35 is provided upstream of the second operating port 34 in the direction in which the gaming ball flows down. The through gate 35 has a through hole (not shown) that penetrates vertically, and a gaming ball that enters the through gate 35 flows down through the gaming area PA after winning. This allows a gaming ball that enters the through gate 35 to enter the second operating port 34.

[0027] Based on a win at the through gate 35, the normal power device 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the win at the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38, which is located in the lower right corner of the game area PA, an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role release, the stop result corresponding to that result is displayed, and the variable display on the normal map display section 38a is terminated, the game transitions to the normal power open state. In the normal power open state, the normal power device 34a is opened in a predetermined manner.

[0028] The map display unit 38a is configured with a segment display in which a plurality of LED display segments are arranged in a predetermined manner, but is not limited to this and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device, etc. The image displayed variably on the map display unit 38a may be configured to variably display multiple types of letters, multiple types of symbols, multiple types of characters, or multiple types of colors that are switched between.

[0029] In the normal map unit 38, a normal map reserve display unit 38b is provided adjacent to the normal map display unit 38a. Up to four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display unit 38b.

[0030] A winning lottery is triggered by the entry into the first operating port 33 or the second operating port 34. The result of the lottery is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Specifically, the special symbol unit 37 includes a special symbol display unit 37a. The display area of ​​the special symbol display unit 37a is smaller than the display surface 41a of the symbol display unit 41. A winning lottery is triggered by a win through the first actuation port 33 or the second actuation port 34, and the special symbol display unit 37a displays a variable or predetermined symbol. The result corresponding to the lottery result is then displayed. The special symbol display unit 37a is configured as a segment display in which multiple LED display segments are arranged in a predetermined manner. However, this is not limited to this, and the special symbol display unit 37a may be configured as a liquid crystal display, an organic electroluminescence display, a cathode ray tube (CRT), a dot matrix display, or another type of display device. The symbols displayed on the special symbol display unit 37a may include a configuration in which multiple characters, symbols, characters, or colors are displayed.

[0032] In the special symbol unit 37, a special symbol reserve display unit 37b is provided adjacent to the special symbol display unit 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special symbol reserve display unit 37b.

[0033] More specifically, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

[0034] In the symbol display device 41, when a variable or predetermined display of symbols is performed in the special symbol display unit 37a based on a winning entry in the first actuation port 33 or a winning entry in the second actuation port 34, a variable or predetermined display of symbols is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows, an upper row, a middle row, and a lower row, as multiple display areas, and in each symbol row, main symbols numbered "1" through "9" are scrolled and displayed in ascending or descending order. In this scrolling display, scrolling of all symbol rows is first started, then switched from scrolling display to standby display in the order of the upper symbol row → the lower symbol row → the middle symbol row, and finally ended with a predetermined symbol being statically displayed in each symbol row. Then, in a game where the game result is a jackpot, a predetermined combination of symbols is displayed stationary on a predetermined pay line on the display surface 41a of the symbol display device 41. Specifically, if the most favorable jackpot result described below is obtained, the same odd numbered symbol combination will be displayed in a stopped state, if the low probability jackpot result described below is obtained, the same even numbered symbol combination will be displayed in a stopped state, and if the low prize high probability jackpot result described below is obtained, a symbol combination that is not the same symbol combination but would not be displayed in a stopped state if the low prize high probability jackpot result is not obtained will be displayed in a stopped state.

[0035] In addition, the symbol display device 41 not only displays effects triggered by winning a prize in the first actuation port 33 or the second actuation port 34, but also displays effects during the opening / closing execution mode to which it transitions after a winning jackpot. Furthermore, based on a prize in either actuation port 33, 34, display begins on the special symbol display unit 37a and the symbol display device 41, and one game session is played until a predetermined result is displayed and the game ends. Furthermore, the manner in which the symbols are displayed in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol rows, the direction of the symbol display in the symbol rows, the number of symbols in each symbol row, etc. can be changed as appropriate. Furthermore, the symbols displayed in the symbol display device 41 are not limited to the above-mentioned patterns; for example, a configuration in which only numbers are displayed as symbols may be used.

[0036] If a jackpot is won in a lottery based on a win through the first operating port 33 or the second operating port 34, the system transitions to an open / close execution mode in which a prize can be won in the special electric winning device 32. The special electric winning device 32 includes a large prize opening (not shown) that leads to the back side of the game board 24, and an open / close door 32a that opens and closes the large prize opening. The open / close door 32a is positioned in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which game balls cannot win, and is switched to an open state in which game balls can win if an internal lottery is selected to transition to the open / close execution mode. The open / close execution mode is a mode that is transitioned to when a win is achieved. Note that while a prize can be won in the closed state, it may be configured to be less likely to win than in the open state.

[0037] FIG. 4 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

[0038] As already explained, a gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the gaming area PA. In other words, a gaming ball that is launched from the gaming ball launching mechanism 27 and flows into the gaming area PA is discharged from the gaming area PA by entering any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the gaming board 24.

[0039] On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, respectively. The game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, and are guided to the lower end of the game board 24 on the back side of the game board 24, where they are collected by a discharge ball collection section (not shown). The game balls collected by the discharge ball collection section are then discharged to a ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passage sections 42-48 is provided with various detection sensors 42a-48a for detecting gaming balls. These discharge passage sections 42-48 and detection sensors 42a-48a will be described below. As already explained, four general winning openings 31 are provided, and therefore, there are discharge passage sections 42-44 corresponding to each of the four general winning openings. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage section 42 corresponding to the leftmost general winning opening 31 and the second discharge passage section 43 corresponding to the general winning opening 31 adjacent to it on the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located midway along the first discharge passage section 42, and the second winning opening detection sensor 43a is provided so that its detection range is located midway along the second discharge passage section 43. A gaming ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a as it passes through the first discharge passage 42, and a gaming ball that enters the general winning opening 31 adjacent to it on the right is detected by the second winning opening detection sensor 43a as it passes through the second discharge passage 43. A third discharge passage 44 is provided for the two general winning openings 31 on the right, and is formed so that the two general winning openings 31 merge midway. The third discharge passage 44 has entrance-side regions corresponding to the two general winning openings 31, and these entrance-side regions merge midway to form a single exit-side region. A third winning opening detection sensor 44a is provided so that a detection range is located midway in the exit-side region of the third discharge passage 44. A gaming ball that enters either of the two general winning openings 31 on the right is detected by the third winning opening detection sensor 44a as it passes through the third discharge passage 44.

[0041] A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at a position midway through the fourth discharge passage section 45, and a gaming ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a as it passes through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists at a position midway through the fifth discharge passage section 46, and a gaming ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a as it passes through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second operating port detection sensor 47a is provided so that its detection range exists at a midpoint of the sixth discharge passage section 47, and a gaming ball that enters the second operating port 34 is detected by the second operating port detection sensor 47a as it passes through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that its detection range exists at a midpoint of the seventh discharge passage section 48, and a gaming ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage section 48.

[0042] A gaming ball that is detected by one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on its way down the gaming area PA is detected by the gate detection sensor 49a.

[0043] Although electromagnetic induction type proximity sensors are used as the various detection sensors 42a-49a, any sensor can be used as long as it can detect gaming balls individually. The various detection sensors 42a-49a are electrically connected to the main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a gaming ball, and output a HI level signal when they are detecting a gaming ball. However, this is not a limitation, and the relationship between HI and LOW may be reversed.

[0044] As shown in Fig. 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the game board 24 having the above-described configuration to the resin base 21. As shown in Fig. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of ​​the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into the window portion 51. The window panel 52 is formed of colorless and transparent glass, but is not limited to this and may be formed of colorless and transparent synthetic resin, or may be formed of colored and transparent as long as the game area PA is visible through the window panel 52 from the front of the pachinko machine 10.

[0045] A display light-emitting unit 53 is provided above the window 51. A pair of left and right speakers 54 are also provided to output sound effects according to the game status. An upper bulge 55 and a lower bulge 56, which bulge toward the front, are arranged vertically below the window 51. An upper tray 55a that opens upward is provided inside the upper bulge 55, and a lower tray 56a that also opens upward is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls dispensed from the dispensing device (described later) and guiding them in a row toward the game ball launching mechanism 27. The lower tray 56a also has the function of storing surplus game balls in the upper tray 55a.

[0046] Next, the configuration of the rear side of the gaming machine main body 12 will be described.

[0047] As shown in Fig. 2, a main control device 60 that mainly controls the game is mounted on the back of the inner frame 13 (specifically, the game board 24). Fig. 5 is a front view of the main control device 60.

[0048] As shown in FIG. 5, the main control device 60 is configured by housing a main control board 61 in a board box 60a. An MPU 62 is mounted on one of the board surfaces, which is the element mounting surface, of the main control board 61. The board box 60a is formed transparent so that the MPU 62 housed in the board box 60a can be seen from outside the board box 60a. Although the board box 60a is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 62 housed in the board box 60a can be seen from outside the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 so that an opposing wall portion 60b of the board box 60a that faces the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine main body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the base box 60a and the MPU 62 through the opposing wall portion 60b.

[0049] The board box 60a is formed by combining multiple case bodies 60c one behind the other. These multiple case bodies 60c are provided with connecting portions 60e that prevent the case bodies 60c from being separated and leave traces of the separation. The connecting portions 60e are arranged side by side along one side of the roughly rectangular board box 60a. This allows for the case bodies 60c to be prevented from being separated by destroying some of the connecting portions 60e, and then the case bodies 60c can be separated by reconnecting other connecting portions 60e. Furthermore, because the connecting portions 60e are destroyed when the case bodies 60c are separated, it is possible to visually check the connecting portions 60e to determine whether the case bodies 60c have been separated fraudulently. Furthermore, a sealing sticker 60f is attached to the side of the board box 60a opposite to the side on which the connecting portions 60e are arranged, so as to straddle the boundary between the case bodies 60c. When the sealing sticker 60f is peeled off, an adhesive layer remains on the case body 60c. This makes it possible to leave a trace when the sealing sticker 60f is peeled off when the case bodies 60c are separated.

[0050] In the main control device 60 configured as described above, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the gaming hall manager is inserted and turned ON to trigger an opportunity to change the setting state of the pachinko machine 10 within the range of "Setting 1" to "Setting 6," an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned ON, a reset button 68c which is operated to clear data in a main RAM 65 (described later) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c which notify the results of game history management. In addition, the MPU 62 mounted on the main control board 61 is provided with a read terminal 68d for connecting to a connection terminal of an external device so that the external device can read the game history management results or the information (programs and data) stored in the main ROM 64. The setting state of the pachinko machine 10 is not limited to six stages from "Setting 1" to "Setting 6" and may be any number of stages.

[0051] The setting key insertion portion 68a, the update button 68b, the reset button 68c, the reading terminal 68d (i.e., the MPU 62), and the first to third notification display devices 69a to 69c are all provided on the device mounting surface of the main control board 61. As already explained, the device mounting surface of the main control board 61 faces the opposing wall portion 60b of the board box 60a, but the setting key insertion portion 68a, the update button 68b, the reset button 68c, and the reading terminal 68d are not covered by the opposing wall portion 60b. That is, the opposing wall portion 60b has separate openings in the areas facing the setting key insertion portion 68a, the update button 68b, the reset button 68c, and the reading terminal 68d. This allows the setting key to be inserted into the setting key insertion portion 68a, the update button 68b to be pressed, and the reset button 68c to be pressed, and the reading terminal 68d to be connected to a connection terminal for an external device, without the need to open the board box 60a.

[0052] By inserting a setting key into the setting key insertion portion 68a and rotating it in a predetermined direction, the setting key insertion portion 68a is turned on. In this state, by starting the supply of operating power to the pachinko machine 10 (i.e., by starting the supply of operating power to the MPU 62 of the main control device 60), the pachinko machine 10 enters a changeable state in which the setting state can be changed. In this state, each time the update button 68b is pressed once, the setting state of the pachinko machine 10 changes by one step in ascending order within the range of "Setting 1" to "Setting 6." Note that if the update button 68b is operated when the setting key is in the "Setting 6" state, the setting state is updated to "Setting 1." Furthermore, by rotating the setting key inserted into the setting key insertion portion 68a from the ON position in the direction opposite to the predetermined direction and returning it to its initial position, the setting key insertion portion 68a enters an OFF state. When the setting key insertion portion 68a enters an OFF state, the changeable state ends, and the game becomes playable with the setting values ​​at that time. In other words, after the changeable state has ended, the set value cannot be changed even if the update button 68b is operated.

[0053] The ON operation of the setting key insertion section 68a is valid only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the setting value cannot be changed.

[0054] The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10, and the larger the value of "setting n" (n is an integer between "1" and "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in detail later, there are two winning / losing lottery modes that determine the probability of winning a jackpot result: a low probability mode in which the probability of winning is relatively low, and a high probability mode in which the probability of winning is relatively high, and the higher the setting value, the higher the probability of winning a jackpot result in the low probability mode. On the other hand, regardless of the setting value, the probability of winning a jackpot result in the high probability mode is constant.

[0055] As described above, the reset button 68c is operated to clear the data in the main RAM 65, but in order to clear the data, it is necessary to start the supply of operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The ON operation of the reset button 68c is valid only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the data in the main RAM 65 cannot be cleared.

[0056] As already explained, the reading terminal 68d is connected to a connection terminal of an external device so that the external device can read the game history management results or the information (programs and data) stored in the main ROM 64, but in order to output data to the external device, it is necessary to start the supply of operating power to the pachinko machine 10 with the connection terminal of the external device connected to the reading terminal 68d (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The connection of an external device to the reading terminal 68d is enabled only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if an external device is connected to the reading terminal 68d after the MPU 62 of the main control device 60 has completed processing at the start of the supply of operating power, no external output to the external device will be performed.

[0057] Each of the first to third alarm display devices 69a to 69c is a segment display with an array of seven LED display segments, but is not limited to this and may be a single light-emitting element of a multicolor type, a liquid crystal display device, or an organic electroluminescence (EL) display. Each of the first to third alarm display devices 69a to 69c is installed so that its display surface faces the direction in which the element mounting surface of the main control board 61 faces, and is covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed to be transparent, the display surfaces of the first to third alarm display devices 69a to 69c housed within the board box 60a can be seen from outside the board box 60a. Furthermore, as already explained, the main control device 60 is mounted on the back surface of the resin base 21 in the board box 60a so that the opposing wall portion 60b that faces the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the rear surface of the resin base 21 is exposed toward the front of the pachinko machine 10, it becomes possible to visually observe the display surfaces of the first to third alarm display devices 69a to 69c through the opposing wall portion 60b.

[0058] The display surface of the first notification display device 69a displays not only the numbers "0" through "9" but also various characters, including alphabetic characters. Meanwhile, the second notification display device 69b and the third notification display device 69c display the numbers "0" through "9." The first through third notification display devices 69a through 69c are used to notify the results of game history management; the details of these notifications will be described later. In addition, when the setting state of the pachinko machine 10 is in a changeable state, in which it is possible to change the setting state, a value corresponding to the current setting value is displayed on the third notification display device 69c. The value corresponding to the setting value may be displayed on the first notification display device 69a or the second notification display device 69b. Alternatively, the setting value before the changeable state may be displayed on one of the first through third notification display devices 69a through 69c, and the current setting value may be displayed on another of the first through third notification display devices 69a through 69c.

[0059] As shown in Figure 2, a back pack unit 15 is installed to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a transparent synthetic resin, to which a dispensing mechanism 73 and a control device assembly unit 74 are attached.

[0060] The payout mechanism 73 includes a tank 75 to which gaming balls supplied from the island equipment of the gaming hall are successively replenished, and a payout device 76 for paying out the gaming balls stored in the tank 75. The gaming balls paid out from the payout device 76 are discharged into the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power on and off.

[0061] The control device aggregate unit 74 is equipped with a payout control device 77 having the function of controlling the payout device 76, and a power supply / launch control device 78 which generates and outputs the predetermined power required by the various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply / launch control device 78 are stacked one behind the other so that the payout control device 77 is at the rear of the pachinko machine 10.

[0062] <Electrical configuration of pachinko machine 10> FIG. 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0063] The main control device 60 comprises a main control board 61 that is responsible for the main control of the game, and a power outage monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 has a main CPU 63, which is an arithmetic processing device including a control unit and an arithmetic unit, as well as a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also has built-in interrupt circuits, timer circuits, data input / output circuits, various counter circuits such as random number generators, etc.

[0064] The main ROM 64 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0065] The main RAM 65 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM or DRAM, and is used for both reading and writing. The main RAM 65 is randomly accessible and takes less time to read data than the main ROM 64 when compared for the same data capacity. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0066] The management IC 66 is a management device that manages the game history based on information supplied from the main CPU 63. As will be described in detail later, the management IC 66 grasps the ball entry history of game balls into the general winning opening 31, the special electric winning device 32, the first actuation opening 33, the second actuation opening 34, and the outlet 24a, and grasps the ball entry frequency into the general winning opening 31, the special electric winning device 32, the first actuation opening 33, and the second actuation opening 34 based on the grasped ball entry history. The management IC 66 also grasps the occurrence frequency of the opening / closing execution mode and the high frequency support mode, which will be described later.

[0067] The MPU 62 is provided with an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply / launch control device 78 having the function of supplying operating power, and operating power is supplied to the MPU 62 via the power outage monitoring board 67.

[0068] Various sensors, such as the ball entry detection sensors 42a-49a, are connected to the input side of the MPU 62. As already explained, the ball entry detection sensors 42a-49a include the first prize entry detection sensor 42a, the second prize entry detection sensor 43a, the third prize entry detection sensor 44a, the special electric current detection sensor 45a, the first operation port detection sensor 46a, the second operation port detection sensor 47a, the outlet detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a-49a, the main CPU 63 determines whether a ball has entered each entry area. In addition, the main CPU 63 executes various lotteries based on whether a ball has entered the first operation port 33, and also executes various lotteries based on whether a ball has entered the second operation port 34.

[0069] The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is positioned at the ON operation position or the OFF operation position. The main CPU 63 then determines whether the setting key insertion section 68a is positioned at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b has been pressed. The main CPU 63 then determines whether the update button 68b has been pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c has been pressed. The main CPU 63 then determines whether the reset button 68c has been pressed based on the detection result from the sensor.

[0070] The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio / light emitting control device 81. A prize ball command is output to the payout control device 77, for example, when a gaming ball enters a prize ball entry section among the entry sections, where the occurrence of the ball entry corresponds to the payout of the gaming ball. Various commands such as a variation command, a type command, and an opening command are output to the audio / light emitting control device 81.

[0071] The output side of the MPU 62 is connected to a special power drive unit 32b that opens and closes the opening / closing door 32a of the special power winning device 32, a normal power drive unit 34b that opens and closes the normal power device 34a of the second operating port 34, a special power unit 37, and a normal power unit 38. Incidentally, the special power unit 37 is provided with a special power display unit 37a and a special power reserve display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal power unit 38 is provided with a normal power display unit 38a and a normal power reserve display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 controls the drive of various drive units and various display units through these driver circuits.

[0072] That is, in the opening / closing execution mode, the main CPU 63 executes drive control of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the normal power device 34a is won, the main CPU 63 executes drive control of the normal power drive unit 34b so that the normal power device 34a is opened and closed. Also, during each game round, the main CPU 63 executes display control of the special chart display unit 37a. Also, when the lottery result of whether or not the normal power device 34a is to be opened is clearly displayed, the main CPU 63 executes display control of the normal chart display unit 38a. In addition, when a prize is won at the first operating port 33 or the second operating port 34, or when a changing display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart reserve display unit 37b, and when a prize is won at the through gate 35, or when a changing display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart reserve display unit 38b.

[0073] The first to third notification display devices 69a to 69c are connected to the output side of the MPU 62. The results of the game history management by the management IC 66 are notified through displays on the first to third notification display devices 69a to 69c. When the setting state of the pachinko machine 10 is changed, the current setting value is displayed on the third notification display device 69c. In this case, the display of the first notification display device 69a and the second notification display device 69b is controlled by the management IC 66 and not by the main CPU 63, whereas the display of the third notification display device 69c is controlled by both the main CPU 63 and the management IC 66. Display control of the third notification display device 69c by the main CPU 63 takes priority over display control by the management IC 66.

[0074] However, without being limited to this, the third notification display device 69c may also be configured so that the display is controlled by the management IC 66 and not by the main CPU 63. In this case, when the current setting value is to be displayed on the third notification display device 69c upon changing the setting state of the pachinko machine 10, it is preferable that the main CPU 63 instructs the management IC 66 to display the setting value.

[0075] The MPU 62 is provided with a read terminal 68d. A sensor (not shown) is provided on the read terminal 68d, and the sensor detects whether or not a connection terminal for an external device is connected to the read terminal 68d. The master CPU 63 then determines whether or not a connection terminal for an external device is connected to the read terminal 68d based on the detection result from the sensor. Furthermore, if an external device is connected to the read terminal 68d, the results of game history management in the management IC 66 or information (programs and data) stored in the master ROM 64 are output to the external device.

[0076] The power failure monitoring board 67 relays between the main control board 61 and the power supply / launch control device 78, and monitors the stable DC voltage of 24 volts, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0077] The power supply and launch control device 78 is connected to a commercial power source (external power source) in, for example, an amusement hall. Based on the external power supplied from the commercial power source, the power supply and launch control device 78 generates the necessary operating power for the main control board 61, the payout control device 77, and other components, and supplies the generated operating power to them. The power supply and launch control device 78 is provided with a power supply unit for power outages, such as a backup capacitor, so that even when the power supply to the pachinko machine 10 is turned off, the power supply unit for power outages supplies power for memory retention to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply and launch control device 78 also controls the launch of the game ball launching mechanism 27, which is activated when predetermined launch conditions are met. The payout mechanism 73 is also provided with a power switch, as already explained. Turning the power switch ON starts the supply of operating power to the pachinko machine 10, and turning the power switch OFF stops the supply of operating power to the pachinko machine 10.

[0078] The audio and light emitting control device 81 drives and controls the display light emitting unit 53 and speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 executes display control of the pattern display device 41 based on commands received from the audio and light emitting control device 81.

[0079] <Electrical configuration for performing various lotteries in the main CPU 63> Next, the electrical configuration for performing various lotteries in the main CPU 63 will be described with reference to FIG.

[0080] During play, the master CPU 63 uses various counter information to determine whether a jackpot occurs, set the display of the special symbol display unit 37a, set the symbol display of the symbol display unit 41, and set the display of the normal symbol display unit 38a. Specifically, as shown in FIG. 7, the master CPU 63 uses a hit random number counter C1 used to determine whether a jackpot occurs, a jackpot type counter C2 used to determine the type of jackpot, a reach random number counter C3 used to determine whether a reach occurs when the symbol display unit 41 changes due to a miss, a random number initial value counter CINI used to set the initial value of the hit random number counter C1, and a change type counter CS to determine the display duration of the special symbol display unit 37a and the symbol display unit 41. Furthermore, the master CPU 63 uses a normal power feature release counter C4 used to determine whether the normal power feature 34a of the second operating port 34 is set to a normal power release state. The counters C1-C3, CINI, CS, and C4 are provided in the various counter area 65b of the master RAM 65.

[0081] Each counter C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

[0082] The reserve storage area 65a comprises a reserve area RE and an execution area AE. The reserve area RE comprises a first reserve area RE1, a second reserve area RE2, a third reserve area RE3 and a fourth reserve area RE4, and a combination of numerical information of the win random number counter C1, the jackpot type counter C2 and the reach random number counter C3 is stored as reserve information in one of the reserve areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

[0083] In this case, when multiple consecutive wins occur in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first hold area RE1 to the fourth hold area RE4 in chronological order from the first hold area RE1 to the second hold area RE2 to the third hold area RE3 to the fourth hold area RE4. By providing four hold areas RE1 to RE4 in this way, up to four winning histories of game balls entering the first actuation port 33 or the second actuation port 34 can be reserved and stored.

[0084] The number of items that can be stored on hold is not limited to four and can be any number, such as two, three, five or more, or it can be singular.

[0085] The execution area AE is an area for moving the various numerical information stored in the first holding area RE1 of the holding area RE when the variable display of the special chart display section 37a begins, and when one game round begins, a win / loss determination is made based on the various numerical information stored in the execution area AE.

[0086] Each of the counters will now be described in detail.

[0087] First, the normal power accessory opening counter C4 will be described. The normal power accessory opening counter C4 is configured to be incremented by one in sequence within a range of, for example, 0 to 250, and to return to "0" after reaching the maximum value. The normal power accessory opening counter C4 is periodically updated, and is stored in the normal power reserve area 65c of the main RAM 65 when a gaming ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the normal power accessory 34a to the open state based on the value of the stored normal power accessory opening counter C4.

[0088] In the present pachinko machine 10, a plurality of types of support modes are set so that the manner of support by the normal power device 34a differs from one another. In detail, the support modes are set to a high frequency support mode and a low frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 is opened per unit time is relatively high or low when compared in a situation where game balls are continuously launched in the same manner into the game area PA.

[0089] In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power device opening counter C4 is the same (for example, 4 / 5 in both), but in the high-frequency support mode, the number of times the normal power device 34a opens when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for each opening is set to be longer.In this case, if the normal power opening state is won in the high-frequency support mode and the normal power device 34a opens multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each opening.Furthermore, in the high-frequency support mode, the minimum time ensured between one normal power opening lottery and the next normal power opening lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0090] As described above, in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into first actuation port 33 is higher than in second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in first actuation port 33. When a winning entry into second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

[0091] The configuration for increasing the frequency of normal power release per unit time in the high-frequency support mode compared to the low-frequency support mode is not limited to the above, and may be configured to increase the probability of winning the normal power release state in the normal power release lottery, for example. In addition, in a configuration in which multiple types of reserved time (e.g., the time of variable display executed by the normal power display unit 38a based on winning at the through gate 35) are available for the period between one normal power release lottery and the next, the high-frequency support mode may be configured to be more likely to select a shorter reserved time or to have a shorter average reserved time than the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of the following conditions: increasing the number of releases, lengthening the open time, shortening the reserved time between one normal power release lottery and the next, shortening the average reserved time, and increasing the winning probability.

[0092] As already explained, the pachinko machine 10 has setting states "Setting 1" to "Setting 6." The opening frequency and opening mode of the normal power device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and opening mode of the normal power device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not limited to this, and at least one of the opening frequency and opening mode of the normal power device 34a for at least one of the low-frequency support mode and the high-frequency support mode may be configured to vary depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the opening frequency of the normal power device 34a in the low-frequency support mode, or the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the low-frequency support mode. In addition, the higher the set value, the higher the frequency of opening of the normal power device 34a in the high frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the high frequency support mode.

[0093] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to increment by one within a range of, for example, 0 to 599, and return to "0" after reaching a maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated, and is stored in the reserve storage area 65a of the main RAM 65 when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0094] The random number value that results in a jackpot win is stored as a hit / miss table in the main ROM 64. Figure 8 is an explanatory diagram for explaining the various tables stored in the main ROM 64. As the hit / miss table, low-probability hit / miss tables 64a to 64f for the low-probability mode and high-probability hit / miss table 64g for the high-probability mode are stored.

[0095] The low-probability hit / miss tables 64a to 64f are provided in one-to-one correspondence with the setting states of "Setting 1" to "Setting 6." That is, there is a low-probability hit / miss table 64a for Setting 1 that is referenced when the setting state of the pachinko machine 10 is "Setting 1," a low-probability hit / miss table 64b for Setting 2 that is referenced when the setting state of the pachinko machine 10 is "Setting 2," a low-probability hit / miss table 64c for Setting 3 that is referenced when the setting state of the pachinko machine 10 is "Setting 3," a low-probability hit / miss table 64d for Setting 4 that is referenced when the setting state of the pachinko machine 10 is "Setting 4," a low-probability hit / miss table 64e for Setting 5 that is referenced when the setting state of the pachinko machine 10 is "Setting 5," and a low-probability hit / miss table 64f for Setting 6 that is referenced when the setting state of the pachinko machine 10 is "Setting 6."

[0096] These low-probability tables 64a-64f are set so that the higher the setting value, the higher the probability of winning a jackpot. Specifically, when the low-probability table 64a for setting 1 is referenced, the jackpot result occurs at approximately 1 / 320, when the low-probability table 64b for setting 2 is referenced, the jackpot result occurs at approximately 1 / 310, when the low-probability table 64c for setting 3 is referenced, the jackpot result occurs at approximately 1 / 300, when the low-probability table 64d for setting 4 is referenced, the jackpot result occurs at approximately 1 / 290, when the low-probability table 64e for setting 5 is referenced, the jackpot result occurs at approximately 1 / 280, and when the low-probability table 64f for setting 6 is referenced, the jackpot result occurs at approximately 1 / 270. As a result, when the setting state of the pachinko machine 10 is set at a higher value, the jackpot result is more likely to occur in the low-probability mode, which is advantageous for the player.

[0097] On the other hand, only one type of high-probability win / loss table 64g is provided so that it is common to all settings, from "Setting 1" to "Setting 6." The high-probability win / loss table 64g is set to have a higher probability of winning a jackpot than the low-probability win / loss tables 64a to 64f, regardless of the setting, from "Setting 1" to "Setting 6." Specifically, when the high-probability win / loss table 64g is referenced, the jackpot result occurs at approximately 1 / 30. This makes it possible to make the high-probability mode more advantageous than the low-probability mode, regardless of the setting of the pachinko machine 10. Furthermore, even in the lowest setting, "Setting 1," the high-probability mode can be set, thereby increasing the probability of winning a jackpot compared to the low-probability mode of the highest setting, "Setting 6." Furthermore, it is possible to prevent an advantage or disadvantage from arising depending on the setting of the pachinko machine 10 for the high-probability mode, and it is also possible to reduce the storage capacity required to pre-store the high-probability win / loss table 64g in the main ROM 64.

[0098] The jackpot type counter C2 is configured to be incremented by 1 in sequence within a range of 0 to 29, and to return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically, and is stored in the reserve storage area 65a when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0099] A plurality of jackpot results are set in this pachinko machine 10. These plurality of jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special power winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning / losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the normal power device 34a of the second operating port 34 after the opening and closing execution mode ends.

[0100] As the manner of opening and closing control of the special power winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special power winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds of play are played up to the upper limit.

[0101] A round game is a game that continues until one of the following conditions is met: a predetermined maximum duration has elapsed, or a predetermined maximum number of game balls have entered the special winning device 32. The number of rounds in the open / close execution mode triggered by a jackpot result is a fixed number of rounds, regardless of the type of jackpot result that triggered the transition. Specifically, the maximum number of rounds is set to 15 regardless of the jackpot result.

[0102] Furthermore, in this pachinko machine 10, a plurality of types are set for one opening mode of the special electric winning device 32, with different opening durations from when the special electric winning device 32 is opened until when it is closed. In detail, a long-time mode in which the opening duration is set to 29 seconds, which is a long time, and a short-time mode in which the opening duration is set to 0.06 seconds, which is a short time shorter than the long time, are set.

[0103] In this pachinko machine 10, when the launch operation device 28 is operated by a player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched toward the play area PA every 0.6 seconds. The upper limit for the number of balls required to complete a round game is set to nine. In this case, the long-time mode among the above-mentioned release modes sets the release duration to a time longer than the product of the game ball launch cycle and one round game. On the other hand, the short-time mode sets the release duration to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when a single release is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of prizes in one round game. When a single release is performed in the short-time mode, it is expected that the special electric winning device 32 will not win, or that only one prize will be won, even if one is won.

[0104] In the high frequency winning mode, the special power winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special power winning device 32 is opened once in each round of play in a short time mode.

[0105] In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of rounds of play in one round in the high frequency winning mode and low frequency winning mode are not limited to the above values ​​and are arbitrary, as long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

[0106] The allocation destination of the jackpot result for the jackpot type counter C2 is stored as an allocation table 64h in the main ROM 64 as shown in Fig. 8. In the allocation table 64h, a low probability jackpot result, a low winning high probability jackpot result, and a most advantageous jackpot result are set as the allocation destination of the jackpot result in the event of a jackpot result.

[0107] A low probability jackpot result is a jackpot result in which the opening / closing execution mode becomes a high frequency winning mode, and after the opening / closing execution mode ends, the winning / losing lottery mode becomes a low probability mode and the support mode becomes a high frequency support mode. However, this high frequency support mode will transition to a low frequency support mode if the number of games played after the transition reaches the termination reference number (specifically, 100 times).

[0108] A low-prize, high-probability jackpot result is a jackpot result in which the open / close execution mode becomes a low-frequency win mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0109] The most favorable jackpot result is a jackpot result in which the open / close execution mode becomes a high-frequency winning mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0110] In relation to the above game states, the normal game state refers to a state in which the win / lose lottery mode is a low probability mode and the support mode is a low frequency support mode, rather than the open / close execution mode. Also, a low-prize, high-probability jackpot result may not be set as a game result. In addition, in the open / close execution mode in a low-prize, high-probability jackpot result, the number of rounds of play may be fewer than in the case of a low-probability jackpot result and a most favorable jackpot result.

[0111] In the distribution table 64h, of the values ​​of the jackpot type counter C2 from "0 to 29", "0 to 9" corresponds to a low probability jackpot result, "10 to 14" corresponds to a low probability jackpot result with a high probability of winning, and "15 to 29" corresponds to the most favorable jackpot result.

[0112] Only one type of allocation table 64h is provided so that it is common to any of the setting states of "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage in the allocation pattern of the jackpot result from depending on the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to previously store the allocation table 64h in the main ROM 64.

[0113] The allocation of jackpot results may be different depending on the settings of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result, or the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result or a low-prize, high-probability jackpot result. In this case, the higher the setting value, the higher the probability of entering a high-probability mode after a jackpot result. Also, the higher the setting value, the lower the probability of being allocated to a low-prize, high-probability jackpot result, or the higher the setting value, the higher the probability of being allocated to a low-prize, high-probability jackpot result. In this case, the higher the setting value, the higher the probability of the high-frequency winning mode opening / closing execution mode occurring.

[0114] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to increment by one within a range of, for example, 0 to 238, and return to "0" after reaching a maximum value. In the present pachinko machine 10, an expectation effect is set as one type of display effect in the symbol display device 41. In a gaming machine equipped with a symbol display device 41 capable of displaying varying symbols, in which the final stop result in a game round resulting in a predetermined jackpot result is a prize-related result, the expectation effect refers to a display state that makes the player believe that the variable display state is likely to result in the prize-related result from the start of the variable display of symbols on the symbol display device 41 until the stop result is derived and displayed. Specifically, the prize-related result is the display of a combination of symbols with the same number on one of the pay lines.

[0115] There are two types of expectation effects: a reach display and a notice display that is set to anticipate the occurrence of a reach display or a corresponding result before the reach display occurs.

[0116] The reach display includes a display state in which a reach symbol combination is displayed by stopping the display of symbols in some of the multiple symbol rows displayed on the display surface 41a of the symbol display device 41, and in that state, a variable display of symbols is performed in the remaining symbol rows. Also included are a reach effect in which, in a state in which a reach symbol combination is displayed as described above, a variable display of symbols is performed in the remaining symbol rows, and a reach effect is performed by displaying predetermined characters or the like as a moving image on the background screen, and a reach effect in which a reach symbol combination is displayed in a reduced size or is not displayed, and then a predetermined character or the like is displayed as a moving image on almost the entire display surface 41a.

[0117] The preview display includes a mode in which a character is displayed separately from the symbols on the symbol row when symbols are displayed variably in all symbol rows or when symbols are displayed variably in some symbol rows after the display of the variable symbols on the display surface 41a of the symbol display device 41 has started. It also includes a mode in which the background screen is displayed in a predetermined mode different from its previous mode, or a mode in which the symbols on the symbol row are displayed in a predetermined mode different from their previous mode. Such a preview display can occur in both game rounds when a reach display is made and when a reach display is not made, but is set to occur with a higher probability when a reach display is made than when a reach display is not made.

[0118] The reach display is executed regardless of the value of the reach random number counter C3 in a game in which the same symbol combination is finally stopped and displayed. Also, in a game in which a jackpot result is reached and the same symbol combination is not stopped and displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Also, in a game in which a miss result is reached, the reach display is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0119] On the other hand, the decision on whether to display a notice is not made by the main control device 60 but by the audio and light emitting control device 81. In this case, the audio and light emitting control device 81 executes a lottery process for the notice display so as to satisfy at least one of the conditions that a notice display is more likely to occur in a game round corresponding to a jackpot result than a game round corresponding to a loss result, and that a notice display with a low occurrence rate is more likely to occur. Incidentally, this lottery result is reflected when the effect for the game round is executed by the symbol display device 41.

[0120] Here, the probability of a reach display occurring in a game that results in a loss is the same regardless of the setting state of "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage from arising depending on the setting state of the pachinko machine 10 regarding the probability of a reach display occurring in a game that results in a loss. However, this is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of a reach display occurring in a game that results in a loss.

[0121] Next, the variation type counter CS will be explained. The variation type counter CS is configured to be incremented by 1 in sequence within a range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variation type counter CS is used in determining the display duration in the special symbol display unit 37a and the display duration of the symbol in the symbol display device 41 in the main CPU 63. The variation type counter CS is updated once each time the timer interrupt process described below is executed, and is also repeatedly updated within the remaining time until the next timer interrupt process is executed. Then, the buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special symbol display unit 37a and at the start of the variation of the symbol by the symbol display device 41.

[0122] <Regarding the processing configuration of the main CPU 63> Next, we will explain each process executed to progress the game by the main CPU 63. The processes of the main CPU 63 are roughly divided into main processing that is started when the power is turned on, and timer interrupt processing that is started periodically (every 4 millisecond period in this embodiment).

[0123] <Main processing> First, the main processing will be described with reference to the flowchart of FIG.

[0124] First, a power-on wait process is executed (step S101). In this power-on wait process, for example, the main process is started and a predetermined wait time (specifically, 1 second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial setting of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

[0125] Thereafter, it is determined whether the setting key insertion unit 68a has been turned on (step S103). If the setting key insertion unit 68a has not been turned on (step S103: NO), it is determined whether the reset button 68c has been pressed (step S104). If the reset button 68c has been pressed (step S104: YES), each area of ​​the main RAM 65 is cleared to "0" except for the area in which setting value information indicating the setting state of the pachinko machine 10 is set, and the areas cleared to "0" are initialized (step S105). In other words, if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning on the setting key insertion unit 68a, the setting value information is maintained in the state before the supply of operating power to the pachinko machine 10 was stopped, and the clearing process of the main RAM 65 is executed, and the memory area where the clearing process was executed is initialized. This makes it possible to initialize other areas of the main RAM 65 without changing the setting values. In step S105, various registers of the main CPU 63 are also cleared to "0" and then initialized.

[0126] If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is provided in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and a predetermined power outage process is executed normally, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved at the time of power outage, that is, the validity of the stored data (step S107). If the process of step S105 is executed or if a positive determination is made in step S107, it is determined whether the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

[0127] If a negative determination is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S109), and then an infinite loop is executed. The operation prohibition process is released by executing an all-clear process (step S117) described later.

[0128] If the determinations in all of steps S106 to S108 are affirmative, a power-on setting process is executed (step S110). In the power-on setting process, predetermined areas of the main RAM 65 are set to initial values, such as initializing the power outage flag, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After executing the process of step S110, a recognition process (step S111) is executed to cause the management IC 66 to recognize various information, and a data output process is executed to output various data to an external device connected to the read terminal 68d of the MPU 62 (step S112). The details of the recognition process and the data output process will be described later.

[0129] The main CPU 63 is configured to periodically execute timer interrupt processing, but the occurrence of timer interrupt processing is prohibited when the main processing is started. This state in which the occurrence of timer interrupt processing is prohibited is released when the processing of step S112 is completed and before the processing of step S113 is executed, and execution of the timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 starts, the data output processing of step S112 ends and the timer interrupt processing is not executed until before the processing of step S113 is started. Therefore, processing for progressing the game in the main CPU 63 is not started until this situation is reached.

[0130] Thereafter, the process proceeds to the remaining process of steps S113 to S116. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining process of steps S113 to S116. In this respect, the remaining process of steps S113 to S116 can be said to be non-periodic processing that is executed non-periodically.

[0131] In the remaining process, first, in step S113, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing. In the following step S114, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S115, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, current numerical information is read from the corresponding counter in the main RAM 65, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, it is cleared to "0". Thereafter, in step S116, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is prohibited to a state in which it is permitted. After the processing of step S116 is executed, the process returns to step S113, and the processing of steps S113 to S116 is repeated.

[0132] On the other hand, if the setting key insertion section 68a is turned ON (step S103: YES), all areas of the main RAM 65, including areas in which setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0," and the areas cleared to "0" are initialized (step S117). In other words, when an operation to change the setting state of the pachinko machine 10 is performed, all areas of the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the storage areas for which the clearing process was performed are initialized. Also, in step S117, various registers of the main CPU 63 are cleared to "0" and then initialized. Note that this is not a limitation, and a configuration may be adopted in which the all-clear process of the main RAM 65 is not performed unless the reset button 68c is pressed even when an operation to change the setting state of the pachinko machine 10 is performed, but the all-clear process is performed when the reset button 68c is pressed and an operation to change the setting state of the pachinko machine 10 is performed.

[0133] Thereafter, in step S118, a set value update process is executed, and in step S119, a set value update signal output process is executed, and then the process proceeds to step S110. The set value update process will be described below. The set value update signal output process will be described in detail later. Figure 10 is a flowchart showing the set value update process.

[0134] First, a setting value counter provided in the main RAM 65 is set to "1" (step S201). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the setting value up to that point.

[0135] Thereafter, a process for starting display of the set value is executed (step S202). In the process for starting display of the set value, the third notification display device 69c is controlled to display the number "1" corresponding to "Setting 1". When changing the set value, the manager of the gaming hall can grasp the current setting status of the pachinko machine 10 by checking the third notification display device 69c.

[0136] Thereafter, on the condition that the setting key insertion section 68a has not been turned OFF (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from LOW level to HI level. If the determination in step S204 is negative, the process returns to step S203, and it is determined whether the setting key insertion section 68a has been turned OFF.

[0137] If the update button 68b has been pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S206: YES), the setting value counter is set to "1" (step S207). As a result, the setting value is updated to the next higher setting each time the update button 68b is pressed once, and if the update button 68b is pressed once when the setting is "6," the setting will return to "1."

[0138] If a negative determination is made in step S206, or if the processing of step S207 is executed, a display update process of the setting value is executed (step S208). In the display update process of the setting value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter of the main RAM 65 is displayed. By checking the third notification display device 69c, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

[0139] After executing the process of step S208, the process returns to step S203, and it is determined whether the setting key insertion unit 68a has been turned OFF. If the setting key insertion unit 68a has not been turned OFF (step S203: NO), the process from step S204 onwards is executed again. If the setting key insertion unit 68a has been turned OFF (step S203: YES), a process of ending the display of the setting value is executed (step S209). In the process of ending the display of the setting value, the display of the setting value on the third notification display device 69c is ended.

[0140] <Timer interrupt processing> Next, the timer interrupt process will be described with reference to the flowchart in Fig. 11. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

[0141] First, a power outage information storage process is executed (step S301). In the power outage information storage process, it is monitored whether a power outage signal corresponding to the occurrence of a power outage has been received from the power outage monitoring board 67, and if a power outage is identified, a power outage process is executed and then an infinite loop is entered. In the power outage process, the power outage flag in the main RAM 65 is set to "1", and a checksum is calculated and stored.

[0142] Then, a lottery random number update process is executed (step S302). In the lottery random number update process, the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power feature release counter C4 are updated. Specifically, the current numerical information is sequentially read from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power feature release counter C4, and after executing a process of adding 1 to each of the read numerical information, a process of overwriting the counter from which it was read is executed. In this case, when the counter value exceeds the maximum value, each is cleared to "0". Then, in step S303, a random number initial value update process is executed as in step S114, and a variable counter update process is executed in step S304 as in step S115.

[0143] Thereafter, a fraud detection process is executed to monitor whether or not a predetermined event set as a target for fraudulent use has occurred (step S305). In this fraud detection process, the occurrence of multiple types of events is monitored, and if a predetermined event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S306, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S306, the process from step S307 onwards is executed.

[0144] In step S307, port output processing is executed. In the port output processing, if output information has been set in the previous timer interrupt processing, processing is executed to output corresponding to that output information to the various drive units 32b, 34b. For example, if information to switch the special power winning device 32 to an open state is set, output of a drive signal to the special power drive unit 32b is started, and if information to switch to a closed state is set, output of the drive signal is stopped. Also, if information to switch the normal power device 34a of the second operating port 34 to an open state is set, output of a drive signal to the normal power drive unit 34b is started, and if information to switch to a closed state is set, output of the drive signal is stopped.

[0145] Then, a read process is executed (step S308). In the read process, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in subsequent processes.

[0146] Thereafter, a ball entry detection process is executed (step S309). In the ball entry detection process, signals received from each ball entry detection sensor 42a-49a are read, and based on the read results, it is determined whether or not a ball has entered the out gate 24a, the general winning gate 31, the special electric winning device 32, the first operating gate 33, the second operating gate 34, and the through gate 35. Details of the ball entry detection process will be explained later.

[0147] Thereafter, a timer update process is executed (step S310) for collectively updating the numerical information of the multiple types of timer counters provided in the main RAM 65. In this case, the timer counters in which the stored numerical information is updated by subtraction are handled collectively, but it is also possible to collectively update both the subtraction type timer counters and the addition type timer counters.

[0148] Thereafter, a launch control process is executed to control the launch of gaming balls (step S311). While the launch operation to the launch operation device 28 continues, one gaming ball is launched at a predetermined launch cycle of 0.6 seconds. In the following step S312, as an input status monitoring process, based on the information read in the reading process of step S308, a disconnection check is performed for each ball entry detection sensor 42a-49a and whether the gaming machine main body 12 and the front door frame 14 are open is performed.

[0149] Thereafter, a special symbol special power control process is executed to control the execution of a game round and the execution of the open / close execution mode (step S313). The special symbol special power control process will be described in detail later.

[0150] Then, a normal map normal power control process is executed (step S314). In the normal map normal power control process, if a winning entry has occurred in the through gate 35, a process is executed to acquire the reserved information on the normal map side, and if the reserved information on the normal map side is stored, an opening judgment is made for the reserved information, and further, a process is executed to perform a normal map performance triggered by the opening judgment. Also, based on the result of the opening judgment, a process is executed to open and close the normal power device 34a of the second operating port 34. In this case, if the support mode is the low frequency support mode, a corresponding process is executed, and if the support mode is the high frequency support mode, a corresponding process is executed. Also, if the opening / closing execution mode is selected, the support mode immediately before will be the low frequency support mode even if it was the high frequency support mode.

[0151] In the following step S315, based on the processing results of the immediately preceding steps S313 and S314, output information is set to reflect the increase or decrease in the number of reserved information related to the special map display unit 37a in the special map reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the ordinary map display unit 38a in the ordinary map reserved display unit 38b. Also, in step S315, based on the processing results of the immediately preceding steps S313 and S314, output information is set to update the display contents of the special map display unit 37a, and output information is set to update the display contents of the ordinary map display unit 38a.

[0152] Thereafter, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation result (step S316). Also, a payout output process is executed to set the prize ball command as an output target (step S317). Also, an external information setting process is executed to control the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process (step S318). Thereafter, a management output process is executed to output information corresponding to the ball entry result in the game area PA to the management IC 66 (step S319). The details of the management output process will be explained later.

[0153] Next, the special picture special power control process in step S313 will be described with reference to the flowchart of FIG.

[0154] First, a process for acquiring reserved information is executed (step S401). In the process for acquiring reserved information, it is determined whether a winning has occurred in the first actuation port 33 or the second actuation port 34. If a winning has occurred, it is determined whether the number of reserved balls in the reserved ball storage area 65a is less than the upper limit ("4" in this embodiment). If the number of reserved balls is less than the upper limit, the number of reserved balls is incremented by one, and the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 updated in the previous step S302 is stored in the first reserved area among the empty reserved areas RE1 to RE4 in the reserved ball area RE. Note that if a winning has occurred in both the first actuation port 33 and the second actuation port 34 at the same time, the process for acquiring the reserved information is executed multiple times within the range of one execution of the process for acquiring reserved information. Furthermore, if new reserved information is acquired, a corresponding acquisition command is sent to the sound and light-emitting control device 81. When the audio / light emitting control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to display content corresponding to the increase in pending information items.

[0155] Thereafter, the information of the special picture special power counter provided in the main RAM 65 is read (step S402), and the special picture special power address table provided in the main ROM 64 is read (step S403). Then, a start address corresponding to the information of the special picture special power counter is obtained from the special picture special power address table (step S404), and the process jumps to the process indicated by the obtained start address among the processes of steps S406 to S412 (step S405). The special picture special power counter is a counter that allows the main CPU 63 to grasp which of the various processes of steps S406 to S412 should be executed, and the special picture special power address table has the start address of the program for executing the processes of steps S406 to S412 set in correspondence with the numerical information of the special picture special power counter.

[0156] In step S406, a special chart change start process is executed. Fig. 13 is a flowchart showing the special chart change start process.

[0157] In the special chart change start process, if the number of reserved information items stored in the reserved area RE is one or more (step S501: YES), a data setting process is executed (step S502). In the data setting process, the number of reserved items is first subtracted by one, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. Then, a process is executed to shift the data stored in each of the reserved areas RE1 to RE4 of the reserved area RE. This data shift process shifts the data stored in the first reserved area RE1 to the fourth reserved area RE4 sequentially to the lower areas. Specifically, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, the third reserved area RE3 to the second reserved area RE2, and the fourth reserved area RE4 to the third reserved area RE3, and then the fourth reserved area RE4 is cleared to "0." At this time, a shift command is sent to the audio and light-emitting control device 81 to acknowledge that the data in the reserved areas has been shifted. When the audio / light emitting control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to a display content corresponding to the reduction in pending information items.

[0158] After executing the data setting process, the win / loss table is read from the main ROM 64 (step S503). Specifically, first, the current win / loss lottery mode is determined by reading information indicating the win / loss lottery mode from the main RAM 65. If it is the high probability mode, the high probability win / loss table 64g is read from the main ROM 64. On the other hand, if it is the low probability mode, the setting state of the pachinko machine 10 is determined by reading the value of the setting value counter in the main RAM 65. Then, the low probability win / loss tables 64a to 64f corresponding to the determined setting value are read from the main ROM 64.

[0159] Thereafter, the winning / losing table 64a-64g read in step S503 is referred to in order to execute the winning / losing determination process (step S504). In the winning / losing determination process, it is determined whether or not the winning / losing determination information stored in the execution area AE, i.e., the numerical information related to the winning random number counter C1, matches the jackpot numerical information set in the winning / losing table 64a-64g read in step S503.

[0160] If the result of the win / loss determination process is a jackpot winning result (step S505: YES), an allocation determination process is executed (step S506). In the allocation determination process, information for allocation determination from the information stored in the execution area AE, i.e., the numerical information related to the jackpot type counter C2, is read out. Then, by referring to the allocation table 64h provided in the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out corresponds to. Specifically, it is determined which jackpot result it corresponds to: a low-probability jackpot result, a low-prize-winning high-probability jackpot result, or a most advantageous jackpot result.

[0161] Thereafter, a stop result setting process for the jackpot result is executed (step S507). Specifically, information on the form of the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for the jackpot result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the form of the pattern to be stopped and displayed on the special symbol display unit 37a is set differently for each type of jackpot result.

[0162] Thereafter, a flag set process corresponding to the distribution determination result is executed (step S508). Specifically, flags corresponding to the types of each jackpot result are provided in the main RAM 65, and in step S508, the flag corresponding to the result of the distribution determination process in step S506 is set to "1".

[0163] On the other hand, if it is determined in step S505 that the result is not a jackpot, a stop result setting process for a loss result is executed (step S509). Specifically, information on the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for a loss result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. The information on the pattern pattern selected in this case is different from the information on the pattern pattern selected in the case of a jackpot result.

[0164] After executing either the process of step S508 or step S509, a process for determining the duration of the game round is executed (step S510). In this process, the numerical information of the fluctuation type counter CS is acquired. Also, it is determined whether or not a reach display will occur on the pattern display device 41 in the current game round. Specifically, if the game round related to the start of the current fluctuation results in a low-probability jackpot result or a most favorable jackpot result, it is determined that a reach display will occur. Also, if neither of the jackpot results are obtained and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

[0165] If it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game round corresponding to the numerical information of the current variation type counter CS. On the other hand, if it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game round corresponding to the numerical information of the current variation type counter CS. Incidentally, the duration of the game round that can be obtained by reference to the reach non-occurrence duration table is different from the duration of the game round that can be obtained by reference to the reach occurrence duration table.

[0166] The duration of game plays when a reach does not occur is set so that the greater the number of reserved information stored in the reserved area RE, the shorter the duration of game plays. Furthermore, the non-reach duration table is set so that a shorter duration of game plays is selected when the support mode is in high-frequency support mode than when it is in low-frequency support mode, when the number of reserved information is the same. However, this is not limited to this, and the duration of game plays may not vary depending on the number of reserved information or the support mode, or the above relationship may be reversed. Furthermore, the above configuration may be applied to the duration of game plays when a reach occurs. Furthermore, separate duration tables may be set for various jackpot results, miss reach results, and miss results without a reach occurrence. In this case, the duration of game plays is allocated according to each game result.

[0167] Then, the information on the duration of the game acquired in step S510 is set in the special symbol special power timer counter provided in the main RAM 65 (step S511). The numerical information set in the special symbol special power timer counter is updated in the timer update process (step S310). Incidentally, as a performance for a game, the special symbol display unit 37a displays a changing pattern, and the pattern display device 41 displays a changing pattern. When each of these changing displays ends, the stop result of that game is displayed (the pattern display device 41 is in a state where a predetermined pattern combination is waiting on the active line), and the final stop is displayed for a final stop period (for example, 0.5 seconds). In this case, the duration of the game acquired in step S510 is the total time for one game.

[0168] Thereafter, the variation command and the type command are transmitted to the audio and light emitting control device 81 (step S512). The variation command includes information on the duration of the game rounds. Here, as described above, the duration of the game rounds acquired by referring to the non-reach duration table is different from the duration of the game rounds acquired by referring to the reach occurrence duration table. Therefore, even if the variation command does not include information on whether or not a reach has occurred, the audio and light emitting control device 81 can determine whether or not a reach has occurred from the information on the duration of the game rounds. In this regard, it can be said that the variation command includes information indicating whether or not a reach has occurred. Note that the variation command may also include information directly indicating whether or not a reach has occurred. Furthermore, the type command includes information on the game result.

[0169] When the sound and light emitting control device 81 receives a variation command and a type command from the main CPU 63, it causes the display light emitting unit 53, the speaker unit 54, and the pattern display device 41 to execute a game round effect. In this case, the game round effect is executed in a manner corresponding to the content of the variation command and the type command. In addition, the pattern display device 41 displays a variation of the patterns as a game round effect, and when the game round effect ends, a combination of patterns corresponding to the results of the win / loss determination process and the allocation determination process is displayed in a stopped state.

[0170] Thereafter, the display of the changing pattern on the special pattern display unit 37a is started (step S513). Then, the special pattern special power counter is incremented by 1 (step S514). In this case, since the numerical information of the special pattern special power counter is "0" when the special pattern change start process is executed, the numerical information of the special pattern special power counter becomes "1". Then, the 11th output flag provided in the main RAM 65 is set to "1" (step S515). The 11th output flag is a flag for specifying in the main CPU 63 that information output indicating that a game round has started should be executed to the management IC 66.

[0171] Returning to the explanation of the special symbol special power control process (FIG. 52), in step S407, special symbol variation process is executed. In the special symbol variation process, it is determined whether or not it is during the duration of the game round and before the final stop display, and if it is before the final stop display, a process is executed to regularly change the display mode of the image in the special symbol display unit 37a. When it is time to display the final stop, the numerical information of the special symbol special power counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special symbol variation process to that corresponding to the special symbol determination process. Note that in this embodiment, a final stop command is not sent from the main CPU 63 to the audio and light emission control device 81.

[0172] In step S408, a special symbol determination process is executed. In the special symbol determination process, the display mode of the image on the special symbol display unit 37a is set to a display mode corresponding to the lottery result of the current game round. In addition, in the special symbol determination process, it is determined whether the final stop period has elapsed, and if the period has elapsed, it is determined whether a transition to the opening and closing execution mode will occur. If a transition to the opening and closing execution mode does not occur, the numerical information of the special symbol special power counter is cleared to "0." If a transition to the opening and closing execution mode occurs, the numerical information of the special symbol special power counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special symbol determination process to that corresponding to the special power start process.

[0173] In step S409, special power start processing is executed. In the special power start processing, if the processing for starting the opening period in the current opening / closing execution mode has not yet been executed, the opening period setting processing is executed. An opening command is also sent to the audio and light-emitting control device 81. Upon receiving the opening command, the audio and light-emitting control device 81 causes the display light-emitting unit 53, speaker unit 54, and symbol display device 41 to execute an opening effect. If the opening period has elapsed, a start processing is executed to start the first round of play. In this start processing, the special power winning device 32 is set to an open state and the end conditions for the round of play are set. When setting this end condition, an upper limit duration for continuing the special power winning device 32 in an open state in the current first round of play is set, and the upper limit number of game balls that can win the special power winning device 32 in the current first round of play is set in a winning number counter provided in the main RAM 65.

[0174] In step S410, special line open processing is executed. In the special line open processing, it is determined whether the end condition for the round game has been met. If the end condition has been met, the special line winning device 32 is closed. Then, if the round game that has just finished is not the last round game executed, the numerical information of the special line counter is incremented by 1 to update the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line closed processing. If the round game that just finished is the last round game executed, the numerical information of the special line counter is incremented by 2 to update the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line end processing.

[0175] In step S411, special line closed processing is executed. In the special line closed processing, it is determined whether or not the interval period between rounds of play has elapsed. The interval period is set when the previous round of play ends. If the interval period has elapsed, the special line winning device 32 is set to an open state and the end conditions for the round of play are set. Then, by subtracting 1 from the numerical information of the special chart special line counter, the numerical information of the counter is updated from that corresponding to the special line closed processing to that corresponding to the special line open processing.

[0176] In step S412, special call termination processing is executed. In the special call termination processing, if the processing to start the ending period in this opening / closing execution mode has not yet been executed, the ending period (for example, 5 seconds) is set and an ending command is sent to the sound and light emission control device 81. By receiving the ending command, the sound and light emission control device 81 causes the display light emitting unit 53, speaker unit 54 and pattern display device 41 to execute an ending performance. When the ending period has elapsed, the win / lose lottery mode and support mode after the end of the opening / closing execution mode are each set to a mode corresponding to the jackpot result that triggered the start of this opening / closing execution mode.

[0177] Next, we will explain the configuration in the main CPU 63 for determining whether or not a game ball has entered the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, second operating port 34, and through gate 35 based on the detection results of each ball entry detection sensor 42a to 49a. Figure 14 is an explanatory diagram for explaining the configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0178] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so that it can handle eight types of signals simultaneously. An area in which information "0" or "1" is stored according to the voltage of each signal is provided in one-to-one correspondence with each terminal. That is, this area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals are input to the input port 63a, in order to limit the number of signals that can be input simultaneously to eight, the group of signals to be input to the input port 63a is switched through switching control by a driver IC.

[0179] In the ball entry detection process (step S309) of the timer interrupt process (FIG. 11), the signal group to be input to the input port 63a is set to the signal group from each ball entry detection sensor 42a-49a. In such a setting, the 0th bit D0 stores information corresponding to the detection signal from the first winning opening detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the second winning opening detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the third winning opening detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special power detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the first operating opening detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the second operating opening detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the outlet detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0180] Each of the ball entry detection sensors 42a-49a outputs a LOW-level signal indicating that it is not detecting a ball when it has not detected the passage of a game ball, and outputs a HI-level signal indicating that it is detecting a ball when it has detected the passage of a game ball. The input port 63a stores "0" in the corresponding bit when it receives a LOW-level signal, and stores "1" in the corresponding bit when it receives a HI-level signal. In other words, when the ball entry detection sensors 42a-49a have not detected the passage of a game ball, the corresponding bit stores "0" indicating that it is not detecting a game ball, and when it has detected the passage of a game ball, the corresponding bit stores "1" indicating that it is detecting a game ball.

[0181] FIG. 15 is a flowchart showing the ball scoring detection process executed in step S309 of the timer interrupt process (FIG. 11).

[0182] When it is confirmed that the 0th bit D0 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the first winning opening detection sensor 42a (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by 1 (step S603). The first output flag is a flag that specifies to the main CPU 63 that information indicating that one gaming ball has been detected by the first winning opening detection sensor 42a should be output to the management IC 66. The 10-prize ball counter is a counter that specifies to the main CPU 63 the number of times that 10 gaming balls should be paid out. If the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Fig. 11), and when the 10 prize ball command is output once, the value of the 10 prize ball counter is decremented by 1. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0183] When it is confirmed that the first bit D1 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the second winning opening detection sensor 43a (step S604: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S605), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S606). The second output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the second winning opening detection sensor 43a should be output to the management IC 66.

[0184] When it is confirmed that the second bit D2 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the third winning opening detection sensor 44a (step S607: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S608), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S609). The third output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the third winning opening detection sensor 44a should be output to the management IC 66.

[0185] When it is confirmed that the third bit D3 has changed from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the special electric detection sensor 45a (step S610: YES). In this case, the special electric winning flag provided in the main RAM 65 is set to "1" (step S611), the fourth output flag provided in the main RAM 65 is set to "1" (step S612), and further, the value of the 15-ball counter provided in the main RAM 65 is incremented by 1 (step S613). The special electric winning flag is a flag for the main CPU 63 to identify that one game ball has entered the special electric winning device 32 during round play in the open / close execution mode. In the special chart special electric control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the special electric winning flag is set to "1," it is determined that one game ball has entered the special electric winning device 32, and the number of remaining balls that can enter the special electric winning device 32 in a round of play is subtracted by 1. When the process of subtracting 1 from the number of remaining balls that can enter is executed, the special electric winning flag is cleared to "0." The fourth output flag is a flag that specifies to the main CPU 63 that information indicating that one game ball has been detected by the special electric detection sensor 45a should be output to the management IC 66. The 15-ball counter is a counter that specifies to the main CPU 63 the number of times that 15 game balls should be paid out. If the value of the 15 prize ball counter is 1 or more, a 15 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Fig. 11), and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0186] When it is confirmed that the fourth bit D4 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the first actuation port detection sensor 46a (step S614: YES). In this case, the first actuation winning flag provided in the main RAM 65 is set to "1" (step S615), the fifth output flag provided in the main RAM 65 is set to "1" (step S616), and further the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S617). The first actuation winning flag is a flag for the main CPU 63 to identify that one gaming ball has entered the first actuation port 33. In the special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the first activation winning flag is set to "1," a process for storing new reserved information is executed, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power control process (step S313), it is confirmed that the first activation winning flag is set to "1," and when a process corresponding to that confirmation is executed, the first activation winning flag is cleared to "0." The fifth output flag is a flag for specifying in the main CPU 63 that information indicating that one game ball has been detected by the first activation port detection sensor 46a should be output to the management IC 66. The single prize ball counter is a counter for specifying in the main CPU 63 the number of times one game ball should be paid out. If the value of the 1 prize ball counter is 1 or more, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Fig. 11), and when the 1 prize ball command is output once, the value of the 1 prize ball counter is decremented by 1. When the payout control device 77 receives the 1 prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0187] When it is confirmed that the fifth bit D5 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the second actuation port detection sensor 47a (step S618: YES). In this case, the second actuation winning flag provided in the main RAM 65 is set to "1" (step S619), and the sixth output flag provided in the main RAM 65 is set to "1" (step S620), and further the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S621). The second actuation winning flag is a flag that allows the main CPU 63 to identify that one gaming ball has entered the second actuation port 34. In the special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the second activation winning flag is set to "1," a process for storing new reserved information is executed, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power control process (step S313), it is confirmed that the second activation winning flag is set to "1," and when a process corresponding to that confirmation is executed, the second activation winning flag is cleared to "0." The sixth output flag is a flag for specifying in the main CPU 63 that information indicating that one game ball has been detected by the second activation port detection sensor 47a should be output to the management IC 66.

[0188] When it is confirmed that the sixth bit D6 has changed from a state in which the information "0" is stored to a state in which the information "1" is stored, it is determined that one gaming ball has been detected by the outlet detection sensor 48a (step S622: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S623). The seventh output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the outlet detection sensor 48a should be output to the management IC 66.

[0189] When it is confirmed that the seventh bit D7 has changed from a state in which "0" information is stored to a state in which "1" information is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, the gate winning flag provided in the main RAM 65 is set to "1" (step S625). The gate winning flag is a flag for the main CPU 63 to identify that one game ball has entered the through gate 35. In the normal map normal power control process (step S314) of the timer interrupt process (FIG. 11), by confirming that "1" has been set in the gate winning flag, the process is executed to store the current numerical information of the normal power device opening counter C4 as normal map side reserved information in the normal power reserve area 65c, provided that the number of normal map side reserved information stored in the normal power reserve area 65c is less than the upper limit of four. In the normal map normal power control process (step S314), it is confirmed that the gate winning flag is set to "1", and when the process corresponding to that confirmation is executed, the gate winning flag is cleared to "0".

[0190] As already explained, the timer interrupt process (FIG. 11) is started at a 4-millisecond cycle, so when one of the ball entry detection sensors 42a-49a starts detecting one game ball, the main CPU 63 determines that one game ball has been detected by the ball entry detection sensor 42a-49a while the sensor 42a-49a continues to detect that one game ball. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0191] Next, we will explain the processing executed by the dispensing control device 77. First, we will explain the electrical configuration of the dispensing control device 77 and various devices that communicate with the dispensing control device 77, with reference to the block diagram of Figure 16.

[0192] The dispensing control device 77 is equipped with an MPU 91. The MPU 91 includes a dispensing side CPU 92, which is a processing unit including a control unit and a calculation unit, as well as a dispensing side ROM 93, a dispensing side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, etc.

[0193] The dispensing ROM 93 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The dispensing ROM 93 stores various control programs and fixed value data executed by the dispensing CPU 92.

[0194] The dispensing-side RAM 94 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM and DRAM, and is used for both reading and writing. The dispensing-side RAM 94 is randomly accessible and takes less time to read data than the dispensing-side ROM 93 when compared for the same data capacity. The dispensing-side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing-side ROM 93.

[0195] The payout CPU 92 is capable of bidirectional communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout CPU 92 controls the operation of the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. The payout CPU 92 also monitors whether the payout device 76 is in a state where game balls can be paid out normally, and if it determines that the payout device 76 is in a state where game balls cannot be paid out normally, it stops the payout device 76 even if information on the number of unpaid prize balls is stored in the payout RAM 94. The payout CPU 92 also transmits a payout limit command to the main CPU 63 indicating that the payout device 76 is in a state where game balls cannot be paid out normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the audio / light-emitting control device 81 so that the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54 issue a notification indicating that the payout device 76 is in a state where game balls cannot be paid out normally. The states in which game balls cannot be dispensed normally include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been replenished with game balls, an abnormal dispense state in which the dispenser 76 does not operate normally, a main body open state in which the game machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

[0196] A full tank detection sensor (not shown) is provided midway along the game ball passageway leading from the payout device 76 to the lower tray 56a, and the detection result of the full tank detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

[0197] A no-ball detection sensor (not shown) is provided midway along the game ball passageway leading from tank 75 to payout device 76, and the detection result of the no-ball detection sensor is input to payout-side CPU 92. Payout-side CPU 92 determines that a no-ball state exists when the no-ball detection sensor continues to not detect a game ball, and determines that the no-ball state has been released when the state in which the no-ball detection sensor continues to not detect a game ball is released.

[0198] The payout device 76 is provided with a payout detection sensor (not shown) for detecting game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout side CPU 92. When a game ball is detected by the payout detection sensor, the payout side CPU 92 determines that one game ball has been paid out from the payout device 76. Furthermore, the payout side CPU 92 determines that an abnormal payout state exists when the payout detection sensor continues to not detect a game ball even though the payout device 76 is being driven and controlled so that a game ball is paid out, and determines that the abnormal payout state has been released when the state in which the payout detection sensor continues to not detect a game ball is released.

[0199] A front door open sensor 95 is provided on the front portion of the inner frame 13 (see FIG. 2), and the detection result of the front door open sensor 95 is input to the dispensing-side CPU 92. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing-side CPU 92, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that the front door frame 14 is closed when it receives a closed detection signal from the front door open sensor 95, and determines that the front door frame 14 is open when it receives an open detection signal from the front door open sensor 95. In addition, the dispensing-side CPU 92 transmits a front door open command to the main-side CPU 63 when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main-side CPU 63 when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

[0200] A main body open sensor 96 is provided on the front portion of the rear pack unit 15 (see FIG. 2), and the detection result of the main body open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the payout side CPU 92. When the payout side CPU 92 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when the payout side CPU 92 receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state. In addition, the payout side CPU 92 transmits a main body open command to the main side CPU 63 when it determines that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body close command to the main side CPU 63 when it determines that the gaming machine main body 12 has changed from an open state to a closed state. The main CPU 63 determines that the gaming machine main body 12 is in an open state when it receives a main body open command, and determines that the gaming machine main body 12 is in a closed state when it receives a main body close command.

[0201] The timer interrupt process executed by the dispensing CPU 92 will be described with reference to the flowchart of Figure 17. The timer interrupt process is repeatedly started at a predetermined cycle (for example, every 2 milliseconds).

[0202] First, a full tank process is executed (step S701). In the full tank process, as already explained, it is determined whether the tank is full based on the detection result of the full tank detection sensor, and if the tank is full, it executes a process to stop the payout of game balls and sends a command indicating the full tank state to the main CPU 63. Furthermore, if the full tank state is released, it executes a process to enable the payout of game balls and sends a command indicating that the full tank state has been released to the main CPU 63.

[0203] Thereafter, no-ball processing is executed (step S702). In the no-ball processing, as already explained, it is determined whether or not the no-ball state is present based on the detection result of the no-ball detection sensor, and if the no-ball state is present, it executes processing to stop the payout of game balls and sends a command indicating the no-ball state to the main CPU 63. Furthermore, if the no-ball state is released, it executes processing to enable the payout of game balls and sends a command indicating that the no-ball state has been released to the main CPU 63.

[0204] Thereafter, a payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already explained, it is determined whether or not a payout abnormality state exists based on the detection result of the payout detection sensor, and if a payout abnormality state exists, a process to stop the payout of game balls is executed, and a command indicating that a payout abnormality state exists is sent to the main CPU 63. Furthermore, if the payout abnormality state is released, a process to enable the payout of game balls is executed, and a command indicating that the payout abnormality state has been released is sent to the main CPU 63.

[0205] Thereafter, a front door open monitoring process is executed (step S704). In the front door open monitoring process, as already explained, it is determined whether or not the front door frame 14 is in the open state based on the detection result of the front door open sensor 95, and if the front door frame 14 is in the open state, a process to stop the payout of game balls is executed and a front door open command is sent to the main CPU 63. Furthermore, if the front door frame 14 is closed, a process to enable the payout of game balls is executed and a front door close command is sent to the main CPU 63.

[0206] Thereafter, a main body open monitoring process is executed (step S705). In the main body open monitoring process, as already explained, it is determined whether or not the gaming machine main body 12 is in the open state based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is in the open state, a process to stop the payout of game balls is executed and a main body open command is sent to the main CPU 63. Furthermore, if the gaming machine main body 12 is closed, a process to enable the payout of game balls is executed and a main body close command is sent to the main CPU 63.

[0207] Then, a command read process is executed (step S706). In the command read process, a process is executed to read the prize ball command sent by the main CPU 63, and the prize ball command is stored in the payout RAM 94. Then, a prize ball setting process is executed to add the number corresponding to the received prize ball command to the unpaid prize ball number information in the payout RAM 94 (step S707), and then a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S708). In the payout control process, when the unpaid prize ball number information stored in the payout RAM 94 is a value of 1 or more, the payout device 76 is driven and controlled, and when the payout detection sensor detects one game ball, the value of the prize ball number information is decremented by 1. Then, when the value of the prize ball number information becomes "0," the drive control of the payout device 76 is stopped. Thereafter, an external information setting process is executed to control the start and end of output of an external signal according to the results of the various processes executed in this timer interrupt process (step S709).

[0208] Next, a configuration for externally outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall will be described.

[0209] As shown in Fig. 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with a large number of external terminals, some of which are electrically connected to the main CPU 63, and some of which are electrically connected to the dispensing CPU 92. Since the main CPU 63 and the dispensing CPU 92 are each electrically connected to the external terminal board 97 in this manner, the main CPU 63 and the dispensing CPU 92 can externally output information to the hall computer HC, as shown in Fig. 16.

[0210] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and another external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the configuration of this electrical connection in detail, a signal relay board 98 is provided midway along the signal path from the front door open sensor 95 to the dispensing side CPU 92. The signal relay board 98 has a branch path SL2 branching from the signal path SL1 from the front door open sensor 95 to the dispensing side CPU 92. The branch path SL2 is connected to the front door open external terminal on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the dispensing side CPU 92, but also to the front door open external terminal on the external terminal board 97. This allows a signal indicating whether the front door frame 14 is open to be output to the hall computer HC without control by the dispensing side CPU 92.

[0211] Regarding the main body open sensor 96 in more detail, the signal relay board 98 is provided with a branch path SL4 that branches off from the signal path SL3 that runs from the main body open sensor 96 toward the payout CPU 92. The branch path SL4 is connected to an external terminal for main body open on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the main body open sensor 96 is not only input to the payout CPU 92, but also to the external terminal for main body open on the external terminal board 97. This makes it possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through control by the payout CPU 92.

[0212] Next, we will explain the content of the information externally output to the hall computer HC from the main CPU 63 and the payout CPU 92. First, we will explain the content of the information externally output from the main CPU 63 to the hall computer HC.

[0213] In the external information setting process (step S318) in the timer interrupt process (FIG. 11), the main CPU 63 performs setting for outputting information to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the opening / closing execution mode is in progress, information indicating that the support mode is in the high frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (for example, 100) of game balls have been discharged from the game area PA through any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, information indicating that a game ball has entered the first operating port 33, and information indicating that a game ball has entered the second operating port 34.

[0214] In the external information setting process (step S709) in the timer interrupt process (FIG. 17), the payout side CPU 92 sets the output of information to each external terminal assigned to the payout side CPU 92 on the external terminal board 97. The information output from the payout side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0215] The hall computer HC can grasp the manner in which game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, The payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10. - Ball payout rate in normal game mode, not in open / close execution mode or high frequency support mode (hereinafter, this ball payout rate will be referred to as "B") Ball payout rate in open / close execution mode - Ball payout rate in high frequency support mode The number of times a game is played until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S"). BS x "Number of winning balls for winning into the first actuation port 33 and the second actuation port 34" The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1") The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2") B-(S1 x "number of winning balls for winning into the first operating port 33" + S2 x "number of winning balls for winning into the second operating port 34") Probability of opening / closing execution mode occurring per unit play Probability of high frequency support mode occurring per unit play This allows the hall computer HC to manage the manner in which game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are paid out when one game ball enters the corresponding ball entry section.

[0216] <Configuration for managing winning status of gaming balls> Next, we will explain the configuration for managing game history using the management IC 66. First, we will explain the electrical configuration of the management IC 66 with reference to the block diagram of FIG.

[0217] As already explained, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 also includes an I / F 101 and the read terminal 68d already explained.

[0218] The I / F 101 is an interface for transmitting and receiving signals to and from devices external to the MPU 62. The I / F 101 is electrically connected to the main CPU 63 via an internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a-49a and commands from the dispensing CPU 92 are input to the MPU 62 through the input port of the I / F 101, and the main CPU 63 executes various processes based on the input detection results and command contents, as described above. Furthermore, when a signal is output to a device such as the special call driver 32b as a result of the execution of various processes by the main CPU 63, the signal is output through the output port of the I / F 101. Furthermore, when a command is output to the dispensing CPU 92 and the audio / light-emitting control device 81 as a result of the execution of various processes by the main CPU 63, the command is output through the output port of the I / F 101.

[0219] The management IC 66 includes a management I / F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, a history memory 117, and a calculation result memory 131. These devices are connected to each other via an internal bus 66a provided in the management IC 66 so as to enable two-way communication.

[0220] The management side I / F 111 is an interface for receiving various signals from the main CPU 63 via a group of signal paths 118 for one-way communication built in the MPU 62, and for transmitting various signals to the reading terminal 68d via a group of signal paths 119 for one-way communication built in the MPU 62. Various signals from the main CPU 63 are input to an input port of the management side I / F 111, and various signals to the reading terminal 68d are output from an output port of the management side I / F 111. The main CPU 63 is electrically connected to the reading terminal 68d via a group of signal paths 120 for two-way communication built in the MPU 62.

[0221] The management CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., non-volatile storage means) such as a NOR flash memory or a NAND flash memory that does not require an external power supply to retain its memory, and is used as a read-only memory. The management ROM 113 stores various control programs executed by the management CPU 112 and fixed value data. The management RAM 114 is a memory (i.e., volatile storage means) such as an SRAM or a DRAM that requires an external power supply to retain its memory, and is used as a read / write memory. The management RAM 114 is randomly accessible, and when compared for the same data capacity, requires a faster read time than the management ROM 113. The management RAM 114 temporarily stores various data and the like in response to the execution of the control programs stored in the management ROM 113.

[0222] The RTC 115 is a real-time clock that constantly measures date and time information and is configured to be able to output the measured date and time information (hereinafter also referred to as date and time information) in accordance with instructions from the management CPU 112. The RTC 115 is provided with a backup power supply, so that it is possible to measure date and time information even when the power to the pachinko machine 10 is cut off.

[0223] The correspondence memory 116 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as an SRAM or DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a-122p provided in the input port 121 of the management side I / F 111 and the types of signals input to those buffers 122a-122p. The contents of the correspondence memory 116 will be described in detail later.

[0224] The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information related to the game history received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be explained later.

[0225] The calculation result memory 131 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c, and are also output to an external device connected to the reading terminal 68d.

[0226] Next, a description will be given of the configuration of the input port 121 provided in the management side I / F 111. Fig. 19 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111.

[0227] The input port 121 is provided with a plurality of buffers 122a to 122p. Specifically, first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can receive one type of signal via signal paths 118a to 118p, and each of the first to sixteenth buffers 122a to 122p stores information of "0" as first data when the signal to be input is at a LOW level, and stores information of "1" as second data when the signal to be input is at a HI level. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0228] A first signal corresponding to the detection result of the first winning opening detection sensor 42a is input to the first buffer 122a. In this case, the main CPU 63 outputs a LOW level first signal when the first winning opening detection sensor 42a does not detect a new gaming ball, and outputs a HI level first signal for a specific period when the first winning opening detection sensor 42a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level first signal has been input to the first buffer 122a.

[0229] A second signal corresponding to the detection result of the second winning opening detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a LOW level second signal when the second winning opening detection sensor 43a does not detect a new gaming ball, and outputs a HI level second signal for a specific period when the second winning opening detection sensor 43a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

[0230] A third signal corresponding to the detection result of the third winning opening detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a LOW level third signal when the third winning opening detection sensor 44a does not detect a new gaming ball, and outputs a HI level third signal for a specific period when the third winning opening detection sensor 44a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

[0231] A fourth signal corresponding to the detection result of the special electric charge detection sensor 45a is input to the fourth buffer 122d. In this case, the main CPU 63 outputs a LOW level fourth signal when the special electric charge detection sensor 45a has not detected a new gaming ball, and outputs a HI level fourth signal for a specific period when the special electric charge detection sensor 45a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

[0232] A fifth signal corresponding to the detection result of the first actuation port detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a LOW level fifth signal when the first actuation port detection sensor 46a does not detect a new gaming ball, and outputs a HI level fifth signal for a specific period when the first actuation port detection sensor 46a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

[0233] A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW-level sixth signal when the second actuation port detection sensor 47a does not detect a new gaming ball, and outputs a HI-level sixth signal for a specific period when the second actuation port detection sensor 47a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI-level sixth signal has been input to the sixth buffer 122f.

[0234] A seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g. In this case, the main CPU 63 outputs a LOW level seventh signal when the outlet detection sensor 48a does not detect a new gaming ball, and outputs a HI level seventh signal for a specific period when the outlet detection sensor 48a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0235] An eighth signal corresponding to whether or not the open / close execution mode is in progress is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs the eighth signal at a low level when the open / close execution mode is not in progress, and continuously outputs the eighth signal at a high level when the open / close execution mode is in progress.

[0236] A ninth signal corresponding to whether or not the high frequency support mode is in effect is input to the ninth buffer 122i. In this case, the primary CPU 63 continuously outputs a LOW level ninth signal when the high frequency support mode is not in effect, and continuously outputs a HI level ninth signal when the high frequency support mode is in effect.

[0237] A tenth signal corresponding to whether or not the front door frame 14 is open is input to the tenth buffer 122j. In this case, the main CPU 63 continuously outputs a low-level tenth signal when the front door frame 14 is closed, and continuously outputs a high-level tenth signal when the front door frame 14 is open.

[0238] An eleventh signal corresponding to whether a game round has started is input to the eleventh buffer 122k. In this case, the main CPU 63 continuously outputs a LOW-level eleventh signal until a game round starts, and outputs a HI-level eleventh signal for a specific period of time once a game round has started. This specific period is long enough for the management CPU 112 to determine that a HI-level eleventh signal has been input to the eleventh buffer 122k.

[0239] A setting value update signal is input to the fifteenth buffer 122o to make the management CPU 112 recognize that a new setting has been made to the setting state of the pachinko machine 10 by the main CPU 63. In this case, the main CPU 63 outputs a LOW level setting value update signal when a new setting has not been made to the setting state of the pachinko machine 10, and when a new setting has been made to the setting state of the pachinko machine 10, outputs a pulse signal in which a HI level setting value update signal is maintained for a specific period of time for the number of times corresponding to the newly set setting value. This specific period is a period sufficient for the management CPU 112 to determine that a HI level setting value update signal has been input to the fifteenth buffer 122o.

[0240] An output instruction signal is input to the sixteenth buffer 122p to cause the management CPU 112 to recognize an opportunity to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output the history information, and outputs a HI level output instruction signal for a specific period when there is a need to output the history information. This specific period is long enough for the management CPU 112 to determine that a HI level output instruction signal has been input to the sixteenth buffer 122p.

[0241] Although the twelfth buffer 122l, the thirteenth buffer 122m, and the fourteenth buffer 122n can receive signals from the main CPU 63, they are blank and do not receive normal signals in the present pachinko machine 10. In this way, by providing a greater number of buffers 122a-122p as input ports 121 of the management I / F 111 than the number of types of signals output from the main CPU 63 to the management IC 66 in the present pachinko machine 10, the management IC 66 can be used in models other than the present pachinko machine 10. This makes it possible to increase the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and the first to sixteenth buffers 122a to 122p so as to correspond one-to-one to the first to sixteenth buffers 122a to 122p, respectively, but this is not limited to this, and the signal paths 118l to 118n may not be formed between the main CPU 63 and the buffers 122l to 122n to be blanked.

[0242] The fact that a set value update signal is input to the fifteenth buffer 122o and that an output instruction signal is input to the sixteenth buffer 122p was determined in the design stage of the management IC 66, and the management CPU 112 can determine that a set value update signal is input to the fifteenth buffer 122o and that an output instruction signal is input to the sixteenth buffer 122p without receiving an instruction from the main CPU 63. On the other hand, the types of signals that are input to the first to fourteenth buffers 122a to 122n were not determined in the design stage of the management IC 66, and the types of these signals are identified by the management CPU 112 upon receiving an instruction from the main CPU 63. The identification of the types of these signals by the management CPU 112 is performed by transmitting a type identification command from the main CPU 63 to the management CPU 112 when control is started in the main CPU 63 and the management CPU 112 following the start of supply of operating power to the MPU 62, as will be described in detail later. In this case, the information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of various signals while operating power is being supplied, the information stored in the correspondence memory 116 is referenced.

[0243] 20 is an explanatory diagram for explaining the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to fourteenth correspondence areas 123a to 123n in one-to-one correspondence with the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I / F 111.

[0244] The first correspondence area 123a stores information indicating that the signal input to the first buffer 122a is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the first buffer 122a. The first correspondence area 123a also stores information indicating that the signal is the general winning opening 31, as well as information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The second correspondence area 123b stores information indicating that the signal is the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the second buffer 122b. The second correspondence area 123b also stores information indicating that the signal is the general winning opening 31, as well as information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31. The third correspondence area 123c stores information indicating that the signal input to the third buffer 122c is from the general winning opening 31, as information for the management CPU 112 to identify the type of signal input to the third buffer 122c. In addition to the information indicating that the signal is from the general winning opening 31, the third correspondence area 123c also stores information on the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31.

[0245] The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is the special electric winning device 32, as information for the management CPU 112 to identify the type of signal input to the fourth buffer 122d. The fourth correspondence area 123d also stores information indicating that the signal is the special electric winning device 32, as well as information on the number of game balls (15) that will be paid out when one game ball enters the special electric winning device 32. The fifth correspondence area 123e stores information indicating that the signal is the first actuation port 33, as information for the management CPU 112 to identify the type of signal input to the fifth buffer 122e. The fifth correspondence area 123e also stores information indicating that the signal is the first actuation port 33, as well as information on the number of game balls (1) that will be paid out when one game ball enters the first actuation port 33. The sixth correspondence area 123f stores information indicating that the signal input to the sixth buffer 122f is the second actuation port 34, as information for the management CPU 112 to identify the type of signal. The sixth correspondence area 123f also stores information indicating that the signal is the second actuation port 34, as well as information on the number of game balls (1) that will be paid out when one game ball enters the second actuation port 34. The seventh correspondence area 123g stores information indicating that the signal is the outlet 24a, as information for the management CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0246] The eighth correspondence area 123h stores information indicating the open / close execution mode as information for the management CPU 112 to identify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating the high frequency support mode as information for the management CPU 112 to identify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating the front door frame 14 as information for the management CPU 112 to identify the type of signal input to the tenth buffer 122j. The eleventh correspondence area 123k stores information indicating the start of a game round as information for the management CPU 112 to identify the type of signal input to the eleventh buffer 122k.

[0247] The twelfth correspondence area 123l stores information indicating that the signal is blank and does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the twelfth buffer 122l. The thirteenth correspondence area 123m stores information indicating that the signal is blank and does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the thirteenth buffer 122m. The fourteenth correspondence area 123n stores information indicating that the signal is blank and does not correspond to any of the signals, as information for the management CPU 112 to identify the type of signal input to the fourteenth buffer 122n.

[0248] As described above, by configuring the management CPU 112 to specify what kind of signals are input to the first to fourteenth buffers 122a to 122n by receiving instructions from the main CPU 63, it becomes possible to use the management IC 66 in models other than this pachinko machine 10. This makes it possible to increase the versatility of the management IC 66.

[0249] Furthermore, instead of outputting information for recognizing the type of signal each time a signal corresponding to the storage of history information is output to the first to fourteenth buffers 122a to 122n, information for recognizing the type of signal is output in advance, and information for specifying the type of signal to be input to the first to fourteenth buffers 122a to 122n by the management CPU 112 based on the output information is stored in the correspondence memory 116. This makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration in which information for recognizing the type of signal is output each time a signal corresponding to the storage of history information is output to the first to fourteenth buffers 122a to 122n.

[0250] Furthermore, the information for specifying the types of signals input to the first to fourteenth buffers 122a to 122n by the management CPU 112 is output when the supply of operating power starts. This allows the management CPU 112 to specify the types of signals input to the first to fourteenth buffers 122a to 122n when a game is started in the pachinko machine 10.

[0251] Furthermore, the information that a setting value update signal is input to the 15th buffer 122o and the information that an output instruction signal is input to the 16th buffer 122p are set during the design stage of the management IC 66. This makes it possible to omit the process for identifying the type of signal input to the 15th buffer 122o and the 16th buffer 122p for the setting value update signal and output instruction signal, which are reliably used not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load for the process for identifying the type of such signal.

[0252] Next, a description will be given of the history memory 117 of the management IC 66. FIG.

[0253] The history memory 117 is provided with a history area 124 for sequentially storing history information. The history area 124 contains a plurality of pointer information items set with consecutive numbers, and a history information storage area 125 is set in one-to-one correspondence with each pointer information item. The history information storage area 125 can store a combination of RTC information and correspondence information. Each history information storage area 125 has a data capacity of 2 bytes, with 1 byte of data allocated as an area for storing RTC information and 1 byte of data allocated as an area for storing correspondence information. When it becomes necessary to store correspondence information according to signals input to the first to fourteenth buffers 122a to 122n (in the case of the present pachinko machine 10, these are actually the first to eleventh buffers 122a to 122k), the current date and time information measured by the RTC 115 is first stored in the area for storing RTC information in the history information storage area 125 corresponding to the pointer information currently being written. Thereafter, the correspondence information corresponding to the buffer 122a to 122n that triggered the current information storage is read from the correspondence area 123a to 123n corresponding to the buffer 122a to 122n in the correspondence memory 116, and the read correspondence information is stored in an area for storing correspondence information in the history information storage area 125 that corresponds to the pointer information currently being written.

[0254] Specifically, regarding the correspondence information stored in the history information storage area 125, as already explained, signals corresponding to the detection results of the ball entry detection sensors 42a-48a are input to the first to seventh buffers 122a-122g, and therefore, information corresponding to the types of the ball entry detection sensors 42a-48a is stored in the first to seventh correspondence areas 123a-123g in the correspondence memory 116. More specifically, information corresponding to the types of ball entry sections corresponding to the ball entry detection sensors 42a-48a is stored in the first to seventh correspondence areas 123a-123g. As already explained, in this pachinko machine 10, the first to third prize entry opening detection sensors 42a-44a all detect game balls that have entered the general prize entry opening 31, and therefore, the first to third correspondence areas 123a-123c corresponding to these first to third prize entry opening detection sensors 42a-44a all store information indicating that it is the general prize entry opening 31. Further, the fourth correspondence area 123d stores information indicating that it is the special electric winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the outlet 24a. If the buffer 122a-122n that triggered the current information storage is any of the first to seventh buffers 122a-122g, information on the type of ball entry portion corresponding to that buffer 122a-122g is read from any of the first to seventh correspondence areas 123a-123g, and the read information on the type of ball entry portion is stored as is in the area for storing correspondence information in the history information storage area 125.

[0255] On the other hand, the eighth buffer 122h receives a signal indicating whether or not it is in the opening / closing execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in the high frequency support mode, the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open, and the eleventh buffer 122k receives a signal indicating whether or not a game has started. Therefore, the eighth correspondence area 123h stores information indicating the opening / closing execution mode, the ninth correspondence area 123i stores information indicating the high frequency support mode, the tenth correspondence area 123j stores information indicating the front door frame 14, and the eleventh correspondence area 123k stores information indicating a game has started.

[0256] As already explained, the main CPU 63 continuously outputs the eighth signal at a low level when the open / close execution mode is not in effect, and continuously outputs the eighth signal at a high level when the open / close execution mode is in effect. Therefore, the control CPU 112 can determine that the open / close execution mode has started when the eighth signal changes from a low level to a high level, and can determine that the open / close execution mode has ended when the eighth signal changes from a high level to a low level. When the eighth signal changes from a low level to a high level, or when it changes from a high level to a low level, the control CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the eighth signal changes from a low level to a high level, not only the information indicating the open / close execution mode read from the eighth correspondence area 123h but also the start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the eighth signal changes from HI level to LOW level, not only the information indicating the opening / closing execution mode read from the eighth correspondence area 123h but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

[0257] As already explained, the main CPU 63 continuously outputs the ninth signal at a low level when the high-frequency support mode is not active, and continuously outputs the ninth signal at a high level when the high-frequency support mode is active. This allows the management CPU 112 to determine that the high-frequency support mode has started when the ninth signal changes from a low level to a high level, and to determine that the high-frequency support mode has ended when the ninth signal changes from a high level to a low level. When the ninth signal changes from a low level to a high level, or when it changes from a high level to a low level, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from a low level to a high level, not only the information indicating the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the 9th signal changes from HI level to LOW level, not only the information indicating the high frequency support mode read from the 9th correspondence area 123i but also the termination information are stored in an area for storing correspondence information in the history information storage area 125.

[0258] As already explained, the main CPU 63 continuously outputs a LOW-level tenth signal when the front door frame 14 is closed, and continuously outputs a HI-level tenth signal when the front door frame 14 is open. Therefore, the management CPU 112 determines that the front door frame 14 is open when the tenth signal changes from a LOW level to a HI-level, and determines that the front door frame 14 is closed when the tenth signal changes from a HI-level to a LOW-level. When the tenth signal changes from a LOW level to a HI-level, or when it changes from a HI-level to a LOW-level, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the tenth signal changes from a LOW level to a HI-level, not only the information indicating the front door frame 14 read from the tenth correspondence area 123j but also the opening start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence relationship area 123j but also the opening completion information are stored in an area for storing correspondence relationship information in the history information storage area 125.

[0259] As already explained, the main CPU 63 continues to output a LOW level 11th signal until the start timing of a game round arrives, and when the start timing of a game round arrives, it outputs a HI level 11th signal for a specific period of time. Therefore, the management CPU 112 determines that a game round has started when the 11th signal changes from a LOW level to a HI level. In other words, when the 11th signal changes from a LOW level to a HI level, information indicating that this is a game round read from the 11th correspondence area 123k is stored in an area for storing correspondence information in the history information storage area 125.

[0260] The history information storage area 125 is provided for a number of times that will enable storage of all the history information generated during ten consecutive business days, during which game balls are continuously shot in the pachinko machine 10 from opening to closing. For example, if history information is generated 60,000 times per day, more than 600,000 history information storage areas 125 will be provided. This makes it possible to store and hold all the history information for at least ten days in the history memory 117.

[0261] The history memory 117 is provided with a pointer area 126 separate from the history area 124. The pointer area 126 stores information that allows the management CPU 112 to identify the pointer information currently being written to in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, information specifying pointer information of "0" as the write target is set in the pointer area 126. Then, each time a new piece of history information is stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information is to be written and history information is stored in the history information storage area 125 corresponding to the last pointer information, the information in the pointer area 126 is updated so that pointer information of "0" is the write target. As a result, when a trigger occurs to store history information that exceeds the storable number of pieces of history information, the history information is overwritten with new history information, starting with the oldest history information stored in the history information storage area 125.

[0262] Furthermore, when an external device attempts to read history information from the history memory 117, the history information storage area 125 is cleared to all "0"s, and the information in the pointer area 126 is updated so that pointer information of "0" becomes the write target. This makes it possible to prevent history information that has once been read from becoming the read target again.

[0263] Next, a specific processing configuration for managing game history using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence between the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I / F 111 and the signal types in the correspondence memory 116 will be described. Fig. 22 is a flowchart showing the recognition processing executed by the main side CPU 63. The recognition processing is executed in step S111 in the main processing (Fig. 9).

[0264] First, "14" is set in a recognition output counter provided in the main RAM 65 (step S801). The recognition output counter is a counter used by the main CPU 63 to identify the remaining number of times information output is required to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n of the input port 121 in the management I / F 111 correspond to. As already explained, the first to fourteenth buffers 122a to 122n are the 14 buffers to be recognized for signal type, so "14" is set in the recognition output counter.

[0265] Thereafter, an output process of an identification start command is executed (step S802). The primary CPU 63 outputs various commands to the management CPU 112 to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n correspond to. When outputting these commands, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 to store history information are used to output commands to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n correspond to. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which a signal path for outputting the commands is provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Furthermore, in the output process of the identification start command, the output state of the ninth signal is switched to HI level at the timing when the output of the identification start command is started so that the management CPU 112 recognizes that a new command has been sent. Furthermore, the output period of the identification start command and the period during which the output state of the ninth signal is maintained at HI level are set to be long enough for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence memory 116.

[0266] Thereafter, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and thereafter, the (n+1)th buffer is set as the signal type, so that recognition setting of the signal types corresponding to the first to fourteenth buffers 122a to 122n is performed. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is the general winning port 31 and the number of prize balls therein is read out; if the recognition output counter is "11", a type identification command indicating that it is the special winning device 32 and the number of prize balls therein is read out; if the recognition output counter is "10", a type identification command indicating that it is the first operating port 33 and the number of prize balls therein is read out; if the recognition output counter is "9", a type identification command indicating that it is the second operating port 34 and the number of prize balls therein is read out; if the recognition output counter is "8", a type identification command indicating that it is the outlet 31 is read out; If the recognition output counter is "7", a type identification command indicating that it is in the open / close execution mode is read out; if the recognition output counter is "6", a type identification command indicating that it is in the high frequency support mode is read out; if the recognition output counter is "5", a type identification command indicating that it is the front door frame 14 is read out; if the recognition output counter is "4", a type identification command indicating that it is a game play; if the recognition output counter is "3" to "1", a type identification command indicating that it is blank is read out.

[0267] Thereafter, the control unit 112 executes an output process of the read type identification command (step S804). The type identification command, like the identification start command, has an 8-bit data capacity, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In the output process of the identification type command, the control unit 112 switches the output state of the ninth signal to HI level at the timing when output of the identification type command starts to make the control CPU 112 recognize that a new command has been sent. In addition, the output period of the identification type command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the control CPU 112 to recognize the output states of the identification type command and the ninth signal. By receiving the identification type command, the control CPU 112 stores information corresponding to the identification type command in the correspondence areas 123a to 123n corresponding to the buffer currently being set among the first to fourteenth buffers 122a to 122n.

[0268] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after decrementing by 1 is "0" (step S806). If the value of the recognition output counter is 1 or more (step S806: NO), processing is executed to output a type identification command corresponding to the value of the recognition output counter after decrementing by 1 (steps S803 and S804).

[0269] On the other hand, if the value of the recognition output counter is "0" (step S806: YES), an identification end command output process is executed (step S807). The identification end command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the identification end command output process, the output state of the ninth signal is switched to HI level at the timing when output of the identification end command is started so that the management CPU 112 recognizes that a new command has been transmitted. In addition, the output period of the identification end command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identification end command and the output state of the ninth signal. By receiving the identification end command, the management CPU 112 determines that the process of storing information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence memory 116 has been completed.

[0270] Next, the management processing executed by the management CPU 112 will be described with reference to the flowchart in Fig. 23. The management processing is started when the supply of operating power to the management CPU 112 is started. The processing speed of the management CPU 112 is configured to be faster than the processing speed of the main CPU 63, and the combination of processing from step S908 onwards in the management processing is executed 16 or more times from the time one timer interrupt processing (Fig. 11) is started in the main CPU 63 until the next timer interrupt processing (Fig. 11) is started.

[0271] First, it is determined whether or not an identification start command has been received from the main CPU 63 (step S901). If an identification start command has not been received (step S901: NO), a setting update recognition process is executed (step S902), and then the process returns to step S901. In the setting update recognition process, the details of which will be described later, when a new setting is made to the setting status of the pachinko machine 10 in the main CPU 63, a process corresponding to that setting is executed.

[0272] When an identification start command is received from the main CPU 63 (step S901: YES), the value of a setting target counter provided in the control RAM 114 is cleared to "0" (step S903). The setting target counter is a counter that allows the control CPU 112 to identify the type of buffers 122a to 122n for which a signal type is to be set. The first buffer 122a is the first to be set as a signal type, and thereafter the nth buffer and then the (n+1)th buffer are set as signal type settings.

[0273] Thereafter, on the condition that a type identification command has been received from the main CPU 63 (step S904: YES), a correspondence setting process is executed (step S905). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter in the control RAM 114, among the first to fourteenth correspondence areas 123a to 123n of the correspondence memory 116. Thereafter, the value of the setting target counter in the control RAM 114 is incremented by 1 (step S906).

[0274] If a negative determination is made in step S904, or if the processing of step S906 is executed, it is determined (step S907) whether or not an identification end command has been received from the main CPU 63. If an identification end command has not been received (step S907: NO), the process returns to step S904, and the processing of steps S905 and S906 is executed again on the condition that a new type identification command is received from the main CPU 63 (step S904: YES).

[0275] If an identification end command has been received from the main CPU 63 (step S907: YES), the processes of steps S908 to S910 are repeatedly executed. In step S908, details of which will be described later are executed, a history setting process is executed for storing history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S909, details of which will be described later are executed, a display output process is executed for calculating various parameters using the history information stored in the history memory 117 and notifying the first to third notification display devices 69a to 69c of the calculation results. In step S910, details of which will be described later are executed, an external output process is executed for outputting the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d.

[0276] Fig. 24 is a time chart showing how information on the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence memory 116. Fig. 24(a) shows a period during which commands are output from the main CPU 63 to the control CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Fig. 24(b) shows a period during which the output state of the ninth signal is at HI level, Fig. 24(c) shows an execution period of an identification state during which processing is executed to identify the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n, and Fig. 24(d) shows the timing at which the correspondence setting process (step S905) is executed by the control CPU 112.

[0277] When the supply of operating power to the primary CPU 63 and the control CPU 112 begins, output of the identification start command using the first to eighth signals begins at time t1, as shown in FIG. 24(a). Also, at time t1, the output state of the ninth signal is changed from low to high, as shown in FIG. 24(b). Thereafter, at time t2, while the output of the identification start command is continuing, the output state of the ninth signal is changed from high to low, as shown in FIG. 24(b). The control CPU 112 determines that a command has been sent from the primary CPU 63 by confirming that the output state of the ninth signal has changed from high to low, and determines the content of the command received from the primary CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification start command has been received, the control CPU 112 makes a positive determination in step S901 of the control process (FIG. 23), thereby entering the identification state. Then, at time t3, output of the identification start command is stopped, as shown in FIG. 24(a).

[0278] Then, at timing t4, as shown in FIG. 24(a), output of the first type identification command using signals 1 to 8 begins. Also, at timing t4, as shown in FIG. 24(b), the output state of signal 9 changes from LOW to HI at timing t4. Then, at timing t5, while the type identification command continues to be output, the output state of signal 9 changes from HI to LOW at timing t5, as shown in FIG. 24(b). The management CPU 112 determines that a command has been sent from the main CPU 63 by confirming that the output state of signal 9 has changed from HI to LOW, and identifies the content of the command received from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command has been received, the management CPU 112 executes a correspondence setting process at timing t5, as shown in FIG. 24(d). In this correspondence setting process, information indicating the general winning slot 31 and the number of prize balls therein are stored in the first correspondence area 123a of the correspondence memory 116. After that, at timing t6, the output of the type identification command is stopped as shown in FIG. 24(a).

[0279] Thereafter, from timing t7 to timing t9, from timing t10 ​​to timing t12, from timing t13 to timing t15, and from timing t16 to timing t18, similar to timing t4 to timing t6, the correspondence setting process corresponding to the type identification command output from the main CPU 63 is executed by the management CPU 112. In this case, from timing t16 to timing t18, the correspondence setting process corresponding to the 14th type identification command is completed.

[0280] Then, at timing t19, output of the identification end command using the first to eighth signals is started as shown in FIG. 24(a). Also, at timing t19, the output state of the ninth signal is changed from low level to high level as shown in FIG. 24(b). Then, at timing t20, while the output of the identification end command is continuing, the output state of the ninth signal is changed from high level to low level as shown in FIG. 24(b). The control side CPU 112 determines that a command has been sent from the primary side CPU 63 by confirming that the output state of the ninth signal has changed from high level to low level, and determines the content of the command received from the primary side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification end command has been received, the identification state of the control side CPU 112 ends at timing t20 as shown in FIG. 24(c). Then, at timing t21, output of the identification end command is stopped as shown in FIG. 24(a).

[0281] As described above, the configuration allows the management CPU 112 to recognize whether a command is being output using the 9th signal, so that the management CPU 112 can clearly recognize that a command is being output even when the command is output using the 1st to 8th signals (i.e., the 1st to 8th signal paths) used to instruct the management CPU 112 when to store history information.

[0282] Next, a description will be given of a processing configuration for storing history information in the history memory 117. Fig. 25 is a flowchart showing the management output processing executed by the main CPU 63. The management output processing is executed in step S319 in the timer interrupt processing (Fig. 11).

[0283] First, "11" is set to the management target counter provided in the main RAM 65 (step S1001). The management target counter is a counter that allows the main CPU 63 to determine whether there are any management targets that have not yet been identified as targets for determining whether or not the signal output status to the management CPU 112 should be changed in this management output process, and to determine whether or not the signal output status to the management CPU 112 should be changed for each management target. In one management output process, the management targets for which the main CPU 63 determines whether or not the signal output status to the management CPU 112 should be changed are the seven ball entry detection sensors 42a-48a, whether or not the open / close execution mode is being executed, whether or not the high frequency support mode is being executed, whether or not the front door frame 14 is being opened / closed, and whether or not a game round has started, a total of 11 targets. Therefore, the management target counter is initially set to "11".

[0284] Then, it is determined whether the signal output state to the management side CPU 112 for the management object corresponding to the current value of the management object counter is at HI level (step S1002). If it is not at HI level (step S1002: NO), it is determined whether the value of the management object counter is 5 or more, thereby identifying which of the seven ball entry detection sensors 42a to 48a is the management object corresponding to the value of the management object counter (step S1003).

[0285] If the determination in step S1003 is affirmative, it is determined whether or not "1" is set to the output flag of the main RAM 65 corresponding to the value of the managed counter (step S1004). Specifically, if the value of the managed counter is "11" and corresponds to the first winning opening detection sensor 42a, it is determined whether or not "1" is set to the first output flag, if the value of the managed counter is "10" and corresponds to the second winning opening detection sensor 43a, it is determined whether or not "1" is set to the second output flag, if the value of the managed counter is "9" and corresponds to the third winning opening detection sensor 44a, it is determined whether or not "1" is set to the third output flag, if the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is determined whether or not "1" is set to the If the value of the managed counter is "7" and corresponds to the first actuation port detection sensor 46a, it determines whether the fourth output flag is set to "1"; if the value of the managed counter is "6" and corresponds to the second actuation port detection sensor 47a, it determines whether the sixth output flag is set to "1"; and if the value of the managed counter is "5" and corresponds to the outlet 24a, it determines whether the seventh output flag is set to "1." As already explained, these first to seventh output flags are set to "1" in the ball entry detection process (Figure 15).

[0286] If the output flag corresponding to the value of the managed counter is set to "1" (step S1004: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HI level (step S1005), and then the output flag corresponding to the value of the managed counter is cleared to "0" (step S1006).

[0287] If a negative determination is made in step S1003, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed counter to a HI level (step S1007). Specifically, if the value of the managed counter is "4," it is determined whether a transition to the open / close execution mode has occurred; if the value of the managed counter is "3," it is determined whether a transition to the high-frequency support mode has occurred; if the value of the managed counter is "2," it is determined whether the front door frame 14 has entered an open state; and if the value of the managed counter is "1," it is determined whether an eleventh output flag is set to "1" to determine whether a game round has started. If a positive determination is made in step S1007, the output state of the signal corresponding to the value of the managed counter is set to a HI level (step S1008). Note that, if the processing of step S1008 is executed when the value of the managed counter is "1," the eleventh output flag is cleared to "0."

[0288] If the determination in step S1002 is affirmative, it is determined whether or not an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to a LOW level (step S1009). Specifically, if the value of the counter to be managed is 5 or greater or "1" and the current management target is one of the ball entry detection sensors 42a-48a or the start of a game round, it is determined whether or not a HI output duration (specifically, 10 milliseconds) has elapsed since the output state of the signal corresponding to the value of the counter to be managed, among the first to seventh signals and the eleventh signal, was switched from a LOW level to a HI level. This HI output duration is set in the management-side CPU 112 to a period longer than the longest processing interval of the history setting process (step S908) of the management process (FIG. 23), and is a period that allows the management-side CPU 112 to reliably identify the output state of the signal that switched from a LOW level to a HI level. Furthermore, if the value of the managed counter is "4" and the current managed object is in the open / close execution mode, it is determined whether the open / close execution mode has ended, if the value of the managed counter is "3" and the current managed object is in the high-frequency support mode, it is determined whether the high-frequency support mode has ended, and if the value of the managed counter is "2" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. If an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed object counter to a LOW level (step S1009: YES), the output state of the signal corresponding to the value of the managed object counter is set to a LOW level (step S1010).

[0289] If a negative determination is made in step S1004, if the processing of step S1006 is executed, if a negative determination is made in step S1007, if the processing of step S1008 is executed, if a negative determination is made in step S1009, or if the processing of step S1010 is executed, the value of the managed object counter in the main RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the managed object counter after the decrement by 1 is "0" (step S1012). If the value of the managed object counter is 1 or greater (step S1012: NO), the processing from step S1002 onwards is executed for the managed object corresponding to the new value of the managed object counter.

[0290] Next, the history setting process executed by the management-side CPU 112 will be described with reference to the flowchart of Fig. 26. The history setting process is executed in step S908 of the management process (Fig. 23).

[0291] First, the number of buffers to be checked by the management CPU 112 among the first to fourteenth buffers 122a to 122n is set in a confirmation target counter provided in the management RAM 114 (step S1101). Specifically, the number of correspondence relationship areas in which information other than information indicating that the correspondence relationship areas are blank is identified among the first to fourteenth correspondence relationship areas 123a to 123n in the correspondence relationship memory 116 is stored, and the information of the identified number is set in the confirmation target counter. As already explained, in this pachinko machine 10, information other than information indicating that the correspondence relationship areas are blank is stored in the first to eleventh correspondence relationship areas 123a to 123k, and therefore, in step S1101, "11" is set in the confirmation target counter.

[0292] Thereafter, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current value of the counter to be checked, among the first to fourteenth buffers 122a to 122n, has been switched from LOW to HIGH (step S1102) by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked has changed from "0" to "1." Note that when the value of the counter to be checked is "n," the nth buffers 122a to 122n are the target for checking the numerical information. For example, if the value of the counter to be checked is "11," the eleventh buffer 122k is the target for checking the numerical information, and if the value of the counter to be checked is "5," the fifth buffer 122e is the target for checking the numerical information.

[0293] If the determination in step S1102 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S1103). Then, a write process to the history memory 117 is executed (step S1104). In this write process, the pointer information in the history area 124 currently being written is identified by referencing the pointer area 126 of the history memory 117, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written. Furthermore, correspondence information is read from the correspondence areas 123a to 123n corresponding to the current counter value to be checked, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information being written. Furthermore, if the correspondence information is any of information indicating the open / close execution mode, information indicating the high-frequency support mode, and information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information being written. If the value of the counter to be checked is "n," the n-th correspondence area 123a to 123n is the target for reading out the correspondence information. For example, if the value of the counter to be checked is "11," the eleventh correspondence area 123k is the target for reading out the correspondence information, and if the value of the counter to be checked is "5," the fifth correspondence area 123e is the target for reading out the correspondence information.

[0294] By executing the write process as described above, if the value of the counter to be checked is any of the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, second operating port 34, and number of games played, a combination of RTC information and correspondence information indicating that it is any of the outlet 24a, general winning port 31, special electric winning device 32, first operating port 33, second operating port 34, and number of games played is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Also, if the value of the counter to be checked is any of the opening / closing execution mode, high-frequency support mode, and front door frame 14, a combination of RTC information, correspondence information indicating that it is any of the opening / closing execution mode, high-frequency support mode, and front door frame 14, and start information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written.

[0295] Thereafter, the target pointer is updated (step S1105). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after incrementing by one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

[0296] If a negative determination is made in step S1102, or if the processing of step S1105 is executed, it is determined whether or not correspondence information for which it should be confirmed whether the signal output has been switched to a LOW level is stored in the correspondence areas 123a to 123n corresponding to the current value of the counter to be confirmed (step S1106). Specifically, if the current value of the counter to be confirmed is "8" to "10", any of information indicating the opening / closing execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14 is stored in the corresponding correspondence areas 123h to 123j, and therefore a positive determination is made in step S1106.

[0297] If the determination in step S1106 is affirmative, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current counter value to be checked among the first to fourteenth buffers 122a to 122n has been switched from HI level to LOW level by checking whether the numerical information stored in the buffer corresponding to the current counter value to be checked has changed from "1" to "0" (step S1107). If the determination in step S1107 is affirmative, RTC information is read (step S1108) as in step S1103, and a write process to the history memory 117 is executed (step S1109). In this write process, the RTC information read in step S1108 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, correspondence information is read from the correspondence area 123a to 123n corresponding to the current counter value to be checked, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. In addition, not only the correspondence information but also the termination information is written to the history information storage area 125 corresponding to the pointer information to be written. By executing the write process in this manner, when the value of the counter to be checked is either the open / close execution mode, the high frequency support mode, or the front door frame 14, a combination of the RTC information, the correspondence information indicating either the open / close execution mode, the high frequency support mode, or the front door frame 14, and the termination information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Thereafter, the target pointer update process is executed in the same manner as in step S1105 (step S1110).

[0298] If a negative determination is made in step S1106, if a negative determination is made in step S1107, or if the processing of step S1110 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the confirmation target counter after decrementing by 1 is "0" (step S1112). If the value of the confirmation target counter is 1 or greater (step S1112: NO), the processing of step S1102 and subsequent steps is executed for the confirmation target corresponding to the new value of the confirmation target counter.

[0299] Next, the manner in which history information is stored in history memory 117 will be described with reference to the time chart of Fig. 27. Fig. 27(a) shows a period in which a HI level signal is input to any of the first to seventh and eleventh buffers 122a to 122g and 122k, Fig. 27(b) shows a period in which a HI level signal is input to eighth buffer 122h, Fig. 27(c) shows a period in which a HI level signal is input to ninth buffer 122i, Fig. 27(d) shows a period in which a HI level signal is input to tenth buffer 122j, and Fig. 27(e) shows the timing of writing history information to history memory 117.

[0300] At time t1, the output state of a signal input to one of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from LOW to HI at time t1, as shown in FIG. 27(a). Therefore, at time t1, history information is written to history memory 117, as shown in FIG. 27(e). Thereafter, at time t2, the signal that was switched to HI at time t1, as shown in FIG. 27(a), is switched to LOW. However, since this signal is input to one of the first to seventh and eleventh buffers 122a to 122g, 122k, and the switching to LOW does not result in history information being stored, no writing of history information is executed at time t2, as shown in FIG. 27(e).

[0301] Thereafter, at times t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to any of the first to seventh and eleventh buffers 122a to 122g and 122k is switched from LOW to HIGH, as shown in Fig. 27(a). Therefore, at each of these times, history information is written, as shown in Fig. 27(e).

[0302] As shown in FIG. 27(b), the output state of the signal input to the eighth buffer 122h is HI level from time t4 to time t7. This eighth buffer 122h corresponds to whether or not the open / close execution mode is occurring. Therefore, as shown in FIG. 27(e), history information is written at time t4, when the output state of the signal input to the eighth buffer 122h switches to HI level, and at time t7, when the output state of the signal switches to LOW level. In this case, the history information written at time t4 includes start information, and the history information written at time t7 includes end information. This makes it possible to determine the execution period of the open / close execution mode by checking the history information in the history memory 117.

[0303] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is during the opening / closing execution mode. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 is during the opening / closing execution mode by comparing the RTC information.

[0304] As shown in FIG. 27(c), the output state of the signal input to the ninth buffer 122i is HI level from time t8 to time t11. This ninth buffer 122i corresponds to whether or not the high frequency support mode is active. Therefore, as shown in FIG. 27(e), history information is written at time t8, when the output state of the signal input to the ninth buffer 122i switches to HI level, and at time t11, when the output state of the signal switches to LOW level. In this case, the history information written at time t8 includes start information, and the history information written at time t11 includes end information. This makes it possible to determine the execution period of the high frequency support mode by checking the history information in the history memory 117.

[0305] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 is from the high frequency support mode. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 is from the high frequency support mode by comparing the RTC information.

[0306] As shown in FIG. 27(d), the output state of the signal input to the tenth buffer 122j is HI level from time t12 to time t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in FIG. 27(e), history information is written at time t12, when the output state of the signal input to the tenth buffer 122j switches to HI level, and at time t15, when the output state of the signal switches to LOW level. In this case, the history information written at time t12 includes start information, and the history information written at time t15 includes end information. This makes it possible to determine the period during which the front door frame 14 is open by checking the history information in the history memory 117.

[0307] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open by comparing the RTC information.

[0308] Next, we will explain the output process of the setting value update signal that is executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Figure 28 is a flowchart showing the output process of the setting value update signal that is executed by the main CPU 63. The output process of the setting value update signal is executed in step S119 in the main processing (Figure 9).

[0309] A value corresponding to the currently set setting value of the pachinko machine 10 is set in a pulse number counter provided in the main RAM 65 (step S1201). Specifically, the value of the setting value counter in the main RAM 65 is set in the pulse number counter. Thereafter, it is determined whether or not the setting value update signal directed to the management CPU 112 is at HI level (step S1202). As already explained, the setting value update signal is input to the fifteenth buffer 122o of the input port 121 in the management IC 66. Here, the output process of the setting value update signal is executed at a timing prior to the recognition process, which is a process for having the management CPU 112 identify the types of signals input to the first to fourteenth buffers 122a to 122n of the input port 121 in the main process (FIG. 9). In contrast, since the setting value update signal is set in the management IC 66 during the design stage of the pachinko machine 10 to be input to the 15th buffer 122o, even if the output process of the setting value update signal is executed before the recognition process, it is possible for the management CPU 112 to identify that the signal input to the 15th buffer 122o is a setting value update signal.

[0310] If the determination in step S1202 is negative, the value of a LOW level counter provided in the main RAM 65 is decremented by 1 (step S1203), and it is determined whether the value of the LOW level counter after decrementing by 1 is "0" (step S1204). The LOW level counter is a counter used by the main CPU 63 to determine whether the setting value update signal has been maintained at a LOW level for a predetermined period while multiple pulses at which the setting value update signal is at a HI level are output. If the value of the LOW level counter is "0" (step S1204: YES), this means that it is time to set the setting value update signal to a HI level, and so the setting value update signal is set to a HI level (step S1205).

[0311] Thereafter, "20" is set in the HI level counter provided in the main RAM 65 (step S1206). The HI level counter is a counter used by the main CPU 63 to specify the period during which the setting value update signal is maintained at a HI level. The value set in the HI level counter is decremented by 1 approximately every 10 microseconds, so that the setting value update signal is maintained at a HI level for 200 microseconds when one pulse is output. This period during which the HI level is maintained is long enough for the control CPU 112 to specify that the setting value update signal has been changed from a LOW level to a HI level.

[0312] If the set value update signal is at HI level (step S1202: YES), the value of the HI level counter in the main RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI level counter after decrementing by 1 is "0" (step S1208). If the value of the HI level counter is "0" (step S1208: YES), this means that it is time to set the set value update signal to LOW level, so the set value update signal is set to LOW level (step S1209).

[0313] Thereafter, the value of the pulse number counter in the main RAM 65 is decremented by 1 (step S1210), and it is determined whether the value of the pulse number counter after decrementing by 1 is "0" (step S1211). If the value of the pulse number counter is not "0" (step S1211: NO), this means that the output of pulse signals in response to the setting value update signal for the number of pulses corresponding to the currently set setting value of the pachinko machine 10 has not been completed, and therefore "20" is set in the LOW level counter in the main RAM 65 (step S1212). The value set in the LOW level counter is decremented by 1 at approximately 10 microsecond intervals, so that the LOW level is maintained for 200 microseconds between multiple pulse outputs in response to the setting value update signal. This period of time during which the LOW level is maintained is sufficient for the management CPU 112 to determine that the setting value update signal has been changed from HI level to LOW level.

[0314] If the value of the pulse number counter is "0" (step S1211: YES), this means that the output of pulse signals by the setting value update signal for the number of times corresponding to the currently set setting value of the pachinko machine 10 has been completed, and therefore output processing of a setting value identification end command is executed (step S1213). The setting value identification end command is a command for making the management CPU 112 recognize that the output of the setting value update signal for making the management CPU 112 recognize the currently set setting value of the pachinko machine 10 has been completed. When outputting the setting value identification end command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used, just like the identification start command, type identification command, and identification end command. However, the signal pattern of the setting value identification end command is different from that of the identification start command, type identification command, and identification end command.

[0315] As described above, in the setting value update signal output process, pulse signals of the setting value update signal, the number of which corresponds to the value of the setting value of the pachinko machine 10 that was set when the current supply of operating power began, are output to the management IC 66. The management side CPU 112 executes the setting update recognition process to grasp the number of pulse signals of the setting value update signal, and based on that, grasps the setting value of the pachinko machine 10 that was set this time.

[0316] 29 is a flowchart showing the setting update recognition process executed by the management CPU 112. The setting update recognition process is executed in step S902 of the management process (FIG. 23).

[0317] It is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from a LOW level to a HIGH level (step S1301). If a positive determination is made in step S1301, the value of a setting value grasp counter provided in the management-side RAM 114 is set to "1" (step S1302). The setting value grasp counter is a counter for specifying the setting value of the pachinko machine 10 by the management-side CPU 112; for example, a value of "1" on the setting value grasp counter means "setting 1," and a value of "6" on the setting value grasp counter means "setting 6."

[0318] Thereafter, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HI level again (step S1303). If the determination in step S1303 is affirmative, the value of the setting value grasp counter in the management-side RAM 114 is incremented by 1 (step S1304). As a result, the setting value of the pachinko machine 10 identified in the management-side CPU 112 is increased by one level.

[0319] If a negative determination is made in step S1303 or if the processing of step S1304 is executed, it is determined whether or not a set value identification end command has been received from the main CPU 63 based on the input states of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, the processing returns to step S1303.

[0320] If the determination in step S1305 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S1306). Then, a write process to the history memory 117 is executed (step S1307). In this write process, the pointer information in the history area 124 that is the current write target is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1306 is written to the history information storage area 125 of the history area 124 that corresponds to the pointer information that is the write target. In addition, both information for identifying that it is a setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 that corresponds to the pointer information that is the write target. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

[0321] Thereafter, the target pointer is updated (step S1308). In this update, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after incrementing by one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after incrementing by one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

[0322] As a result of the setting update recognition process being executed as described above, when the setting state of the pachinko machine 10 is newly set, the fact that the setting was made, the date and time when the setting was made, and the combination of setting values ​​when the setting was made are stored as history information in the history area 124. As a result, by reading and analyzing the information stored in the history memory 117 using an external device connected to the reading terminal 68d, it becomes possible to know the date and time when the setting state of the pachinko machine 10 was newly set and the contents of the setting values ​​when the setting was made.

[0323] Here, even if the setting state of the pachinko machine 10 is newly set, the information stored in the history memory 117 is maintained as is. This makes it possible to prevent the history information in the history memory 117 from being erased even if the setting state of the pachinko machine 10 is newly set, and various parameters described below are calculated using history information that exists across the timing of changing the setting state of the pachinko machine 10. In this case, since the date and time when the setting state of the pachinko machine 10 was newly set is stored in the history memory 117 as described above, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters for the period after the setting state of the pachinko machine 10 was newly set and during which the setting state was maintained.

[0324] Next, the display output process executed by the management-side CPU 112 will be described with reference to the flowchart of Fig. 30. The display output process is executed in step S909 of the management process (Fig. 23).

[0325] First, it is determined whether it is time for calculation (step S1401). If 51 seconds have passed since the supply of operating power to the management CPU 112 started, or if 51 seconds have passed since the previous affirmative determination in step S1401, a positive determination is made in step S1401. If a positive determination is made in step S1401, the number of balls that enter during normal times is calculated (step S1402). Specifically, the number of balls that enter the outlet 24a is calculated by first counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the ball is the outlet 24a. In addition, the number of balls that enter the general winning opening 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the ball is the general winning opening 31. In addition, the number of balls that have entered the special power winning device 32 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the device is the special power winning device 32 is stored in the history area 124 of the history memory 117. In addition, the number of balls that have entered the first operating port 33 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the device is the first operating port 33 is stored in the history area 124 of the history memory 117. In addition, the number of balls that have entered the second operating port 34 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the device is the second operating port 34 is stored in the history area 124 of the history memory 117.

[0326] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating that it is the front door frame 14 in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating that it is the front door frame 14, the number of balls entering each of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 is in the open state is calculated (step S1403). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating that it is the front door frame 14 in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating that it is the front door frame 14 is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire consecutive pointer information, if there are multiple sections between the history information storage area 125 in which correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which correspondence information and end information indicating that it is the front door frame 14 are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which correspondence information and start information indicating that it is the front door frame 14 are stored, but the history information storage area 125 in which RTC information corresponding to a time later than that history information storage area 125 is stored does not store correspondence information and end information indicating that it is the front door frame 14, all of the history information in the history information storage area 125 in which RTC information corresponding to a time later than that of the history information storage area 125 in which correspondence information and start information indicating that it is the front door frame 14 is stored is treated as if the front door frame 14 is in an open state.

[0327] Thereafter, various parameters are calculated using the calculation results of steps S1402 and S1403 (step S1404). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1403, is subtracted from the number of balls that entered the outlet 24a calculated in step S1402. Then, the following first to eighth parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1402 and the number of balls that entered the outlet 24a calculated in step S1403 is set as the number of balls that entered the outlet 24a, the difference between the number of balls that entered the general winning port 31 calculated in step S1402 and the number of balls that entered the general winning port 31 calculated in step S1403 is set as the number of balls that entered the outlet 24a, and the difference between the number of balls that entered the general winning port 31 calculated in step S1402 and the number of balls that entered the special winning device 32 calculated in step S1402 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1403 is designated as the number of balls that enter K3, the difference in the number of balls that enter the first operating port 33 calculated in step S1402 from the number of balls that enter the first operating port 33 calculated in step S1403 is designated as the number of balls that enter K4, and the difference in the number of balls that enter the second operating port 34 calculated in step S1402 from the number of balls that enter the second operating port 34 calculated in step S1403 is designated as the number of balls that enter K5. First parameter: Total number of game balls paid out (K2 x "Number of prize balls for winning at the general winning port 31" + K3 x "Number of prize balls for winning at the special winning device 32" + K4 x "Number of prize balls for winning at the first operating port 33" + K5 x "Number of prize balls for winning at the second operating port 34") / Ratio of the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D1"). Second parameter: The ratio of the total number of game balls entering the general winning slot 31 (K2) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) Third parameter: The ratio of the total number of game balls entering the special winning device 32 (K3) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) Fourth parameter: The ratio of the total number of game balls entering the first operating port 33 (K4) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D2") Fifth parameter: The ratio of the total number of game balls entering the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D3") Sixth parameter: D1 - (D2 x "Number of winning balls for winning into the first operating port 33" + D3 x "Number of winning balls for winning into the second operating port 34") Seventh parameter: (K3 × "Number of prize balls for winning at the special electric winning device 32" + K5 × "Number of prize balls for winning at the second operating port 34") / Total number of game balls paid out (K2 × "Number of prize balls for winning at the general winning port 31" + K3 × "Number of prize balls for winning at the special electric winning device 32" + K4 × "Number of prize balls for winning at the first operating port 33" + K5 × "Number of prize balls for winning at the second operating port 34") ratio Eighth parameter: K3 × "Number of prize balls for winning the special electric winning device 32" / Total number of game balls paid out (K2 × "Number of prize balls for winning the general winning port 31" + K3 × "Number of prize balls for winning the special electric winning device 32" + K4 × "Number of prize balls for winning the first operating port 33" + K5 × "Number of prize balls for winning the second operating port 34") ratio In step S1404, the first to eighth parameters, which are the calculation results, are stored in a normal time storage area in calculation result memory 131. The first to eighth parameters stored in the normal time storage area are held until the next time step S1404 is executed. In other words, when the next time step S1404 is executed and the first to eighth parameters are calculated, the newly calculated first to eighth parameters are stored in the normal time storage area, overwriting the previous calculation results of the first to eighth parameters that had been stored in the normal time storage area.

[0328] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the opening and closing execution mode, the number of balls entering each of the outlet 24a, the general winning port 31, the special power winning device 32, the first operating port 33, and the second operating port 34 that occurred in the opening and closing execution mode is calculated (step S1405). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the opening and closing execution mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections in the entire consecutive pointer information between the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode and the history information storage area 125 storing the correspondence relationship information and end information indicating the opening and closing execution mode, the total number of balls entered for each section is calculated. Furthermore, if there is a history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode, but the history information storage area 125 storing the RTC information corresponding to a time later than the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode does not store the correspondence relationship information and end information indicating the opening and closing execution mode, all history information in the history information storage area 125 storing the RTC information corresponding to a time later than the history information storage area 125 storing the correspondence relationship information and start information indicating the opening and closing execution mode is treated as being in the opening and closing execution mode.

[0329] Thereafter, the number of balls that entered each of the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state during the period of the opening / closing execution mode identified in step S1405 is calculated (step S1406). The method for calculating these numbers of balls is the same as in step S1403, except that it is based on the period of the opening / closing execution mode identified in step S1405.

[0330] Thereafter, various parameters are calculated using the calculation results of steps S1405 and S1406 (step S1407). Specifically, first, the number of balls that entered the outlet 24a while the front door frame 14 was open, calculated in step S1406, is subtracted from the number of balls that entered the outlet 24a calculated in step S1405. Then, the following 11th to 18th parameters are calculated using the number of balls that entered the outlet 24a after the subtraction. The difference between the number of balls that entered the outlet 24a calculated in step S1405 and the number of balls that entered the outlet 24a calculated in step S1406 is set as the number of balls that entered the outlet 24a, the difference between the number of balls that entered the general winning port 31 calculated in step S1405 and the number of balls that entered the general winning port 31 calculated in step S1406 is set as the number of balls that entered the outlet 24a, and the difference between the number of balls that entered the general winning port 31 calculated in step S1405 and the number of balls that entered the special winning device 32 calculated in step S1405 is set as the number of balls that entered the special winning device 32. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1406 is designated as the number of balls that enter K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1405 from the number of balls that enter the first operating port 33 calculated in step S1406 is designated as the number of balls that enter K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1405 from the number of balls that enter the second operating port 34 calculated in step S1406 is designated as the number of balls that enter K15. 11th parameter: Total number of game balls paid out (K12 × "number of prize balls for winning at the general winning port 31" + K13 × "number of prize balls for winning at the special winning device 32" + K14 × "number of prize balls for winning at the first operating port 33" + K15 × "number of prize balls for winning at the second operating port 34") / ratio of the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D11"). 12th parameter: The ratio of the total number of game balls entering the general winning slot 31 (K12) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 13th parameter: The ratio of the total number of game balls entering the special winning device 32 (K13) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 14th parameter: The ratio of the total number of game balls entering the first operating port 33 (K14) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D12") 15th parameter: The ratio of the total number of game balls entering the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13") 16th parameter: D11 - (D12 x "Number of winning balls for winning into the first operating port 33" + D13 x "Number of winning balls for winning into the second operating port 34") 17th parameter: (K13 × "Number of prize balls for winning the special electric winning device 32" + K15 × "Number of prize balls for winning the second operating port 34") / Total number of game balls paid out (K12 × "Number of prize balls for winning the general winning port 31" + K13 × "Number of prize balls for winning the special electric winning device 32" + K14 × "Number of prize balls for winning the first operating port 33" + K15 × "Number of prize balls for winning the second operating port 34") ratio 18th parameter: K13 × "Number of prize balls for winning the special electric winning device 32" / Total number of game balls paid out (K12 × "Number of prize balls for winning the general winning port 31" + K13 × "Number of prize balls for winning the special electric winning device 32" + K14 × "Number of prize balls for winning the first operating port 33" + K15 × "Number of prize balls for winning the second operating port 34") ratio In step S1407, the 11th to 18th parameters, which are the calculation results, are stored in a storage area for the open / close execution mode in the calculation result memory 131. The 11th to 18th parameters stored in the storage area for the open / close execution mode are held until the next time step S1407 is executed. In other words, when the next time step S1407 is executed and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the storage area for the open / close execution mode, overwriting the previous calculation results of the 11th to 18th parameters that had been stored in the storage area for the open / close execution mode.

[0331] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high frequency support mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the high frequency support mode, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, and the second operating hole 34 that occurred in the high frequency support mode situation is calculated (step S1408). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high frequency support mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the high frequency support mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections within the entire set of consecutive pointer information between history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode and history information storage area 125 storing correspondence relationship information and end information indicating the high frequency support mode, the total number of balls scored for each section is calculated. Furthermore, if there is a history information storage a...

Claims

[Claim 1] a history storage execution means for storing, when a predetermined event occurs as a result of a game being played, history information of the game corresponding to the event in the history storage means; information deriving means for deriving behavior information corresponding to a game result by utilizing the history information stored in the history storage means; a behavior information storage means for storing the behavior information derived by the information derivation means; a mode information display control means for controlling the display of the mode information stored in the mode information storage means on the information display means; a predetermined correspondence display control means for controlling, based on the occurrence of a predetermined display trigger that occurs before a new display corresponding to the aspect information is started, a predetermined correspondence display corresponding to the occurrence of the predetermined display trigger on the information display means before the new display corresponding to the aspect information is started; a setting means for setting a set value corresponding to the advantage of a player; a situation generating means for generating a setting possible situation in which the setting means can set the setting value; Equipped with the aspect information storage means includes a plurality of specific storage areas so as to be able to store each of the plurality of aspect information; the aspect information display control means controls the information display means to sequentially execute displays corresponding to the plurality of aspect information stored in the plurality of specific storage areas in accordance with a predetermined display order, and when the information display means is caused to execute displays corresponding to the aspect information after the predetermined corresponding displays have been executed by the information display means, the information display means starts with a display corresponding to the aspect information corresponding to the first order in the predetermined display order, The gaming machine is equipped with a control means for executing various processes, The control means an area processing execution means for executing an area processing which is a process using a program stored in a storage area within a predetermined address range in the program storage means; an out-of-area processing execution means for executing out-of-area processing, which is processing using a program stored in a storage area in an address range outside the predetermined address range in the program storage means; Equipped with the intra-area processing execution means includes means for executing, as the intra-area processing, a process that can identify whether the setting value set as the target for use is normal or not; This gaming machine is an intra-area corresponding storage area into which information can be written and read when the intra-area process is executed, and into which information can be read but not written when the extra-area process is executed; an outside-area corresponding storage area into which information can be written and read when the outside-area processing is executed, and into which information can be read but not written when the inside-area processing is executed; Equipped with the in-area process execution means is configured to be able to clear predetermined information in the in-area corresponding storage area when the setting possible state is reached, the intra-area corresponding storage area has a work area for intra-area processing and a stack area for intra-area processing, A gaming machine characterized in that an area for storing information on the setting values ​​set by the setting means is provided in a work area for processing within the area.

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