Encoder, computing device and encoding method

Abstract

To provide an encoder capable of improving efficiency, a calculation device, and a coding method.SOLUTION: According to an embodiment, an encoder includes a first element part and a control unit. The first element part includes first to ninth quantum bits. The control unit executes a second quantum bit gate on the second quantum bit and the first quantum bit and a second quantum bit gate on the fourth quantum bit and the third quantum bit, and then a second quantum bit gate on the third quantum bit and the second quantum bit. The control unit executes a second quantum bit gate on the sixth quantum bit and the seventh quantum bit and the second quantum bit gate on the eighth quantum bit and the ninth quantum bit, and then a second quantum bit gate on the seventh quantum bit and the eighth quantum bit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to an encoder, a computing device and an encoding method. [Background technology]

[0002] For example, quantum bits are encoded in computing devices, etc., and there is a need to improve the efficiency of encoding. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] A. Fowler et al., Phys. Rev. A86, 032324 (2012). Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention provide an encoder, a computing device and an encoding method that can improve efficiency. [Means for solving the problem]

[0005] According to an embodiment of the present invention, an encoder includes a first element unit and a control unit. The first element unit includes a first qubit, a second qubit coupleable with the first qubit, a third qubit coupleable with the second qubit, a fourth qubit coupleable with the third qubit, a fifth qubit coupleable with the fourth qubit, a sixth qubit coupleable with the fifth qubit, a seventh qubit coupleable with the sixth qubit, an eighth qubit coupleable with the seventh qubit, and a ninth qubit coupleable with the eighth qubit. The control unit is capable of performing first control. The first control includes encoding a surface code with a code distance of 3 by executing a two-qubit gate for the second qubit and the first qubit, executing a two-qubit gate for the third qubit and the second qubit, executing a two-qubit gate for the fourth qubit and the third qubit, executing a two-qubit gate for the fourth qubit and the third qubit, executing a two-qubit gate for the fourth qubit and the fifth qubit, executing a two-qubit gate for the sixth qubit and the fifth qubit, executing a two-qubit gate for the sixth qubit and the seventh qubit, executing a two-qubit gate for the seventh qubit and the eighth qubit, and executing a two-qubit gate for the eighth qubit and the ninth qubit. In the first control, the control unit executes the two-qubit gate for the third qubit and the second qubit after the two-qubit gate for the second qubit and the first qubit and the two-qubit gate for the fourth qubit and the third qubit. In the first control, the control unit executes the two-qubit gate for the seventh qubit and the eighth qubit after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram illustrating an encoder according to the first embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating control in the encoder according to the first embodiment. [Figure 3] FIG. 3 is a schematic diagram illustrating an encoder according to the first embodiment. [Figure 4] FIG. 4 is a schematic diagram illustrating control of the encoder according to the first embodiment. [Figure 5] FIG. 5 is a schematic diagram illustrating control of the encoder according to the first embodiment. [Figure 6] FIG. 6 is a schematic diagram illustrating control of the encoder according to the first embodiment. [Figure 7] FIG. 7 is a schematic diagram illustrating control in the encoder according to the first embodiment. [Figure 8] FIG. 8 is a schematic diagram illustrating control in the encoder according to the first embodiment. [Figure 9] FIG. 9 is a schematic diagram illustrating an encoder according to the second embodiment. [Figure 10] FIG. 10 is a schematic diagram illustrating an encoder according to the second embodiment. [Figure 11] FIG. 11 is a flowchart illustrating control in the encoder according to the second embodiment. [Figure 12] FIG. 12 is a schematic diagram illustrating a part of the control in the encoder according to the second embodiment. [Figure 13] 13(a) and 13(b) are schematic diagrams illustrating control in the encoder according to the second embodiment. [Figure 14] FIG. 14 is a schematic diagram illustrating an encoder of a reference example. [Figure 15] FIG. 15 is a graph illustrating the performance of the encoder. [Figure 16] FIG. 16 is a schematic diagram illustrating a computing device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic diagram illustrating an encoder according to the first embodiment. FIG. 2 is a schematic diagram illustrating control in the encoder according to the first embodiment. FIG. 1 illustrates the concept of a surface code with a code distance of 3.

[0009] As shown in FIG. 1, the first element portion 10E includes a first quantum bit Qa1, a second quantum bit Qa2, a third quantum bit Qa3, a fourth quantum bit Qa4, a fifth quantum bit Qa5, a sixth quantum bit Qa6, a seventh quantum bit Qa7, an eighth quantum bit Qa8, and a ninth quantum bit Qa9.

[0010] The second qubit Qa2 can be coupled to the first qubit Qa1. The third qubit Qa3 can be coupled to the second qubit Qa2. The fourth qubit Qa4 can be coupled to the third qubit Qa3. The fifth qubit Qa5 ​​can be coupled to the fourth qubit Qa4. The sixth qubit Qa6 can be coupled to the fifth qubit Qa5. The seventh qubit Qa7 can be coupled to the sixth qubit Qa6. The eighth qubit Qa8 can be coupled to the seventh qubit Qa7. The ninth qubit Qa9 can be coupled to the eighth qubit Qa8.

[0011] 1, an encoder 110 according to the embodiment includes a first element unit 10E and a control unit 70. With respect to the first element unit 10E, the control unit 70 is capable of executing a first control OP1 (see FIG. 2). The first control OP1 is capable of executing a plurality of two-qubit gates.

[0012] 2 illustrates a plurality of two-qubit gates, including, for example, a two-qubit gate G21 for the second qubit Qa2 and the first qubit Qa1, a two-qubit gate G32 for the third qubit Qa3 and the second qubit Qa2, a two-qubit gate G43 for the fourth qubit Qa4 and the third qubit Qa3, a two-qubit gate G45 for the fourth qubit Qa4 and the fifth qubit Qa5, a two-qubit gate G65 for the sixth qubit Qa6 and the fifth qubit Qa5, a two-qubit gate G67 for the sixth qubit Qa6 and the seventh qubit Qa7, a two-qubit gate G78 for the seventh qubit Qa7 and the eighth qubit Qa8, and a two-qubit gate G89 for the eighth qubit Qa8 and the ninth qubit Qa9.

[0013] The first control OP1 includes encoding a surface code of code distance 3 by executing a two-qubit gate G21, a two-qubit gate G32, a two-qubit gate G43, a two-qubit gate G45, a two-qubit gate G65, a two-qubit gate G67, a two-qubit gate G78, and a two-qubit gate G89.

[0014] In the embodiment, the order of these two-qubit gates is set as follows: In the embodiment, in the first control OP1, the control unit 70 executes the two-qubit gate G21 related to the second qubit Qa2 and the first qubit Qa1, and the two-qubit gate G43 related to the fourth qubit Qa4 and the third qubit Qa3, followed by the two-qubit gate G32 related to the third qubit Qa3 and the second qubit Qa2.

[0015] In the first control OP1, the control unit 70 executes a two-qubit gate G78 relating to the seventh quantum bit Qa7 and the eighth quantum bit Qa8 after a two-qubit gate G67 relating to the sixth quantum bit Qa6 and the seventh quantum bit Qa7 and a two-qubit gate G89 relating to the eighth quantum bit Qa8 and the ninth quantum bit Qa9.

[0016] For example, as shown in FIG. 2, the first control OP1 includes a first partial control SP1 and a second partial control SP2. These partial controls correspond to processing steps. The second partial control SP2 is executed after the first partial control SP1. In this example, in the first partial control SP1, a two-qubit gate G21, a two-qubit gate G43, a two-qubit gate G67, and a two-qubit gate G89 are executed. In the first partial control SP1, a two-qubit gate G45 and a two-qubit gate G65 may also be executed.

[0017] As shown in FIG. 2, in the second partial control SP2, the two-qubit gate G32 and the two-qubit gate G78 are executed.

[0018] By executing multiple two-qubit gates in this order, efficient encoding is possible. For example, encoding can be performed using eight controlled NOT gates (hereinafter referred to as CNOT gates). According to the embodiment, an encoder that can improve efficiency can be provided.

[0019] An example of the encoder 110 is described below. FIG. 3 is a schematic diagram illustrating an encoder according to the first embodiment. FIG. 4 is a schematic diagram illustrating control of the encoder according to the first embodiment. In the example in Figure 3, the quantum state of an atom trapped by light is considered a qubit (see Dolev Bluvstein et al., Nature 604, 451 (2022)).

[0020] As shown in Fig. 3, first to ninth quantum bits Qa1 to Qa9 are provided. These quantum bits are, for example, one atom. The atom is, for example, rubidium. 87 It is Rb.

[0021] The control unit 70 irradiates a plurality of atoms (first to ninth quantum bits Qa1 to Qa9) with excitation light 71 (e.g., laser). The control unit 70 can execute a controlled Z gate (hereinafter, referred to as a CZ gate) by irradiating two adjacent atoms with manipulation light 72 (e.g., laser).

[0022] 3 illustrates an example of an operation on the third quantum bit Qa3 and the fourth quantum bit Qa4. In this case, operation light 72 is irradiated onto the third quantum bit Qa3 and the fourth quantum bit Qa4.

[0023] A CZ gate is an example of a two-qubit gate. In a CZ gate, when both qubits are in the "1" state, the phase is inverted.

[0024] As shown in Figure 4, for example, a CZ gate is equivalent to a CNOT gate when sandwiched between two Hadamard gates H. In a CZ gate, operations on two quantum bits are symmetric (top and bottom of Figure 4). Two consecutive Hadamard gates H are omitted because they are equivalent to the state before the operation.

[0025] The CNOT gate is another example of a two-qubit gate. In a CNOT gate, when the control qubit is in the "0 state," it does nothing and maintains its previous state, while when the control qubit is in the "1 state," it flips the "0 state" of the target qubit to the "1 state" and vice versa.

[0026] In an embodiment, as shown in FIG. 1, in a surface code with a code distance of 3, 9 qubits are connected to 4 X stabilizer operators S x , and four Z stabilizer operators S z It has four X stabilizer operators S xincludes the X1X2 operator, the X2X3X4X5 operator, the X5X6X7X8 operator, and the X8X9 operator. The four Z stabilizer operators S z includes the Z6Z7 operator, the Z1Z2Z5Z6 operator, the Z4Z5Z8Z9 operator, and the Z3Z4 operator. In the encoded state of the surface code with a code distance of 3, the nine qubits are in a simultaneous eigenstate where the eigenvalues ​​of the eight stabilizer operators are "1". In the surface code with a code distance of 3, the encoded Z operator Z L corresponds to the operator Z1Z2Z3. Encoding X operator X L corresponds to the X1X6X7 operator. In the "encoded 0 state" of the surface code with code distance 3, the nine qubits are encoded by the encoded Z operator ZL is an eigenstate whose eigenvalue is "1".

[0027] For example, there is a first reference example encoding method for nine quantum bits as illustrated in FIG. 1. In the first reference example, first, as a preparatory control, nine quantum bits are set to a "0 state." In the "0 state," the quantum bits are in an eigenstate in which the eigenvalue of the Z operator is "1." After this, four X stabilizer operators S x Measurements are repeated three times for each qubit, thereby measuring the error. In this first reference example, 36 CNOT gates, four ancillary qubits, and 12 readouts are required. The stabilizer measurement is, for example, a syndrome measurement.

[0028] In contrast, in the embodiment, encoding can be performed with, for example, eight CNOT gates.

[0029] 5 and 6 are schematic diagrams illustrating control of the encoder according to the first embodiment. As shown in Figure 5, the above-mentioned first partial control SP1 and second partial control SP2 operations are performed for the first quantum bit Qa1, the second quantum bit Qa2, the third quantum bit Qa3, the fourth quantum bit Qa4, the fifth quantum bit Qa5, the sixth quantum bit Qa6, the seventh quantum bit Qa7, the eighth quantum bit Qa8, and the ninth quantum bit Qa9 (see Figure 6).

[0030] Before the first portion control SP1, a pre-portion control SP0 can be performed. In the pre-portion control SP0, the nine qubits are set to the |0> state. In the pre-portion control SP0, a Hadamard gate H can be performed for the second qubit Qa2, the fourth qubit Qa4, the sixth qubit Qa6, and the eighth qubit Qa8. Figure 4 illustrates the change of the stabilizer.

[0031] In an embodiment, as described above, two-qubit gate G32 occurs after two-qubit gate G43 and two-qubit gate G21. Two-qubit gate G78 occurs after two-qubit gate G67 and two-qubit gate G89. These two-qubit gates are, for example, CNOT gates.

[0032] In a CNOT gate, for example, a two-qubit gate Gij is executed with respect to the ith qubit Qai and the jth qubit Qaj. "i" is an integer between 1 and 9. "j" is (i±1) and is a positive integer. Execution of the two-qubit gate Gij includes, when the state of the ith qubit Qai is one of the first state and the second state (e.g., the first state), transitioning the state of the jth qubit Qaj to another state, and, when the state of the ith qubit Qai is the other of the first state and the second state (e.g., the second state), maintaining the state of the jth qubit Qaj.

[0033] For example, execution of a two-qubit gate G43 relating to the fourth qubit Qa4 and the third qubit Qa3 includes transitioning the state of the third qubit Qa3 to another state when the state of the fourth qubit Qa4 is one of the above states (e.g., the first state), and maintaining the state of the third qubit Qa3 when the state of the fourth qubit Qa4 is the other of the above states (e.g., the second state).

[0034] In the embodiment, highly fault-tolerant coding is possible. In the first partial control SP1, the "weight" of the stabilizer is 3 or less. Therefore, the number of errors can be considered to be 1 or less. An error with a "weight" of 2 that occurs in the CNOT gate in the second partial control SP2 can be corrected and is not a practical problem. The "weight" corresponds to the number of Pauli operators other than the identity operator.

[0035] 2, the first control OP1 includes a first partial control SP1 and a second partial control SP2 subsequent to the first partial control SP1. The first partial control SP1 includes the execution of a two-qubit gate G21, a two-qubit gate G43, a two-qubit gate G45, a two-qubit gate G65, a two-qubit gate G67, and a two-qubit gate G89. In the example of FIG. 2, the second partial control SP2 includes the execution of a two-qubit gate G32 and a two-qubit gate G78.

[0036] 7 and 8 are schematic diagrams illustrating control in the encoder according to the first embodiment. As shown in Fig. 7 and 8, in these examples, the first control OP1 includes a first partial control SP1, a second partial control SP2 after the first partial control SP1, and a third partial control SP3 after the second partial control SP2.

[0037] In the example of Figure 7, the first partial control SP1 includes the execution of a two-qubit gate G21, a two-qubit gate G43, a two-qubit gate G67, and a two-qubit gate G89. The second partial control SP2 includes the execution of a two-qubit gate G32 and a two-qubit gate G45. The third partial control SP3 includes the execution of a two-qubit gate G65 and a two-qubit gate G78. Efficient encoding is also possible in the example of Figure 5.

[0038] In the example of Figure 8, the first partial control SP1 includes the execution of a two-qubit gate G21, a two-qubit gate G43, a two-qubit gate G65, and a two-qubit gate G89. The second partial control SP2 includes the execution of a two-qubit gate G45 and a two-qubit gate G67. The third partial control SP3 includes the execution of a two-qubit gate G32 and a two-qubit gate G78. Efficient encoding is also possible in the example of Figure 8.

[0039] (Second embodiment) FIG. 9 is a schematic diagram illustrating an encoder according to the second embodiment. As shown in Fig. 9, the encoder 120 according to the embodiment includes an encoding element unit 20E and a control unit 70. Fig. 9 illustrates the concept of a code obtained by concatenating two surface codes with a code distance of 3.

[0040] In the following, an example will be described in which the quantum state of an atom trapped by light is used as a quantum bit. FIG. 10 is a schematic diagram illustrating an encoder according to the second embodiment. 10 illustrates the case where the code distance is 3 (i.e., the code distance N is 3). As shown in Fig. 10, the encoding element unit 20E includes a first encoded quantum bit Qc1 of code distance N, a second encoded quantum bit Qc2 of code distance N, a third encoded quantum bit Qc3 of code distance N, a fourth encoded quantum bit Qc4 of code distance N, a fifth encoded quantum bit Qc5 of code distance N, a sixth encoded quantum bit Qc6 of code distance N, a seventh encoded quantum bit Qc7 of code distance N, an eighth encoded quantum bit Qc8 of code distance N, and a ninth encoded quantum bit Qc9 of code distance N.

[0041] The second-encoded qubit Qc2 can be coupled to the first-encoded qubit Qc1. The third-encoded qubit Qc3 can be coupled to the second-encoded qubit Qc2. The fourth-encoded qubit Qc4 can be coupled to the third-encoded qubit Qc3. The fifth-encoded qubit Qc5 can be coupled to the fourth-encoded qubit Qc4. The sixth-encoded qubit Qc6 can be coupled to the fifth-encoded qubit Qc5. The seventh-encoded qubit Qc7 can be coupled to the sixth-encoded qubit Qc6. The eighth-encoded qubit Qc8 can be coupled to the seventh-encoded qubit Qc7. The ninth-encoded qubit Qc9 can be coupled to the eighth-encoded qubit Qc8.

[0042] In this example, the first to ninth encoded quantum bits Qc1 to Qc9 included in the encoding element unit 20E each include the first element unit 10E (see FIG. 1). The code at level 1 corresponds to the code of the first element unit 10E (first to ninth encoded quantum bits Qa1 to Qa9). The code at level 2 corresponds to the code of the encoding element unit 20E (first to ninth encoded quantum bits Qc1 to Qc9).

[0043] In the following, it is assumed that level 1 codes of the concatenated code are surface codes with a code distance of 3. In an embodiment, any code with a code distance of N may be used, where "N" is an integer equal to or greater than 2. Level 2 codes of the concatenated code are surface codes with a code distance of 3.

[0044] An example of encoding in the encoder 120 will now be described. FIG. 11 is a flowchart illustrating control in the encoder according to the second embodiment. 11, the control unit 70 can execute a second control OP2 and a third control OP3. The second control OP2 corresponds to level 2 encoding. The third control OP3 corresponds to error detection control. The control unit 70 can execute a first level encoding control OL1 before the second control OP2.

[0045] Fig. 12 is a schematic diagram illustrating a portion of the control in the encoder according to the second embodiment. Fig. 12 illustrates a first-level encoding control OL1. Fig. 12 illustrates the first-level encoding control OL1 for the third encoding qubit Qc3 and the fourth encoding qubit Qc4.

[0046] 12, the third encoded quantum bit Qc3 includes the first to ninth quantum bits Qa1 to Qa9 of the third encoded quantum bit Qc3. The fourth encoded quantum bit Qc4 includes the first to ninth quantum bits Qa1 to Qa9 of the fourth encoded quantum bit Qc4. For example, a level 1 encoded CNOT gate is performed between the first to ninth quantum bits Qa1 to Qa9 included in the third encoded quantum bit Qc3 and the first to ninth quantum bits Qa1 to Qa9 included in the fourth encoded quantum bit Qc4. The level 1 encoded CNOT gate corresponds to a "transversal CNOT." In an embodiment, the encoded CZ gate may also be performed in the same manner as in FIG. 12.

[0047] 12 is performed for the other two encoding qubits. At this time, the control unit 70 executes the two-qubit gate G32 after the two-qubit gate G21 and the two-qubit gate G43 in the first-level encoding control OL1. The control unit 70 executes the two-qubit gate G67 and the two-qubit gate G89 in the first-level encoding control OL1, and then executes the two-qubit gate G78. Such first-level encoding control OL1 is performed for all nine level-1 encoding qubits.

[0048] 12, the level 1 code is a surface code with a code distance of 3. When the level 1 code has a code distance of N, the first level coding control OL1 is changed and executed according to the code distance N.

[0049] As shown in FIG. 11, the control unit 70 executes a first level encoding control OL1 and then a second control OP2. 13(a) and 13(b) are schematic diagrams illustrating control in the encoder according to the second embodiment. The second control OP2 includes the execution of an encoding two-qubit gate Gc21 for the second encoded qubit Qc2 and the first encoded qubit Qc1 (see FIG. 13(a)). The second control OP2 includes the execution of an encoding two-qubit gate Gc32 for the third encoded qubit Qc3 and the second encoded qubit Qc2 (see FIG. 13(b)). The second control OP2 includes the execution of an encoding two-qubit gate Gc43 for the fourth encoded qubit Qc4 and the third encoded qubit Qc3 (see FIG. 13(a)). The second control OP2 includes the execution of an encoding two-qubit gate Gc45 for the fourth encoded qubit Qc4 and the fifth encoded qubit Qc5 (see FIG. 13(a)). The second control OP2 includes the execution of an encoding two-qubit gate Gc65 for the sixth encoded qubit Qc6 and the fifth encoded qubit Qc5 (see FIG. 13(a)). The second control OP2 includes the execution of an encoded two-qubit gate Gc67 for the sixth encoded qubit Qc6 and the seventh encoded qubit Qc7 (see FIG. 13(a)). The second control OP2 includes the execution of an encoded two-qubit gate Gc78 for the seventh encoded qubit Qc7 and the eighth encoded qubit Qc8 (see FIG. 13(b)). The second control OP2 includes the execution of an encoded two-qubit gate Gc89 for the eighth encoded qubit Qc8 and the ninth encoded qubit Qc9 (see FIG. 13(a)).

[0050] The second control OP2 includes encoding the code with code distance N and the surface code with code distance 3 into a concatenated code with code distance 3N using the above-mentioned multiple encoding two-qubit gates.

[0051] 10 illustrates a portion of the second control OP2. The control unit 70 irradiates the first to ninth quantum bits Qa1 to Qa9 (see FIG. 2, etc.) included in the first to ninth encoded quantum bits Qc1 to Qc9, respectively, with excitation light 71. The control unit 70 can execute a CZ gate by irradiating two adjacent atoms with manipulation light 72 (e.g., a laser).

[0052] 10 illustrates an example of an operation on the third encoded quantum bit Qc3 and the fourth encoded quantum bit Qc4. In this case, the third encoded quantum bit Qc3 and the fourth encoded quantum bit Qc4 are irradiated with operation light 72. An encoded CZ gate is executed on the third encoded quantum bit Qc3 and the fourth encoded quantum bit Qc4.

[0053] 11, in the second control OP2, the control unit 70 executes the encoding two-qubit gate Gc21 and the encoding two-qubit gate Gc43, followed by the encoding two-qubit gate Gc32. In the second control OP2, the control unit 70 executes the encoding two-qubit gate Gc67 and the encoding two-qubit gate Gc89, followed by the encoding two-qubit gate Gc78.

[0054] As shown in FIG. 11, the control unit 70 executes the third control operation OP3 after the second control operation OP2. The third control OP3 includes detecting errors with respect to at least one of the second encoded quantum bit Qc2, the third encoded quantum bit Qc3, and the fourth encoded quantum bit Qc4, and at least one of the sixth encoded quantum bit Qc6, the seventh encoded quantum bit Qc7, and the eighth encoded quantum bit Qc8.

[0055] The control unit 70 determines whether or not there is an error (fourth control operation OP4). If there is an error, the process returns to the first level encoding control operation OL1 (or the second control operation OP2). If there is no error, the encoding ends. The control unit 70 repeats the second control operation OP2 and the third control operation OP3 until no errors are detected.

[0056] FIG. 14 is a schematic diagram illustrating an encoder of a reference example. As shown in FIG. 14, in the encoder 129 of the second reference example, "N" is 3. In this case, the code distance is 9. 9×9 (81) quantum bits Qax are provided. In the 81 quantum bits Qax, in the "0 state" of the surface code with a code distance of 9, 40 X stabilizer operators S x , 40 Z stabilizer operators S z, and the encoding Z operator Z L is a simultaneous eigenstate with eigenvalue "1".

[0057] In the second reference example, first, as a preparatory control, 81 quantum bits Qax are set to the "0 state." In the "0 state," the quantum bits Qax are in an eigenstate in which the eigenvalue of the Z operator is "1." Then, 40 X stabilizer operators S x The measurements are repeated nine times and the error is estimated. x Measuring this requires 1242 CNOT gates, 40 ancillary qubits, and 360 readouts.

[0058] In contrast to this, in the embodiment, encoding can be performed efficiently by the second control OP2 and the third control OP3.

[0059] As described above, each of the first to ninth encoded qubits Qc1 to Qc9 includes a first element unit 10E (see FIG. 1). As already explained, the first element unit 10E includes a first qubit Qa1, a second qubit Qa2 that can be coupled to the first qubit Qa1, a third qubit Qa3 that can be coupled to the second qubit Qa2, a fourth qubit Qa4 that can be coupled to the third qubit Qa3, a fifth qubit Qa5 ​​that can be coupled to the fourth qubit Qa4, a sixth qubit Qa6 that can be coupled to the fifth qubit Qa5, a seventh qubit Qa7 that can be coupled to the sixth qubit Qa6, an eighth qubit Qa8 that can be coupled to the seventh qubit Qa7, and a ninth qubit Qa9 that can be coupled to the eighth qubit Qa8 (see FIG. 1).

[0060] In the second embodiment, the first-level encoding control OL1 executed by the control unit 70 corresponds to the first control OP1 described with respect to the first embodiment. As described with respect to the first embodiment, the first control OP1 includes a two-qubit gate G21 for the second qubit Qa2 and the first qubit Qa1, a two-qubit gate G32 for the third qubit Qa3 and the second qubit Qa2, a two-qubit gate G43 for the fourth qubit Qa4 and the third qubit Qa3, a two-qubit gate G45 for the fourth qubit Qa4 and the fifth qubit Qa5, a two-qubit gate G65 for the sixth qubit Qa6 and the fifth qubit Qa5, a two-qubit gate G67 for the sixth qubit Qa6 and the seventh qubit Qa7, a two-qubit gate G78 for the seventh qubit Qa7 and the eighth qubit Qa8, and a two-qubit gate G89 for the eighth qubit Qa8 and the ninth qubit Qa9.

[0061] The first control OP1 includes encoding a surface code of code distance 3 by executing a two-qubit gate G21, a two-qubit gate G32, a two-qubit gate G43, a two-qubit gate G45, a two-qubit gate G65, a two-qubit gate G67, a two-qubit gate G78, and a two-qubit gate G89. The code of code distance N is a surface code of code distance 3.

[0062] As already explained, in the first control OP1, the control unit 70 executes the two-qubit gate G21 and the two-qubit gate G43, followed by the two-qubit gate G32. In the first control OP1, the control unit 70 executes the two-qubit gate G67 and the two-qubit gate G89, followed by the two-qubit gate G78.

[0063] In encoder 120, the third control OP3 may further include performing error detection on the fifth encoding qubit Qc5, thereby enabling encoding to be performed with higher efficiency.

[0064] In an embodiment, in the third control OP3, error detection may be performed for the second encoding qubit Qc2, the fifth encoding qubit Qc5, and the eighth encoding qubit Qc8. This allows for more efficient encoding. In this case, the second control OP2 also includes encoding a code with a code distance of N and a surface code with a code distance of 3 into a concatenated code with a code distance of 3N. In the second control OP2, the control unit 70 executes the encoding two-qubit gate Gc21 and the encoding two-qubit gate Gc43, followed by the encoding two-qubit gate Gc32. In the second control OP2, the control unit 70 executes the encoding two-qubit gate Gc67 and the encoding two-qubit gate Gc89, followed by the encoding two-qubit gate Gc78. The control unit 70 executes the third control OP3 after the second control OP2. The third control OP3 includes detecting errors for the second encoding qubit Qc2, the fifth encoding qubit Qc5, and the eighth encoding qubit Qc8. In this case, the control unit 70 also determines whether there is an error (fourth control operation OP4). If there is an error, the process returns to the second control operation OP2. The control unit 70 repeats the first level encoding control operation OL1 (or the second control operation OP2) and the third control operation OP3 until no errors are detected. This allows efficient encoding.

[0065] FIG. 15 is a graph illustrating the performance of the encoder. FIG. 15 shows the simulation results of an encoder corresponding to the case where the code distance is 3 (i.e., N=3) (see FIG. 9). FIG. 15 illustrates the simulation results of the decoding error probability under four conditions. Under the first condition CD1, error detection (Error-detecting teleportation: EDT, see H. Goto and H. Uchikawa, Scientific Reports 3, 2044 (2013) Fault-tolerant quantum computation with a soft-decision decoder for error correction and detection by teleportation | Scientific Reports (nature.com)) is performed for the second encoding qubit Qc2, the fifth encoding qubit Qc5, and the eighth encoding qubit Qc8. Under the second condition CD2, error detection is performed for the second encoding qubit Qc2 and the eighth encoding qubit Qc8. Under the third condition CD3, error detection is performed for the fifth encoding qubit Qc5. Under the fourth condition CD4, error detection is not performed. The horizontal axis of FIG. 15 represents the error probability P CNOT The vertical axis of FIG. 15 is the decoding error probability P C FIG. 15 shows examples of function expressions calculated for each of the four conditions.

[0066] As shown in FIG. 15, the decoding error probability P C is obtained. Under the first condition CD1, the exponent of the function equation is 5.3954. Under the second condition CD2, the exponent of the function equation is 4.7145. Under the third condition CD3, the exponent of the function equation is 3.5085. Under the fourth condition CD4, the exponent of the function equation is 3.4921. Under the second condition CD2, the exponent is improved compared to the third condition CD3. Under the first condition CD1, the exponent is improved compared to the second condition CD2.

[0067] Under the second condition CD2, the decoding error probability P is lower than under the third condition CD3.C Under the first condition CD1, the decoding error probability P C is obtained.

[0068] In the embodiment, it is preferable to adopt the first condition CD1 or the second condition CD2. C is obtained.

[0069] (Third embodiment) FIG. 16 is a schematic diagram illustrating a computing device according to the third embodiment. 16, a calculation device 310 according to the embodiment includes an encoder according to the embodiment (for example, the encoder 110). The calculation device 310 includes, for example, a first element unit 10E.

[0070] In computing device 310, for example, the states of first to ninth quantum bits Qa1 to Qa9 correspond to the quantum states of atoms trapped by light, for example.

[0071] The calculation device 310 may include, for example, the encoding element unit 20E. For example, the encoded quantum bits obtained by the second control OP2 and the third control OP3 are used in the calculation.

[0072] (Fourth embodiment) The fourth embodiment relates to an encoding method. The encoding method according to the embodiment may include the control of the control unit 70 described in relation to the first and second embodiments.

[0073] In the encoding method according to the embodiment, for example, a first control OP1 is executed for the first element unit 10E to encode a surface code with a code distance of 3. As already described, the first element unit 10E includes first to ninth quantum bits Qa1 to Qa9. In the first control OP1, a two-qubit gate G21 and a two-qubit gate G43 are executed followed by a two-qubit gate G32 (see FIG. 2). In the first process (first control OP1), a two-qubit gate G67 and a two-qubit gate G89 are executed followed by a two-qubit gate G78 (see FIG. 2).

[0074] In the third embodiment, the control described with reference to Fig. 11 may be executed. According to the embodiment, it is possible to provide an encoding method that can improve efficiency.

[0075] The embodiment may include the following configurations (e.g., technical solutions). (Configuration 1) a first element portion; A control unit; Equipped with The first element portion is a first qubit; and a second qubit coupleable to the first qubit; a third qubit coupleable with the second qubit; a fourth qubit coupleable with the third qubit; a fifth qubit coupleable with the fourth qubit; a sixth qubit coupleable with the fifth qubit; a seventh qubit coupleable with the sixth qubit; an eighth qubit coupleable with the seventh qubit; a ninth qubit coupleable with the eighth qubit; Including, The control unit is capable of executing a first control, The first control is performing a two-qubit gate on the second qubit and the first qubit; performing a two-qubit gate on the third qubit and the second qubit; and performing a two-qubit gate on the fourth qubit and the third qubit; and performing a two-qubit gate on the fourth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the fifth qubit; and performing a two-qubit gate on the sixth qubit and the seventh qubit; performing a two-qubit gate on the seventh qubit and the eighth qubit; and performing a two-qubit gate on the eighth qubit and the ninth qubit; and encoding a surface code with a code distance of 3 by the control unit, in the first control, executes the two-qubit gate regarding the third qubit and the second qubit after the two-qubit gate regarding the second qubit and the first qubit and the two-qubit gate regarding the fourth qubit and the third qubit; an encoder in which, under the first control, the control unit executes the two-qubit gate for the seventh qubit and the eighth qubit after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit.

[0076] (Configuration 2) the first control includes a first partial control and a second partial control subsequent to the first partial control, The first partial control includes: said performing said two-qubit gate with respect to said second qubit and said first qubit; said performing said two-qubit gate with respect to said fourth qubit and said third qubit; said performing said two-qubit gate with respect to said fourth qubit and said fifth qubit; said performing said two-qubit gate with respect to said sixth qubit and said fifth qubit; said performing said two-qubit gate on said sixth qubit and said seventh qubit; said performing said two-qubit gate on said eighth qubit and said ninth qubit; Including, The second partial control is said performing said two-qubit gate with respect to said third qubit and said second qubit; said performing said two-qubit gate on said seventh qubit and said eighth qubit; 2. The encoder of claim 1,

[0077] (Configuration 3) the first control includes a first partial control, a second partial control after the first partial control, and a third partial control after the second partial control, The first partial control includes: said performing said two-qubit gate with respect to said second qubit and said first qubit; said performing said two-qubit gate with respect to said fourth qubit and said third qubit; said performing said two-qubit gate on said sixth qubit and said seventh qubit; said performing said two-qubit gate on said eighth qubit and said ninth qubit; Including, The second partial control is said performing said two-qubit gate with respect to said third qubit and said second qubit; said performing said two-qubit gate with respect to said fourth qubit and said fifth qubit; Including, The third partial control is said performing said two-qubit gate with respect to said sixth qubit and said fifth qubit; said performing said two-qubit gate on said seventh qubit and said eighth qubit; 2. The encoder of claim 1,

[0078] (Configuration 4) the first control includes a first partial control, a second partial control after the first partial control, and a third partial control after the second partial control, The first partial control includes: said performing said two-qubit gate with respect to said second qubit and said first qubit; said performing said two-qubit gate with respect to said fourth qubit and said third qubit; said performing said two-qubit gate with respect to said sixth qubit and said fifth qubit; said performing said two-qubit gate on said eighth qubit and said ninth qubit; Including, The second partial control is said performing said two-qubit gate with respect to said fourth qubit and said fifth qubit; said performing said two-qubit gate on said sixth qubit and said seventh qubit; Including, The third partial control is said performing said two-qubit gate with respect to said third qubit and said second qubit; said performing said two-qubit gate on said seventh qubit and said eighth qubit; 2. The encoder of claim 1,

[0079] (Configuration 5) a coding element unit; A control unit; Equipped with The encoding element unit a first encoding qubit of code distance N; a second encoding qubit of the code distance N that is combinable with the first encoding qubit; a third encoding qubit of the code distance N that is combinable with the second encoding qubit; a fourth encoding qubit of the code distance N that is combinable with the third encoding qubit; a fifth encoding qubit of the code distance N that is combineable with the fourth encoding qubit; a sixth encoding qubit of the code distance N, which is combineable with the fifth encoding qubit; a seventh encoding qubit of the code distance N, combinable with the sixth encoding qubit; an eighth encoding qubit of the code distance N, combinable with the seventh encoding qubit; a ninth encoding qubit of the code distance N, combinable with the eighth encoding qubit; Including, N is an integer of 2 or more, The control unit is capable of executing second control and third control, The second control is performing an encoded two-qubit gate on the second encoded qubit and the first encoded qubit; performing an encoded two-qubit gate on the third encoded qubit and the second encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the third encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the seventh encoded qubit; and performing an encoded two-qubit gate on the seventh encoded qubit and the eighth encoded qubit; and performing an encoded two-qubit gate on the eighth encoded qubit and the ninth encoded qubit; and and encoding the code with code distance N and the surface code with code distance 3 into a concatenated code with code distance 3N by the control unit, in the second control, executes the encoding two-qubit gate for the third encoded qubit and the second encoded qubit after the encoding two-qubit gate for the second encoded qubit and the first encoded qubit and the encoding two-qubit gate for the fourth encoded qubit and the third encoded qubit; the control unit, in the second control, executes the encoding two-qubit gate for the seventh encoded qubit and the eighth encoded qubit after the encoding two-qubit gate for the sixth encoded qubit and the seventh encoded qubit and the encoding two-qubit gate for the eighth encoded qubit and the ninth encoded qubit; the control unit executes the third control after the second control, the third control includes detecting an error with respect to at least one of the second encoded qubit, the third encoded qubit, and the fourth encoded qubit, and at least one of the sixth encoded qubit, the seventh encoded qubit, and the eighth encoded qubit; The control unit repeats the second control and the third control until the error is no longer detected.

[0080] (Configuration 6) each of the first to ninth encoding quantum bits includes a first element unit; The first element portion is a first qubit; and a second qubit coupleable to the first qubit; a third qubit coupleable with the second qubit; a fourth qubit coupleable with the third qubit; a fifth qubit coupleable with the fourth qubit; a sixth qubit coupleable with the fifth qubit; a seventh qubit coupleable with the sixth qubit; an eighth qubit coupleable with the seventh qubit; a ninth qubit coupleable with the eighth qubit; Including, The control unit is capable of executing a first control, The first control is performing a two-qubit gate on the second qubit and the first qubit; performing a two-qubit gate on the third qubit and the second qubit; and performing a two-qubit gate on the fourth qubit and the third qubit; and performing a two-qubit gate on the fourth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the fifth qubit; and performing a two-qubit gate on the sixth qubit and the seventh qubit; performing a two-qubit gate on the seventh qubit and the eighth qubit; and performing a two-qubit gate on the eighth qubit and the ninth qubit; and encoding the surface code of the code distance 3 by The code of the code distance N is a surface code of the code distance 3, the control unit, in the first control, executes the two-qubit gate regarding the third qubit and the second qubit after the two-qubit gate regarding the second qubit and the first qubit and the two-qubit gate regarding the fourth qubit and the third qubit; 6. The encoder of claim 5, wherein the control unit, in the first control, executes the two-qubit gate for the seventh qubit and the eighth qubit after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit.

[0081] (Configuration 7) 7. The encoder of configuration 5 or 6, wherein the third control further includes performing error detection on the fifth encoding quantum bit and the eighth encoding quantum bit.

[0082] (Configuration 8) a coding element unit; A control unit; Equipped with The encoding element unit a first encoding qubit of code distance N; a second encoding qubit of the code distance N that is combinable with the first encoding qubit; a third encoding qubit of the code distance N that is combinable with the second encoding qubit; a fourth encoding qubit of the code distance N that is combinable with the third encoding qubit; a fifth encoding qubit of the code distance N that is combineable with the fourth encoding qubit; a sixth encoding qubit of the code distance N, which is combineable with the fifth encoding qubit; a seventh encoding qubit of the code distance N, combinable with the sixth encoding qubit; an eighth encoding qubit of the code distance N, combinable with the seventh encoding qubit; a ninth encoding qubit of the code distance N, combinable with the eighth encoding qubit; Including, The control unit is capable of executing second control and third control, The second control is performing an encoded two-qubit gate on the second encoded qubit and the first encoded qubit; performing an encoded two-qubit gate on the third encoded qubit and the second encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the third encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the seventh encoded qubit; and performing an encoded two-qubit gate on the seventh encoded qubit and the eighth encoded qubit; and performing an encoded two-qubit gate on the eighth encoded qubit and the ninth encoded qubit; and and encoding the code with code distance N and the surface code with code distance 3 into a concatenated code with code distance 3N by the control unit, in the second control, executes the encoding two-qubit gate for the third encoded qubit and the second encoded qubit after the encoding two-qubit gate for the second encoded qubit and the first encoded qubit and the encoding two-qubit gate for the fourth encoded qubit and the third encoded qubit; the control unit, in the second control, executes the encoding two-qubit gate for the seventh encoded qubit and the eighth encoded qubit after the encoding two-qubit gate for the sixth encoded qubit and the seventh encoded qubit and the encoding two-qubit gate for the eighth encoded qubit and the ninth encoded qubit; the control unit executes the third control after the second control, the third control includes detecting errors with respect to the second encoded quantum bit, the fifth encoded quantum bit, and the eighth encoded quantum bit; The control unit repeats the second control and the third control until the error is no longer detected.

[0083] (Configuration 9) each of the first to ninth encoding quantum bits includes a first element unit; The first element portion is a first qubit; and a second qubit coupleable to the first qubit; a third qubit coupleable with the second qubit; a fourth qubit coupleable with the third qubit; a fifth qubit coupleable with the fourth qubit; a sixth qubit coupleable with the fifth qubit; a seventh qubit coupleable with the sixth qubit; an eighth qubit coupleable with the seventh qubit; a ninth qubit coupleable with the eighth qubit; Including, The control unit is capable of executing a first control, The first control is performing a two-qubit gate on the second qubit and the first qubit; performing a two-qubit gate on the third qubit and the second qubit; and performing a two-qubit gate on the fourth qubit and the third qubit; and performing a two-qubit gate on the fourth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the fifth qubit; and performing a two-qubit gate on the sixth qubit and the seventh qubit; performing a two-qubit gate on the seventh qubit and the eighth qubit; and performing a two-qubit gate on the eighth qubit and the ninth qubit; and encoding the surface code of the code distance 3 by The code of the code distance N is a surface code of the code distance 3, the control unit, in the first control, executes the two-qubit gate regarding the third qubit and the second qubit after the two-qubit gate regarding the second qubit and the first qubit and the two-qubit gate regarding the fourth qubit and the third qubit; 9. The encoder of claim 8, wherein the control unit, in the first control, executes the two-qubit gate for the seventh qubit and the eighth qubit after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit.

[0084] (Configuration 10) A computing device comprising the encoder according to any one of configurations 1 to 4.

[0085] (Configuration 11) 11. The computing device according to configuration 10, wherein the states of the first to ninth quantum bits correspond to quantum states of atoms trapped by light.

[0086] (Configuration 12) The encoder according to any one of configurations 5 to 9 is provided, A computing device that uses the encoded quantum bits obtained by the second control and the third control for calculation.

[0087] (Configuration 13) 13. The computing device according to configuration 12, wherein the states of the first to ninth encoded quantum bits correspond to quantum states of atoms trapped by light.

[0088] (Configuration 14) Execute a first control for encoding a surface code with a code distance of 3 for the first element unit; The first element portion is a first qubit; and a second qubit coupleable to the first qubit; a third qubit coupleable with the second qubit; a fourth qubit coupleable with the third qubit; a fifth qubit coupleable with the fourth qubit; a sixth qubit coupleable with the fifth qubit; a seventh qubit coupleable with the sixth qubit; an eighth qubit coupleable with the seventh qubit; a ninth qubit coupleable with the eighth qubit; Including, The execution of the first control includes: performing a two-qubit gate on the second qubit and the first qubit; performing a two-qubit gate on the third qubit and the second qubit; and performing a two-qubit gate on the fourth qubit and the third qubit; and performing a two-qubit gate on the fourth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the fifth qubit; and performing a two-qubit gate on the sixth qubit and the seventh qubit; performing a two-qubit gate on the seventh qubit and the eighth qubit; and performing a two-qubit gate on the eighth qubit and the ninth qubit; and Including, in the first control, performing the two-qubit gate for the second qubit and the first qubit and the two-qubit gate for the fourth qubit and the third qubit, followed by the two-qubit gate for the third qubit and the second qubit; an encoding method in which, in the first control, the two-qubit gate for the seventh qubit and the eighth qubit is executed after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit.

[0089] According to the embodiments, an encoder, a computing device, and an encoding method that can improve efficiency can be provided.

[0090] The embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configurations of each element, such as an element unit, a quantum bit, and a control unit, included in an encoder or a computing device, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0091] Any combination of two or more elements of each example within the scope of technical feasibility is also included within the scope of the present invention as long as it encompasses the gist of the present invention.

[0092] All encoders, computing devices, and encoding methods that can be implemented by a person skilled in the art by appropriately modifying the design based on the encoder, computing device, and encoding method described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0093] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention.

[0094] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0095] 10E: first element unit, 20E: encoding element unit, 70: control unit, 71: excitation light, 72: operation light, 110, 120, 129: encoder, 310: calculation device, G21, G32, G43, G45, G65, G67, G78, G89: 2-qubit gate, Gc21, Gc32, Gc43, Gc45, Gc67, Gc78, Gc89: encoding 2-qubit gate, OL1: first level encoding control, OP1 to OP4: first to fourth controls, P c : decoding error rate, P CNOT : Error probability, Qa1 to Qa9: 1st to 9th quantum bits, Qax: quantum bit, Qc1 to Qc9: 1st to 9th encoding quantum bits, SP0: Pre-partial control, SP1 to SP3: 1st to 3rd partial control

Claims

1. a first element portion; A control unit; Equipped with The first element portion is a first qubit; and a second qubit coupleable to the first qubit; a third qubit coupleable to the second qubit; a fourth qubit coupleable with the third qubit; a fifth qubit coupleable with the fourth qubit; a sixth qubit coupleable with the fifth qubit; a seventh qubit coupleable with the sixth qubit; an eighth qubit coupleable with the seventh qubit; a ninth qubit coupleable with the eighth qubit; Including, The control unit is capable of executing a first control, The first control is performing a two-qubit gate on the second qubit and the first qubit; performing a two-qubit gate on the third qubit and the second qubit; and performing a two-qubit gate on the fourth qubit and the third qubit; and performing a two-qubit gate on the fourth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the seventh qubit; performing a two-qubit gate on the seventh qubit and the eighth qubit; performing a two-qubit gate on the eighth qubit and the ninth qubit; and encoding a surface code with a code distance of 3 by the control unit, in the first control, executes the two-qubit gate regarding the third qubit and the second qubit after the two-qubit gate regarding the second qubit and the first qubit and the two-qubit gate regarding the fourth qubit and the third qubit; The control unit, under the first control, executes the two-qubit gate for the seventh qubit and the eighth qubit after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit.

2. the first control includes a first partial control and a second partial control subsequent to the first partial control, The first partial control includes: the performing of the two-qubit gate with respect to the second qubit and the first qubit; said performing said two-qubit gate with respect to said fourth qubit and said third qubit; said performing said two-qubit gate with respect to said fourth qubit and said fifth qubit; the performing of the two-qubit gate with respect to the sixth qubit and the fifth qubit; said performing said two-qubit gate with respect to said sixth qubit and said seventh qubit; said performing said two-qubit gate with respect to said eighth qubit and said ninth qubit; Including, The second partial control includes: the performing of the two-qubit gate with respect to the third qubit and the second qubit; said performing said two-qubit gate on said seventh qubit and said eighth qubit; The encoder of claim 1 , comprising:

3. the first control includes a first partial control, a second partial control after the first partial control, and a third partial control after the second partial control, The first partial control includes: the performing of the two-qubit gate with respect to the second qubit and the first qubit; said performing said two-qubit gate with respect to said fourth qubit and said third qubit; said performing said two-qubit gate with respect to said sixth qubit and said seventh qubit; said performing said two-qubit gate with respect to said eighth qubit and said ninth qubit; Including, The second partial control includes: the performing of the two-qubit gate with respect to the third qubit and the second qubit; said performing said two-qubit gate with respect to said fourth qubit and said fifth qubit; Including, The third partial control is the performing of the two-qubit gate with respect to the sixth qubit and the fifth qubit; said performing said two-qubit gate with respect to said seventh qubit and said eighth qubit; The encoder of claim 1 , comprising:

4. the first control includes a first partial control, a second partial control after the first partial control, and a third partial control after the second partial control, The first partial control includes: the performing of the two-qubit gate with respect to the second qubit and the first qubit; said performing said two-qubit gate with respect to said fourth qubit and said third qubit; the performing of the two-qubit gate with respect to the sixth qubit and the fifth qubit; said performing said two-qubit gate with respect to said eighth qubit and said ninth qubit; Including, The second partial control includes: said performing said two-qubit gate with respect to said fourth qubit and said fifth qubit; said performing said two-qubit gate with respect to said sixth qubit and said seventh qubit; Including, The third partial control is the performing of the two-qubit gate with respect to the third qubit and the second qubit; said performing said two-qubit gate with respect to said seventh qubit and said eighth qubit; The encoder of claim 1 , comprising:

5. a coding element unit; A control unit; Equipped with The encoding element unit a first encoding qubit of code distance N; a second encoding qubit of the code distance N that is combinable with the first encoding qubit; a third encoding qubit of the code distance N, combinable with the second encoding qubit; a fourth encoding qubit of the code distance N, which is combineable with the third encoding qubit; a fifth encoding qubit of the code distance N, which is combineable with the fourth encoding qubit; a sixth encoding qubit of the code distance N, which is combineable with the fifth encoding qubit; a seventh encoding qubit of the code distance N, which is combineable with the sixth encoding qubit; an eighth encoding qubit of the code distance N, combinable with the seventh encoding qubit; a ninth encoding qubit of the code distance N, which is combineable with the eighth encoding qubit; Including, N is an integer of 2 or more, The control unit is capable of executing second control and third control, The second control is performing an encoded two-qubit gate on the second encoded qubit and the first encoded qubit; performing an encoded two-qubit gate on the third encoded qubit and the second encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the third encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the seventh encoded qubit; and performing an encoded two-qubit gate on the seventh encoded qubit and the eighth encoded qubit; and performing an encoded two-qubit gate on the eighth encoded qubit and the ninth encoded qubit; and and encoding the code with code distance N and the surface code with code distance 3 into a concatenated code with code distance 3N by the control unit, in the second control, executes the encoded two-qubit gate for the third encoded qubit and the second encoded qubit after the encoded two-qubit gate for the second encoded qubit and the first encoded qubit and the encoded two-qubit gate for the fourth encoded qubit and the third encoded qubit; the control unit, in the second control, executes the encoded two-qubit gate for the seventh encoded qubit and the eighth encoded qubit after the encoded two-qubit gate for the sixth encoded qubit and the seventh encoded qubit and the encoded two-qubit gate for the eighth encoded qubit and the ninth encoded qubit; the control unit executes the third control after the second control, the third control includes detecting an error with respect to at least one of the second encoded qubit, the third encoded qubit, and the fourth encoded qubit, and at least one of the sixth encoded qubit, the seventh encoded qubit, and the eighth encoded qubit; The control unit repeats the second control and the third control until the error is no longer detected.

6. a coding element unit; A control unit; Equipped with The encoding element unit a first encoding qubit of code distance N; a second encoding qubit of the code distance N that is combinable with the first encoding qubit; a third encoding qubit of the code distance N, combinable with the second encoding qubit; a fourth encoding qubit of the code distance N, which is combineable with the third encoding qubit; a fifth encoding qubit of the code distance N, which is combineable with the fourth encoding qubit; a sixth encoding qubit of the code distance N, which is combineable with the fifth encoding qubit; a seventh encoding qubit of the code distance N, which is combineable with the sixth encoding qubit; an eighth encoding qubit of the code distance N, combinable with the seventh encoding qubit; a ninth encoding qubit of the code distance N, which is combineable with the eighth encoding qubit; Including, The control unit is capable of executing second control and third control, The second control is performing an encoded two-qubit gate on the second encoded qubit and the first encoded qubit; performing an encoded two-qubit gate on the third encoded qubit and the second encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the third encoded qubit; and performing an encoded two-qubit gate on the fourth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the fifth encoded qubit; and performing an encoded two-qubit gate on the sixth encoded qubit and the seventh encoded qubit; and performing an encoded two-qubit gate on the seventh encoded qubit and the eighth encoded qubit; and performing an encoded two-qubit gate on the eighth encoded qubit and the ninth encoded qubit; and and encoding the code with code distance N and the surface code with code distance 3 into a concatenated code with code distance 3N by the control unit, in the second control, executes the encoded two-qubit gate for the third encoded qubit and the second encoded qubit after the encoded two-qubit gate for the second encoded qubit and the first encoded qubit and the encoded two-qubit gate for the fourth encoded qubit and the third encoded qubit; the control unit, in the second control, executes the encoded two-qubit gate for the seventh encoded qubit and the eighth encoded qubit after the encoded two-qubit gate for the sixth encoded qubit and the seventh encoded qubit and the encoded two-qubit gate for the eighth encoded qubit and the ninth encoded qubit; the control unit executes the third control after the second control, the third control includes detecting errors with respect to the second encoded quantum bit, the fifth encoded quantum bit, and the eighth encoded quantum bit; The control unit repeats the second control and the third control until the error is no longer detected.

7. A computing device comprising an encoder according to any one of claims 1 to 4.

8. 8. The computing device according to claim 7, wherein the states of the first to ninth quantum bits correspond to quantum states of atoms trapped by light.

9. Execute a first control for encoding a surface code with a code distance of 3 for the first element unit; The first element portion is a first qubit; and a second qubit coupleable to the first qubit; a third qubit coupleable to the second qubit; a fourth qubit coupleable with the third qubit; a fifth qubit coupleable with the fourth qubit; a sixth qubit coupleable with the fifth qubit; a seventh qubit coupleable with the sixth qubit; an eighth qubit coupleable with the seventh qubit; a ninth qubit coupleable with the eighth qubit; Including, The execution of the first control includes: performing a two-qubit gate on the second qubit and the first qubit; performing a two-qubit gate on the third qubit and the second qubit; and performing a two-qubit gate on the fourth qubit and the third qubit; and performing a two-qubit gate on the fourth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the fifth qubit; performing a two-qubit gate on the sixth qubit and the seventh qubit; performing a two-qubit gate on the seventh qubit and the eighth qubit; performing a two-qubit gate on the eighth qubit and the ninth qubit; and Including, in the first control, performing the two-qubit gate for the third qubit and the second qubit after the two-qubit gate for the second qubit and the first qubit and the two-qubit gate for the fourth qubit and the third qubit; In the first control, the two-qubit gate for the seventh qubit and the eighth qubit is executed after the two-qubit gate for the sixth qubit and the seventh qubit and the two-qubit gate for the eighth qubit and the ninth qubit.

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