Sequence pattern generator and transmission start timing control method therefor

Abstract

To provide a sequence pattern generation device capable of controlling Skew between lanes in a plurality of lanes by controlling transmission start timing of a sequence pattern of a plurality of outputs.SOLUTION: A sequence pattern generation device comprises: a primary module 2 and a secondary module 3 each having two data signal outputs; and a device control section 16 by which, when synchronizing starts of sequences of outputs of data signals, delay amounts are set, phases of clocks of the primary module 2 and the secondary module 3 are matched, and the sequences are started with the delay amounts which are set to a primary data generation section 26 and a secondary data generation section 36 after locking the phases of the clocks of the primary data generation section 26 in the primary module 2 and the secondary data generation section 36 in the secondary module 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a sequence pattern generator that generates and outputs any sequence pattern set by a user. [Background technology]

[0002] In recent years, various digital communication devices have been required to have higher transmission capacity due to the increase in the number of users and the spread of multimedia communication. As an index for evaluating the quality of digital signals in these digital communication devices, the bit error rate (BER), which is defined as the number of bit errors in received data compared to the total number of received data, is known.

[0003] In the error rate measurement apparatus for measuring the bit error rate described above, a test signal containing fixed data is transmitted to the device under test, and the signal under test input via the device under test is compared bit by bit with a reference signal, thereby measuring the error rate of the signal under test.

[0004] This type of error rate measuring apparatus uses a pulse pattern generator that generates a data signal with a predetermined pulse pattern that is input as a test signal to a device under test that is compatible with recent high-speed data communications.

[0005] Patent Document 1 describes a pulse pattern generator that sets a master-side phase difference target value according to the frequency of a reference clock signal and also sets a slave-side phase difference target value using correction data in a memory unit in order to keep the phase states of multiple data signals constant. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5432352 Summary of the Invention [Problem to be solved by the invention]

[0007] High-speed serial bus standards such as USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express) have a state machine called the Link Training & Status State Machine (LTSSM), which manages the initialization of communication between devices and the adjustment of link speed.

[0008] Furthermore, conventional error rate measurement devices are equipped with a function (sequence pattern function) that controls PCIe GEN1-5 and USB3.1 LTSSM by rapidly switching specific patterns defined by the standard from a pulse pattern generator (PPG) and causes transition to a specific state. The patterns that cause the device under test (DUT) to transition to a specific state are defined by the standard, and the sequence pattern function can combine and output the output order of these patterns.

[0009] The PCIe standard defines the number of lanes as variations such as x1, x2, x4, x8, and x16, and transmits a pattern defined for each lane to cause the DUT to transition states. The number of lanes varies depending on the DUT.

[0010] If there is only one lane, such as x1, there is no need to consider the operation of the other lanes. However, in order to simultaneously transition states in a DUT with multiple lanes, such as x2 or x4, an allowable skew, which is the allowable time for phase shift between lanes in the pattern input to the DUT, is defined, and the sequence pattern for each lane must be sent to the DUT within the range of shift corresponding to the allowable skew.

[0011] When evaluating a DUT with multiple lanes, current sequence pattern transmitters cannot control the skew of each lane, and therefore cannot transmit sequence patterns within the skew range allowed by PCIe.

[0012] Furthermore, since it is not possible to control the skew of each lane, it is not possible to perform a skew tolerance test to determine how much skew can be handled normally.

[0013] Therefore, an object of the present invention is to provide a sequence pattern generator that can control skew between multiple lanes by controlling the timing at which the transmission of sequence patterns of multiple outputs starts. [Means for solving the problem]

[0014] The sequence pattern generator of the present invention is a sequence pattern generator (1) that can be fitted with one or more modules (2, 3) having one or more data signal outputs, the total number of the data signal outputs being two or more, and is equipped with a device control unit (16) that, when synchronizing the start of a sequence of the data signal outputs, causes the control units (29, 39) of all the modules having outputs to be synchronized to set delay amounts in the data generation units (26, 36), aligns the clock phases of all the modules having outputs to be synchronized, and starts the sequence with the set delay amount after the clock phases of the data generation units of the modules are locked.

[0015] With this configuration, when synchronizing the start of a sequence of data signal outputs, a delay amount is set in the data generator by the control units of all modules with outputs to be synchronized, the clock phases of all modules with outputs to be synchronized are aligned, and once the clock phases of the data generators of the modules are locked, the sequence starts with the set delay amount. Therefore, by controlling the transmission start timing of the sequence patterns of multiple outputs, it is possible to control skew between multiple lanes.

[0016] In the sequence pattern generator of the present invention, the control section controls the delay amount within ±500 mUI by controlling the phase of the clock of the data generation section, and controls the delay amount for the portion of the delay greater than ±500 mUI by shifting the output bits of the data generation section in 1 UI units.

[0017] With this configuration, the delay amount within ±500 mUI is controlled by controlling the clock phase of the data generator, and the delay amount beyond ±500 mUI is controlled by having the data generator shift the output bits in 1 UI increments, making it easy to control the delay amount.

[0018] Furthermore, the transmission start timing control method for a sequence pattern generator of the present invention is a transmission start timing control method for a sequence pattern generator (1) that can be equipped with one or more modules (2, 3) each having one or more data signal outputs, the total number of data signal outputs being two or more, and when synchronizing the start of a sequence of the data signal outputs, comprises the steps of: setting a delay amount in the data generating units (26, 36) of all of the modules having outputs to be synchronized; matching the clock phases of all of the modules having outputs to be synchronized; and starting the sequence with the set delay amount after the clock phases of the data generating units (26, 36) of the modules are locked.

[0019] With this configuration, when synchronizing the start of a sequence of data signal outputs, a delay amount is set in the data generator by the control units of all modules with outputs to be synchronized, the clock phases of all modules with outputs to be synchronized are aligned, and once the clock phases of the data generators of the modules are locked, the sequence starts with the set delay amount. Therefore, by controlling the transmission start timing of the sequence patterns of multiple outputs, it is possible to control skew between multiple lanes. [Effects of the Invention]

[0020] The present invention can provide a sequence pattern generator that can control skew between multiple lanes by controlling the timing at which the transmission of sequence patterns of multiple outputs starts. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram of a sequence pattern generator according to one embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an example of an output setting screen of a sequence pattern generator according to one embodiment of the present invention. [Figure 3] FIG. 3 is a flowchart illustrating the sequence start process of the sequence pattern generating device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A sequence pattern generator according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] 1, a sequence pattern generator 1 according to one embodiment of the present invention includes a primary module 2 and a secondary module 3, each capable of outputting two data signals. The primary module 2 and the secondary module 3 are connected by wiring via a bridge route 4. The primary module 2 and the secondary module 3 may each output one data signal, or two or more data signals.

[0024] The primary module 2 and secondary module 3 are detachably mounted in slots (not shown) in the main body of the measurement device 11. In the slots (not shown) of the measurement device 11, multiple modules such as the primary module 2, secondary module 3, clock module 12, and measurement module 13 are detachably mounted, as shown in FIG.

[0025] As shown in Figure 1, the measuring device 11 is equipped with an operation unit 14, a display unit 15, and a device control unit 16, and multiple modules (primary module 2, secondary module 3, clock module 12, measurement module 13, etc.) selected according to the measurement content can be freely added, removed, or rearranged in slots not shown, allowing various measurements of the object to be measured based on standards in a variety of forms.

[0026] The clock module 12 is configured by a clock generator, and generates a reference clock signal (a half-rate clock or a full-rate clock) to be input to the primary module 2 and the secondary module 3.

[0027] The clock module 12 is not limited to a configuration that can be attached to and detached from a slot (not shown) of the measuring device 11, and an external clock generator separate from the measuring device 11 can also be used.

[0028] The measurement module 13 performs various measurements of the object to be measured based on the set values ​​of the measurement parameters set by operating the operation unit 14 .

[0029] Operation unit 14 includes, for example, a pointing device such as a mouse or touch screen that operates a pointer or icons on the display screen of display unit 15, and keys, switches, buttons, etc. that are provided on the main body of measuring device 11. Operation unit 14 performs initial settings such as the initial value (minimum or maximum value) of the bit rate that can be generated by sequence pattern generator 1, the initial division ratios of primary frequency divider 21 and secondary frequency divider 31 (described later) of primary module 2 and secondary module 3, the initial delay amounts of delay circuit units 22, 23, and 24 of primary module 2 and delay circuit units 32, 33, and 34 of secondary module 3, and the allowable ranges of phase difference target values ​​of primary phase comparator 25 and secondary phase comparator 35, as well as operations related to various measurements, such as issuing instructions to start or stop measurement, specifying a measurement channel for setting measurement parameters, and setting / changing / referring to measurement parameters on the setting screen.

[0030] The display unit 15 is composed of, for example, an LCD display provided on the main body of the measuring device 11, and displays on the display screen a setting screen for performing initial settings on the operation unit 14, a setting screen for a specified measurement channel, a measurement screen, etc.

[0031] The device control unit 16 is composed of a microcomputer equipped with, for example, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc., and controls the primary module 2, secondary module 3, clock module 12, measurement module 13, operation unit 14, and display unit 15, including setting control of each module based on the operation of operation unit 14, variable control of the bit rate, output control of the reference clock signal, various measurement controls of the object to be measured based on the measurement signal, and display control of the setting screen and measurement screen.

[0032] Next, the configurations of the primary module 2 and secondary module 3 that make up the sequence pattern generator 1 will be described.

[0033] As shown in FIG. 1, the primary module 2 is configured to include a primary frequency dividing unit 21, a primary first delay circuit unit 22, a primary second delay circuit unit 23, a primary third delay circuit unit 24, a primary phase comparing unit 25, a primary data generating unit 26, a primary first data multiplexing unit 27, a primary second data multiplexing unit 28, and a primary control unit 29.

[0034] The primary frequency divider 21 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), divides the reference clock signal generated by the clock module 12 or an external clock source by 1 / N, and inputs this 1 / N divided frequency-divided clock signal to the primary first delay circuit 22 and the primary phase comparator 25.

[0035] The reference clock signal is a half-rate clock or full-rate clock of a frequency (e.g., 1.25 GHz to 16 GHz) at which sequence pattern generator 1 can operate, and is generated, for example, by a clock source prepared by the user, an internal synthesizer built into measuring device 11 together with sequence pattern generator 1, or an external synthesizer separate from measuring device 11. Then, a reference clock signal of the same phase is input to primary module 2 and secondary module 3.

[0036] Primary first delay circuit unit 22 is configured by, for example, an IQ modulator, and adjusts the delay amount by varying the phase angle of the frequency-divided clock signal from primary frequency divider unit 21 under the control of primary control unit 29 so that an optimal phase relationship is established between the reference clock signal and the data signal (parallel data) input from primary data generator 26 to primary first data multiplexer 27 and primary second data multiplexer 28. The frequency-divided clock signal with the delay amount adjusted is input to primary phase comparator 25 via primary second delay circuit unit 23, and is also input to secondary second delay circuit unit 33 and secondary third delay circuit unit 34 of secondary module 3 via bridge route 4.

[0037] The primary second delay circuit unit 23 is configured with an electronic delay in which delay elements (gate delays) that adjust the delay amount of the frequency-divided clock signal by electrically switching in units of several picoseconds are connected in multiple stages. The primary second delay circuit unit 23 functions as a bypass circuit that passes the frequency-divided clock signal whose delay amount has been adjusted by the primary first delay circuit unit 22 as is and inputs it to the primary phase comparator unit 25.

[0038] Primary third delay circuit unit 24 is configured with electronic delays similar to those of primary second delay circuit unit 23, and is provided with the same number of electronic delays as the number of transmission lanes of the parallel data generated by primary data generation unit 26. For example, if the number of transmission lanes of parallel data is eight, primary third delay circuit unit 24 is configured with eight electronic delays. This primary third delay circuit unit 24 adjusts the delay amount appropriately for each piece of data under the control of primary control unit 29 in order to adjust the skew of each piece of parallel data input from primary data generation unit 26 to primary first data multiplexing unit 27 and primary second data multiplexing unit 28.

[0039] The primary phase comparison unit 25 compares the phases of the divided clock signal P1 input from the primary frequency dividing unit 21 and the divided clock signal P2 input from the primary frequency dividing unit 21, passing through the primary first delay circuit unit 22 and input from the primary second delay circuit unit 23 via the bridge route 4, treating these signals as clock and data input to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28, and outputs a phase difference signal (voltage signal) P2-P1 corresponding to the phase difference to the primary control unit 29.

[0040] The primary data generating unit 26 is provided on a single FPGA (Field Programmable Gate Array) that is partially configurable, and generates parallel data for a predetermined number of transmission lanes (e.g., 4 Gbps x 8 lanes) as a data signal of any pulse pattern set by the user, at the timing of the divided clock signal from the primary third delay circuit unit 24, and outputs it to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28.

[0041] The primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 are composed of, for example, a multiplexer (MUX) or a D-type flip-flop circuit, and multiplex the parallel data input from the primary data generating unit 26 into serial data at the timing of a reference clock signal and output it.

[0042] The primary control unit 29 controls the primary frequency dividing unit 21, the delay circuit units 22, 23, and 24 of the primary module 2, the primary phase comparison unit 25, the primary data generating unit 26, the primary first data multiplexing unit 27, and the primary second data multiplexing unit 28 in order to synchronize the phases of multiple data signals based on any pulse pattern set by the user and output them.

[0043] The primary control unit 29 stores the primary side phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 as correction data in a table that corresponds to each predetermined step of the frequency (bit rate) of the reference clock signal.

[0044] The primary control unit 29 sets a primary-side phase difference target value that the primary phase comparison unit 25 of the primary module 2 aims at, in accordance with the frequency (bit rate) of the reference clock signal.

[0045] The primary-side phase difference target value has a one-to-one correspondence with each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, the maximum and minimum allowable values ​​are a fixed tolerance range of ±1 cycle (for example, ±31.25 psec for 32 Gbit / s, which corresponds to the cycle in which the phase of the primary frequency divider 21 changes) from the center voltage value. Also, if the reference clock signal is a full-rate clock, the maximum and minimum allowable values ​​are a fixed tolerance range of ±0.5 cycles from the center voltage value.

[0046] Furthermore, when setting a primary-side phase difference target value at a reference clock signal frequency (bit rate) that is not stored in the primary control unit 29, the value is calculated by linear interpolation from two points of correction data at reference clock signal frequencies (bit rates) before and after the reference clock signal frequency (bit rate).

[0047] The primary control unit 29 adjusts and controls the delay amount of each delay circuit unit 22, 23, 24 of the primary module 2. Specifically, when initial settings are performed by the operation unit 14, the primary control unit 29 adjusts and controls each delay circuit unit 22, 23, 24 of the primary module 2 to the initial delay amount.

[0048] In addition, when outputting the four data signals while keeping the pattern generation timing constant, the primary control unit 29 adjusts and controls the delay amount of the primary second delay circuit unit 23 so that the voltage reading value of the primary phase comparison unit 25 (the voltage value according to the phase difference signal P2-P1) becomes approximately equal to the center voltage value.

[0049] Similar to the primary module 2, the secondary module 3 is configured to include a secondary frequency dividing unit 31, a secondary first delay circuit unit 32, a secondary second delay circuit unit 33, a secondary third delay circuit unit 34, a secondary phase comparison unit 35, a secondary data generating unit 36, a secondary first data multiplexing unit 37, a secondary second data multiplexing unit 38, and a secondary control unit 39.

[0050] The secondary frequency divider 31, like the primary frequency divider 21 of the primary module 2, is composed of a 1 / N divider (N: a positive integer of 2 or more), and divides a reference clock signal that is in phase with the reference clock signal input to the primary frequency divider 21 of the primary module 2 by 1 / N, and inputs this 1 / N divided frequency-divided clock signal to the secondary first delay circuit 32 and the secondary phase comparator 35.

[0051] The secondary first delay circuit unit 32 is configured with an IQ modulator, similar to the primary first delay circuit unit 22 of the primary module 2. This secondary first delay circuit unit 32 is essentially an unnecessary component, but is provided to allow commonality between the primary module 2 and the secondary module 3. The output of the secondary first delay circuit unit 32 here is open so that even if a divided clock signal is input from the secondary frequency divider unit 31, it is not output anywhere.

[0052] Similar to primary second delay circuit unit 23 of primary module 2, secondary second delay circuit unit 33 is composed of an electronic delay in which delay elements (gate delays) are connected in multiple stages, which adjust the delay amount of the frequency-divided clock signal by electrically switching in units of several picoseconds, for example. Secondary second delay circuit unit 33 adjusts the delay amount of the frequency-divided clock signal received from primary module 2 under the control of secondary control unit 39 so that the phase relationship between the reference clock signal and the data signal (parallel data) input from secondary data generation unit 36 ​​to secondary first data multiplexing unit 37 and secondary second data multiplexing unit 38 becomes equivalent to the phase relationship between the reference clock signal and the data signal (parallel data) input to primary first data multiplexing unit 27 and primary second data multiplexing unit 28 of primary module 2.

[0053] The secondary third delay circuit unit 34 is configured with electronic delays, similar to the primary third delay circuit unit 24 of the primary module 2, and has the same number of electronic delays as the number of transmission lanes of the parallel data generated by the secondary data generation unit 36. In order to adjust the skew of each piece of parallel data input from the secondary data generation unit 36 ​​to the secondary first data multiplexing unit 37 and secondary second data multiplexing unit 38, the secondary third delay circuit unit 34 adjusts the delay amount appropriately for each piece of data under the control of the secondary control unit 39.

[0054] The secondary phase comparator 35 compares the phase of the divided clock signal S1 from the secondary divider 31 with the divided clock signal S2 input from the secondary second delay circuit 33 via the bridge route 4 from the primary first delay circuit 22 of the primary module 2, and outputs a phase difference signal (voltage signal) corresponding to the phase difference S2-S1 to the secondary control unit 39.

[0055] The secondary data generating unit 36, like the primary data generating unit 26 of the primary module 2, is provided on a single FPGA that is partially configurable, and generates parallel data of a predetermined number of transmission lanes (e.g., 4 Gbps x 8 lanes) as a data signal of any pulse pattern set by the user, at the timing of the divided clock signal from the secondary third delay circuit unit 34, and outputs it to the secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38.

[0056] The secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38, like the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 of the primary module 2, are composed of, for example, a multiplexer (MUX) or a D-type flip-flop circuit, and multiplex the parallel data input from the secondary data generating unit 36 ​​into serial data at the timing of the reference clock signal and output it.

[0057] The secondary control unit 39 controls the secondary frequency dividing unit 31, the delay circuit units 32, 33, and 34 of the secondary module 3, the secondary phase comparison unit 35, the secondary data generating unit 36, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 in order to synchronize the phases of multiple data signals based on any pulse pattern set by the user and output them.

[0058] The secondary control unit 39 stores, as tabular correction data, a secondary-side phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3, and correction values ​​for absorbing delay amount errors caused by variations in the characteristics and wiring of each delay circuit unit 22, 23, 24 of the primary module 2 and each delay circuit unit 32, 33, 34 of the secondary module 3, and phase shifts caused by deterioration in the duty ratio of the primary frequency divider unit 21 and the secondary frequency divider unit 31, which are associated with each predetermined step of the frequency (bit rate) of the reference clock signal.

[0059] The correction value is a value obtained by subtracting the primary-side phase difference target value (voltage read value) from the secondary-side phase difference target value (voltage read value).

[0060] The secondary control unit 39 sets a secondary-side phase difference target value that the secondary phase comparison unit 35 of the secondary module 3 aims at, in accordance with the frequency (bit rate) of the reference clock signal.

[0061] The secondary-side phase difference target value has a one-to-one correspondence with each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, the maximum and minimum allowable values ​​are ±1 cycle (e.g., ±31.25 psec for 32 Gbit / s, which corresponds to the period during which the phase of the secondary frequency divider 31 changes) from the center voltage value. If the reference clock signal is a full-rate clock, the maximum and minimum allowable values ​​are ±0.5 cycles from the center voltage value.

[0062] Furthermore, when setting a secondary-side phase difference target value at a frequency (bit rate) of a reference clock signal that is not stored in the secondary control unit 39, the value is calculated by linear interpolation from two points of correction data at the frequencies (bit rates) of the reference clock signal before and after the frequency (bit rate) of the reference clock signal.

[0063] In addition, correction data can be stored in advance, in which the central voltage value, maximum value, and minimum value of the primary side phase difference target value at each predetermined step of the frequency (bit rate) of the reference clock signal are added with a correction value to become the central voltage value, maximum value, and minimum value of the secondary side phase difference target value.

[0064] The secondary control unit 39 adjusts and controls the delay amount of each delay circuit unit 32, 33, 34 of the secondary module 3. Specifically, when initial settings are performed by the operation unit 14, the secondary control unit 39 adjusts and controls each delay circuit unit 32, 33, 34 of the secondary module 3 to the initial delay amount.

[0065] In addition, when outputting the four data signals while maintaining constant pattern generation timing, the secondary control unit 39 adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the voltage reading value (voltage value corresponding to the phase difference S2-S1) of the secondary phase comparison unit 35 becomes approximately equal to the center voltage value.

[0066] Furthermore, when the secondary control unit 39 determines that the voltage reading value (voltage value corresponding to the phase difference signal P2-P1) of the primary phase comparison unit 25 of the primary module 2 and the voltage reading value (voltage value corresponding to the phase difference signal S2-S1) of the secondary phase comparison unit 35 of the secondary module 3 are not equal, it adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the phase advances or lags by an inverse multiple of the reference clock signal depending on the change state of the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3.

[0067] For example, when the reference clock signal is a half-rate clock, if the voltage read value of the secondary phase comparator 35 is changing in an upward trend, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase is advanced by 2 UI. On the other hand, if the voltage read value of the secondary phase comparator 35 is changing in a downward trend, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase is delayed by 2 UI.

[0068] When the pattern generation timing of the four data signals is kept constant after the initial setting, the secondary control unit 39 inhibits the secondary frequency dividing unit 31 if the bit rate is varied by a predetermined amount.

[0069] When the secondary control unit 39 inhibits the secondary frequency divider unit 31 by varying the bit rate from the initial value (the minimum or maximum value of the bit rate range) in increments of a predetermined amount, it compares the voltage reading (voltage value corresponding to the phase difference signal P2-P1) of the primary phase comparator unit 25 of the primary module 2 with the voltage reading (voltage value corresponding to the phase difference signal S2-S1) of the secondary phase comparator unit 35 of the secondary module 3, and determines whether the two voltage readings are equal (whether P2-P1=S2-S1).

[0070] In the configuration of Figure 1 described above, the primary module 2 and the secondary module 3 have the same internal configuration in order to standardize them, but the secondary first delay circuit section 32 of the secondary module 3 may be omitted.

[0071] In the sequence pattern generator 1 of this embodiment, each of the primary module 2 and secondary module 3 has two outputs (Data1 and Data2), and can output a maximum of four data signals. However, by adding modules, the number of outputs can be increased without being limited to this number.

[0072] When a plurality of data signals are output in synchronization with each other, the sequence pattern generator 1 of this embodiment can control the transmission start timing of each of the outputs of the plurality of data signals.

[0073] The device control section 16 allows the user to set the start timing of outputting the data signal, for example, on an output setting screen 101 as shown in FIG.

[0074] In FIG. 2, a UI unit delay amount designation radio button 111 allows the user to select setting of the amount of change in transmission start timing in UI units (hereinafter also referred to as "delay amount").

[0075] The UI unit delay setting unit 112 sets the amount of delay in units of UIs. When zero is set in the UI unit delay setting unit 112, the transmission start timing is not changed, and when a value other than zero is set, a delay amount according to that value is added. The UI unit delay setting unit 112 sets the amount of delay in units of mUIs, for example. The UI unit delay setting unit 112 can set a delay amount of ±128 UI in units of 2 mUIs, for example.

[0076] The second-unit delay amount specification radio button 113 allows the user to select setting the delay amount in seconds.

[0077] The second-unit delay setting unit 114 sets the delay amount in units of seconds. When zero is set in the second-unit delay setting unit 114, the transmission start timing is not changed, and when a value other than zero is set, a delay amount according to the value is added. The second-unit delay setting unit 114 sets the delay amount in units of picoseconds, for example.

[0078] When either the UI unit delay amount specification radio button 111 or the second unit delay amount specification radio button 113 is turned on, the other is turned off.

[0079] If the delay amount is a positive number, the transmission start timing is delayed from the reference time for synchronization, and if it is a negative number, the transmission start timing is advanced from the reference time for synchronization.

[0080] The control units 29 and 39 control the delay amount within ±500 mUI by controlling the phase of the clock input to the data generation units 26 and 36 .

[0081] The control units 29 and 39 control the amount of delay for a portion of the delay greater than ±500 mUI by causing the data generation units 26 and 36 to shift the output bits in 1 UI units.

[0082] For example, when a delay of 2.3 UI is to be generated, the control units 29 and 39 generate a delay of 0.3 UI by controlling the phase of the clock in addition to a bit shift of 2 UI in the data generation units 26 and 36.

[0083] The operation differs between synchronizing two outputs within modules 2 and 3 and synchronizing outputs across modules 2 and 3. The settings for the outputs to be synchronized and the delay amount are input by operating the operation unit 14 and stored in the device control unit 16.

[0084] When two outputs in modules 2 and 3 are synchronized, when the start of transmission is selected for one of the outputs by input to operation unit 14, device control unit 16 notifies control units 29 and 39 of modules 2 and 3 of the set delay amount, and causes data generation units 26 and 36 to set the delay amount.

[0085] The control units 29 and 39 control the clocks and bit shifts of the data generating units 26 and 36 in accordance with the set delay amount.

[0086] The device control unit 16 sends a request to the control units 29 and 39 of the modules 2 and 3 to reset the internal circuits of the sequencers.

[0087] When the control units 29 and 39 receive a request to reset the internal circuits of the sequencer, they reset the data generation units 26 and 36. When the resetting of the data generation units 26 and 36 is completed, the control units 29 and 39 transmit a reset completion notification to the device control unit 16. When the resetting of the data generation units 26 and 36 is completed, the data generation units 26 and 36 enter a reset state.

[0088] When the device control unit 16 receives the reset completion from the control units 29 and 39, it transmits a reset release to the control units 29 and 39.

[0089] When the control units 29, 39 receive the reset release, they release the reset state of the data generation units 26, 36. When the reset state is released, the data generation units 26, 36 start generating sequence data with the set delay amount and output it to the first data multiplexing units 27, 37 and the second data multiplexing units 28, 38.

[0090] In this way, when synchronizing two outputs in modules 2 and 3, clock synchronization is established within modules 2 and 3, so by resetting data generating units 26 and 36 and then releasing the reset, a delay is added, the sequence is started, and the timing at which the sequence transmission starts can be controlled.

[0091] When synchronizing outputs across modules 2 and 3, when an input to operation unit 14 selects the start of transmission for one of the outputs to be synchronized, device control unit 16 notifies control units 29 and 39 of modules 2 and 3 of the set delay amount, and causes data generation units 26 and 36 to set the delay amount.

[0092] The control units 29 and 39 control the clocks and bit shifts of the data generating units 26 and 36 in accordance with the set delay amount.

[0093] The device control unit 16 sets all outputs that are the targets for starting transmission to a state in which the start of transmission has been selected.

[0094] The device control section 16 causes the control sections 29 and 39 to perform clock phase control so that the clocks of all modules having outputs to be synchronized are synchronized.

[0095] When the device control unit 16 completes the clock phase control, it waits until the clock phases of the data generation units 26, 36 of all modules having outputs to be synchronized are locked.

[0096] The data generators 26 and 36 are composed of FPGAs, and the clock is input to the FPGA transceiver. The FPGA transceiver divides and multiplies the clock internally, using a PLL (phase locked loop) here. If the frequency or phase of the input clock changes significantly, the PLL will lose phase lock.

[0097] For this reason, the device control unit 16 waits until the phases of the data generation units 26 and 36 are locked after they are unlocked. Until the phases are locked, the clock output from the PLL is unstable, and a stable clock can be obtained after the phases are locked.

[0098] When the clock phases of the data generating units 26, 36 of all modules having outputs to be synchronized are locked, the device control unit 16 sends a request to reset the internal circuits of the sequence to the control units 29, 39 of all modules having outputs to be synchronized.

[0099] When the control units 29 and 39 receive a request to reset the internal circuits of the sequencer, they reset the data generation units 26 and 36. When the resetting of the data generation units 26 and 36 is completed, the control units 29 and 39 transmit a reset completion notification to the device control unit 16. When the resetting of the data generation units 26 and 36 is completed, the data generation units 26 and 36 enter a reset state.

[0100] When the device control unit 16 receives the reset completion from the control units 29 and 39, it transmits a reset release to the control units 29 and 39.

[0101] When the control units 29, 39 receive the reset release, they release the reset state of the data generation units 26, 36. When the reset state is released, the data generation units 26, 36 start generating sequence data with the set delay amount and output it to the first data multiplexing units 27, 37 and the second data multiplexing units 28, 38.

[0102] In this way, when synchronizing outputs across modules 2 and 3, the clock phases of all modules having outputs to be synchronized are aligned, and the sequence is started only after the clock phases of data generators 26 and 36 are locked, so a delay is added before the sequence is started, making it possible to control the timing at which the sequence transmission starts.

[0103] The sequence start process performed by the sequence pattern generator 1 according to this embodiment configured as described above will be described with reference to Fig. 3. The sequence start process described below is started when an input to the operation unit 14 selects the start of transmission for any one of the outputs to be synchronized.

[0104] In step S1, device control unit 16 notifies control units 29 and 39 of all modules having outputs to be synchronized of the delay amounts set for all outputs to be synchronized, and causes them to set the delay amounts. After executing the process of step S1, device control unit 16 executes the process of step S2.

[0105] In step S2, the device control unit 16 determines whether or not the synchronization setting is inter-module synchronization.

[0106] If it is determined that inter-module synchronization exists, device control section 16 executes the process of step S3. If it is determined that inter-module synchronization does not exist, device control section 16 executes the process of step S6.

[0107] In step S3, device control unit 16 sets all outputs to be synchronized to a state in which start of transmission has been selected. After executing the process of step S3, device control unit 16 executes the process of step S4.

[0108] In step S4, device control unit 16 causes control units 29 and 39 to perform clock phase control so that the clocks of all modules having outputs to be synchronized are synchronized. After executing the process of step S4, device control unit 16 executes the process of step S5.

[0109] In step S5, device control unit 16 waits for the clock phases of data generation units 26, 36 of all modules having outputs to be synchronized to be locked. After executing the process of step S5, device control unit 16 executes the process of step S6.

[0110] In step S6, device control unit 16 causes control units 29, 39 of all modules having outputs to be synchronized to reset data generation units 26, 36. After executing the process of step S6, device control unit 16 executes the process of step S7.

[0111] In step S7, the device control section 16 determines whether or not the resetting of the data generating sections 26 and 36 has been completed.

[0112] If it is determined that the resetting of the data generating units 26, 36 is complete, the device control unit 16 executes the process of step S8. If it is determined that the resetting of the data generating units 26, 36 is not complete, the device control unit 16 executes the process of step S7.

[0113] In step S8, the device control unit 16 causes the control units 29, 39 of all modules having outputs to be synchronized to release the reset states of the data generation units 26, 36. After executing the process of step S8, the data generation units 26, 36 execute the process of step S9.

[0114] In step S9, the data generating sections 26 and 36 start transmitting the sequence pattern with the set delay amount. After executing the process of step S9, the device control section 16 ends the sequence start process.

[0115] The delay amount can be set in step S1 not only at the start of the sequence, but also at any timing, for example, while the sequence is being transmitted.

[0116] In this way, in the above-described embodiment, when synchronizing the output of a data signal, the device control unit 16 causes the control units 29, 39 of all modules having outputs to be synchronized to set delay amounts in the data generation units 26, 36, aligns the clock phases of all modules having outputs to be synchronized, and starts the sequence with the set delay amount once the clock phases of the data generation units 26, 36 are locked.

[0117] As a result, when synchronizing the output of data signals, delay amounts are set in the data generators 26, 36 by the control units 29, 39 of all modules having outputs to be synchronized, the clock phases of all modules having outputs to be synchronized are aligned, and once the clock phases of the data generators 26, 36 are locked, the sequence starts with the set delay amount. Therefore, by controlling the transmission start timing of the sequence patterns of multiple outputs, it is possible to control skew between multiple lanes.

[0118] Furthermore, the control units 29 and 39 control the delay amount within ±500 mUI by controlling the phase of the clock of the data generation units 26 and 36, and control the delay amount for the portion of the delay amount greater than ±500 mUI by causing the data generation units 26 and 36 to shift the output bits in 1 UI units.

[0119] As a result, for delays within ±500 mUI, the delay amount is controlled by controlling the phase of the clocks of the data generators 26 and 36, and for delays greater than ±500 mUI, the delay amount is controlled by having the data generators 26 and 36 shift the output bits in 1 UI units. This makes it easy to control the delay amount.

[0120] In this embodiment, the measuring device 11 is shown as being equipped with an operation unit 14, a display unit 15, and a device control unit 16, but a personal computer connected to the measuring device 11 may also be configured to perform the functions of the operation unit 14, the display unit 15, and the device control unit 16.

[0121] While an embodiment of the present invention has been disclosed, it will be apparent to one skilled in the art that modifications may be made thereto without departing from the scope of the present invention, and it is intended that all such modifications and equivalents be included in the following claims. [Explanation of symbols]

[0122] 1 Sequence pattern generator 2 Primary Module 3 Secondary Modules 14 Control section 15 Display 16 Device control section 26 Primary Data Generator 29 Primary control section 36 Secondary Data Generator 39 Secondary control section

Claims

1. A sequence pattern generator (1) capable of mounting one or more modules (2, 3) each having one or more data signal outputs, the total number of the data signal outputs being two or more, A sequence pattern generating device comprising a device control unit (16) that, when synchronizing the start of a sequence of data signal outputs, causes the control units (29, 39) of all of the modules having outputs to be synchronized to set delay amounts in the data generating units (26, 36), aligns the phases of the clocks of all of the modules having outputs to be synchronized, and starts the sequence with the set delay amount after the phases of the clocks of the data generating units of the modules are locked.

2. 2. The sequence pattern generator according to claim 1, wherein the control unit controls the delay amount within ±500 mUI by controlling the phase of the clock of the data generation unit, and controls the delay amount for a portion of the delay amount greater than ±500 mUI by shifting output bits of the data generation unit in 1 UI units.

3. A transmission start timing control method for a sequence pattern generator (1) capable of mounting one or more modules (2, 3) each having one or more data signal outputs, the total number of which is two or more, comprising: When synchronizing the start of the sequence of output of the data signal, a step of setting a delay amount in the data generating units (26, 36) of all the modules having outputs to be synchronized; a step of synchronizing the phases of the clocks of all of the modules having outputs to be synchronized; and starting a sequence with a set delay amount after the phase of the clock of the data generating unit (26, 36) of the module is locked.

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