Matrix-weighted intra-prediction of video signals

Abstract

The present disclosure provides a method for performing simplified matrix-weighted intra prediction, which may include determining a classification of a target block and generating a matrix-weighted intra prediction (MIP) signal based on the classification, where determining the classification of the target block includes determining that the target block belongs to a first class depending on whether the target block has a size of 4x4, or determining that the target block belongs to a second class depending on whether the target block has a size of 8x8, 4xN, or Nx4 (where N is an integer from 8 to 64).

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 894,489, filed August 30, 2019, which is incorporated by reference in its entirety.

[0002] Technical Field FIELD OF THE DISCLOSURE

[0002] The present disclosure relates generally to video processing, and more particularly to methods and systems for performing simplified matrix weighted intra prediction of video signals. [Background technology]

[0003] background

[0003] A video is a set of static pictures (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, most commonly based on prediction, transform, quantization, entropy coding, and in-loop filtering. Video coding standards, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Versatile Video Coding (VVC / H.266) standard, and the AVS standard, which specify specific video coding formats, are developed by standardization organizations. As more advanced video coding techniques are adopted into video standards, the coding efficiency of new video coding standards becomes higher. Summary of the Invention [Means for solving the problem]

[0004] Disclosure Overview

[0004] An embodiment of the present disclosure provides a method for performing simplified matrix-weighted intra prediction. The method may include determining a classification of a target block and generating a matrix-weighted intra prediction (MIP) signal based on the classification, where determining the classification of the target block includes determining that the target block belongs to a first class according to the target block having a size of 4x4, or determining that the target block belongs to a second class according to the target block having a size of 8x8, 4xN, or Nx4 (where N is an integer from 8 to 64).

[0005]

[0005] Embodiments of the present disclosure also provide a system for performing simplified matrix-weighted intra prediction. The system may include a memory for storing a set of instructions and at least one processor configured to execute the set of instructions to cause the system to determine a classification of a target block and generate a matrix-weighted intra prediction (MIP) signal based on the classification, wherein determining the classification of the target block includes determining that the target block belongs to a first class depending on whether the target block has a size of 4x4, or determining that the target block belongs to a second class depending on whether the target block has a size of 8x8, 4xN, or Nx4, where N is an integer between 8 and 64.

[0006]

[0006] An embodiment of the present disclosure provides a non-transitory computer-readable medium storing a set of instructions, the set of instructions being executable by at least one processor of a computer system to cause the computer system to perform a method for processing video content. The method may include determining a classification of a target block and generating a matrix-weighted intra-prediction (MIP) signal based on the classification, wherein determining the classification of the target block includes determining that the target block belongs to a first class in accordance with the target block having a size of 4x4, or determining that the target block belongs to a second class in accordance with the target block having a size of 8x8, 4xN, or Nx4, where N is an integer between 8 and 64.

[0007] BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying drawings, in which various features are not drawn to scale. [Brief explanation of the drawings]

[0008] [Figure 1] 8 illustrates the structure of an exemplary video sequence consistent with embodiments of the present disclosure. [Figure 2A]

[0009] 1 shows a schematic diagram of an exemplary encoding process performed by a hybrid video coding system consistent with embodiments of the present disclosure. [Figure 2B]

[0010] 1 shows a schematic diagram of another exemplary encoding process performed by a hybrid video coding system consistent with embodiments of the present disclosure. [Figure 3A]

[0011] 1 shows a schematic diagram of an exemplary decoding process performed by a hybrid video coding system consistent with embodiments of the present disclosure. [Figure 3B]

[0012] 1 shows a schematic diagram of another exemplary decoding process performed by a hybrid video coding system consistent with embodiments of the present disclosure. [Figure 4]

[0013] 1 is a block diagram of an exemplary device for encoding or decoding video consistent with embodiments of the present disclosure. [Figure 5]

[0014] 1 shows an exemplary schematic diagram of matrix weighted intra prediction, consistent with embodiments of the present disclosure. [Figure 6]

[0015] 1 shows a table containing three exemplary classes used in matrix weighted intra prediction consistent with embodiments of this disclosure. [Figure 7]

[0016] 10 shows an exemplary lookup table for determining the offset "sO", consistent with embodiments of the present disclosure. [Figure 8]

[0017] 10 shows an exemplary lookup table for determining the shift "sW", consistent with embodiments of the present disclosure. [Figure 9]

[0018] 10 illustrates an example matrix illustrating an example exclusion operation consistent with embodiments of the present disclosure. [Figure 10]

[0019] 10 shows another example matrix illustrating another example exclusion operation consistent with embodiments of the present disclosure. [Figure 11]

[0020] 1 is a flowchart of an exemplary method for processing video content consistent with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Detailed Description

[0021] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which, unless otherwise indicated, like numerals in different figures represent the same or similar elements. The implementations described in the following description of exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with aspects related to the present invention as recited in the appended claims. Unless otherwise specified, the term "or" encompasses all possible combinations, unless impracticable. For example, if a component is stated to include A or B, that component can include A or B, or A and B, unless otherwise specified or impracticable. As a second example, if a component is stated to include A, B, or C, that component can include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise specified or impracticable.

[0010]

[0022] Video coding systems are often used to compress digital video signals, for example to reduce the storage space consumed or to reduce the transmission bandwidth consumption associated with such signals. With the increasing popularity of high-definition (HD) video (e.g., having a resolution of 1920x1080 pixels) in various applications of video compression, such as online video streaming, video conferencing, or video surveillance, there is a continuing need to develop video coding tools that can increase the efficiency of compressing video data.

[0011]

[0023] For example, video surveillance applications are becoming more and more widely used in many application scenarios (e.g., security, traffic, environmental monitoring, etc.), and the number and resolution of surveillance devices are increasing rapidly. Many video surveillance application scenarios choose to provide users with HD video to capture more information, and HD video has more pixels per frame to capture such information. However, HD video bitstreams may have high bitrates that require high bandwidth for transmission and large storage space. For example, a surveillance video stream with an average resolution of 1920 x 1080 may require as much as 4 Mbps of bandwidth for real-time transmission. Furthermore, video surveillance generally involves continuous monitoring, which can pose great challenges to storage systems when storing video data. Therefore, the high bandwidth and large storage space demands of HD video have become major limitations to the large-scale deployment of HD video in video surveillance.

[0012]

[0024] A video is a set of still pictures (or "frames") arranged in chronological order to store visual information. A video capture device (e.g., a camera) can be used to capture and store these pictures in chronological order, and a video playback device (e.g., a television, a computer, a smartphone, a tablet computer, a video player, or any end-user terminal with display capabilities) can be used to display these pictures in chronological order. Furthermore, in some applications, a video capture device can transmit captured video in real time to a video playback device (e.g., a computer with a monitor) for purposes such as surveillance, conferencing, or live broadcasting.

[0013]

[0025] To reduce the storage space and transmission bandwidth required by such applications, video can be compressed before storage and transmission and decompressed before display. This compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or dedicated hardware. A module for compression is generally referred to as an "encoder," and a module for decompression is generally referred to as a "decoder." Encoders and decoders can be collectively referred to as a "codec." Encoders and decoders can be implemented as various suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders may include circuitry such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders may include program code, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process fixed in a computer-readable medium. Video compression and decompression may be implemented by various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, H.26x series, etc. In some applications, a codec may decompress video from a first coding standard and recompress the decompressed video using a second coding standard, in which case the codec may be called a "transcoder."

[0014]

[0026] A video coding process can identify and retain useful information that can be used to reconstruct a picture and ignore information that is not important for reconstruction. If the ignored, unimportant information cannot be perfectly reconstructed, then such a coding process can be called "lossy." Otherwise, such a coding process can be called "lossless." Most coding processes are lossy; this is a tradeoff to reduce the required storage space and transmission bandwidth.

[0015]

[0027] Useful information about the picture being coded (called the "current picture") includes changes relative to a reference picture (e.g., a previously coded and reconstructed picture). Such changes can include pixel position changes, luminance changes, or color changes, of which position changes are the most relevant. Position changes of pixels representing an object can reflect the object's movement between the reference picture and the current picture.

[0016]

[0028] Depending on whether the reference picture is the current picture itself or another picture, the coding of the current picture can be classified as "inter prediction" and "intra prediction." Intra prediction can exploit spatial redundancy (e.g., correlation between pixels within a frame) by calculating a predicted value by extrapolation from already coded pixels. Inter prediction can exploit temporal differences (e.g., motion vectors) between adjacent frames (e.g., a reference frame and a target frame) and may enable the codec of the target frame. This disclosure relates to techniques used for intra prediction.

[0017]

[0029] The present disclosure provides a method, an apparatus, and a system for performing simplified matrix-weighted intra prediction of a video signal. By eliminating redundant matrix subtraction operations in the MIP prediction process, the prediction process of blocks with different sizes can be unified and the calculation process can also be simplified.

[0018]

[0030] 1 illustrates the structure of an example video sequence 100 consistent with embodiments of the present disclosure. Video sequence 100 may be live video or captured and archived video. Video 100 may be real video, computer-generated video (e.g., computer game video), or a combination thereof (e.g., real video with augmented reality effects). Video sequence 100 may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., video files stored in a storage device), or a video feed interface (e.g., a video broadcast transceiver) for receiving video from a video content provider.

[0019]

[0031] As shown in FIG. 1, video sequence 100 may include a series of pictures arranged temporally along a timeline, including pictures 102, 104, 106, and 108. Pictures 102-106 are consecutive, with more pictures between pictures 106 and 108. In FIG. 1, picture 102 is an I-picture, and its reference picture is picture 102 itself. Picture 104 is a P-picture, and its reference picture is picture 102, as indicated by the arrow. Picture 106 is a B-picture, and its reference pictures are pictures 104 and 108, as indicated by the arrows. In some embodiments, the reference picture of a picture (e.g., picture 104) need not immediately precede or follow that picture. For example, the reference picture of picture 104 may be a picture preceding picture 102. It should be noted that the reference pictures of pictures 102-106 are merely examples, and this disclosure does not limit the reference picture embodiments to the examples shown in FIG.

[0020]

[0032] Typically, video codecs do not encode or decode an entire picture at once because such a task is computationally complex. Rather, video codecs may divide a picture into elementary segments and encode or decode the picture segment by segment. In this disclosure, such elementary segments are referred to as basic processing units ("BPUs"). For example, structure 110 in FIG. 1 illustrates an example structure for a picture (e.g., any of pictures 102-108) in video sequence 100. In structure 110, the picture is divided into 4x4 basic processing units, the boundaries of which are indicated by dashed lines. In some embodiments, the basic processing units may be referred to as "macroblocks" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC) and as "coding tree units" ("CTUs") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). Basic processing units can have variable sizes within a picture, such as 128x128, 64x64, 32x32, 16x16, 4x8, 16x32, or any arbitrary shape and size of pixels. The size and shape of the basic processing unit can be selected for a picture based on a balance between coding efficiency and the level of detail one wishes to preserve within the basic processing unit.

[0021]

[0033] A basic processing unit may be a logical unit that may include various types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color picture may include a luma component (Y) representing achromatic luminance information, one or more chroma components (e.g., Cb and Cr) representing color information, and associated syntax elements of the basic processing unit, where the luma and chroma components may have the same size. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luma and chroma components may be referred to as "coding tree blocks" ("CTBs"). Any operation performed on a basic processing unit can be repeated for each of its luma and chroma components.

[0022]

[0034] Video coding involves multiple stages of operation, examples of which are detailed in Figures 2A-2B and 3A-3B. For each stage, the size of the basic processing unit may still be too large to process and therefore may be further divided into segments referred to in this disclosure as "basic processing sub-units." In some embodiments, the basic processing sub-units may be referred to as "blocks" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC) or as "coding units" ("CUs") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing sub-units may have the same or smaller size than the basic processing units. Similar to basic processing units, basic processing sub-units are also logical units that may contain various types of video data (e.g., Y, Cb, Cr, and related syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on a basic processing sub-unit can be repeated for each of its luma and chroma components. It should be noted that such division can be performed to further levels depending on the processing needs. It should also be noted that different stages can divide the basic processing unit using different schemes.

[0023]

[0035] For example, in a mode decision stage (one example of which is detailed in FIG. 2B ), the encoder may decide which prediction mode (e.g., intra-picture prediction or inter-picture prediction) to use for a basic processing unit, which may be too large to make such a decision. The encoder may divide the basic processing unit into multiple basic processing sub-units (e.g., CUs in H.265 / HEVC or H.266 / VVC) and determine the type of prediction for each individual basic processing sub-unit.

[0024]

[0036] As another example, in the prediction stage (one example of which is detailed in FIG. 2A), the encoder may perform prediction operations at the level of elementary processing sub-units (e.g., CUs). However, in some cases, elementary processing sub-units may still be too large to process. The encoder may further divide the elementary processing sub-units into smaller segments (e.g., called "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC) and perform prediction operations at that level.

[0025]

[0037] As another example, in the transform stage (one example of which is detailed in FIG. 2A ), the encoder may perform a transform operation on a residual elementary processing sub-unit (e.g., a CU). However, in some cases, the elementary processing sub-unit may still be too large to process. The encoder may further divide the elementary processing sub-unit into smaller segments (e.g., called "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC) and perform the transform operation at that level. It should be noted that the division scheme of the same elementary processing sub-unit may be different between the prediction stage and the transform stage. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU may have different sizes and numbers.

[0026]

[0038] In structure 110 of Figure 1, basic processing units 112 are further divided into 3x3 basic processing sub-units, the boundaries of which are shown by dotted lines. Different basic processing units of the same picture can be divided into basic processing sub-units in different ways.

[0027]

[0039] In some implementations, to provide parallel processing and error resilience for video encoding and decoding, a picture can be divided into regions for processing, thereby allowing the encoding or decoding process for a region of a picture to not depend on information from any other region of the picture. In other words, each region of a picture can be processed independently. This allows a codec to process different regions of a picture in parallel, thus increasing coding efficiency. Furthermore, if data for a region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same picture without relying on the corrupted or lost data, thus providing error resilience. Some video coding standards allow a picture to be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: "slices" and "tiles." It should also be noted that various pictures in video sequence 100 may have different partitioning schemes for dividing the picture into regions.

[0028]

[0040] For example, in Figure 1, structure 110 is divided into three regions 114, 116, and 118, the boundaries of which are shown as solid lines within structure 110. Region 114 includes four basic processing units. Regions 116 and 118 each include six basic processing units. It should be noted that the basic processing units, basic processing sub-units, and regions of structure 110 in Figure 1 are merely examples, and the present disclosure does not limit the embodiments thereof.

[0029]

[0041] FIG. 2A shows a schematic diagram of an example encoding process 200A consistent with embodiments of this disclosure. An encoder may encode a video sequence 202 into a video bitstream 228 according to process 200A. Similar to video sequence 100 of FIG. 1, video sequence 202 may include a set of pictures (referred to as "original pictures") arranged in chronological order. Similar to structure 110 of FIG. 1, each original picture of video sequence 202 may be divided by the encoder into basic processing units, basic processing sub-units, or regions for processing. In some embodiments, the encoder may perform process 200A at the level of the basic processing units for each original picture of video sequence 202. For example, the encoder may perform process 200A in an iterative manner, where the encoder may encode a basic processing unit in one iteration of process 200A. In some embodiments, the encoder may perform process 200A in parallel for regions (e.g., regions 114-118) of each original picture of video sequence 202.

[0030]

[0042] 2A , an encoder may feed a basic processing unit (referred to as an “original BPU”) of an original picture of a video sequence 202 to a prediction stage 204 to generate prediction data 206 and a predicted BPU 208. The encoder may subtract the predicted BPU 208 from the original BPU to generate a residual BPU 210. The encoder may feed the residual BPU 210 to a transform stage 212 and a quantization stage 214 to generate quantized transform coefficients 216. The encoder may feed the prediction data 206 and the quantized transform coefficients 216 to a binary coding stage 226 to generate a video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 may be referred to as a “forward path.” During process 200A, after quantization stage 214, the encoder may feed quantized transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate a reconstructed residual BPU 222. The encoder may add the reconstructed residual BPU 222 to predicted BPU 208 to generate a prediction reference 224 used in prediction stage 204 of the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A may be referred to as a "reconstruction path." The reconstruction path may be used to ensure that both the encoder and decoder use the same reference data for prediction.

[0031]

[0043] The encoder may iteratively perform process 200A to encode each original BPU of the original picture (in the forward path) and generate a predicted reference 224 for encoding the next original BPU of the original picture (in the reconstruction path). After encoding all original BPUs of the original picture, the encoder may proceed to encode the next picture in the video sequence 202.

[0032]

[0044] Referring to process 200A, an encoder may receive a video sequence 202 generated by a video capture device (e.g., a camera). As used herein, the term "receive" may refer to receiving, inputting, obtaining, retrieving, acquiring, reading, accessing, or any action in any manner to input data.

[0033]

[0045] In the prediction stage 204, in the current iteration, the encoder receives the original BPU and a prediction reference 224 and can perform a prediction operation to generate prediction data 206 and a predicted BPU 208. The prediction reference 224 can be generated from the reconstruction path of a previous iteration of the process 200A. The purpose of the prediction stage 204 is to reduce information redundancy by extracting prediction data 206 from the prediction data 206 and the prediction reference 224 that can be used to reconstruct the original BPU as a predicted BPU 208.

[0034]

[0046] Ideally, predicted BPU 208 would be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, predicted BPU 208 generally differs slightly from the original BPU. To record such differences, after generating predicted BPU 208, the encoder may subtract it from the original BPU to generate residual BPU 210. For example, the encoder may subtract pixel values ​​(e.g., grayscale or RGB values) of predicted BPU 208 from corresponding pixel values ​​of the original BPU. As a result of such subtraction between corresponding pixels of the original BPU and predicted BPU 208, each pixel of residual BPU 210 may have a residual value. Compared to the original BPU, prediction data 206 and residual BPU 210 may have fewer bits, which can be used to reconstruct the original BPU without significant loss of quality.

[0035]

[0047] To further compress the residual BPU 210, in the transform stage 212, the encoder can reduce spatial redundancy in the residual BPU 210 by decomposing the residual BPU 210 into a set of two-dimensional "basis patterns," each associated with a "transform coefficient." The basis patterns can have the same size (e.g., the size of the residual BPU 210). Each basis pattern can represent a variation frequency (e.g., luminance variation frequency) component of the residual BPU 210. None of the basis patterns can be reconstructed from any combination (e.g., a linear combination) of any other basis patterns. In other words, the decomposition can decompose the variation of the residual BPU 210 into the frequency domain. Such a decomposition is similar to a discrete Fourier transform of a function, the basis patterns are similar to basis functions (e.g., trigonometric functions) of the discrete Fourier transform, and the transform coefficients are similar to the coefficients associated with the basis functions.

[0036]

[0048] Different transform algorithms can use different basis patterns. For example, various transform algorithms can be used in transform stage 212, such as a discrete cosine transform, a discrete sine transform, etc. The transform in transform stage 212 is reversible. That is, the encoder can reconstruct residual BPU 210 by inversely operating the transform (referred to as an "inverse transform"). For example, to reconstruct a pixel of residual BPU 210, the inverse transform can multiply the value of the corresponding pixel in the basis pattern by the associated respective coefficient and add the products to obtain a weighted sum. In video coding standards, both the encoder and decoder can use the same transform algorithm (and therefore the same basis pattern). Therefore, the encoder can record only the transform coefficients, and the decoder can reconstruct residual BPU 210 from the transform coefficients without receiving the basis pattern from the encoder. Although the transform coefficients may have fewer bits compared to residual BPU 210, they can be used to reconstruct residual BPU 210 without significant loss of quality. Therefore, the residual BPU 210 is further compressed.

[0037]

[0049] The encoder can further compress the transform coefficients in the quantization stage 214. In the transform process, different basis patterns can represent different fluctuation frequencies (e.g., luminance fluctuation frequencies). Because the human eye is generally good at recognizing low-frequency fluctuations, the encoder can ignore high-frequency fluctuation information without causing significant quality degradation during decoding. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (referred to as a "quantization parameter") and rounding the quotient to its nearest neighbor. After such an operation, some transform coefficients of high-frequency basis patterns can be converted to zero, and transform coefficients of low-frequency basis patterns can be converted to smaller integers. The encoder can ignore zero-valued quantized transform coefficients 216, thereby further compressing the transform coefficients. The quantization process is also invertible, and the quantized transform coefficients 216 can be reconstructed into transform coefficients in the inverse operation of quantization (referred to as "dequantization").

[0038]

[0050] Quantization stage 214 may be lossy because the encoder ignores the remainder of such a division in a rounding operation. Typically, quantization stage 214 may contribute the greatest information loss in process 200A. The greater the information loss, the fewer bits the quantized transform coefficients 216 may require. To achieve different levels of information loss, the encoder may use different values ​​of the quantization parameter or any other parameter of the quantization process.

[0039]

[0051] In the binary coding stage 226, the encoder may encode the prediction data 206 and the quantized transform coefficients 216 using a binary coding technique, such as entropy coding, variable length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the encoder may encode other information in the binary coding stage 226, such as the prediction mode used in the prediction stage 204, parameters of the prediction operation, the type of transform in the transform stage 212, parameters of the quantization process (e.g., quantization parameters), and encoder control parameters (e.g., bitrate control parameters). The encoder may generate a video bitstream 228 using the output data of the binary coding stage 226. In some embodiments, the video bitstream 228 may be further packetized for network transmission.

[0040]

[0052] Referring to the reconstruction path of process 200A, in an inverse quantization stage 218, the encoder may perform inverse quantization on the quantized transform coefficients 216 to generate reconstructed transform coefficients. In an inverse transform stage 220, the encoder may generate a reconstructed residual BPU 222 based on the reconstructed transform coefficients. The encoder may add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224 to be used in the next iteration of process 200A.

[0041]

[0053] It should be noted that other variations of process 200A can be used to encode video sequence 202. In some embodiments, an encoder can perform the stages of process 200A in a different order. In some embodiments, one or more stages of process 200A can be combined into a single stage. In some embodiments, a single stage of process 200A can be separated into multiple stages. For example, transform stage 212 and quantization stage 214 can be combined into a single stage. In some embodiments, process 200A can include additional stages. In some embodiments, process 200A can omit one or more stages in FIG. 2A .

[0042]

[0054] 2B shows a schematic diagram of another example encoding process 200B consistent with embodiments of the present disclosure. Process 200B may be modified from process 200A. For example, process 200B may be used by an encoder compliant with a hybrid video coding standard (e.g., the H.26x series). Compared to process 200A, the forward path of process 200B further includes a mode decision stage 230 and separates prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B additionally includes a loop filter stage 232 and a buffer 234.

[0043]

[0055] Generally, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-picture prediction or "intra-prediction") can use pixels of one or more already coded neighboring BPUs in the same picture to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs. Spatial prediction can reduce the inherent spatial redundancy of a picture. Temporal prediction (e.g., inter-picture prediction or "inter-prediction") can use regions of one or more already coded pictures to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include coded pictures. Temporal prediction can reduce the inherent temporal redundancy of a picture.

[0044]

[0056] Referring to process 200B, in the forward path, the encoder performs prediction operations in a spatial prediction stage 2042 and a temporal prediction stage 2044. For example, in the spatial prediction stage 2042, the encoder may perform intra prediction. With respect to an original BPU of a picture being coded, the prediction reference 224 may include one or more neighboring BPUs coded (in the forward path) and reconstructed (in the reconstruction path) within the same picture. The encoder may generate the predicted BPU 208 by extrapolating the neighboring BPUs. Extrapolation techniques may include, for example, linear extrapolation or interpolation, polynomial extrapolation or interpolation, etc. In some embodiments, the encoder may perform extrapolation at the pixel level, such as by extrapolating the value of a corresponding pixel for each pixel of the predicted BPU 208. The neighboring BPUs used for extrapolation may be located relative to the original BPU from various directions, such as vertically (e.g., above the original BPU), horizontally (e.g., to the left of the original BPU), diagonally (e.g., bottom-left, bottom-right, top-left, or top-right of the original BPU), or any direction specified within the video coding standard used. For intra prediction, the prediction data 206 may include, for example, the positions (e.g., coordinates) of the neighboring BPUs used, the sizes of the neighboring BPUs used, parameters of the extrapolation, the orientation of the neighboring BPUs used relative to the original BPU, etc.

[0045]

[0057] As another example, in the temporal prediction stage 2044, the encoder may perform inter-prediction. With respect to the original BPU of the current picture, the prediction reference 224 may include one or more pictures (referred to as "reference pictures") that have been coded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, a reference picture may be coded and reconstructed for each BPU. For example, the encoder may add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a reconstructed BPU. Once all reconstructed BPUs of the same picture are generated, the encoder may generate the reconstructed picture as a reference picture. The encoder may perform a "motion estimation" operation to search for a matching region within a range (referred to as a "search window") of the reference picture. The position of the search window in the reference picture may be determined based on the position of the original BPU in the current picture. For example, the search window may be centered at a location having the same coordinates in the reference picture as the original BPU in the current picture, and may extend over a predetermined distance. When the encoder identifies a region within the search window that is similar to the original BPU (e.g., by using a pel recursion algorithm, a block matching algorithm, etc.), the encoder can determine that region as a matching region. The matching region may have different dimensions (e.g., smaller, equal, larger, or different shape) than the original BPU. Because the reference picture and the current picture are separated in time in a timeline (e.g., as shown in FIG. 1), the matching region can be considered to "move" to the position of the original BPU over time. The encoder can record the direction and distance of such movement as a "motion vector." If multiple reference pictures are used (e.g., picture 106 in FIG. 1), the encoder can find the matching region for each reference picture and determine its associated motion vector. In some embodiments, the encoder can assign weights to the pixel values ​​of the matching region in each matching reference picture.

[0046]

[0058] Motion estimation can be used to identify various types of motion, such as, for example, translation, rotation, scaling, etc. In inter prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, a motion vector associated with the matching region, the number of reference pictures, weights associated with the reference pictures, etc.

[0047]

[0059] To generate the predicted BPU 208, the encoder may perform a "motion compensation" operation. Motion compensation may be used to reconstruct the predicted BPU 208 based on the prediction data 206 (e.g., a motion vector) and the prediction reference 224. For example, the encoder may shift matching regions of a reference picture according to a motion vector, within which the encoder may predict the original BPU of the current picture. If multiple reference pictures are used (e.g., picture 106 of FIG. 1), the encoder may shift matching regions of the reference pictures according to their respective motion vectors and average pixel values ​​of the matching regions. In some embodiments, if the encoder assigns weights to pixel values ​​of the matching regions of the respective matching reference pictures, the encoder may add a weighted sum of pixel values ​​of the shifted matching regions.

[0048]

[0060] In some embodiments, inter-prediction can be unidirectional or bidirectional. Unidirectional inter-prediction can use one or more reference pictures that are in the same temporal direction relative to the current picture. For example, picture 104 in FIG. 1 is a unidirectional inter-predicted picture in which the reference picture (i.e., picture 102) precedes picture 104. Bidirectional inter-prediction can use one or more reference pictures that are in both temporal directions relative to the current picture. For example, picture 106 in FIG. 1 is a bidirectional inter-predicted picture in which the reference pictures (i.e., pictures 104 and 108) are in both temporal directions relative to picture 104.

[0049]

[0061] Continuing with reference to the forward path of process 200B, after spatial prediction step 2042 and temporal prediction step 2044, in mode decision step 230, the encoder may select a prediction mode (e.g., one of intra-prediction or inter-prediction) for the current iteration of process 200B. For example, the encoder may perform a rate-distortion optimization technique, in which the encoder may select a prediction mode to minimize the value of a cost function depending on the bitrates of the candidate prediction modes and the distortion of the reconstructed reference picture under the candidate prediction modes. Depending on the selected prediction mode, the encoder may generate a corresponding predicted BPU 208 and predicted data 206.

[0050]

[0062] In the reconstruction path of process 200B, if an intra-prediction mode is selected in the forward path, after generating a prediction reference 224 (e.g., a current BPU that has been coded and reconstructed in a current picture), the encoder can directly feed the prediction reference 224 to a spatial prediction stage 2042 for later use (e.g., to extrapolate the next BPU of the current picture). If an inter-prediction mode is selected in the forward path, after generating a prediction reference 224 (e.g., a current picture in which all BPUs have been coded and reconstructed), the encoder can feed the prediction reference 224 to a loop filter stage 232, where the encoder can apply a loop filter to the prediction reference 224 to reduce or eliminate distortions (e.g., blocking artifacts) caused by inter-prediction. For example, the encoder can apply various loop filter techniques in the loop filter stage 232, such as deblocking, sample adaptive offset, adaptive loop filter, etc. The loop filtered reference pictures may be stored in a buffer 234 (or "decoded picture buffer") for later use (e.g., for use as inter-predicted reference pictures for future pictures in the video sequence 202). The encoder may store one or more reference pictures in the buffer 234 for use in the temporal prediction stage 2044. In some embodiments, the encoder may encode loop filter parameters (e.g., loop filter strength) along with the quantized transform coefficients 216, the prediction data 206, and other information in a binary coding stage 226.

[0051]

[0063] FIG. 3A shows a schematic diagram of an example decoding process 300A consistent with embodiments of the present disclosure. Process 300A may be a decompression process corresponding to compression process 200A of FIG. 2A. In some embodiments, process 300A may be similar to the reconstruction path of process 200A. A decoder may follow process 300A to decode video bitstream 228 into video stream 304. Video stream 304 may be very similar to video sequence 202. However, due to information loss in the compression and decompression processes (e.g., quantization stage 214 of FIGS. 2A-2B), video stream 304 is generally not identical to video sequence 202. Similar to processes 200A and 200B of FIGS. 2A-2B, a decoder may perform process 300A at the level of a basic processing unit (BPU) for each picture encoded in video bitstream 228. For example, the decoder may perform process 300A in an iterative manner, where the decoder may decode a basic processing unit in one iteration of process 300A. In some embodiments, the decoder may perform process 300A in parallel for a region (e.g., regions 114-118) of each picture encoded in video bitstream 228.

[0052]

[0064] In FIG. 3A , a decoder may feed a portion of a video bitstream 228 associated with a basic processing unit of a coded picture (referred to as a “coded BPU”) to a binary decoding stage 302. In the binary decoding stage 302, the decoder may decode the portion into prediction data 206 and quantized transform coefficients 216. The decoder may feed the quantized transform coefficients 216 to an inverse quantization stage 218 and an inverse transform stage 220 to generate a reconstructed residual BPU 222. The decoder may feed the prediction data 206 to a prediction stage 204 to generate a predicted BPU 208. The decoder may add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a predicted reference 224. In some embodiments, the predicted reference 224 may be stored in a buffer (e.g., a decoded picture buffer in computer memory). The decoder may feed the predicted reference 224 to the prediction stage 204 for performing a prediction operation in a next iteration of the process 300A.

[0053]

[0065] The decoder may iteratively perform process 300A to decode each coded BPU of the coded picture and generate a predicted reference 224 for coding the next coded BPU of the coded picture. After decoding all coded BPUs of the coded picture, the decoder may output the picture to the video stream 304 for display and proceed to decode the next coded picture in the video bitstream 228.

[0054]

[0066] In binary decoding stage 302, the decoder may perform the inverse operation of the binary coding technique used by the encoder (e.g., entropy coding, variable length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm). In some embodiments, in addition to prediction data 206 and quantized transform coefficients 216, the decoder may decode other information in binary decoding stage 302, such as, for example, a prediction mode, parameters of the prediction operation, type of transform, parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bitrate control parameters), etc. In some embodiments, if video bitstream 228 is transmitted in packets over a network, the decoder may depacketize video bitstream 228 before feeding it to binary decoding stage 302.

[0055]

[0067] 3B shows a schematic diagram of another example decoding process 300B consistent with embodiments of the present disclosure. Process 300B may be modified from process 300A. For example, process 300B may be used by a decoder that complies with a hybrid video coding standard (e.g., the H.26x series). Compared to process 300A, process 300B further divides prediction stage 204 into spatial prediction stage 2042 and temporal prediction stage 2044, and additionally includes loop filter stage 232 and buffer 234.

[0056]

[0068] In process 300B, for a coded basic processing unit (referred to as a "current BPU") of a coded picture being decoded (referred to as a "current picture"), prediction data 206 decoded by the decoder from binary decoding stage 302 may include various types of data depending on which prediction mode was used by the encoder to code the current BPU. For example, if intra prediction was used by the encoder to code the current BPU, prediction data 206 may include a prediction mode indicator (e.g., a flag value) indicating intra prediction, parameters of the intra prediction operation, etc. The parameters of the intra prediction operation may include, for example, the positions (e.g., coordinates) of one or more neighboring BPUs used as references, sizes of the neighboring BPUs, parameters of extrapolation, directions of the neighboring BPUs relative to the original BPU, etc. In another example, if inter prediction was used by the encoder to code the current BPU, prediction data 206 may include a prediction mode indicator (e.g., a flag value) indicating inter prediction, parameters of the inter prediction operation, etc. Parameters for inter-prediction operations may include, for example, the number of reference pictures associated with the current BPU, weights associated with each of the reference pictures, the locations (e.g., coordinates) of one or more matching regions within each reference picture, one or more motion vectors associated with each of the matching regions, etc.

[0057]

[0069] Based on the prediction mode indicator, the decoder may decide whether to perform spatial prediction (e.g., intra prediction) in a spatial prediction step 2042 or temporal prediction (e.g., inter prediction) in a temporal prediction step 2044. Details of performing such spatial or temporal prediction are shown in FIG. 2B and will not be repeated below. After performing such spatial or temporal prediction, the decoder may generate a predicted BPU 208. As described in FIG. 3A, the decoder may add the predicted BPU 208 and the reconstructed residual BPU 222 to generate a prediction reference 224.

[0058]

[0070] In process 300B, the decoder may feed the predicted reference 224 to a spatial prediction stage 2042 or a temporal prediction stage 2044 for performing a prediction operation within the next iteration of process 300B. For example, if the current BPU is decoded using intra prediction in spatial prediction stage 2042, after generating the prediction reference 224 (e.g., the decoded current BPU), the decoder may feed the prediction reference 224 directly to spatial prediction stage 2042 for later use (e.g., to extrapolate the next BPU of the current picture). If the current BPU is decoded using inter prediction in temporal prediction stage 2044, after generating the prediction reference 224 (e.g., the reference picture from which all BPUs are decoded), the encoder may feed the prediction reference 224 to a loop filter stage 232 to reduce or eliminate distortion (e.g., blocking artifacts). The decoder may apply a loop filter to the prediction reference 224 in the manner described in FIG. 2B . The loop filtered reference pictures may be stored in a buffer 234 (e.g., a decoded picture buffer in computer memory) for later use (e.g., for use as inter-prediction reference pictures for future coded pictures of the video bitstream 228). The decoder may store one or more reference pictures in the buffer 234 for use in the temporal prediction stage 2044. In some embodiments, if the prediction mode indicator in the prediction data 206 indicates that inter-prediction was used to encode the current BPU, the prediction data may further include loop filter parameters (e.g., loop filter strength).

[0059]

[0071] FIG. 4 is a block diagram of an example device 400 for encoding or decoding video consistent with embodiments of the present disclosure. As shown in FIG. 4, device 400 may include a processor 402. When processor 402 executes the instructions described herein, device 400 may become a dedicated machine for encoding or decoding video. Processor 402 may be any type of circuit capable of manipulating or processing information. For example, processor 402 may include any combination of any number of central processing units (“CPUs”), graphics processing units (“GPUs”), neural processing units (“NPUs”), microcontroller units (“MCUs”), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general purpose array logic (GALs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), systems-on-chips (SoCs), application-specific integrated circuits (ASICs), etc. In some embodiments, processor 402 may be a set of processors grouped together as a single logical entity. For example, as shown in Figure 4, processor 402 may include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0060]

[0072] Device 400 may also include memory 404 configured to store data (e.g., a set of instructions, computer code, intermediate data, etc.). For example, as shown in FIG. 4, the stored data may include program instructions (e.g., program instructions for implementing steps in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 can access the program instructions and data for processing (e.g., via bus 410) and execute the program instructions to operate on or process the data for processing. Memory 404 may include high-speed random access storage or non-volatile storage. In some embodiments, memory 404 may include any combination of any number of random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, etc. Memory 404 may also be a collection of memories (not shown in FIG. 4) grouped together as a single logical entity.

[0061]

[0073] Bus 410, such as an internal bus (e.g., a CPU memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Express port), or the like, may be a communication device that transfers data between components within device 400.

[0062]

[0074] For ease of explanation and to avoid ambiguity, this disclosure will collectively refer to the processor 402 and other data processing circuitry as "data processing circuitry." The data processing circuitry may be implemented entirely as hardware or as a combination of software, hardware, or firmware. In addition, the data processing circuitry may be a single, independent module or may be fully or partially combined within any other component of the device 400.

[0063]

[0075] Device 400 may further include a network interface 406 for providing wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communication network, etc.) In some embodiments, network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, transponders, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication ("NFC") adapters, cellular network chips, etc.

[0064]

[0076] In some embodiments, device 400 may optionally further include a peripheral interface 408 for providing connection to one or more peripheral devices. As shown in Figure 4, peripheral devices may include, but are not limited to, a cursor control device (e.g., a mouse, touchpad, or touchscreen), a keyboard, a display (e.g., a cathode ray tube display, a liquid crystal display, or a light emitting diode display), a video input device (e.g., a camera or input interface coupled to a video archive), etc.

[0065]

[0077] It should be noted that a video codec (e.g., a codec that executes process 200A, 200B, 300A, or 300B) can be implemented as any combination of software or hardware modules within device 400. For example, some or all of the stages of process 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instructions loadable into memory 404. In another example, some or all of the stages of process 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, etc.).

[0066]

[0078] This disclosure provides a method executable by an encoder and / or decoder to simplify matrix-weighted intra prediction (MIP). The MIP method is a newly added intra prediction technique in VVC. The MIP mode is applied to blocks whose aspect ratio max(width, height) / min(width, height) is equal to or less than 4. Furthermore, the MIP mode is applied only to the luma component. A MIP flag is signaled in parallel with the intra sub-partition mode, the multi-reference line intra prediction mode, or the most probable mode.

[0067]

[0079] When a block is coded using MIP mode, as in conventional intra prediction modes, one line of reconstructed neighboring boundary samples on the left side of the block and one line of reconstructed neighboring boundary samples on the top side of the block are used as inputs to predict the block. If reconstructed neighboring boundary samples are not available, they can be generated as in conventional intra prediction. To predict the luma sample, the reconstructed neighboring boundary samples are first averaged to form a reduced boundary vector, neighbor red and generate neighbor red [0] represents the first element of the reduced boundary vector. Then, for the matrix-vector multiplication process, the reduced boundary vector neighbor red Using the input vector input red is generated, and a reduced prediction signal pred red Finally, the reduced prediction signal pred red Then, bilinear interpolation is applied to generate the MIP predicted signal output pred. An explanatory diagram of the MIP prediction process is shown in Figure 5.

[0068]

[0080] MIP blocks are divided into three classes according to the width (W) and height (H) of the block: Class 0: When W=H=4 (i.e., 4x4 blocks), Class 1: max{W,H}=8 (i.e., 4x8, 8x4, 8x8 blocks), and Class 2: When max{W,H}>8.

[0069]

[0081] As shown in Table 6 in Figure 6, the differences between the three classes are the number of modes, the number of matrices, the size of the matrices, and the input vector red The size of (the input of the matrix vector multiplication process) and the reduced prediction signal pred red (the output of the matrix vector multiplication process).

[0070]

[0082] In the following description, Class 0, Class 1, and Class 2 are denoted as S0, S1, and S2, respectively. i is a matrix set S i (i=0,1,2) represents the number of matrices in the matrix multiplication process.

number

number

number

[0071]

[0083] MIP mode k is N i If it is greater than or equal to, the reduced boundary vector neighbor red and the reduced prediction signal pred red In the steps of generating , respectively, a swap operation and a transpose operation are performed. Details of these two operations are described above. In addition, the following equations (2) and (3) are used to determine whether a swap operation or a transpose operation is required.

number

[0072]

[0084] As mentioned above, the generation of the output prediction signal pred for the current block is based on the following three steps: averaging, matrix-vector multiplication and linear interpolation, which are described in detail below.

[0073]

[0085] From the boundary samples, four samples of Class 0 and eight samples of Class 1 and Class 2 are extracted by averaging. For example, the reduced boundary vector neighbor red can be generated by averaging the reconstructed adjacent boundary samples according to the following rule:

[0074]

[0086] Class 0: Every third sample is averaged. Reduced boundary vector neighbor red The size is 4x1.

[0075]

[0087] Class 1 and Class 2: For the reconstructed neighbor boundary samples above the current block, average samples every W / 4. For the reconstructed neighbor boundary samples to the left of the current block, average samples every H / 4. Reduced boundary vector neighbor red The size is 8x1.

[0076]

[0088] Reduced boundary vector neighbor red is the vector obtained by averaging the reconstructed adjacent boundary samples above the current block

number

number

number

number

number

[0077]

[0089] Then, the input vector for matrix-vector multiplication, red is generated as follows:

[0078]

[0090] For Class 0 and Class 1, input red [0]=neighbor red [0]-(1<<(bitDepth-1)) input red [j]=neighbor red [j]-neighbor red [0], j=1,…,size(neighbor red )-1 formula (5) is.

[0079]

[0091] Regarding Class 2, input red [j]=neighbor red [j+1]-neighbor red [0], j=0,…,size(neighbor red )-2 Equation (6) is.

[0080]

[0092] In the above equations (5) and (6), neighbor red [0] is the vector neighbor red According to equations (5) and (6), the inputs of Class0, Class1, and Class2 arered The sizes inSize are 4, 8, and 7, respectively.

[0081]

[0093] Vector input red The result is a reduced prediction signal pred based on the set of subsampled samples in the current block. red For example, the reduced input vector input red From the width W red and height H red The reduced prediction signal pred is a signal based on downsampled blocks of red where W red and H red is defined as the following equations (7) and (8).

number

[0082]

[0094] As mentioned above, if the variable "isTransposed" is equal to 1, the reduced prediction signal pred red The final reduced prediction signal pred red The size of W red ×H red Assuming that

number

number

[0083]

[0095] The reduced prediction signal pred' is calculated by calculating the matrix vector product according to the following equation (11): red The vector of is calculated. pred' red =M·input red+neighbor red [0] Formula (11)

[0084]

[0096] Then, following the raster scan order, matrices pred of sizes 4x4, 4x8, 8x4 and 8x8 are generated. red Vector pred' in red Place the matrix pred of size 4x4. red A vector pred' of size 16x1 is placed inside red An example of arranging is shown below. pred' red =[A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P] T

number

[0085]

[0097] In other words, x=0...W' red -1 and y=0...H' red -1, the matrix pred red can be calculated using equation (12) as follows:

number

[0086]

[0098] In the above equation (12), the variable "inSize" is the input vector input as explained above. red is the size of the reduced prediction signal pred red The matrix M used to generate k is taken from one of three matrix sets S0, S1, S2 according to the block size classification and MIP mode k.

[0087]

[0099] The variables oW and sW are two default values ​​depending on which matrix is ​​used for matrix-vector multiplication. The variable oW is used to limit the precision of each element in the matrix to 7 bits, so that all elements are equal to or greater than 0. For example, the factor oW can be defined as the following equation (13):

number

[0088]

[0100] In the above equation (13), s is an offset and is derived from a look-up table. For example, Table 7 in Figure 7 shows an exemplary look-up table for s according to some disclosed embodiments.

[0089]

[0101] Additionally, the variable "sW" is derived using another lookup table. Table 8 in Figure 8 shows an example lookup table for sW according to some disclosed embodiments.

[0090]

[0102] In the formula, two variables "inch" and "incW" used to exclude half of the rows of the matrix for 4x16 and 16x4 blocks are defined as equations (14) and (15) below.

number

[0091]

[0103] In the above equation (15), the variable predC is W' red ×H' red The reduced prediction signal pred red is used to place the , and is defined as the following equation (16).

number

[0092]

[0104] An input vector input with size inSize equal to 7 red and a matrix of 64 rows and 7 columns is used for blocks belonging to Class 2, generating a 64 element vector. However, for 4x16 and 16x4 blocks, only 32 elements are needed, according to the following formula:

number

[0093]

[0105] 9 illustrates an example pruning operation according to some disclosed embodiments. As shown in FIG. 9, for a 4×16 block with isTransposed=0 and a 16×4 block with isTransposed=1, every second row is pruned from the matrix. Therefore, the reduced prediction signal pred red contains 32 elements, arranged in a 4x8 matrix.

[0094]

[0106] 10 illustrates an exemplary pruning operation according to some disclosed embodiments. As shown in FIG. 10, for a 16×4 block with isTransposed=0 and a 4×16 block with isTransposed=1, the last 8 rows of every 16 rows are pruned from the matrix. Thus, the reduced prediction signal pred red contains 32 elements, arranged in an 8x4 array.

[0095]

[0107] The output prediction signal at the remaining positions is the reduced prediction signal pred based on the subsampled set. red is generated by linear interpolation from , which is a single-step linear interpolation in each direction.

[0096]

[0108] As described above, the prediction for MIP mode is generated using three steps, including averaging of neighboring reconstructed samples, matrix-vector multiplication, and bilinear interpolation. The prediction process for MIP mode is different from that of conventional intra-prediction mode. Although MIP mode improves coding efficiency, its design can be complicated in the following two aspects:

[0097]

[0109] Regarding the first aspect, the exclusion operation for 4x16 and 16x4 blocks in the matrix-vector multiplication process can be problematic for three reasons: First, the exclusion operation not only adds extra operations, but also makes the prediction process uneven because it only applies to 16x4 and 4x16 blocks. Second, for 16x4 and 4x16 blocks, the reduced prediction signal pred red Therefore, the size of the untransposed reduced prediction signal (e.g., W' red and H' red ) is required. Third, as shown in the following equation (17), red The size of can be different for 16x4 and 4x16 blocks.

number

[0098]

[0110] Regarding the second aspect, an offset sO is added to the reduced prediction signal in the matrix multiplication process to limit the precision of each element in the matrix to 7 bits and ensure that all elements are non-negative. However, this can be unnecessary and complicated for three reasons: First, extra memory is required to store the table of offsets sO. The table contains a total of 34 elements, each of which is 7 bits. Therefore, a total of 238 bits of memory is required. Second, a lookup table operation is required to determine the value of sO using the class index and matrix number. Third, the reduced prediction signal pred red Additional multiplication and addition operations are required to generate the matrix M and the input vector input red In addition to calculating the matrix-vector multiplication between sO and the input vector input red For a 4x4 block, the total number of multiplications per sample required to generate the prediction signal increases to 5.

[0099]

[0111] This disclosure provides a method to solve these problems without affecting the bit rate. Some exemplary methods use 8 bits instead of 7 bits to store the matrix. The equation can then be rewritten as the following equation (18):

number

[0100]

[0112] In the above equation (18), an offset sO is subtracted from every element in the matrix. The above method of storing and calculating the matrix-vector product can produce bit-identical results. However, the number of bits for storing the matrix increases by 4882 (i.e., 5120×1−34×7) bits, and the bit width for the multiplication operation expands to 8 bits.

[0101]

[0113] The method for eliminating the exclusion operation and the lookup table for sO is described below.

[0102]

[0114] Two methods are provided to eliminate the extra matrix exclusion operations in the MIP prediction process. According to the first method for eliminating the exclusion operations, the irrational classification method in the traditional MIP method can be corrected by moving 4x16 and 16x4 blocks from Class2 to Class1, so that the generated reduced prediction signal pred red does not exceed the limit on the shorter side.

[0103]

[0115] In an exemplary embodiment, the rules for MIP classification are modified as follows: Class 0: 4×4 Class 1: 4×N, 8×8, and N×4, where N is an integer between 8 and 64 Class 2: Others.

[0104]

[0116] This modification allows blocks having sizes of 8x8, 4x8, 4x16, 4x32, 4x64, 8x4, 16x4, 32x4, or 64x4 to be moved from Class 2 to Class 1. Therefore, blocks having sizes of 8x8, 4x8, 4x16, 4x32, 4x64, 8x4, 16x4, 32x4, or 64x4 can use matrices in set S1, each of which has 16 rows and 8 columns, in the matrix multiplication process. In this way, a 4x4 reduced prediction signal pred red Only 16 elements are generated to form , so the subtraction operation can be eliminated. This modification can be represented as follows, with the changes highlighted in double strikethrough or italics: If both cbWidth and cbHeight are equal to 4, then MipSizeId[x][y] is set equal to 0. Otherwise, if cbWidth*cbHeight is less than or equal to 64, then MipSizeId[x][y] is set equal to 1. Otherwise, MipSizeId[x][y] is set equal to 2.

[0105]

[0117] This solution has at least three advantages.

[0106]

[0118] First, the matrix multiplication process is simplified and unified. For blocks of size 4x16 or 16x4, the exclusion operation is eliminated. Therefore, the check for whether to perform the exclusion operation and the two variables "inch" and "incW" can be deleted. Furthermore, all blocks do not require additional operations on the matrix during the matrix-vector multiplication process. Therefore, the matrix multiplication process is unified.

[0107]

[0119] Second, the number of multiplications and additions of 4x16 and 16x4 blocks in the matrix multiplication process is reduced. In some embodiments, for blocks of size 4x16 or 16x4, a 32x7 matrix may be used to perform matrix-vector multiplication, while in the provided embodiment, a 16x8 matrix may be used. Thus, the number of multiplications and additions of 4x16 or 16x4 blocks can be reduced.

[0108]

[0120] Third, pred red The derivation of the reduced prediction signal pred red The size of W' is consistent before and after the transposition. red and H' red The additional derivation for pred is eliminated. red The derivation of the size of can be simplified as the following equations (19) and (20).

number

[0109]

[0121] Reduced prediction signal pred red The size of is unified by the following equation (21).

number

[0110]

[0122] According to the second method for eliminating the exclusion operation, the rules of MIP classification are modified as follows. Class 0: 4×4 Class 1: 4x8, 8x4, 4x16 and 16x4 Class 2: Others.

[0111]

[0123] The 4x16 and 16x4 blocks (in italics in the modified MIP classification above) are moved to Class 1, and the 8x8 blocks are moved to Class 2. This modification eliminates the exclusion operation and further simplifies the MIP classification rules. In some embodiments, this modification can be represented as follows, with the changes highlighted in double strikethrough or italics: If both cbWidth and cbHeight are equal to 4, then MipSizeId[x][y] is set equal to 0. Otherwise, if Min(cbWidth, cbHeight) is equal to 4, then MipSizeId[x][y] is set equal to 1. Otherwise, MipSizeId[x][y] is set equal to 2.

[0112]

[0124] To eliminate the table of offsets sO, embodiments of the present disclosure provide a method for modifying the values ​​of matrix M and offsets sO without a lookup table.

[0113]

[0125] In the first exemplary embodiment, the offset sO is calculated for Class 0 by the matrix

number

number

number

[0114]

[0126] In the second exemplary embodiment, for all classes, the offset sO is replaced with the first element in each matrix. In addition, the matrix used for Class2

number

number

[0115]

[0127] The modified matrix is ​​stored instead of the original matrix, and no further operations are added during the encoding and decoding process. There are at least two advantages: First, the table of offsets sO that depends on the class index and matrix number can be eliminated, thereby saving 238 bits of memory space. Second, the process of extracting offsets from the matrix is ​​unified for all classes.

[0116]

[0128] In the third exemplary embodiment, the first element of each matrix is ​​replaced with the corresponding offset sO according to Table 7 in Figure 7. And therefore, the table of sO can be eliminated. When performing matrix-vector multiplication, the offset is derived from the first element of each matrix. The modified matrix is ​​stored instead of the original matrix, and no further operations are added during the encoding and decoding process.

[0117]

[0129] In the fourth exemplary embodiment, the offset sO is replaced with a fixed value, so that the lookup table can be eliminated without any derivation process for the offset. In one example, the fixed value is 66, which is the minimum value among all matrices. All matrices are modified as follows: M'=M-sO+66 Equation (23)

[0118]

[0130] In the above equation (23), sO is derived from Table 7 (FIG. 7). Then, the matrix-vector multiplication process in equation (12) can be modified as follows:

number

[0119]

[0131] The modified matrix M' is stored in place of the original matrix and no further operations are added during the encoding and decoding process.

[0120]

[0132] As another example, the fixed value is 64. All matrices are modified as follows: M'=M-sO+64 Equation (25)

[0121]

[0133] In the above equation (25), sO is derived from Table 7. Then, the matrix vector multiplication process can be modified as follows:

number

[0122]

[0134] Additionally, negative numbers in the modified matrix need to be corrected to 0. When implementing the embodiments of the present disclosure, only one value is changed from -2 to 0. The modified matrix M' is stored instead of the original matrix, and no further operations are added during the encoding and decoding process. The multiplication by 64 operation can be replaced with a shift operation. Therefore, sO and the input vector input redMultiplications between x and y can be replaced with left-shift operations. For a 4x4 block, the total number of multiplications per sample required to generate the prediction signal is reduced from 5 to 4.

[0123]

[0135] In the third example, the fixed value is 128. All matrices are modified as follows: M'=M-sO+128 Equation (27)

[0124]

[0136] In the above equation (27), sO is derived from Table 7. Then, the matrix vector multiplication process can be modified as follows:

number

[0125]

[0137] The modified matrix M' is stored instead of the original matrix, and no further operations are added during the encoding and decoding process. The look-up table is eliminated, and multiplications between offsets and input vectors are replaced with left-shift operations. For a 4x4 block, the total number of multiplications per sample required to generate the prediction signal is reduced to 4. In addition, the coding performance remains unchanged.

[0126]

[0138] FIG. 11 is a flowchart of an example method 1100 for processing video content consistent with embodiments of the present disclosure. Method 1100 may be performed by a codec (e.g., an encoder using encoding processes 200A and 200B of FIGS. 2A-2B or a decoder using decoding processes 300A and 300B of FIGS. 3A-3B). For example, a codec may be implemented as one or more software or hardware components of a device (e.g., device 400) for encoding or converting a video sequence into another code. In some embodiments, the video sequence may be an uncompressed video sequence (e.g., video sequence 202) or a compressed video sequence to be decoded (e.g., video stream 304). In some embodiments, the video sequence may be a surveillance video sequence that may be captured by a surveillance device (e.g., video input device of FIG. 4) associated with a processor (e.g., processor 402) of the device. The video sequence may include multiple pictures. The device may perform method 1100 at the picture level. For example, the device may process pictures one at a time in method 1100. In another example, the device may process multiple pictures at a time in method 1100. Method 1100 may include the following steps.

[0127]

[0139] In step 1102, a classification of the target block may be determined. In some embodiments, the classification may include a first class (e.g., Class 0), a second class (e.g., Class 1), and a third class (e.g., Class 2). For a given block, the classification of the given block may be determined based on the size of the given block. For example, the first class may be associated with blocks of size 4x4, and the second class may be associated with blocks of size 8x8, 4xN, or Nx4, where N may be an integer between 8 and 64. For example, N may be equal to 8, 16, 32, or 64. That is, the second class may include blocks of size 8x8, 4x8, 4x16, 4x32, 4x64, 8x4, 16x4, 32x4, or 64x4. The third class may be associated with the remaining blocks.

[0128]

[0140] In some embodiments, the target block may be determined to belong to a third class depending on whether the target block has a size other than 4x4, 8x8, 4xN or Nx4.

[0129]

[0141] In step 1104, a matrix weighted intra prediction (MIP) signal may be generated based on the classification. In some embodiments, a first intra prediction signal for the target block may be generated based on the input vector, the matrix, and the classification of the target block, and the first intra prediction signal may be used to perform bilinear interpolation on the target block to generate the MIP signal.

[0130]

[0142] For example, to generate an input vector, adjacent reconstructed samples of a target block can be averaged according to the classification of the target block. As discussed above, for a first class block, every third adjacent reconstructed sample of the block can be averaged to generate a reduced boundary vector as an input vector. For example, the size of the input vector can be 4×1 for the first class, 8×1 for the second class, and 7×1 for the third class. Also, for a block of the second or third class (e.g., having a size of M×N), every M / 4 adjacent reconstructed samples above the block and every N / 4 adjacent reconstructed samples to the left of the block can be averaged.

[0131]

[0143] Unlike the input vector, the matrix can be selected from a set of matrices (eg, matrix sets S0, S1, or S2) according to the classification and MIP mode index of the target block.

[0132]

[0144] A first intra prediction signal may then be generated by performing matrix-vector multiplication on the matrix and the input vector. In some embodiments, the first intra prediction signal is further associated with a first offset and a second offset. For example, as discussed in Equation (12), the reduced prediction signal may be further biased by a first offset (e.g., oW) and a second offset (e.g., oS). In some embodiments, the first offset and the second offset may be determined based on a matrix index within the set of matrices. For example, the first offset and the second offset may be determined by referring to Table 7 and Table 8, respectively.

[0133]

[0145] The classification of the target block is also related to the size of the first intra-predicted signal, for example, determining that the first intra-predicted signal has a size of 4x4 according to whether the target block belongs to the first class or the second class, and determining that the first intra-predicted signal has a size of 8x8 according to whether the target block belongs to the third class.

[0134]

[0146] In some embodiments, a non-transitory computer-readable storage medium containing instructions is also provided, which may be executed by an apparatus (such as the disclosed encoders and decoders) to perform the above-described methods. Common non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium with a pattern of holes, RAM, PROMs and EPROMs, flash EPROMs or any other flash memory, NVRAM, cache, registers, any other memory chip or cartridge, and networked versions thereof. An apparatus may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0135]

[0147] The embodiments can be further described using the following clauses. 1. A computer-implemented method for processing video content, comprising: determining a classification of the target block; generating a matrix weighted intra prediction (MIP) signal based on the classification; determining a classification of the target block includes: determining that the target block belongs to a first class in response to the target block having a size of 4×4; or determining that the target block belongs to a second class according to whether the target block has a size of 8×8, 4×N, or N×4 (where N is an integer between 8 and 64); 20. A computer-implemented method comprising: 2. Generating an MIP signal generating a first intra prediction signal for the target block based on the input vector, the matrix, and the classification of the target block; performing bilinear interpolation on the target block using the first intra prediction signal to generate an MIP signal; 2. The method according to clause 1, comprising: 3. The method of clause 1 or 2, further comprising averaging adjacent reconstructed samples of the target block according to the classification of the target block to generate the input vector. 4. The method according to clause 2 or 3, wherein the input vector has a size of 4x1 if the target block belongs to a first class, or a size of 8x1 if the target block belongs to a second class. 5. The method of any one of clauses 2 to 4, wherein the matrix is ​​selected from a set of matrices according to the classification and MIP mode index of the target block. 6. The method according to clause 5, wherein the first intra prediction signal is generated by performing matrix-vector multiplication on a matrix and an input vector. 7. The method of clause 6, wherein the first intra prediction signal is generated based on one or more offsets associated with the matrix. 8. The method of clause 7, wherein the one or more offsets are determined based on an index of a matrix in a lookup table. 9. Determining the classification of the target block determining that the target block belongs to a third class in response to the target block having a size other than 4×4, 8×N, 4×N, and N×4; 9. The method of any one of clauses 1 to 8, further comprising: 10. Generating a first intra prediction signal for a target block includes: determining, in response to the target block belonging to the first class or the second class, that the first intra prediction signal has a size of 4×4; determining, in response to the target block belonging to the third class, that the first intra-predicted signal has a size of 8×8; 9. The method of claim 9, comprising: 11. The method of any one of clauses 1 to 10, wherein N is equal to 8, 16, 32, or 64. 12. A system for processing video content, comprising: a memory for storing a set of instructions; and at least one processor, the at least one processor providing the system with: determining a classification of the target block; generating a matrix weighted intra prediction (MIP) signal based on the classification; configured to execute a set of instructions to cause the In determining the classification of the target block, the at least one processor may include: determining that the target block belongs to a first class in response to the target block having a size of 4×4; or determining that the target block belongs to a second class according to the target block having a size of 8×8, 4×N, or N×4 (where N is greater than 4); The system is further configured to execute a set of instructions to further cause: 13. In generating the MIP signal, at least one processor in the system includes: generating a first intra prediction signal for the target block based on the input vector, the matrix, and the classification of the target block; performing bilinear interpolation on the target block using the first intra prediction signal to generate an MIP signal; 13. The system of claim 12, further configured to execute a set of instructions to further cause: 14. At least one processor in the system Averaging adjacent reconstructed samples of the target block according to the classification of the target block to generate an input vector. 14. The system of claim 12 or 13, further configured to execute a set of instructions to further cause: 15. The system of clause 13 or 14, wherein the input vector has a size of 4x1 if the target block belongs to a first class, or a size of 8x1 if the target block belongs to a second class. 16. A system according to any one of clauses 13 to 15, wherein the matrix is ​​selected from a set of matrices according to the classification and MIP mode index of the target block. 17. The system of clause 16, wherein the first intra prediction signal is generated by performing matrix-vector multiplication on a matrix and an input vector. 18. The system of clause 17, wherein the first intra prediction signal is generated based on one or more offsets associated with the matrix. 19. The system of clause 18, wherein the one or more offsets are determined based on an index of a matrix in a lookup table. 20. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computer system to cause the computer system to perform a method for processing video content, the method comprising: determining a classification of the target block; generating a matrix weighted intra prediction (MIP) signal based on the classification; determining a classification of the target block includes: determining that the target block belongs to a first class in response to the target block having a size of 4×4; or determining that the target block belongs to a second class according to whether the target block has a size of 8×8, 4×N, or N×4 (where N is an integer between 8 and 64); 1. A non-transitory computer-readable medium comprising:

[0136]

[0148] It should be noted that relational terms such as "first" and "second" herein are used merely to distinguish one entity or operation from another and do not require or imply any actual relationship or order between those entities or operations. Furthermore, terms such as "comprise," "have," "contain," and "include," and other similar forms, are intended to be equivalent in meaning and are open-ended in that the items following any one of these terms are not intended to be an exhaustive list of such items or to be limited only to the items they list.

[0137]

[0149] As used herein, unless otherwise specified, the word "or" includes all possible combinations unless impracticable. For example, if a database is stated to include A or B, the database can include A or B, or A and B, unless otherwise specified or impracticable. As a second example, if a database is stated to include A, B, or C, the database can include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise specified or impracticable.

[0138]

[0150] It will be understood that the above-described embodiments can be implemented by hardware or software (program code), or a combination of hardware and software. If implemented by software, the software can be stored in the above-described computer-readable medium. The software, when executed by a processor, can perform the disclosed methods. The computational units and other functional units described in this disclosure can be implemented by hardware or software, or a combination of hardware and software. Those skilled in the art will also understand that multiple of the above-described modules / units can be combined into one module / unit, and that each of the above-described modules / units can be further divided into multiple sub-modules / sub-units.

[0139]

[0151] In the foregoing specification, embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications to the described embodiments may be made. Other embodiments may become apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims. The order of steps depicted in the figures is for illustrative purposes only and is not intended to be limited to the particular order of steps. As such, one skilled in the art will recognize that steps can be performed in different orders while implementing the same method.

[0140]

[0152] Although illustrative embodiments have been disclosed in the drawings and herein, many variations and modifications to those embodiments may be made. Accordingly, although specific terms have been employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. 1. A computer-implemented method for processing video content, comprising: The method is implemented in an encoder, determining a classification of the target block, the target block is classified into a first class if it has a size of 4x4; the target block is classified into a second class if it has a size of 8x8, 4x8, or 8x4; the target block is classified into the second class if it has a size of 4×N or N×4 (where N is 16, 32, or 64); the target block is classified into a third class if it has a size other than 4x4, 8x8, 4xN, and Nx4; generating a matrix weighted intra prediction (MIP) signal based on the classification; 20. A computer-implemented method comprising:

2. generating the MIP signal generating a first intra prediction signal for the target block based on the first vector, the matrix, and the classification of the target block; performing bilinear interpolation on the target block using the first intra prediction signal to generate the MIP signal; The method of claim 1 , comprising:

3. The method of claim 1 , further comprising averaging adjacent reconstructed samples of the target block according to the classification of the target block to generate a first vector.

4. 3. The method of claim 2, wherein the first vector has a size of 4x1 if the target block belongs to the first class, or a size of 8x1 if the target block belongs to the second class.

5. The method of claim 2 , wherein the matrix is ​​selected from a set of matrices according to the classification and MIP mode index of the target block.

6. The method of claim 5 , wherein the first intra prediction signal is generated by performing a matrix-vector multiplication on the matrix and the first vector.

7. The method of claim 6 , wherein the first intra prediction signal is generated based on one or more offsets relative to the matrix.

8. The method of claim 7 , wherein the one or more offsets are determined based on an index of the matrix in a look-up table.

9. Generating the first intra prediction signal for the target block comprises: determining, in response to the target block belonging to the first class or the second class, that the first intra-predicted signal has a size of 4x4; determining, in response to the target block belonging to the third class, that the first intra-predicted signal has a size of 8x8; The method of claim 2 , comprising:

10. 1. A system for processing video content, comprising: The system is implemented in a decoder, a memory for storing a set of instructions; and at least one processor, wherein the at least one processor provides the system with: determining a classification of the target block, the target block is classified into a first class if it has a size of 4x4; the target block is classified into a second class if it has a size of 8x8, 4x8, or 8x4; the target block is classified into the second class if it has a size of 4×N or N×4 (where N is 16, 32, or 64); the target block is classified into a third class if it has a size other than 4x4, 8x8, 4xN, and Nx4; generating a matrix weighted intra prediction (MIP) signal based on the classification; a system configured to execute the set of instructions to cause

11. In generating the MIP signal, the at least one processor may include: generating a first intra prediction signal for the target block based on the first vector, the matrix, and the classification of the target block; performing bilinear interpolation on the target block using the first intra prediction signal to generate the MIP signal; 11. The system of claim 10, further configured to execute the set of instructions to further:

12. The at least one processor may include: averaging adjacent reconstructed samples of the target block according to the classification of the target block to generate a first vector.

11. The system of claim 10, further configured to execute the set of instructions to further:

13. 12. The system of claim 11, wherein the first vector has a size of 4x1 if the target block belongs to the first class or a size of 8x1 if the target block belongs to the second class.

14. The system of claim 11 , wherein the matrix is ​​selected from a set of matrices according to the classification and a MIP mode index of the target block.

15. The system of claim 14 , wherein the first intra prediction signal is generated by performing a matrix-vector multiplication on the matrix and the first vector.

16. The system of claim 15 , wherein the first intra prediction signal is generated based on one or more offsets associated with the matrix.

17. The system of claim 16 , wherein the one or more offsets are determined based on an index of the matrix in a look-up table.

18. 1. A method for storing a bitstream, the method comprising: determining a classification of the target block, the target block is classified into a first class if it has a size of 4x4; the target block is classified into a second class if it has a size of 8x8, 4x8, or 8x4; the target block is classified into the second class if it has a size of 4×N or N×4 (where N is 16, 32, or 64); the target block is classified into a third class if it has a size other than 4x4, 8x8, 4xN, and Nx4; generating a matrix weighted intra prediction (MIP) signal based on the classification; encoding the MIP signal into a bitstream; storing the bitstream on a non-transitory computer-readable medium; A method comprising:

19. Generating the first intra prediction signal for the target block comprises: determining, in response to the target block belonging to the first class, that the first vector has a size of 4×1; determining, in response to the target block belonging to the second class, that the first vector has a size of 8×1; or determining, in response to the target block belonging to the third class, that the first vector has a size of 7×1; The method of claim 2 , comprising:

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