Indication device

Abstract

To provide a semiconductor device comprising a configuration that can sufficiently reduce parasitic capacitance between wirings.SOLUTION: In a thin-film transistor of a bottom gate structure using a lamination of a first layer obtained by oxidizing a part or all of a metal thin-film, and an oxide semiconductor layer, an oxide insulating layer serving as a channel protection layer being in contact with a part of the oxide semiconductor layer overlapped with a gate electrode layer is formed. At formation of the insulating layer, the oxide insulating layer covering a peripheral edge part (including a lateral face) of the lamination of the oxide semiconductor layer is formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides with excellent semiconductor properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] When a plurality of thin film transistors are fabricated on an insulating surface, for example, gate wiring and source wiring are At the intersection, there is a gate wiring and a gate line having a different potential. An insulating layer is provided between the source wirings, and the insulating layer acts as a dielectric to form a capacitance. The capacitance is also called parasitic capacitance between wirings, and there is a risk that the signal waveform may become distorted. High raw capacitance can slow down signal transmission.

[0007] Furthermore, an increase in parasitic capacitance can cause crosstalk, where electrical signals leak between wiring, and can also increase power consumption. This leads to increased power.

[0008] In an active matrix display device, the signal wiring for supplying a video signal is If a large parasitic capacitance is formed between the wiring or the electrode, the display quality may be deteriorated. There is.

[0009] Furthermore, when miniaturizing circuits, the spacing between wires becomes narrower, and the parasitic capacitance between wires increases. There is a risk of this occurring.

[0010] One embodiment of the present invention provides a semiconductor device having a structure capable of sufficiently reducing parasitic capacitance between wirings. One of the goals is to

[0011] In addition, when a driver circuit is formed on an insulating surface, the operation of a thin film transistor used in the driver circuit A faster speed is preferable.

[0012] For example, the channel length (L) of a thin film transistor can be shortened or the channel width (W) can be widened. However, shortening the channel length leads to poor switching characteristics, e.g. For example, the on / off ratio becomes smaller. Also, if the channel width W is widened, the thin film transistor However, this increases the capacity load on the server itself.

[0013] Semiconductor device having thin film transistors with stable electrical characteristics even when the channel length is short One of the challenges is to provide

[0014] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required for thin film transistors used in drive circuits. High operating speed is required. In particular, the higher the resolution of the display device, Since the time required to write the display image is shortened, the thin film transistors used in the driver circuit operate quickly. Preferably, it is speed.

[0015] A semiconductor device that creates multiple types of circuits by fabricating multiple types of thin film transistor structures on the same substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device. [Means for solving the problem]

[0016] After forming a metal thin film on an insulating surface, an oxide semiconductor layer thicker than the metal thin film is stacked. Then, a part or all of the metal thin film is oxidized by performing an oxidation treatment such as a heat treatment. The first layer, which is a part or all of a metal thin film that has been oxidized, and the oxide semiconductor layer are stacked together to form a thin film transistor. It is used as the semiconductor layer of a transistor.

[0017] Specifically, when manufacturing multiple types of thin film transistors on the same substrate, at least one A first layer formed by oxidizing a part or all of a metal thin film as a semiconductor layer of a thin film transistor of A stack of a gate insulating film and an oxide semiconductor layer is used.

[0018] In addition, a stack of a first layer obtained by oxidizing a part or all of a metal thin film and an oxide semiconductor layer is used. In a bottom-gate thin film transistor, the oxide semiconductor layer overlapping the gate electrode layer An oxide insulating layer is formed on the surface of the semiconductor substrate to serve as a channel protection layer. An oxide insulating layer is formed to cover the periphery (including the side surface) of the stack of oxide semiconductor layers.

[0019] The oxide insulating layer covering the periphery (including the side surface) of the stack of the oxide semiconductor layer is formed by a gate electrode layer and The distance from the wiring layer (source wiring layer, capacitance wiring layer, etc.) formed above or around it is large. This also reduces parasitic capacitance.

[0020] The oxide insulating layer covers an end portion of the first layer obtained by oxidizing a part or all of the metal thin film, The leakage current can be reduced.

[0021] The oxide insulating layer covering the periphery of the stack of oxide semiconductor layers is formed in the same process as the channel protection layer. Therefore, the parasitic capacitance can be reduced without increasing the number of processes.

[0022] In addition, the oxide insulating layer covering the periphery (including the side surfaces) of the stack of oxide semiconductor layers reduces parasitic capacitance. This can reduce the distortion of the signal waveform.

[0023] In order to reduce parasitic capacitance, an insulating layer with a small dielectric constant is used as the oxide insulating layer sandwiched between the wiring. It is preferred to use a rim material.

[0024] By providing an oxide insulating layer that covers the periphery (including the side surface) of the oxide semiconductor layer, the parasitic capacitance This minimizes the amount of charge and allows high-speed operation of thin-film transistors. The use of fast thin film transistors allows for greater circuit integration.

[0025] One embodiment of the present invention disclosed in this specification is a first thin film transistor and a second thin film transistor. The first thin film transistor has a first gate electrode through a first gate insulating layer. a stack of a first oxide semiconductor layer and a second oxide semiconductor layer overlapping a second thin film transistor; The transistor is formed of a third oxide semiconductor layer overlapping the second gate electrode layer through a second gate insulating layer. The stack of the first oxide semiconductor layer and the second oxide semiconductor layer covers the periphery and the side surfaces. a second oxide semiconductor layer on the oxide insulating layer; The semiconductor device has a source electrode layer and a drain electrode layer.

[0026] As the metal thin film, a material that becomes semiconductive by oxidation treatment, such as indium, zinc, tin, molybdenum, Preferably, tungsten or tungsten is used. The first oxide semiconductor layer is formed on the second oxide semiconductor layer. The first oxide semiconductor layer has a lower electrical resistivity than the second oxide semiconductor layer. In addition, the first oxide semiconductor layer has a low conductivity (i.e., a high conductivity) between the first oxide semiconductor layer and the gate electrode. The thin film transistor is placed on the side with the closest separation distance and is in contact with at least the gate insulating film. By fabricating a thin film transistor with excellent electrical properties (such as field-effect mobility), A transistor can be realized.

[0027] The above configuration solves at least one of the above problems.

[0028] Further, one embodiment of the present invention for realizing the above structure is to form a gate electrode layer, A gate insulating layer is formed on the layer, a metal thin film is formed on the gate insulating layer, and an oxide film is formed on the metal thin film. After forming a semiconductor layer and dehydrating or dehydrogenating the oxide semiconductor layer, The oxide semiconductor layer is in contact with a part of the oxide semiconductor layer, and the oxide semiconductor layer is prevented from being recontaminated with water or hydrogen. An oxide insulating layer is formed to cover the periphery and side surfaces of the oxide semiconductor layer, and the metal thin film is oxidized. A source electrode layer and a drain electrode layer are formed on the oxide insulating layer. Method for manufacturing a semiconductor device in which a drain electrode layer and a protective insulating layer in contact with an oxide semiconductor layer are formed It is the law.

[0029] The metal thin film is formed by sputtering, vacuum deposition, coating, or the like. The thickness of the thin film is set to be thicker than 0 nm and 10 nm or less, preferably 3 nm or more. A laminate of metal thin films may be used, and the total thickness of the metal thin films is 10 nm or less. Oxidizing at least a part of the film means that the film functions as a thin film transistor and has switching characteristics. That is, the source electrode is oxidized to a degree that shows The current flowing between the source and drain electrodes remains almost constant, or the current flowing between the source and drain electrodes remains constant. The metal thin film is oxidized so that the electrode is not in a conductive state. The periphery and sides of the oxidized metal thin film to prevent the drain electrode from becoming conductive An oxide insulating layer is provided covering the

[0030] In addition, the first oxide semiconductor layer (i.e., an oxide semiconductor layer obtained by oxidizing a metal thin film) that is finally obtained The average total thickness of the first oxide semiconductor layer and the second oxide semiconductor layer is 3 nm or more and 30 nm or less.

[0031] The second oxide semiconductor layer preferably contains at least one of the same elements as the metal thin film. If the second oxide semiconductor layer contains at least one of the same elements as the metal thin film, the same etching The second oxide semiconductor layer and the metal thin film are etched in the same etching process using an etching solution or etching gas. Since the residual metal can be removed by the above method, the number of steps can be reduced.

[0032] The oxidation treatment is a heat treatment in either an oxygen-containing atmosphere or a nitrogen atmosphere (20 Even in a nitrogen atmosphere, the metal thin film can be formed by heat treatment. The oxygen in the oxide semiconductor layer (second oxide semiconductor layer) formed on and in contact with the metal thin film In this case, the presence of the metal thin film attracts oxygen from the second oxide semiconductor layer. The oxygen vacancy region can be formed in the second oxide semiconductor layer by removing the oxygen vacancy region. The presence of the metal thin film can be prevented not only by heat treatment in an atmosphere but also by heating in an atmosphere containing oxygen. Due to the presence of the oxygen atoms, oxygen is extracted from the second oxide semiconductor layer, and oxygen vacancies are formed in the second oxide semiconductor layer. By forming an oxygen vacancy region in the second oxide semiconductor layer, This can improve the field effect mobility. The heat treatment may make the interface with the oxide semiconductor layer formed thereon unclear. The oxide semiconductor layer on the gate insulating layer side, i.e., the lower layer of the oxide semiconductor layer, and the oxide semiconductor layer The upper layer exhibits different electrical properties.

[0033] The second oxide semiconductor layer is made of, for example, InMO3(ZnO) m (m>0) A thin film is formed, and a thin film transistor is manufactured using the thin film as an oxide semiconductor layer. M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M can be Ga, or Ga and Ni, or Ga and F. In addition to Ga, the above-mentioned metal elements such as Ga may be contained in the oxide semiconductor. In addition to the metal elements contained as M, Fe, Ni and other transition metal elements are contained as impurity elements. In this specification, InM O3(ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), Ga is used as M. The oxide semiconductor with the structure containing In-Ga-Zn-O is called an In-Ga-Zn-O oxide semiconductor, and the thin film of this oxide semiconductor is called an In-Ga-Zn-O oxide semiconductor. It is also called Ga-Zn-O based non-single crystal film.

[0034] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be used. The oxide semiconductor layer made of the material may contain silicon oxide.

[0035] Heat treatment is carried out under an inert gas atmosphere such as nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment, resulting in low resistance, that is, N-type ( N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer, and a process for forming the oxide insulating film is performed. By performing heat treatment, the oxide semiconductor layer is made into an oxygen-excess state, which increases the resistance, i.e., I In addition, solid-phase oxidation is performed to place the oxide semiconductor layer in an oxygen-excess state. This allows us to obtain thin film transistors with good electrical characteristics and high reliability. Therefore, it is possible to manufacture and provide a semiconductor device that can achieve this.

[0036] Dehydration or dehydrogenation is carried out using an inert gas such as nitrogen or a noble gas (argon, helium, etc.). Heating in an atmosphere at 400°C or higher but lower than the strain point of the substrate, preferably 420°C or higher and 570°C or lower Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer.

[0037] The oxide semiconductor layer that has been dehydrated or dehydrogenated is Even when TDS measurements were performed on the body layer up to 450°C, two peaks of water were observed, and at least 300 The heat treatment conditions should be such that a peak that appears around 100°C is not detected. Thin film transistors using oxide semiconductor layers that have been hydrogenated or dehydrogenated are 45% or less in TDS. Even when measurements are taken down to 0°C, the water peak that appears around 300°C is not detected.

[0038] Then, the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated. When dehydrating or dehydrogenating, the same furnace is used to prevent exposure to the atmosphere. It is important to prevent hydrogen from re-entering the oxide semiconductor. The body layer is made low resistance, i.e., N-type (N - After that, the oxide semiconductor is made high-resistive and becomes I-type. When a thin film transistor is fabricated using a conductor layer, the threshold voltage value of the thin film transistor can be projected. This allows realization of a so-called normally-off switching element. The channel is formed when the gate voltage of the transistor is as positive as possible to the threshold voltage of 0V. It is desirable for semiconductor devices (display devices) that the threshold voltage value of the thin film transistor is negative, current flows between the source and drain electrodes even when the gate voltage is 0V. In an active matrix display device, The electrical characteristics of the thin film transistors that make up the circuit are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin film transistors. Even if the field effect mobility is high, the threshold voltage is high, or the threshold voltage is If the threshold voltage is high, it is difficult to control it as a circuit. In the case of a thin film transistor with a large absolute value of the voltage, when the driving voltage is low, The N-channel type In the case of a thin film transistor, a channel is formed only when a positive voltage is applied to the gate. A transistor in which the drain current flows out is desirable. There are transistors in which a channel is not formed, and transistors in which a channel is formed even under negative voltage conditions and the drain current is A transistor that conducts current is not suitable as a thin film transistor for use in a circuit.

[0039] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. It is also possible to switch to a gas atmosphere, for example, by switching to air in the same furnace where dehydration or dehydrogenation was performed. The furnace is filled with high-purity oxygen gas, N2O gas, or ultra-dry air (dew point Cooling is carried out by filling the container with a temperature of -40°C or less, preferably -60°C or less.

[0040] The moisture content in the film is reduced by heat treatment for dehydration or dehydrogenation, and then the film containing moisture is Cool slowly (or cool) in an atmosphere that is free from dew (dew point is -40°C or less, preferably -60°C or less). By using the oxide semiconductor film, the electrical characteristics of the thin film transistor can be improved and mass production can be achieved. This will realize thin-film transistors that are both reliable and high-performance.

[0041] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). This heat treatment is called a heat treatment for dehydration or dehydrogenation. Dehydrogenation does not only mean that hydrogen is released as H2 by the hydrogenation process, but also means that hydrogen is released as H For convenience, this term is used to refer to the elimination of OH and other groups.

[0042] Heat treatment is carried out under an inert gas atmosphere such as nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment, resulting in low resistance, that is, N-type ( N - To make something (such as a product).

[0043] In addition, the high resistance drain region (HRD) that is oxygen deficient and overlaps with the drain electrode layer is The source electrode (also called the resistance drain region) is also formed. The oxygen-deficient high-resistance source region (HRS) overlaps the layer. e Source region) is formed.

[0044] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least 1×10 18 / cm 3 (less than) The carrier concentration in this specification is determined by Hall effect measurement at room temperature. This refers to the carrier concentration value measured.

[0045] Then, at least a part of the stack of the dehydrated or dehydrogenated oxide semiconductor layers is heated in an oxygen-excess atmosphere. By making the semiconductor into a state where the resistance is further increased, that is, the semiconductor is made into an I-type semiconductor, and a channel forming region is formed. In addition, as a treatment for making the stack of dehydrated or dehydrogenated oxide semiconductor layers into an oxygen-excess state, The oxide insulating film in contact with the stack of the dehydrated or dehydrogenated oxide semiconductor layer is formed by sputtering. or heat treatment after the formation of an oxide insulating film, or heat treatment in an atmosphere containing oxygen, Alternatively, heating in an inert gas atmosphere and then cooling in an oxygen atmosphere, or ultra-dry air (dew point This is done by cooling the mixture to a temperature of -40°C or lower, preferably -60°C or lower.

[0046] In addition, at least a part of the stack of the dehydrated or dehydrogenated oxide semiconductor layers (gate electrode layer In order to make the region (the area overlapping with the region) into a channel formation region, by selectively creating an oxygen excess state, It is also possible to make it highly resistive, i.e., I-type.

[0047] This allows the fabrication of a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. and can be provided.

[0048] Note that a high-resistance drain region is formed in the oxide semiconductor layer overlapping with the drain electrode layer. This makes it possible to improve the reliability of the drive circuit when it is formed. By forming a resistive drain region, the drain electrode layer, the high-resistive drain region, and the channel It is possible to form a structure in which the conductivity can be changed stepwise over the formation region. Therefore, when the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD, Even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high resistance drain region acts as a buffer. This prevents localized high electric fields from being applied, improving the breakdown voltage of the transistor. can be done.

[0049] In addition, a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region (and a high-resistance source region), the The leakage current in the channel forming region can be reduced. By forming a region, the transistor's lead current flowing between the drain electrode layer and the source electrode layer can be The drain electrode layer, the high-resistance drain region on the drain electrode layer side, and the channel The order is the panel formation region, the high resistance source region on the source electrode layer side, and the source electrode layer. In the channel formation region, the current flows from the high-resistance drain region on the drain electrode layer side to the channel region. The leakage current is induced between the gate insulating layer and the channel formation region, which have high resistance when the transistor is off. The back channel (a region away from the gate electrode layer) can be concentrated near the interface. This can reduce leakage current in the surface of the channel forming region.

[0050] In addition, a high-resistance source region overlapping the source electrode layer and a high-resistance drain region overlapping the drain electrode layer are formed. The gate region overlaps with a part of the gate electrode layer via the gate insulating layer, although this depends on the width of the gate electrode layer. As a result, the electric field strength in the vicinity of the end of the drain electrode layer can be more effectively alleviated.

[0051] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices that use electrophoretic display elements and are also called electronic paper. .

[0052] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring of another transistor, The light-emitting device has a portion to which a drain wiring is connected. In the driving circuit of the thin film transistor, the gate electrode of the thin film transistor and the source The gate electrode has a portion for connecting a wiring or a drain wiring.

[0053] In addition, the manufacturing cost of the semiconductor device can be reduced by fabricating the matrix circuit and the driver circuit on the same substrate. The drive circuit includes circuits that prioritize high-speed operation, such as logic circuits. Such a circuit is formed by using a thin film transistor having a stack of a first oxide semiconductor layer and a second oxide semiconductor layer. The other circuits are configured using a single layer of the third oxide semiconductor layer. This allows for circuits that prioritize high-speed operation, such as logic circuits, to be thin-film-coated with different structures than other circuits. A film transistor can be arranged.

[0054] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source A protection circuit for protecting the thin film transistors in the pixel area can be provided on the same substrate as the line. The protection circuit is preferably configured using a nonlinear element using an oxide semiconductor layer. It's nice.

[0055] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate [Effects of the Invention]

[0056] A semiconductor device including a thin film transistor with excellent electrical characteristics using a stacked oxide semiconductor layer is provided. The periphery and side surfaces of the stacked oxide semiconductor layers are covered with an oxide insulating layer, and a leakage current is reduced. Note that the oxide insulating layer can be formed by insulating a periphery and a side surface of the stacked oxide semiconductor layer. is formed in the same process as the oxide insulating layer that functions as a channel protective layer.

[0057] In addition, a thin film transistor having a stacked oxide semiconductor layer and a thin film transistor having a single oxide semiconductor layer over the same substrate can be fabricated. Thin film transistors having a conductor layer can be fabricated to form a variety of circuits. [Brief explanation of the drawings]

[0058] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 5] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11]1A to 1C illustrate a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating an operation thereof; [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are diagrams illustrating the configuration of a shift register and timing charts illustrating the operation thereof; [Figure 18] 1A to 1C illustrate a semiconductor device. [Figure 19] 1A to 1C illustrate a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A to 1C illustrate a semiconductor device. [Figure 26] 1A to 1C illustrate a semiconductor device. [Figure 27] 1A to 1C illustrate a semiconductor device. [Figure 28] 1A to 1C illustrate a semiconductor device. [Figure 29] 1A to 1C illustrate a semiconductor device. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31] 1A to 1C illustrate a semiconductor device. [Figure 32] 1A to 1C illustrate a semiconductor device. [Figure 33] 1A to 1C illustrate a semiconductor device. [Figure 34] 1A to 1C illustrate a semiconductor device. [Figure 35] 1A to 1C illustrate a semiconductor device. [Figure 36] 1A to 1C illustrate a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0059] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiments. In the configuration described below, parts that have the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for corresponding parts, and repeated explanations thereof will be omitted.

[0060] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. This will be explained using FIG.

[0061] FIG. 1A is a plan view of a channel protective thin film transistor 448 disposed in a pixel. 1(B) is a cross-sectional view taken along line D1-D2 in FIG. 1(A) and a cross-sectional view taken along line D5 in FIG. 1(A). FIG. 1C is a cross-sectional view taken along line D3-D4 in FIG. 1A. It is a cross-sectional view. Note that Fig. 2(E) is the same as Fig. 1(B).

[0062] The thin film transistor 448 disposed in the pixel is a channel protection type (also called a channel stop type). 4) is a thin film transistor, and a gate electrode layer 421 is formed on a substrate 400 having an insulating surface. a, a gate insulating layer 402, a stacked oxide semiconductor layer 442 including a channel formation region 423, The oxide insulating layer 426a serving as a channel protective layer, the source electrode layer 425a, and the drain electrode layer 426b are The thin film transistor 448 is covered with an oxide insulating layer 426. a, a protective insulating layer 403 in contact with the source electrode layer 425a and the drain electrode layer 425b, and A planarization insulating layer 404 is laminated on the drain electrode 402. A pixel electrode layer 427 is provided in contact with the electrode layer 425b. are emotionally connected.

[0063] Note that the stacked oxide semiconductor layer 442 is formed by stacking a metal thin film and an oxide semiconductor layer and then depositing a metal thin film. Since it is obtained by oxidizing a thin film, depending on the materials of the metal thin film and oxide semiconductor layer, Since there are no boundaries, the boundaries of the stacks are shown herein as dotted lines.

[0064] The thin film transistor 448 for the pixel has a high resistance source region 424a, a high resistance drain region 424b, and a 24b, and a stack of oxide semiconductor layers 442 including a channel formation region 423. A high-resistance source region 424a is formed in contact with the lower surface of the electrode layer 425a. A high-resistance drain region 424b is formed in contact with the lower surface of the inner electrode layer 425b. The transistor 448 has a high resistance drain region or a high resistance source region even when a high electric field is applied. The region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is as follows.

[0065] The channel formation region of the thin film transistor 448 disposed in the pixel is formed by stacking the oxide semiconductor layer 442, the oxide insulating layer 426a, which is a channel protective layer, is in contact with the gate electrode layer 4 The thin film transistor 448 is formed by the oxide insulating layer 426a. To protect the source electrode layer 425a and the drain electrode layer 425b, etching is performed. This can prevent the oxide semiconductor layer 442 from being etched in the process.

[0066] In addition, the thin film transistor 448 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device having a light-transmitting property, the source electrode layer 425a and the drain electrode layer 425b are A conductive film having the following structure is used.

[0067] A light-transmitting conductive film is also used for the gate electrode layer 421a of the thin film transistor 448. .

[0068] In addition, the pixel where the thin film transistor 448 is disposed has a pixel electrode layer 427 or other The electrode layer (such as a capacitor electrode layer) and the wiring layer (such as a capacitor wiring layer) are transparent to visible light. By using a conductive film having such a high aperture ratio, a display device having a high aperture ratio can be realized. The oxide insulating layer 426a is also preferably formed using a film that transmits visible light.

[0069] It is also preferable that the metal thin film be oxidized to form a film that is transparent to visible light. The thin film is thin, less than 10 nm, and therefore, although it depends on the material, it is translucent to visible light.

[0070] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes As a metal oxide applied to the wiring layer, a conductive film that is semi-transparent to visible light is used. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0071] In addition, the gate wiring and source wiring crossing portion are designed to reduce parasitic capacitance. Between the gate electrode layer 421b and the source electrode layer 425a, the gate insulating layer 402 and the oxide insulating layer The oxide insulating layer 426b is provided in a region overlapping with the channel formation region 423. The oxide insulating layer 426a and the oxide insulating layer 426b in a region that does not overlap with the channel formation region 423 are different from each other. Although the layers are shown with different reference numerals, they are made of the same material and are formed in the same process.

[0072] 2A to 2E, a thin film transistor 448 and a wiring crossover are formed on the same substrate. The process of manufacturing the difference part will be explained. In addition to the pixel part, the thin film transistor of the driver circuit will also be They may be formed on the same substrate in the same process.

[0073] First, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface, and then a first photo Gate electrode layers 421a and 421b are formed by a lithography process. The gate electrode layers 421a and 421b are made of the same light-transmitting material and the same first photolithography. In addition, when forming not only the pixel section but also the drive circuit, In this case, if a capacitance is required for the drive circuit, a capacitance wiring layer is also formed for the drive circuit. The resist mask may be formed by an ink-jet method. When formed, no photomask is used, thereby reducing manufacturing costs.

[0074] The substrate 400 may be a ceramic substrate, a quartz substrate, or a sapphire substrate in addition to a glass substrate. Alternatively, a substrate made of an insulating material such as silicon dioxide may be used. Alternatively, crystallized glass may be used. do.

[0075] In addition, an insulating film serving as a base film is provided between the substrate 400 and the gate electrode layers 421a and 421b. The base film has a function of preventing diffusion of impurity elements from the substrate 400, and is preferably made of silicon nitride. a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film; The insulating film can be formed by a laminated structure.

[0076] The gate electrode layers 421a and 421b are made of a conductive material that is transparent to visible light, e.g., For example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al -Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The thickness of the gate electrode layer 421 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film formation method used in a and 421b is the sputtering method or vacuum deposition method (electron beam evaporation). The arc discharge ion plating method and spray method are used. When using the targeting method, a target containing 2% to 10% by weight of SiO2 is used. The transparent conductive film contains SiOx (X>0) which inhibits crystallization. Prevents crystallization during the heat treatment for dehydration or dehydrogenation in the process It is preferable.

[0077] Next, the gate insulating layer 402 is formed over the gate electrode layers 421a and 421b.

[0078] The gate insulating layer 402 is formed by depositing a silicon oxide layer using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer in a single layer or For example, SiH4, oxygen, and nitrogen are used as the deposition gas. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a laminate, for example, the thickness is 50 nm to 2 a first gate insulating layer having a thickness of 500 nm or less and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer; The second gate insulating layer is laminated to a thickness of 1 m or less.

[0079] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. This is referred to as insulating layer 402.

[0080] Then, on the gate insulating layer 402, indium, zinc, tin, molybdenum, or tungsten is deposited. Also, thin metal films such as tin are formed. Also, thin alloy films or laminated films of these are used. The metal thin film can be formed by sputtering, vacuum deposition, or coating. Here, an indium film is formed by vapor deposition, preferably to a thickness of more than 0 nm and 10 nm or less. The metal thin film is formed to a thickness of 3 nm or more and 5 nm or less. The oxide has a lower electrical resistivity than the oxide semiconductor layer that is subsequently formed on the metal thin film. Depending on the material of the metal thin film and the film forming conditions, the surface of the gate insulating layer 402 may be Instead of a film covering the surface, a part of the gate insulating layer 402 is exposed, for example, metal clusters. In some cases, metals are dispersed in clusters. However, if it becomes an oxide semiconductor by subsequent oxidation treatment, the electromigration of thin film transistors will be In addition, when metals are dispersed in clusters, the metal and The material is not limited to the above-mentioned materials, but aluminum, copper, etc. can also be used. By forming a thin metal film of indium, we aim to improve the electrical characteristics of thin film transistors. Good too.

[0081] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on the metal thin film. Even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film In order to make the oxide semiconductor amorphous, it is preferable to make the film thickness as thin as 50 nm or less. By thinning the film thickness, when a heat treatment is performed after the formation of the oxide semiconductor layer, the film is crystallized. This can prevent the item from getting dirty.

[0082] The oxide semiconductor film is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based film, an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S In this embodiment, an In—Ga—Zn oxide semiconductor film is used. The film is formed by sputtering using an -O-based oxide semiconductor target. The film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically It can be formed by sputtering in an atmosphere of argon and oxygen. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The oxide semiconductor film is formed by adding SiOx (X>0) which inhibits crystallization. To suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in the above is preferred.

[0083] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), dehydration is performed. It is advantageous to carry out a hydrogenation or dehydrogenation step.

[0084] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[at ratio]) The distance between the substrate and the target was 100 mm, the pressure was 0.2 Pa, and the direct current (DC) Power supply: 0.5 kW, argon and oxygen (argon: oxygen = 30 sccm: 20 sccm acid The film is formed in an atmosphere with a flow rate of 40%. This is preferable because it reduces the damage and makes the film thickness distribution uniform. In this embodiment, the oxide semiconductor film is formed of an I A 20 nm thick film was deposited by sputtering using an n-Ga-Zn-O oxide semiconductor target. An In-Ga-Zn-O based non-single crystal film is formed.

[0085] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0086] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0087] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0088] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0089] Next, the stack of the metal thin film and the oxide semiconductor film is formed into island-like layers by a second photolithography process. The metal layer 428 and the island-shaped oxide semiconductor layer 429 are processed. A resist mask for forming the oxide semiconductor layer 429 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0090] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than the distortion point of the substrate, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. The heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. A conductor layer 442 is obtained. In this embodiment, the oxide semiconductor layer is dehydrated or dehydrogenated. From the heating temperature T, use the same furnace to a temperature high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the temperature T. It is not dehydrated or dehydrogenated under a rare gas atmosphere such as helium, neon, or argon. Do the following.

[0091] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0092] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. It may also be a crystalline or polycrystalline film.

[0093] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0094] Alternatively, the metal layer 428 may be oxidized by the first heat treatment to form an oxide semiconductor layer. In addition, the first heat treatment is not limited to oxidizing the metal layer 428. Apart from the treatment, an oxidation treatment may be performed to oxidize the metal layer 428, e.g. After the oxide insulating film is formed by a sputtering method, oxidation treatment may be performed.

[0095] Next, an oxide insulating film 44 is formed over the gate insulating layer 402 and the oxide semiconductor layer by a sputtering method. 6 is formed (see FIG. 2(A)).

[0096] Next, a resist mask is formed by a third photolithography process and selectively etched. After that, the resist mask is removed. At this stage, a region in contact with the oxide insulating layer is formed in the stacked oxide semiconductor layer. The oxide insulating layer 426a overlaps with the gate electrode layer and the gate insulating layer 426b. The overlapping region is a channel formation region. A region overlapping with the oxide insulating layer 426b is also formed.

[0097] The oxide insulating film should have a thickness of at least 1 nm. The film can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the film. In this embodiment, a silicon oxide film with a thickness of 300 nm is deposited as an oxide insulating film by sputtering. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. The silicon oxide film is formed by sputtering using a rare gas (typically argon). In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used under an oxygen and nitrogen atmosphere. A silicon oxide film can be formed by sputtering. The oxide insulating film formed in contact with the body layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, an inorganic insulating film is used to block these substances from entering from the outside, typically an oxide film. A silicon film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. do.

[0098] Next, a second heat treatment (preferably The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see FIG. 2(B)). For example, a second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. As a result of the treatment, an end portion of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426b and an oxide insulating layer 426c are A part of the oxide semiconductor layer 442 overlapping with the insulating layer 426a is heated while being in contact with the oxide insulating layer. Note that when the second heat treatment is performed, the oxide semiconductor layer in the stack that does not overlap with the oxide insulating layer is removed. The oxide semiconductor layer 442 is heated in a partially exposed state. When heat treatment is performed in a nitrogen or inert gas atmosphere in this state, the oxide semiconductor layer 4 The high resistance (I-type) region exposed in 42 can be made low resistance. The oxide insulating layer 426a can be formed between the channel formation region of the oxide semiconductor layer 442 and the oxide insulating layer 426b. The layer is provided on and in contact with the region and functions as a channel protection layer.

[0099] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the stacked oxide semiconductor After forming a light-transmitting conductive film on the conductive layer 442, a fourth photolithography process is performed. A resist mask is formed on the insulating film, and selective etching is performed to form the source electrode layer 425a and The drain electrode layer 425b is formed (see FIG. 2C). The deposition methods include sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion plating. The conductive film is made of a material that is transparent to visible light. Conductive materials such as In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn -Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides The thickness of the film is appropriately selected within the range of 50 nm to 300 nm. When using a sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The transparent conductive film is formed by adding SiOx (X>0) which inhibits crystallization. It is preferable to suppress crystallization during a heat treatment carried out in a subsequent step.

[0100] Note that a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b is used. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0101] Next, the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 A protective insulating layer 403 is formed on the insulating film 5b. In this embodiment, a nitriding layer is formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is the method for forming the protective insulating layer 403. The protective insulating layer 403 is preferably formed of a material that can absorb moisture, hydrogen ions, and OH ions. - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films and nitride films are used. Aluminum nitride film, silicon nitride oxide film, aluminum oxynitride film, etc. are used. The edge layer 403 is a light-transmitting insulating film.

[0102] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403. Examples include polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy. In addition to the above organic materials, organic materials having heat resistance such as acrylic resins can be used. Low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphor glass), BPSG (phosphorus boron glass) and the like can be used. Note that insulating films formed from these materials can also be used. The planarization insulating layer 404 may be formed by stacking a plurality of such films.

[0103] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0104] The method for forming the planarization insulating layer 404 is not particularly limited, and may be a sputtering method, a SO 4 method, or the like, depending on the material. G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing methods such as inkjet printing, offset printing, etc. can be used. The coating can be performed using a coater, curtain coater, knife coater, or the like.

[0105] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. A hole 441 is formed, and the resist mask is removed (see FIG. 2(D)). ) an oxide insulating layer 426b is provided below the contact hole, The amount of planarization insulation removed compared to when no oxide insulating layer is provided below the contact hole is The thickness of the insulating layer can be reduced, and the etching time can be shortened. The depth of the contact hole 441 is smaller than that when no oxide insulating layer is provided below the contact hole. In the region overlapping with the contact hole 441, In addition, the coverage of the light-transmitting conductive film can be improved. A contact hole reaching the gate electrode layer 421b is also formed by this etching. A resist mask for forming a contact hole reaching the drain electrode layer 425b is applied. If the resist mask is formed by the ink jet method, the photoresist Since no mask is used, manufacturing costs can be reduced.

[0106] Next, a light-transmitting conductive film is formed. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The transparent conductive film (abbreviated as O) is formed by sputtering or vacuum deposition. As another material for the conductive film, a nitrogen-containing Al-Zn-O-based non-single crystal film, i.e., Al-Zn- ON-based non-single crystal film, Zn-ON-based non-single crystal film, Sn-Zn-ON-based non-single crystal film The composition ratio (atomic %) of zinc in the Al-Zn-ON non-single crystal film may be: The composition ratio (atomic %) of aluminum in the non-single crystal film is 47 atomic % or less, which is larger than the composition ratio (atomic %) of aluminum in the non-single crystal film. The aluminum composition ratio (atomic %) in the crystalline film is the same as the nitrogen composition ratio (atomic %) in the non-single-crystalline film. The etching process for such materials is carried out with a hydrochloric acid-based solution. ITO etching tends to leave residue, so we used an oxidizing agent to improve etching processability. An indium zinc oxide alloy (In2O3-ZnO) may also be used.

[0107] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0108] Next, a sixth photolithography step is performed to form a resist mask, and then etching is performed. Then, unnecessary portions are removed to form a pixel electrode layer 427, and the resist mask is removed (FIG. 2( See E). ).

[0109] By the above steps, a thin film transistor 448 and a semiconductor device 449 are formed on the same substrate using six masks. It is possible to fabricate wiring intersections with reduced parasitic capacitance. 8 is a high-resistance source region 424a, a high-resistance drain region 424b, and a channel forming region 423 and the oxide semiconductor layer 442. Therefore, the thin film transistor 448 has a high resistance drain region 424 even when a high electric field is applied. b or high-resistance source region 424a acts as a buffer, preventing a local high electric field from being applied, The structure improves the breakdown voltage of the transistor.

[0110] In addition, the storage capacitor formed by the capacitance wiring layer and the capacitance electrode with the gate insulating layer 402 as a dielectric is The thin film transistor 448 and the storage capacitor can be formed on the same substrate. The pixels are arranged in a matrix to form an active matrix display device. For convenience, this specification will refer to such a substrate as an This is called an active matrix substrate.

[0111] In addition, thin film transistors of the driver circuits can be provided on the same substrate. By forming a driving circuit and a pixel section, connection wiring for external signals input to the driving circuit This allows for a reduction in the size and cost of the semiconductor device.

[0112] In addition, the oxide semiconductor layer 442 of the stack of the pixel thin film transistor 448 shown in FIG. The first region 424c and the second region 424d overlapping the oxide insulating layer 426b are located at the periphery. The first region 424c, which is the peripheral portion of the stacked oxide semiconductor layer 442, and the second region 4 The region 24d is in the same oxygen-excess state as the channel formation region 423, and has a structure with a different potential nearby. When a wire or stacked oxide semiconductor layer is arranged, leakage current and parasitic capacitance are reduced. It can be realized.

[0113] In addition, by providing the oxide insulating layer 426b, even if the metal thin film is not oxidized, The structure covers the side of the metal thin film even when the source electrode layer and drain electrode layer are short-circuited. It is as follows.

[0114] In particular, in the driver circuit, in order to achieve high integration, the spacing between multiple wirings and multiple oxide semiconductor layers is The first region 424c is preferably narrowed by overlapping with the oxide insulating layer 426b. It is effective to provide the second region 424d to reduce leakage current and parasitic capacitance. In addition, when a plurality of thin film transistors are arranged in series or in parallel, The oxide semiconductor layer of the transistor is treated as an island, and each element is isolated by oxide insulation. The region overlapping with the oxide insulating layer 426b is used as an element isolation region. In this way, it is possible to arrange multiple thin film transistors in a small area. Therefore, the driver circuit can be highly integrated.

[0115] (Embodiment 2) In this embodiment mode, the thin film transistor described in Embodiment Mode 1 is used to form a pixel on the same substrate. An example of forming a pixel portion and a driver circuit to fabricate an active matrix liquid crystal display device will be shown.

[0116] An example of the cross-sectional structure of an active matrix substrate is shown in FIG.

[0117] In the first embodiment, the thin film transistors and the wiring intersections of the pixel portion are illustrated. In this state, in addition to the thin film transistors and wiring intersections, the thin film transistors of the drive circuit and the storage capacitors The capacitor, gate wiring, and source wiring terminals are also shown in the figure. The terminal portion of the wire can be formed by the same manufacturing process as that described in Embodiment 1. In the display area of ​​the pixel section, the gate wiring, source wiring, and capacitance wiring layer are all The light-transmitting conductive film is used to realize a high aperture ratio.

[0118] In FIG. 3A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is This is a channel protection type thin film transistor provided in a pixel portion. The thin film transistor 220 has the same structure as the thin film transistor 448 of the first embodiment. The width of the gate electrode layer in the channel length direction is equal to the width of the oxide semiconductor layer of the thin film transistor 220. Narrower than the width in the longitudinal direction of the panel.

[0119] The gate electrode layer of the thin film transistor 220 is formed of the same material and in the same process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is connected to the capacitor electrode 231 via the gate insulating layer 202 which serves as a dielectric. The capacitor electrode 231 overlaps with the source of the thin film transistor 220. The light-transmitting layer is formed of the same material and in the same process as the source electrode layer or the drain electrode layer. Therefore, in addition to the thin film transistor 220 having light-transmitting properties, each storage capacitor Since the transparent film also has light-transmitting properties, the aperture ratio can be improved.

[0120] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is made smaller to achieve higher resolution, a high aperture ratio can be achieved. By using a light-transmitting film as a component of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a group of high-density thin film transistors is arranged, a large aperture ratio can be obtained. For example, if two to four pixels are arranged in one pixel, the area of ​​the display region can be sufficiently secured. When there are four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is also transparent, which can improve the aperture ratio. do.

[0121] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is connected to the pixel electrode layer 2 27 is electrically connected to the

[0122] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the gate insulating layer therebetween.

[0123] In addition, in FIG. 3(A), the storage capacitor forms a large capacitance, so the capacitance wiring and the capacitance electrode The gate insulating layer 202 is only provided between the wirings, and the wiring crossings are provided with a gate insulating layer 202 to reduce parasitic capacitance. The gate electrode layer 421b and the wiring formed thereon are provided with the gate insulating layer 202 and the oxide insulating layer 203. In the storage capacitor, a gate insulating layer is provided between the capacitor wiring and the capacitor electrode. In the case where only the oxide insulating layer 202 is used, the oxide insulating layer 266b is selectively removed by etching. Select etching conditions or a material for the gate insulating layer so that only the gate insulating layer 202 remains. In this embodiment, the oxide insulating layer 266b is a silicon oxide film obtained by a sputtering method, and the gate Since the insulating layer 202 is a silicon nitride film obtained by plasma CVD, it can be selectively removed. Note that the oxide insulating layer 266b and the gate insulating layer 202 can be etched under the same etching conditions. When a removable material is used, a part of the gate insulating layer is thinned by etching. It is preferable that the thickness of the gate insulating layer is such that at least the gate insulating layer remains and a capacitance can be formed. In order to increase the storage capacitance, it is preferable to make the thickness of the gate insulating layer thin. Therefore, when the oxide insulating layer 266b is selectively etched, the gate insulating layer on the capacitance wiring is thinned. It may also be configured as a single unit.

[0124] The thin film transistor 260 is a channel protection type thin film transistor provided in the drive circuit. The channel length L is shorter than that of the thin film transistor 220, and the operating speed is increased. The channel length of the channel protection type thin film transistor provided in the drive circuit is It is preferable that L is set to 0.1 μm or more and 2 μm or less. The width of the thin film transistor 260 in the channel length direction is equal to the width of the oxide semiconductor layer of the thin film transistor 260. The end face of the gate electrode layer 261 is wider than the width in the longitudinal direction of the panel, and the end face of the gate electrode layer 261 is in contact with the gate insulating layer 202 and the oxide The insulating layer 266b overlaps with the source electrode layer 265a or the drain electrode layer 265b. .

[0125] In addition, the thin film transistor 260 is formed by forming an oxide semiconductor film after removing the metal thin film. The oxide semiconductor layer is formed as a single layer, and the thickness of the oxide semiconductor layer is thinner than that of the thin film transistor 220. As a result, the operation speed is increased. In the case of a single layer, the metal thin film is selectively etched, so the acid of the thin film transistor 260 is Compared to when the compound semiconductor layers are stacked, the number of photomasks increases by one.

[0126] The thin film transistor 260 is formed by forming a gate electrode layer 261, a gate electrode layer 262, a gate electrode layer 263, a gate electrode layer 264, a gate electrode layer 265, a gate electrode layer 266, a gate electrode layer 267, a gate electrode layer 268, a gate electrode layer 269 ... a source insulating layer 202, at least a channel forming region 263, a high resistance source region 264a, and the oxide semiconductor layer having the high-resistance drain region 264b, the source electrode layer 265a, and the drain electrode layer The oxide insulating layer 26 6a is provided.

[0127] In addition, the gate electrode layer of the thin film transistor 260 of the driving circuit is provided above the oxide semiconductor layer. In this case, the thin film transistor 264 may be electrically connected to the conductive layer 267. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as the tact hole, the planarization insulating layer 204, the protective insulating layer 203, and the oxide The insulating layer 266b and the gate insulating layer 202 are selectively etched to form contact holes. Through this contact hole, the conductive layer 267 and the thin film transistor 26 of the driving circuit are connected. 0 and the gate electrode layer 261 are electrically connected.

[0128] The protective insulating layer 203 is made of an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. A silicon nitride film, an aluminum oxynitride film, or the like is used. In this embodiment mode, a silicon nitride film is used.

[0129] In addition, in the thin film transistor 260, the width of the gate electrode layer 261 is smaller than the width of the oxide semiconductor layer. The oxide insulating layer 266b overlaps with the periphery of the oxide semiconductor layer. The oxide insulating layer 266b overlaps with the gate electrode layer 261. The distance between the drain electrode layer 265b and the gate electrode layer 261 is widened. This serves to reduce the parasitic capacitance formed between the oxide layer and the gate electrode layer 261. The first region 264c and the second region 264d of the oxide semiconductor layer overlapping the oxide insulating layer 266b are The same oxygen-excess state as the channel formation region 263 is present, reducing leakage current and parasitic capacitance. It also has a reducing function.

[0130] In addition, the size of LCD display panels has exceeded 10 inches, reaching 60 inches and even 120 inches. In this case, the wiring resistance of the light-transmitting wiring may become a problem. It is preferable to use metal wiring to reduce wiring resistance. For example, as shown in Figure 3(A), The source electrode layer 265a and the drain electrode layer 265b are made of metal wiring (metal electrodes) such as Ti. do.

[0131] In this case, a metal electrode such as Ti is formed on the dehydrated or dehydrogenated oxide semiconductor layer. A source electrode layer and a drain electrode layer are formed, and a high resistance source region overlapping the source electrode layer is formed. A high-resistance drain region overlapping the drain electrode layer is formed, and a high-resistance source region and a high-resistance The region between the drain region becomes a channel forming region.

[0132] In addition, in order to reduce the wiring resistance, as shown in FIG. 3(A), the source electrode layer 265a and the drain electrode layer 265b are Auxiliary electrode layers 268a and 268b using metal electrodes with lower resistance are formed on the main electrode layer 265b. In this case, metal wiring (metal electrodes) is also formed, so the process is more efficient than in the first embodiment. The number of photomasks increases by one.

[0133] Source electrode layer 265a, drain electrode layer 265b, auxiliary electrode layers 268a, 268b, thin film The source electrode layer and the drain electrode layer of the transistor 220 are formed of a light-transmitting conductive film and a gold film. It is formed by laminating metal conductive films and selectively etching them using a photolithography process. The metal conductive film on the source electrode layer and drain electrode layer of the film transistor 220 is removed.

[0134] During etching of the metal conductive film, the source electrode layer and the drain electrode layer of the thin film transistor 220 are The materials and etching conditions are adjusted appropriately so that the inner electrode layer is not removed.

[0135] For example, an alkaline etchant is used to selectively etch a metal conductive film. The material of the metal conductive film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. or an alloy containing the above elements, or an alloy film of a combination of the above elements, etc. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of aluminum film containing silicon, a titanium film stacked on an aluminum film, A two-layer structure is formed by laminating a Ti film and an aluminum film on top of the Ti film. Also, titanium (Ti) and tantalum (Ta) are used in combination with Al. Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (N d) and scandium (Sc), a film or alloy film made of a single or multiple combinations of elements selected from the group consisting of Alternatively, a nitride film may be used.

[0136] In this embodiment mode, a Ti film is used as the metal conductive film, and the source electrode layer and the drain electrode layer are In-Sn-O oxide was used for the etching, and ammonia hydrogen peroxide (ammonia) was used as the etchant. A mixture of water, hydrogen peroxide, and water is used.

[0137] A drain electrode layer provided between the oxide semiconductor layer and the auxiliary electrode layer 268b made of a metal material. 265b is the low resistance drain region (LRN (Low Resistance N-type conductivity) area, LRD (Low Resistance Drai) n) region), the oxide semiconductor layer, the low-resistance drain region, the metal electrode By using the auxiliary electrode layer 268 having the above structure, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration in the low-resistance drain region is higher than that in the high-resistance drain region. area (HRD area), e.g., 1×1020 / cm 3 More than 1×10 21 / cm 3 It is preferable that the content is within the following range.

[0138] Also, a plurality of gate wirings, source wirings, and capacitance wiring layers are provided depending on the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate wiring, a source wiring, a second terminal electrode having the same potential as the capacitor wiring layer, a third terminal electrode having the same potential as the capacitor wiring layer, and so on are arranged in a row. The number of each terminal electrode may be any number. The contractor should make the appropriate decision.

[0139] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good conductivity. The contact hole is electrically connected to the gate wiring. The wiring electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the planarization insulating layer 204 and the protective insulating layer 205 is used. The edge layer 203 is selectively etched.

[0140] In addition, a second terminal electrode 255 having the same potential as the source wiring 254 and auxiliary wiring 269 of the terminal portion The second terminal electrode layer 224 can be formed of the same light-transmitting material as the pixel electrode layer 227. The electrode 255 is electrically connected to the source wiring through a contact hole that reaches the source wiring 254. The source wiring 254 is connected to the source electrode layer 265a of the thin film transistor 260. On the other hand, the auxiliary wiring 269 is formed of the same material in the same process and has the same potential. 4 is a metal wiring using a metal material with lower resistance than the auxiliary electrode layer of the thin film transistor 260. It is made of the same material and in the same process as 268a and 268b, and has the same potential.

[0141] The third terminal electrode, which has the same potential as the capacitor wiring layer 230, has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitor wiring layer 230 can be formed of a material having the above-mentioned properties. The contact holes are formed at the same time as the contact holes for electrically connecting the capacitor electrodes 231 to the pixel electrode layer 227. The same photomask can be used in the same process.

[0142] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the counter substrate on which the counter electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. The fourth terminal electrode is provided at the terminal portion. This fourth terminal electrode is connected to the common electrode at a fixed potential, for example, GND, 0 The fourth terminal electrode is a terminal for setting V, etc. The fourth terminal electrode has the same light-transmitting property as the pixel electrode layer 227. The insulating film may be formed of a material having the following properties:

[0143] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the wiring layers, a common sputtering target and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gases, resulting in reduced manufacturing costs. It is possible.

[0144] In the structure of FIG. 3A, a photosensitive resin material is used as the planarization insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0145] FIG. 3(B) shows a cross-sectional structure that is partially different from that shown in FIG. 3(A). A) The absence of the planarization insulating layer 204 at the terminal portion and the structure of the thin film transistor of the driving circuit Since the same parts are the same except for the difference in In FIG. 3B, a thin film transistor 270 using metal wiring is disposed. Furthermore, the terminal electrodes are formed using the same material and process as the metal wiring.

[0146] In the structure of FIG. 3(B), a photosensitive resin material is used as the planarization insulating layer 204. Therefore, the step of forming a resist mask can be omitted. In this case, the planarization insulating layer 204 may not be present in the terminal portion. The absence of a planarizing insulating layer makes it easier to make a good connection with the FPC.

[0147] The thin film transistor 270 is formed by forming a gate electrode layer 271, a gate electrode layer 272, a gate electrode layer 273, a gate electrode layer 274, a gate electrode layer 275, a gate electrode layer 276, a gate electrode layer 277, a gate electrode layer 278, a gate electrode layer 279 ... The source insulating layer 202, at least the channel forming region 273, the high resistance source region 274a, and the oxide semiconductor layer having the high-resistance drain region 274b, the source electrode layer 275a, and the drain electrode layer The drain electrode layer 275b is also an oxide insulating layer 27 6a is provided.

[0148] In addition, the first region 274c and the second region 274d of the oxide semiconductor layer overlap with the oxide insulating layer 276b. 4d is in the same oxygen-excess state as the channel formation region 273, and is effective in reducing leakage current and reducing parasitic The oxide semiconductor layer 203 in contact with the protective insulating layer 203 also serves to reduce parasitic capacitance. The third region 274e is provided between the channel forming region 273 and the high resistance source region 274a. In addition, the fourth region 274f of the oxide semiconductor layer in contact with the protective insulating layer 203 is a channel region. The protective insulating layer 203 is provided between the drain forming region 273 and the high-resistance drain region 274b. The third region 274e and the fourth region 274f of the oxide semiconductor layer, which are in contact with each other, are intended to reduce the off-state current. It is possible.

[0149] In addition, the channel protection type thin film transistor has a channel length L of the channel formation region shortened. In order to achieve this, the width of the oxide insulating layer is narrowed, and the source electrode layer and the drain electrode layer are formed on the narrow oxide insulating layer. If a thin oxide insulating layer is provided, there is a risk of short-circuiting on the oxide insulating layer. The source electrode layer 275a and the drain electrode layer 275b are provided at the ends separated from the edge layer 276a. This is the configuration.

[0150] When etching the metal conductive film, the oxide semiconductor layer of the thin film transistor 270 is also removed. The materials and etching conditions are adjusted appropriately so that this does not occur.

[0151] In this embodiment, a Ti film is used as the metal conductive film, and an In-Ga- Zn-O oxide was used, and ammonia hydrogen peroxide (ammonia, water, hydrogen peroxide) was used as an etchant. A mixture of hydrogen peroxide and water is used.

[0152] In addition, the gate electrode layer of the thin film transistor 270 of the driving circuit is provided above the oxide semiconductor layer. Alternatively, the insulating layer 274 may be electrically connected to the conductive layer 277 .

[0153] The second terminal electrode 257, which has the same potential as the source line 256 of the terminal portion, is connected to the pixel electrode layer 227. The source wiring is a metal wiring, and can be formed of a thin film. The source electrode layer 275a of the transistor 270 is formed of the same material and in the same process, and has the same potential. be.

[0154] In addition, thin film transistors are easily damaged by static electricity, etc. The protection circuit is preferably provided over the same substrate as the gate insulating film. It is preferable to configure it using a nonlinear element. For example, the protection circuit is In this embodiment, a plurality of protection circuits are provided between the terminal and the signal line input terminal. In this case, a surge voltage is applied to the scanning lines, signal lines, and capacitance bus lines due to static electricity, etc., and the pixel transistors are turned off. It is designed to prevent damage to transistors, etc. Therefore, the protection circuit has a surge current When a voltage is applied, the charge is released to the common wiring or the common wiring. The protection circuit is composed of nonlinear elements arranged in parallel with the scanning lines. The elements and nonlinear elements may be two-terminal elements such as diodes or three-terminal elements such as transistors. For example, it can be formed in the same process as the thin film transistor 220 in the pixel portion. For example, by connecting the gate terminal and the drain terminal, it can be made to function like a diode. It can have the following characteristics.

[0155] Note that the step of forming the planarization insulating layer 204 may be omitted, and a structure without the planarization insulating layer 204 may be used. In this case, the conductive layer 267, the conductive layer 277, the pixel electrode layer 227, the second terminal electrode 255 and 257 are provided on and in contact with the protective insulating layer 203 .

[0156] This embodiment mode can be freely combined with Embodiment Mode 1.

[0157] (Embodiment 3) In this embodiment, one of the configurations of the terminal portion provided on the same substrate as the thin film transistor is In the second embodiment, an example of the terminal portion of the source wiring is shown. Illustrated are the terminal portions of the source wiring and the gate wiring, which have different configurations from those of the second embodiment. In FIG. 4, the same parts as those in FIG. 3(A) or 3(B) are designated by the same reference numerals. explain.

[0158] 4(A1) and 4(A2) are a top view and a cross-sectional view, respectively, of the gate line terminal portion. FIG. 4(A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 4(A2). In (A1), the conductive layer 225 formed on the protective insulating layer 203 functions as an input terminal. In FIG. 4(A1), the terminal portion is a terminal electrode for connection. The first terminal 221 is made of the same material as the layer 421b, and the second terminal 221 is made of the same material as the source line. a connecting electrode layer 223 formed of a metal electrode material having a lower resistance than the connecting electrode layer 223; The electrode layer 228 overlaps with the gate insulating layer 202 interposed therebetween, and is electrically connected by the conductive layer 225. In addition, when the connection electrode layer 223 has the structure shown in FIG. 3(B), a metal wiring material is used. This can be done.

[0159] 4(B1) and 4(B2) are different from the source line terminal portion shown in FIG. 3(B). 4(B1) shows a top view and a cross-sectional view of the source wiring terminal portion. This corresponds to a cross-sectional view taken along the line C3-C4 in FIG. 4(B2). The conductive layer 225 formed on the insulating layer 203 is a connection terminal electrode that functions as an input terminal. In addition, in FIG. 4(B1), the terminal portion is formed of the same material as the gate wiring. An electrode layer 226 is formed on the gate insulating layer 224 below the second terminal 222 which is electrically connected to the source wiring. The electrode layer 226 is not electrically connected to the second terminal 222. , the electrode layer 226 is set to a potential different from that of the second terminal 222, for example, floating, GND, or 0V. By setting the value to 0, it is possible to form a capacitance for noise countermeasures or static electricity countermeasures. In addition, a metal electrode material having a lower resistance than the second terminal 222 is provided on the second terminal 222. An auxiliary electrode layer 229 made of a material is laminated on the protective insulating layer 203. The second terminal 222 is electrically connected to the conductive layer 225 through the hole. In the case of the configuration shown in (B), a metal wiring material can be used.

[0160] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0161] This embodiment mode can be freely combined with Embodiment Mode 1 or 2.

[0162] (Fourth embodiment) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, A common connection portion is formed on the first substrate for electrically connecting with the counter electrode provided on the second substrate. An example in which a thin film transistor is formed as a switching element on the first substrate is shown. The manufacturing process of the common connection part is made common to the manufacturing process of the switching element of the pixel part. This allows the formation without complicating the process.

[0163] The common connection portion is disposed at a position overlapping the sealant for bonding the first substrate and the second substrate. The sealing material is electrically connected to the counter electrode via conductive particles contained in the sealing material. The common connection part is provided in a place where it does not overlap with the sealing material (excluding the pixel part), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap the opposing electrode. A connection is made.

[0164] FIG. 5A is a cross section of a semiconductor device in which a thin film transistor and a common connection portion are fabricated on the same substrate. FIG.

[0165] In FIG. 5A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is This is a channel protection type thin film transistor provided in a pixel portion. The same structure as the thin film transistor 448 of the first embodiment is used.

[0166] FIG. 5B is a diagram showing an example of a top view of the common connection portion, and the chain line C5-C6 in the diagram This corresponds to the cross section of the common connection part in Fig. 5(A). The same reference numerals will be used for the parts.

[0167] The common potential line 205 is provided on the gate insulating layer 202 and is connected to the source of the thin film transistor 220. The common potential line 2 is made of the same material and in the same process as the source electrode layer and the drain electrode layer. On the substrate 05, an auxiliary wiring 21 made of metal wiring fabricated by the same material and process as the auxiliary electrode layer is formed. 0 is formed.

[0168] The common potential line 205 is covered with a protective insulating layer 203. The thin film transistor 2 has a plurality of openings at positions overlapping the line 205. The contact hole connecting the drain electrode layer 20 and the pixel electrode layer 227 is formed in the same process. It is manufactured.

[0169] In this case, the area size is significantly different, so the contact hole in the pixel area and the common area are In addition, in FIG. 5(A), the pixel section and the common connection section are For example, the length of the chain line C5-C6 at the common connection is 500 mm. The width of a thin film transistor is less than 50 μm, and in fact it is about 10 The area size is more than twice as large, but for ease of understanding, the pixel section and common connection section are shown in Figure 5(A). The figures are shown at different scales.

[0170] The common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made of the same materials and in the same process as

[0171] In this way, the manufacturing process of the common connection portion is common to the manufacturing process of the switching element of the pixel portion. conduct.

[0172] A first substrate on which a pixel section and a common connection section are provided and a second substrate having an opposing electrode are then Secure it in place using a sealant.

[0173] When the sealing material contains conductive particles, the sealing material and the common connection part are overlapped with each other. For example, in a small LCD panel, the diagonal corners of the pixel area are aligned. Two common connection parts are placed over the sealing material. In addition, in large LCD panels, Four or more common connections are arranged overlapping the sealant.

[0174] The common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material. The electrode is electrically connected to the counter electrode of the substrate.

[0175] When using the liquid crystal injection method, a pair of substrates are fixed together with a sealant, and then liquid crystal is injected between the pair of substrates. In addition, when the liquid crystal dropping method is used, a sealing material is applied to the second substrate or the first substrate. After the liquid crystal is dropped, the pair of substrates are bonded together under reduced pressure.

[0176] In this embodiment, an example of a common connection portion electrically connected to the counter electrode is shown. It is not limited to, but is used for connecting parts to other wiring or connecting parts to external connection terminals, etc. It is possible.

[0177] FIG. 5(C) shows a cross-sectional structure that is partially different from that shown in FIG. 5(A). A) and the oxide insulating layer covering the oxide semiconductor layer and the edge of the stack overlapping with the common electrode layer 206 are present. The configuration is the same except for the presence of a metal wiring as a common potential line. The same reference numerals are used in the places, and detailed explanations of the same parts will be omitted.

[0178] The stacked oxide semiconductor layer 207 is provided on the gate insulating layer 202, and The oxide semiconductor layer is formed using the same material and process as the oxide semiconductor layer of the stack of 20. An oxide insulating layer 208 is formed to cover the oxide semiconductor layer 207. A common potential line 209 made of metal wiring is formed. As shown in FIG. 3B of the second embodiment, the source electrode layer of the thin film transistor of the driving circuit Alternatively, the insulating film 12 is formed in the same process as the drain electrode layer.

[0179] The common electrode layer 206 is covered with a protective insulating layer 203, which is connected to a common potential The thin film transistor 209 has a plurality of openings at positions overlapping the line 209. The contact hole connecting the drain electrode layer 20 and the pixel electrode layer 227 is formed in the same process. It is manufactured.

[0180] The common potential line 209 is provided on the protective insulating layer 203 and is connected to the pixel electrode layer 227 of the pixel portion. It is made of the same materials and in the same process as

[0181] In this way, the manufacturing process of the common connection portion is common to the manufacturing process of the switching element of the pixel portion. The common potential line may be made of metal wiring to reduce wiring resistance.

[0182] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 3.

[0183] (Embodiment 5) In the first and second embodiments, an example in which the gate insulating layer is a single layer is shown. An example of lamination is shown below. In FIG. 6, the same parts as in FIG. 3(A) or FIG. 3(B) are will be explained using the same symbols.

[0184] In FIG. 6A, a thin film transistor 280 is a channel protective thin film transistor provided in a pixel. This is an example of a film transistor having two gate insulating layers and two oxide semiconductor layers. The thin film transistor 260 is a channel protection type thin film transistor provided in the drive circuit. The gate insulating layer is a two-layer structure, and the oxide semiconductor layer is a single layer structure. The thin film transistor 260 shown in FIG. 6A is the same as the thin film transistor 260 shown in FIG. Therefore, the description will be omitted here.

[0185] In this embodiment, a first gate insulating layer 282a having a film thickness of 50 nm or more and 200 nm or less, a second gate insulating layer 282b having a thickness of 50 nm or more and 300 nm or less; The first gate insulating layer 282a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. The second gate insulating layer 282b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0186] The thin film transistor 280 includes a gate electrode layer 281, a second gate electrode layer 282, a gate electrode layer 283, a gate electrode layer 284, a gate electrode layer 285, a gate electrode layer 286, a gate electrode layer 287, a gate electrode layer 288, a gate electrode layer 289 ...1, a gate electrode layer 282, The first gate insulating layer 282a, the second gate insulating layer 282b, and at least the channel forming region 283, a stacked oxide having a high-resistivity source region 284a, and a high-resistivity drain region 284b. The gate insulating film 285 includes a gate insulating film 285b, a source electrode layer 285a, and a drain electrode layer 285b. A laminated oxide insulating layer 286a is provided in contact with the panel forming region 283. The first region 284c and the second region 284d of the stacked oxide semiconductor layer overlapping the layer 286b are The oxygen-excess state is the same as that of the channel formation region 283, and the leakage current is reduced and the parasitic capacitance is reduced. The pixel electrode layer 227 also functions to reduce the electric field. is connected to.

[0187] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is connected to the pixel electrode layer 2 27 is electrically connected to the

[0188] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. .

[0189] In addition, in FIG. 6(A), the storage capacitor forms a large capacitance, so the capacitance wiring and the capacitance electrode Only the gate insulating layer is provided between them.

[0190] In this embodiment, a silicon oxide film obtained by a sputtering method is used as the oxide insulating layer 286b. When removing the oxide insulating layer of the stack that overlaps the capacitor wiring layer 230, the second silicon oxide film is removed. In this example, the gate insulating layer is also thinned by etching to form a third gate insulating layer 282c. The first gate insulating layer 282a is a silicon nitride film or a silicon nitride oxide film, and is etched. It functions as an etching stopper to prevent etching damage to the gate electrode layer and substrate.

[0191] By making the third gate insulating layer 282c thin, it is possible to increase the storage capacitance. can.

[0192] Also, Fig. 6(B) shows a cross-sectional structure that is partly different from Fig. 6(A). The thin film transistor 290 is a channel protection type thin film transistor provided in the pixel. In this example, the gate insulating layer is two layers, and the gate insulating layer is two oxide semiconductor layers. The transistor 245 is a channel protection type thin film transistor provided in the driving circuit, and has a gate insulating layer. The thin film transistor shown in FIG. 6(B) has two oxide semiconductor layers, and is an example of a single oxide semiconductor layer. The transistor 245 is formed by the auxiliary electrode layer 26 in the thin film transistor 260 shown in FIG. Since the structure is the same except that 8a and 268b are not provided, a description thereof will be omitted here. Like the thin film transistor 245, a transparent solenoid is used without providing an auxiliary electrode layer in the driver circuit. A structure consisting of only a source electrode layer and a drain electrode layer may also be used.

[0193] In the thin film transistor 290 shown in FIG. 6B, the first a first gate insulating layer 292a and a second gate insulating layer 292b having a thickness of 1 nm to 50 nm; The first gate insulating layer 292a is a 100 nm thick oxide film. The second gate insulating layer 292b is a silicon nitride film having a thickness of 10 nm. A bare film or a silicon nitride oxide film is used.

[0194] The thin film transistor 290 includes a gate electrode layer 291, a second gate electrode layer 292, a gate electrode layer 293, a gate electrode layer 294, a gate electrode layer 295, a gate electrode layer 296, a gate electrode layer 297, a gate electrode layer 298, a gate electrode layer 29 ...1, a gate electrode layer 292, The first gate insulating layer 292a, the second gate insulating layer 292b, and at least the channel forming region 293, a high-resistivity source region 294a, and a high-resistivity drain region 294b. The gate insulating film 295 includes a gate insulating film 295b, a source electrode layer 295a, and a drain electrode layer 295b. An oxide insulating layer 296a is provided in contact with the panel formation region 293.

[0195] In addition, the first region 294c and the second region 294d of the stacked oxide semiconductor layer overlap with the oxide insulating layer 296b. The region 294d is in the same oxygen-excess state as the channel formation region 293, and the leakage current is reduced. In addition, the protective insulating layer 203 also functions to reduce the oxidation of the laminated layer in contact with the protective insulating layer 203. The third region 294e of the nitride semiconductor layer is a channel forming region 293 and a high resistance source region 294 a) and a) of the fourth region of the oxide semiconductor layer in contact with the protective insulating layer 203. 294f is provided between the channel forming region 293 and the high resistance drain region 294b. The third region 294e and the fourth region 294f of the oxide semiconductor layer in contact with the protective insulating layer 203 are 4f can reduce the off current.

[0196] The third region 294e and the fourth region 294f of the oxide semiconductor layer are formed of a silicon nitride film or a nitride film. The protective insulating layer 203 is also in contact with the second gate insulating layer 292b, which is a silicon oxide film. , hydrogen ions, oxygen ions, OH - It does not contain impurities such as The inorganic insulating film used is a silicon nitride film, an aluminum nitride film, a nitride oxide film, and A silicon film, aluminum oxynitride, or the like is used.

[0197] In this embodiment, a silicon oxide film obtained by a sputtering method is used as the oxide insulating layer 296b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, a silicon nitride film or a nitriding oxide film is used. The oxide insulating layer is etched using the second gate insulating layer, which is a silicon dioxide film, as an etching stopper. This is an example of

[0198] In addition, the channel protection type thin film transistor has a channel length L of the channel formation region shortened. In order to achieve this, the width of the oxide insulating layer is narrowed, and the source electrode layer and the drain electrode layer are formed on the narrow oxide insulating layer. If a thin oxide insulating layer is provided, there is a risk of short-circuiting on the oxide insulating layer. The source electrode layer 295a and the drain electrode layer 295b are provided at the ends separated from the edge layer 296a. This is the configuration.

[0199] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 4.

[0200] (Embodiment 6) In this embodiment, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment 1 is shown in FIG. 7 and 8 are the same as those in FIGS. 1 and 2 except for some differences in the process. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted.

[0201] First, according to the first embodiment, a gate electrode layer, a gate insulating layer, a metal thin film, and an oxide film are formed on a substrate. Then, according to the first embodiment, an island-shaped metal layer 428 and an island-shaped An oxide semiconductor layer 429 is formed.

[0202] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than the distortion point of the substrate, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. The heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After that, the oxide semiconductor layer is not exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. A conductive layer 422 is obtained. After that, high-purity oxygen gas, high-purity N2O gas, or ultra-high-purity N2O gas is introduced into the same furnace. Cooling is performed by introducing dry air (dew point below -40°C, preferably below -60°C). Oxygen It is preferable that the gas or N2O gas does not contain water, hydrogen, etc. The purity of oxygen gas or N2O gas introduced into the device should be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or more (i.e. impurities in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0203] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0204] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography process.

[0205] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance It transforms it into an anti-type, i.e., type I.

[0206] Alternatively, the metal layer 428 may be oxidized by the first heat treatment to form an oxide semiconductor layer. In addition, the first heat treatment is not limited to oxidizing the metal layer 428. Apart from the treatment, an oxidation treatment may be performed to oxidize the metal layer 428, e.g. After the oxide insulating film is formed by a sputtering method, oxidation treatment may be performed.

[0207] Next, an oxide insulating film was formed over the gate insulating layer 402 and the oxide semiconductor layer by a sputtering method. (See FIG. 8(A)).

[0208] Next, a resist mask is formed by a third photolithography process and selectively etched. After that, the resist mask is removed. (See FIG. 8(B)).

[0209] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the stacked oxide semiconductor After forming a light-transmitting conductive film on the conductive layer 422, a fourth photolithography process is performed. A resist mask is formed on the insulating film, and selective etching is performed to form the source electrode layer 425a and The drain electrode layer 425b is formed (see FIG. 8C).

[0210] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is carried out in a nitrogen gas atmosphere. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0211] Next, the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 A protective insulating layer 403 is formed on 5b.

[0212] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403 .

[0213] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. A hole 441 is formed and the resist mask is removed (see FIG. 8(D)).

[0214] Next, a light-transmitting conductive film is formed.

[0215] Next, a sixth photolithography step is performed to form a resist mask, and then etching is performed. Then, unnecessary portions are removed to form a pixel electrode layer 427, and the resist mask is removed (FIG. 8( See E). ).

[0216] Through the above steps, the thin film transistor 420 and the side film 421 are formed on the same substrate using six masks. Wire crossings with reduced raw capacitance can be created.

[0217] The pixel thin film transistor 420 is formed by stacking an oxide semiconductor layer 42 2 is a channel-protected thin-film transistor.

[0218] FIG. 7A is a plan view of a channel protection type thin film transistor 420 disposed in a pixel. 7(B) is a cross-sectional view taken along line D7-D8 in FIG. 7(A) and a cross-sectional view taken along line D7-D8 in FIG. 7(A) is a cross-sectional view taken along line D9-D10 in FIG. It should be noted that Fig. 8(E) is the same as Fig. 7(B).

[0219] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 5.

[0220] (Embodiment 7) In this embodiment, an example of the configuration of the storage capacitor that is different from that of the second embodiment is shown in FIG. 9(A) and This is shown in Figure 9(B). Figure 9(A) is the same as Figure 3(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor in the pixel portion.

[0221] FIG. 9(A) shows a structure in which the dielectric is a protective insulating layer 203 and a planarizing insulating layer 204, and the pixel electrode layer 2 27 and the capacitor wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitor. The capacitor wiring layer 250 has the same light-transmitting property as the source electrode layer of the thin film transistor 220 in the pixel portion. Since the material has the same properties and is formed in the same process, the source wiring layer of the thin film transistor 220 The layout is such that they do not overlap.

[0222] The storage capacitor shown in FIG. 9A has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0223] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 3(A) except for the different configuration of the storage capacitor, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0224] FIG. 9B shows a structure in which the dielectric is a gate insulating layer 202, a capacitance wiring layer 230, and the capacitance wiring layer 2 In this example, a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap with the oxide semiconductor layer 30. In addition, the capacitance electrode 231 is laminated on the oxide semiconductor layer 251 in contact therewith, and the storage capacitance The oxide semiconductor layer 251 functions as one electrode of the thin film transistor 22. The oxide semiconductor layer 251 is formed in a different process from the oxide semiconductor layer 250. After that, an oxide semiconductor layer is formed on the capacitor wiring layer 230. Since the gate electrode layer of the transistor 220 is formed using the same material and process as the gate electrode layer of the transistor 220, the The layout is such that it does not overlap with the gate wiring layer of the film transistor 220. The electrode 231 is electrically connected to the pixel electrode layer 227 .

[0225] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0226] The storage capacitors shown in FIGS. 9A and 9B are transparent and have the number of gate wirings. In order to increase the resolution of the displayed image by increasing the number of pixels, it is necessary to provide sufficient capacity even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0227] This embodiment mode can be freely combined with other embodiment modes.

[0228] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0229] The thin film transistors arranged in the pixel portion are formed according to the first, second, fifth and sixth embodiments. In addition, since the thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs, Among the driver circuits, a part of the driver circuit that can be configured with an n-channel TFT is The thin film transistor is formed on the same substrate as the thin film transistor.

[0230] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a plurality of signal lines. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0231] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0232] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0233] In FIG. 14B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, thin-film transistors have lower field-effect mobility than transistors using single-crystal semiconductors. The driving circuit formed on the substrate 5300 can be configured by the film transistor. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yields. do.

[0234] The thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs. 15(A) and 15(B) show the configuration of a signal line driver circuit configured with n-channel TFTs. An example of the operation will be described below.

[0235] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0236] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0237] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_k in order.

[0238] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0239] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0240] Next, the operation of the signal line driver circuit of FIG. 15(A) will be explained with reference to the timing chart of FIG. 15(B). 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0241] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0242] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0243] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. A) By writing to pixels in multiple columns, the writing time can be extended. This makes it possible to prevent insufficient writing of video signal data (DATA).

[0244] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use a circuit configured with thin film transistors shown in 2, 5, and 6. In this case, the polarity of all the transistors in the shift register 5601 is set to N-channel type or P-channel type. The channel type can be configured with only one polarity.

[0245] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 16 and 17.

[0246] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter or a buffer may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S) are input to the shift register. P) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line, and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on all at once, so the buffer must be able to pass a large current. is used.

[0247] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage signal OUT(n-1) is input. The circuit 10_1 receives a signal from a third pulse output circuit 10_3 located two stages later. Similarly, in the n-th pulse output circuit 10_n of the second stage or later, the (n+2)-th pulse of the second stage later is A signal from the output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs a signal to the pulse output circuit of the next stage and / or the next stage before. First output signals OUT(1)(SR) to OUT(N)(SR) for input, another Second output signals OUT(1) to OUT(N) are outputted and are electrically inputted to lines or the like. As shown in FIG. 16(A), the last two stages of the shift register are connected to the next stage signal O. Since UT(n+2) is not input, for example, a second start pulse SP2, The third start pulse SP3 may be input to each of the input terminals.

[0248] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The four clock signals (CK4) are delayed by a quarter period in sequence (i.e., 90° from each other). In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are The clock signal (CK4) is used to control the driving of the pulse output circuit. The signal may be called GCK or SCK depending on the input drive circuit, but here it is called C I will explain as K.

[0249] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0250] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 16B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0251] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are three-terminal thin film transistors. In addition to transistors (also called TFTs: Thin Film Transistors), In this specification, a thin film transistor can be used. When the gate electrode has two gate electrodes through a semiconductor layer, the gate electrode below the semiconductor layer The gate electrode above the semiconductor layer is also called the upper gate electrode.

[0252] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A configuration that can control the threshold voltage is preferable. The threshold voltage of the thin film transistor 28 controls the potential of the upper and / or lower gate electrodes. By controlling the voltage, it is possible to control the voltage to a desired value.

[0253] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. This is explained in (D).

[0254] The pulse output circuit shown in FIG. 16(D) includes the first transistor 31 to the thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a voltage source to which a first high power supply potential VDD is supplied is also provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is sent from the power supply line 53 to the first transistor 31 to the thirteenth transistor 43, and The power supply potential is supplied to the power supply lines. Here, the magnitude relationship of the power supply potential of each power supply line in FIG. 16(D) is as follows: The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC The potential of the first clock signal (CK1) to the second clock signal (CK2) is higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H level and L level at regular intervals. When it is at H level, it is VDD, and when it is at L level, it is VSS. By making the power supply potential VCC lower than the power supply potential VDD of the power supply line 51, the operation is not affected. The potential applied to the gate electrode of the transistor can be kept low without causing a problem. This reduces the shift in the threshold voltage of the transistor, thereby suppressing deterioration. Among the transistors 31 to 43, the first transistor 31 and the sixth transistor The transistors 36 to 9 are the four-terminal thin film transistors shown in FIG. 16(C). It is preferable to use the first transistor 31 and the sixth transistor 28. The operation of the 36th to 9th transistors 39 is controlled by connecting one of the source and drain electrodes. The potential of the node connected to the gate electrode is required to be switched by the control signal of the gate electrode. It is a transistor that responds quickly to the control signal input to the gate electrode (the rise of the on-current A transistor that can reduce malfunctions in the pulse output circuit by having a steep rise time. Therefore, the four-terminal thin film transistor 28 shown in FIG. This makes it possible to control the threshold voltage, resulting in a pulse output circuit that can further reduce malfunctions. It is possible.

[0255] In FIG. 16(D), the first terminal of the first transistor 31 is electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth The sixth transistor 36 has a first terminal electrically connected to the input terminal 24. 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor The gate electrode (the lower gate electrode and the upper gate electrode) of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (lower gate electrode and upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrodes (lower gate electrode and upper gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor 33 are electrically connected to each other. The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the twelfth transistor 42. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are electrically connected. are electrically connected.

[0256] In FIG. 16(D), the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let's say.

[0257] FIG. 17(A) shows the pulse output circuit described in FIG. 16(D) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signals input to or output from the second output terminal 27.

[0258] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a second input terminal CK3 is input. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0259] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0260] In FIG. 16(C) and FIG. 17(A), the node A is set to the floating state. A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0261] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 17(B). In this case, the period 61 in FIG. 17(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0262] As shown in FIG. 17A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0263] If the ninth transistor 39, to whose gate electrode the second power supply potential VCC is applied, is not present, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and source, the gate and drain In both cases, a large bias voltage is applied, which causes a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 rises, but the potential of the second terminal of the first transistor 31 does not rise. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0264] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0265] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of a thin film transistor is reduced, and the on-current and field effect It is possible to increase the mobility and reduce the degree of degradation, so In addition, a transistor using an oxide semiconductor can be Compared to transistors using silicon, a high potential is applied to the gate electrode. The degree of deterioration of the transistor is small. Therefore, the power supply line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD to the Since the number of lines can be reduced, the circuit can be made smaller.

[0266] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The voltage supplied to the gate electrodes (lower gate electrode and upper gate electrode) by the second input terminal 22 is The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The third input terminal 23 is connected to the gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode of the gate electrode 38. The same effect can be achieved by switching the wiring so that the clock signal is supplied by In the shift register shown in FIG. 17A, the seventh transistor 37 and The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 The potential at node B decreases as a result of the potential at node B decreasing. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. 17(A), the seventh The seventh transistor 37 and the eighth transistor 38 are both in an on state. 7 is on, the eighth transistor 38 is off, then the seventh transistor 37 is on. By turning off the eighth transistor 38, the second input terminal 22 and The potential drop at the node B caused by the potential drop at the third input terminal 23 is suppressed by the eighth transistor. The potential drop of the gate electrode of the transistor 38 can be reduced to one time. The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are connected to the third A clock signal is supplied from the input terminal of the eighth transistor 38. A clock signal is supplied from the second input terminal to the gate electrode and the upper gate electrode. In this case, noise can be reduced by reducing the fluctuation of the potential of node B. Therefore, it is preferable.

[0267] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0268] (Embodiment 9) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. The transistor and part or the whole of the driver circuit are formed on the same substrate as the pixel section, On-panel formation is possible.

[0269] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitting diode (LED), specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0270] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0271] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) using the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0272] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show the thin film transistors 4010 and 4011 and the liquid crystal display device. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. 10(A1) and 10(A2) are plan views of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0273] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0274] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 10(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0275] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The insulating layers 4041a and 4041b are formed on the thin film transistors 4010 and 4011. 41b, 4042a, 4042b, 4020, and 4021 are provided.

[0276] The thin film transistors 4010 and 4011 are made of the oxide semiconductor shown in the first, second, fifth and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The transistor 4011 is the thin film transistor 26 shown in the first, second, fifth and sixth embodiments. 0, 245, 270, and the thin film transistor 4010 for the pixel is a thin film transistor 4 20, 448, 220, 280, and 290 can be used. The thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0277] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0278] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0279] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film A room can be used.

[0280] Also, 4035 is a columnar spacer 4035 obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is contained in material 4005.

[0281] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears in a relatively narrow temperature range, so it is important to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0282] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0283] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0284] The thin film transistor 4011 includes an insulating layer 4041a which functions as a channel protection layer and an oxide film. An insulating layer 4041b is formed to cover the peripheral edge (including the side surface) of the laminate of the compound semiconductor layers. Similarly, the thin film transistor 4010 has an insulating layer 4042a which functions as a channel protective layer and and an insulating layer 4042b covering the periphery (including the side surface) of the stack of oxide semiconductor layers. There are.

[0285] An insulating layer 4041 which is an oxide insulating layer covering the periphery (including the side surface) of the stack of oxide semiconductor layers. b, 4042b are the gate electrode layer and the wiring layer (source wiring) formed above or around it. This increases the distance between the wiring layer and the capacitor wiring layer, thereby reducing parasitic capacitance. The layers 4041a, 4041b, 4042a, and 4042b are the oxide insulating layers shown in the first embodiment. The layers 426a and 426b may be formed using the same material and method. In order to reduce the surface irregularities, the insulating layer 4021 is covered with the insulating layer 4021, which functions as a planarizing insulating film. Here, insulating layers 4041a, 4041b, 4042a, and 4042b are implemented. Using the first embodiment, a silicon oxide film is formed by sputtering.

[0286] In addition, an insulating layer 4020 is formed on the insulating layers 4041a, 4041b, 4042a, and 4042b. The insulating layer 4020 is made of the same material as the protective insulating layer 403 described in Embodiment 1. Here, the insulating layer 4020 is formed by a nitride film formed by RF sputtering. A silicon film is formed.

[0287] An insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using the same material and method as the planarization insulating layer 404 shown in Embodiment 1. , acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. In addition to the above organic materials, low dielectric constant materials (L low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) In addition, a plurality of insulating films made of these materials can be stacked. In this way, the insulating layer 4021 may be formed.

[0288] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. The insulating layer 4020 and the gate insulating layer may be formed using a nitride insulating film. In order to achieve this, an insulating layer 4020 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, an area where the external insulating layer is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example, a device as a display device, is used, the device can be prevented from entering moisture. This prevents moisture from entering from the outside for a long period of time even after the device is completed, ensuring long-term reliability of the device. This can improve reliability.

[0289] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0290] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a baking machine. By using both, it becomes possible to manufacture a semiconductor device efficiently.

[0291] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Transparent conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide Materials can be used.

[0292] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0293] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0294] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0295] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0296] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0297] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0298] FIG. 19 shows a semiconductor device using a TFT substrate manufactured by the manufacturing method disclosed in this specification. 1 shows an example of a liquid crystal display module.

[0299] FIG. 19 shows an example of a liquid crystal display module, in which a substrate 2600 and an opposing substrate 2601 are made of a sealing material. 2602, and a pixel portion 2603 including a TFT and the like, a display element including a liquid crystal layer, and A color layer 2604 and a colored layer 2605 are provided to form a display area. - In the case of the RGB method, coloring corresponding to each color of red, green, and blue is required for display. The polarizing layer is provided on the outside of the substrate 2600 and the counter substrate 2601. A plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are provided. 0 and a reflector 2611, and the circuit board 2612 is a flexible wiring board 260 9 is connected to the wiring circuit section 2608 of the substrate 2600, and a control circuit, a power supply circuit, etc. The external circuit is built in. Also, there is a retardation plate between the polarizer and the liquid crystal layer. It may be laminated in this manner.

[0300] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0301] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0302] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0303] (Embodiment 10) An example of electronic paper will be shown as one mode of the semiconductor device.

[0304] Electronic paper is also called an electrophoretic display (electrophoretic display), and has the same properties as paper. The advantages are readability, low power consumption compared to other display devices, and the possibility of making them thin and light. It has points.

[0305] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0306] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0307] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0308] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by thin film transistors can be used.

[0309] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0310] Figure 18 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 1. The thin film transistor can be fabricated in the same manner as the oxide semiconductor layer, and is highly reliable. The thin film transistors shown in the second, fifth and sixth embodiments may also be used as the thin film transistor 581 of this embodiment. It can also be applied.

[0311] The electronic paper in Figure 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0312] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The first electrode layer 587 and the insulating layer 585 are formed as a source electrode layer or a drain electrode layer. The first electrode layer 587 and the substrate 596 are in contact with each other through the opening and are electrically connected. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, The area around the pixel 589 is filled with a filler 595 such as resin. The second electrode layer 588 corresponds to a thin film transistor. It is electrically connected to a common potential line provided on the same substrate as the transistor 581. The second electrode layer 588 and the common electrode layer 589 are connected to each other via conductive particles disposed between the pair of substrates. The position line can be electrically connected.

[0313] Also, instead of the element using the twist ball, an electrophoretic element can be used. A transparent liquid, positively charged white particles, and negatively charged black particles are enclosed in a 1 mm diameter container. Microcapsules with a size of about 0 μm to 200 μm are used. The microcapsules placed between the first and second electrode layers are subjected to an electric field. When the screen is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. The display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lines No light is required, the power consumption is low, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image that has been displayed will be retained. Therefore, it is possible to transmit a signal from a radio wave source to a semiconductor device with a display function (simply a display device or a display The displayed image is preserved even if the device (also called a semiconductor device with a display device) is moved away. It is possible to keep it.

[0314] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0315] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0316] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0317] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0318] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0319] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0320] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0321] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The driving transistor 640 is electrically connected to a common potential line formed on the substrate. 2 is a driving transistor for the light emitting element 6404 .

[0322] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0323] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0324] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0325] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0326] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0327] Note that the pixel configuration shown in Fig. 12 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0328] Next, the configuration of the light emitting element will be described with reference to FIG. 13. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 13(A), (B), and (C). Driving TFTs 7001 and 7011, which are TFTs for driving light emitting elements used in semiconductor devices, The thin film transistor 7021 can be manufactured in a manner similar to that of the thin film transistor described in Embodiment 1, and an oxide semiconductor layer The thin film transistors shown in the second, fifth and sixth embodiments are highly reliable. The transistors can also be used as the driving TFTs 7001, 7011, and 7021.

[0329] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0330] A light emitting element with a top emission structure will be described with reference to FIG.

[0331] In FIG. 13(A), a driving TFT 7001 is an n-type, and light emitted from a light emitting element 7002 is 13A shows a cross-sectional view of a pixel when the light emitting element 70 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. The cathode 7003 is covered with an insulating film 7006. and a conductive film formed over the insulating film 7007, having a low work function and reflecting light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked. When it is made up of multiple layers, the cathode 7003 An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on top of each other in this order. It is not necessary to provide all of these layers. The insulating layer is formed using a conductive material, such as indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium dioxide, indium oxide containing titanium dioxide, Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc A light-transmitting conductive film such as an oxide or an indium tin oxide film containing silicon oxide is used. is also good.

[0332] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering each end portion. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, epoxy, etc. The partition wall 70 is formed using an organic resin film such as a silicon-based resin film, an inorganic insulating film, or polysiloxane. 09 is made of a photosensitive resin material, and the side of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition wall 7009 as an inclined surface. When the material is used, the step of forming a resist mask can be omitted.

[0333] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 13(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0334] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. When 011 is n-type and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, 13B shows a cross-sectional view of the pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. On the cathode 7013, a light-emitting layer 7014 and an anode 7015 are laminated in this order. When the 015 has a light-transmitting property, a shielding layer for reflecting or blocking light is applied to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small electrical conductivity can be used. The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 is composed of a single layer, as in FIG. 13(A), but multiple layers are laminated. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 13(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0335] In addition, a conductive film 7017 and a conductive film 7018 of an adjacent pixel are provided between the conductive film 7017 and the conductive film 7018 of an adjacent pixel, covering the respective edges. A partition wall 7019 is provided. The partition wall 7019 is made of polyimide, acrylic resin, polyamide, or ethylene. The partition wall is formed using an organic resin film such as an epoxy resin film, an inorganic insulating film, or polysiloxane. 7019 is made of a photosensitive resin material, and the side of the partition wall 7019 has a continuous curvature. It is preferable to form the partition wall 7019 so that the inclined surface is formed. When a resin material is used, the step of forming a resist mask can be omitted.

[0336] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0337] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to that shown in FIG. 13(A). It is possible.

[0338] In addition, a conductive film 7027 and a conductive film 7028 of an adjacent pixel are provided between the conductive film 7027 and the conductive film 7028 of an adjacent pixel, covering the respective edges. A partition wall 7029 is provided. The partition wall 7029 is made of polyimide, acrylic resin, polyamide, or ethylene. The partition wall is formed using an organic resin film such as an epoxy resin film, an inorganic insulating film, or polysiloxane. 7029 is made of a photosensitive resin material, and the side of the partition wall 7029 has a continuous curvature. It is preferable to form the partition wall 7029 so that the inclined surface is formed. When a resin material is used, the step of forming a resist mask can be omitted.

[0339] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0340] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0341] In addition, a thin film transistor (TFT for driving light-emitting elements) that controls the driving of light-emitting elements and a light-emitting element In the example shown, the current control TFT is electrically connected between the driving TFT and the light emitting element. The configuration may also be such that FT is connected.

[0342] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the semiconductor devices disclosed in this specification. Various modifications based on the technical concept are possible.

[0343] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 11. FIG. 11 shows a thin film transistor formed on a first substrate. The flat surface of the panel is formed by sealing the transistor and the light-emitting element between the second substrate and the panel with a sealing material. 11(B) corresponds to a cross-sectional view taken along line HI in FIG. 11(A).

[0344] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0345] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0346] The thin film transistors 4509 and 4510 are made of the oxide semiconductor shown in the first, second, fifth, and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The transistor 4509 may be the thin film transistor 26 shown in the first, second, fifth and sixth embodiments. 0, 245, 270, and the thin film transistor 4510 for the pixel is a thin film transistor 4 20, 448, 220, 280, and 290 can be used. The thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0347] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a metal or a silicon dioxide film, and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0348] The thin film transistor 4509 has an insulating layer 4541a functioning as a channel protective layer and an oxide film. An insulating layer 4541b is formed to cover the peripheral edge (including the side surface) of the stack of compound semiconductor layers. Similarly, the thin film transistor 4510 has an insulating layer 4542a which functions as a channel protective layer and and an insulating layer 4542b covering the periphery (including the side surface) of the stack of oxide semiconductor layers. There are.

[0349] An insulating layer 4541 which is an oxide insulating layer covering the periphery (including the side surface) of the stack of oxide semiconductor layers b, 4542b are the gate electrode layer and the wiring layer (source wiring) formed above or around it. This increases the distance between the wiring layer and the capacitor wiring layer, thereby reducing parasitic capacitance. The layers 4541a, 4541b, 4542a, and 4542b are the oxide insulating layers shown in the first embodiment. The layers 426a and 426b may be formed using the same material and method. In order to reduce the surface irregularities, the insulating layer 4543 is covered with the insulating layer 4543, which functions as a planarizing insulating film. Here, insulating layers 4541a, 4541b, 4542a, and 4542b are implemented. Using the first embodiment, a silicon oxide film is formed by sputtering.

[0350] In addition, an insulating layer 4543 is formed on insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 is formed using a material similar to that of the protective insulating layer 403 described in Embodiment 1. Here, the insulating layer 4543 is formed by a nitride film formed by RF sputtering. A silicon film is formed.

[0351] An insulating layer 4544 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using a material and a method similar to those of the planarization insulating layer 404 described in Embodiment 1. Acrylic is used as the insulating layer 4544 .

[0352] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. The insulating layer 4543 and the gate insulating layer may be formed using a nitride insulating film. In order to achieve this, an insulating layer 4543 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, an area where the external insulating layer is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example, a device as a display device, is used, the device can be prevented from entering moisture. This prevents moisture from entering from the outside for a long period of time even after the device is completed, ensuring long-term reliability of the device. This can improve reliability.

[0353] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0354] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or polysiloxane. An opening is formed on the first electrode layer 4517 using a photosensitive material, and the sidewall of the opening is It is preferable to form the inclined surface with a continuous curvature.

[0355] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0356] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0357] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0358] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0359] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0360] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0361] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. Can be made of oil or thermosetting resin, PVC (polyvinyl chloride), acrylic Resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used as a filler. Just use

[0362] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0363] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0364] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0365] This embodiment mode may be appropriately combined with the configurations described in Embodiments 1 to 4 and 6 to 8. It is possible to implement.

[0366] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0367] FIG. 20 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 It consists of two housings, housing 2701 and housing 2703. 03 is integrated with a shaft portion 2711, and performs opening and closing operations around the shaft portion 2711. This configuration allows the device to operate like a paper book. .

[0368] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0369] 20 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0370] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0371] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0372] FIG. 21(A) shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0373] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0374] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0375] FIG. 21(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0376] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0377] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0378] FIG. 22(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 22(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0379] FIG. 22(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and any other configuration may be used as long as it includes at least the semiconductor device disclosed in this specification. The configuration may be such that ancillary equipment is provided as appropriate.

[0380] FIG. 23A is a perspective view showing an example of a portable computer.

[0381] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0382] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0383] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0384] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0385] The portable computer shown in FIG. 23(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display the images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. Slide the 7 to expose the entire screen, and adjust the screen angle to watch TV. In this case, the hinge unit can be opened to display the display portion 9303. Furthermore, it only activates the circuitry that displays the TV broadcast, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0386] FIG. 23(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0387] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0388] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press a button, a program for the Internet Each function can be associated with another function, such as being started.

[0389] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0390] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0391] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0392] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0393] Although FIG. 23B illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape.

[0394] (Embodiment 14) In this embodiment, as one mode of a semiconductor device, the thin film transistor shown in the first, second, fifth and sixth embodiments is used. An example of a display device having a transistor will be described with reference to FIGS. 24 to 35. An example of a liquid crystal display device using a liquid crystal element as a display element will be described with reference to FIGS. 24 to 35. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistors shown in the first, second, fifth and sixth embodiments can be applied. It is a thin film transistor with excellent electrical properties and high reliability that can be fabricated in the same manner as in the process shown in 6. The TFT 628 has a channel protection layer 608, and the TFT 629 has a channel protection layer 611. The semiconductor layer film is an inverted staggered thin film transistor having a channel forming region.

[0395] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are in contact with the panel surface. In this embodiment, the pixels are arranged in a vertical direction. It is designed to be divided into areas (sub-pixels) and tilt the molecules in different directions in each area. This is called multi-domain or multi-domain design. A liquid crystal display device that takes into consideration the design will be described.

[0396] 25 and 26 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of a substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. 24. Also, FIG. 26 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0397] FIG. 24 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state in which the liquid crystal is injected.

[0398] The counter substrate 601 is provided with a colored film 636, a counter electrode layer 640, and protrusions 64 on the counter electrode layer 640. An alignment film 648 is formed on the pixel electrode layer 624, and a counter electrode An alignment film 646 is also formed on the layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between the first and second electrodes 610 and 611.

[0399] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 6 The insulating film 620 covering the insulating film 620 and the insulating film 622 covering the insulating film 620 are formed by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 can be formed by using a thin film transistor such as TFT6. The first capacitor wiring 604 and the gate insulating film 606 are formed at the same time as the gate wiring 602 of 28. and a second capacitance wiring 617 formed at the same time as the wirings 616 and 618.

[0400] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0401] 25 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment 1. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0402] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the display is composed of a pixel electrode layer 624 and a pixel electrode 626. The element electrode layer 624 and the pixel electrode 626 form a sub-pixel.

[0403] 26 shows the planar structure of the opposing substrate side. An opposing electrode layer 640 is formed on a light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 644 are formed to control the alignment of the liquid crystal. In FIG. 26, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how it is being used.

[0404] The equivalent circuit of this pixel structure is shown in Figure 27. Both TFT628 and TFT629 have gate electrodes. The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the liquid crystal elements 651 and 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, the liquid crystal The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0405] When a voltage is applied to the pixel electrode layer 624 in which the slit 625 is provided, a The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated pattern, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0406] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0407] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. 28 is a plan view of the above-mentioned embodiment, and a cross-sectional structure corresponding to the cutting line YZ shown in the figure is shown in FIG.

[0408] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0409] The pixel electrode layer 624 is formed by contact holes passing through the insulating film 620 and the insulating film 622. In the filter 623, the wiring 618 is connected to the TFT 628. In the contact hole 627 that penetrates the insulating film 620 and the insulating film 622, , and is connected to the TFT 629 by a wiring 619. The gate wiring 603 of T629 is separated so that different gate signals can be applied. On the other hand, the wiring 616 functioning as a data line is formed by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 are the same as those shown in the first, second, fifth and sixth embodiments. A thin film transistor can be used as appropriate. A gate insulating film 606 is formed on the capacitor wiring 690 .

[0410] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 surrounds the outside of the pixel electrode layer 624 that spreads in a V shape. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is applied to the TFT 628. The orientation of the liquid crystal is controlled by varying the polarity of the TFT 629. The equivalent circuit is shown in Figure 31. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate The TFT 628 and the TFT 629 are both connected to the wiring 616. The gate wiring 602 and the gate wiring 603 are connected to the gate electrodes 601 and 602. Therefore, the liquid crystal elements 651 and 652 can be made to operate differently. By controlling the operation of T628 and TFT629 individually, the liquid crystal element 651 and the liquid crystal element The orientation of the liquid crystals in 652 can be precisely controlled to widen the viewing angle.

[0411] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 30 shows the structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode has a slit 641 formed therein. The polar layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. This effectively generates an oblique electric field and controls the alignment of the liquid crystal. This allows the liquid crystal to be oriented in different directions depending on the location, thereby widening the viewing angle. In FIG. 30, pixel electrode layers 624 and 626 formed on the substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how it is being used.

[0412] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The liquid crystal layer 640 is disposed between the substrate 600 and the counter substrate 601. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The first liquid crystal element 651 is formed by overlapping the pixel electrode layer 626. The liquid crystal layer 650 and the counter electrode layer 640 are overlapped to form a second liquid crystal element 652. The pixel structure of the display panel described in FIGS. 28 to 31 has a first liquid crystal element in one pixel. It has a multi-domain structure with a first liquid crystal element and a second liquid crystal element.

[0413] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0414] FIG. 32 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The figure shows a state in which the substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. On the counter substrate 601, a colored film 636, a flattening film 637, etc. are formed. No counter electrode is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed on the liquid crystal layer 642 via an alignment film 646 and an alignment film 648 .

[0415] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitor wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. As the TFT 628, the thin film transistor shown in the first, second, fifth and sixth embodiments can be used. The electrode layer 607 may be a pixel electrode layer described in Embodiment 1. The electrode layer 607 may be formed in a shape that is approximately divided into pixel shapes. A gate insulating film 606 is formed on the electrode layer 607 and the capacitor wiring 604. can be.

[0416] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0417] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer shown in Embodiment 1. It is formed using a material.

[0418] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0419] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. A slit 625 is provided in the pixel electrode layer 624. The liquid crystal layer 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is applied to the electrode layer 607. The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. The thickness of the gate insulating film 606 is 50 to 200 nm. Since the thickness is sufficiently small compared to the thickness of the liquid crystal layer, which is about 10 μm, the thickness is substantially parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the orientation of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in a nearly parallel direction. Since the display is horizontal even in this state, the influence of the viewing angle on contrast is minimal, and the viewing angle is wide. In addition, since both the electrode layer 607 and the pixel electrode layer 624 are light-transmitting electrodes, , the aperture ratio can be improved.

[0420] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0421] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0422] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlaid and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. An alignment film 646 and an alignment film 647 are provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via 48 .

[0423] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. The thin film transistors shown in Embodiments 1, 2, 5, and 6 can be applied to this.

[0424] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0425] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer shown in Embodiment 1. As shown in FIG. 35, the pixel electrode layer 624 is formed using a material. The pixel electrode is formed so that a horizontal electric field is generated together with the comb-shaped electrode formed at the same time as the pixel electrode. The comb-tooth portion of the layer 624 alternately interdigitates with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed as follows.

[0426] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. The molecules are rotated horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast and results in a wider viewing angle.

[0427] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode layer 624 are formed through the contact hole 63. It is connected via 3.

[0428] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio.

[0429] (Embodiment 15) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch screen, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce wiring resistance will be shown.

[0430] In FIG. 36(A), the same parts as those in FIG. 3(A) are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. Note that this embodiment mode is applicable to the active matrix substrate shown in Embodiment Mode 1. It can be used.

[0431] 36(A) and 36(B) show an example in which the gate electrode layer of the thin film transistor of the driving circuit is made of metal wiring. In the driver circuit, the gate electrode layer is not limited to a light-transmitting material. In order to form metal wiring, the number of photomasks is smaller than that of the first and second embodiments. increase.

[0432] In FIG. 36(A), the thin film transistor 260 of the driving circuit is formed on the first metal wiring layer 242. The gate electrode layer is formed by laminating the first metal wiring layer 241 on the first metal wiring layer 242. 42 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed using the same material and in the same process as the second metal wiring layer 237. This can be done.

[0433] Similarly, in FIG. 36(B), the thin film transistor 270 of the driving circuit is formed by the first metal wiring layer A second metal wiring layer 243 is stacked on the first metal wiring layer 244 to form a gate electrode layer. The wiring layer 244 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 243 is made of the same material and formed in the same process as the second metal wiring layer 237. It can be achieved.

[0434] When the first metal wiring layer 242 and the conductive layer 267 are electrically connected, the first metal wiring The second metal wiring layer 241 is preferably a metal nitride film to prevent oxidation of the wiring layer 242. Similarly, when the first metal wiring layer 244 and the conductive layer 277 are electrically connected, the first The second metal wiring layer 243 for preventing oxidation of the metal wiring layer 244 is a metal nitride film. preferable.

[0435] First, a layer capable of withstanding the first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0436] In this embodiment, a tungsten film with a thickness of 370 nm and a tantalum nitride film with a thickness of 50 nm are used. Here, the conductive film is a stack of a tantalum nitride film and a tungsten film. It is not limited to Ta, W, Ti, Mo, Al, Cu, or the above-mentioned elements. alloys containing the above elements, alloy films combining the above elements, or films containing the above elements The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and may be formed of a nitride containing the above-mentioned elements. A stack of more than one layer can be used.

[0437] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The first metal wiring layer 237, the first metal wiring layer 242 and the second metal wiring layer 241, the first metal wiring layer 242, ... The wiring layer 244 and the second metal wiring layer 243 are formed. For etching, ICP (Inductively Coupled Plasma) It is recommended to use the ICP etching method. Conditions (amount of power applied to the coil-type electrode, amount of power applied to the substrate-side electrode, By appropriately adjusting the electrode temperature, etc., the film can be etched into the desired tapered shape. By forming the first metal wiring layer 236 and the second metal wiring layer 237 in a tapered shape, Therefore, it is possible to reduce defects in the formation of a light-transmitting conductive film formed in contact therewith.

[0438] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. The gate wiring layer 238 and the gate electrode layer of the thin film transistor 220 are formed. The conductive film is formed using the conductive material having a visible light-transmitting property described in Embodiment 1.

[0439] Note that depending on the material of the light-transmitting conductive film, for example, the gate wiring layer 238 may be made of a first gold If there is an interface in contact with the metal wiring layer 236 or the second metal wiring layer 237, the interface may be damaged during subsequent heat treatment, etc. Therefore, an oxide film is formed, which may increase the contact resistance. It is preferable to use a metal nitride film that prevents oxidation of the first metal wiring layer 236.

[0440] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in Embodiment 1. In this step, an active matrix substrate is manufactured according to the first embodiment.

[0441] In FIGS. 36(A) and 36(B), the gate wiring layer 238 overlapping a part of the second metal wiring layer 237 is As shown, the gate wiring covers the entire first metal wiring layer 236 and the second metal wiring layer 237. That is, the first metal wiring layer 236 and the second metal wiring layer 237 may be a gate The wiring layer 238 can be called an auxiliary wiring for reducing the resistance.

[0442] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is disposed on the protective insulating layer 203. The wiring from the terminal portion is also made of metal. Formed by wiring.

[0443] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0444] In this embodiment, the wiring resistance is reduced by using a part of the metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is set to 60 inches or even 120 inches, High definition and a high aperture ratio can be achieved.

Claims

1. A pixel element including first to third conductive layers and a first oxide semiconductor layer, fourth to sixth conductive layers and a second oxide semiconductor layer provided outside the pixel portion; first to third insulating layers, In the pixel portion, the first oxide semiconductor layer is provided above the first conductive layer and overlaps with the first conductive layer with the first insulating layer interposed therebetween; the second insulating layer is provided above the first oxide semiconductor layer; the second conductive layer is provided above the second insulating layer and has a region in contact with a top surface of the first oxide semiconductor layer through a first contact hole provided in the second insulating layer; the third insulating layer is provided above the second conductive layer, the third conductive layer is provided above the third insulating layer and has a region in contact with an upper surface of the second conductive layer via a second contact hole provided in the third insulating layer; Outside the pixel portion, the second oxide semiconductor layer is provided above the fourth conductive layer and overlaps with the fourth conductive layer with the first insulating layer interposed therebetween; the second insulating layer is provided above the second oxide semiconductor layer; the fifth conductive layer is provided above the second insulating layer and has a region in contact with an upper surface of the second oxide semiconductor layer through a third contact hole provided in the second insulating layer; the third insulating layer is provided above the fifth conductive layer, the sixth conductive layer is provided above the third insulating layer and overlaps with the fourth conductive layer with the third insulating layer, the second insulating layer, the second oxide semiconductor layer, and the first insulating layer interposed therebetween; the first conductive layer and the fourth conductive layer have the same material; the second conductive layer and the fifth conductive layer have the same material; the third conductive layer and the sixth conductive layer are made of the same material and have light-transmitting properties; the first oxide semiconductor layer and the second oxide semiconductor layer have the same material; each of the first insulating layer and the second insulating layer includes silicon oxide; a peripheral portion of the first oxide semiconductor layer having a region in contact with the second insulating layer; a peripheral portion of the second oxide semiconductor layer having a region in contact with the second insulating layer; Display device.

2. A pixel element including first to third conductive layers and a first oxide semiconductor layer, fourth to sixth conductive layers and a second oxide semiconductor layer provided outside the pixel portion; first to third insulating layers, In the pixel portion, the first oxide semiconductor layer is provided above the first conductive layer and overlaps with the first conductive layer with the first insulating layer interposed therebetween; the second insulating layer is provided above the first oxide semiconductor layer; the second conductive layer is provided above the second insulating layer and has a region in contact with a top surface of the first oxide semiconductor layer through a first contact hole provided in the second insulating layer; the third insulating layer is provided above the second conductive layer, the third conductive layer is provided above the third insulating layer and has a region in contact with an upper surface of the second conductive layer via a second contact hole provided in the third insulating layer; Outside the pixel portion, the second oxide semiconductor layer is provided above the fourth conductive layer and overlaps with the fourth conductive layer with the first insulating layer interposed therebetween; the second insulating layer is provided above the second oxide semiconductor layer; the fifth conductive layer is provided above the second insulating layer and has a region in contact with an upper surface of the second oxide semiconductor layer through a third contact hole provided in the second insulating layer; the third insulating layer is provided above the fifth conductive layer, the sixth conductive layer is provided above the third insulating layer and overlaps with the fourth conductive layer with the third insulating layer, the second insulating layer, the second oxide semiconductor layer, and the first insulating layer interposed therebetween; the first conductive layer and the fourth conductive layer have the same material; the second conductive layer and the fifth conductive layer have the same material; the third conductive layer and the sixth conductive layer are made of the same material and have light-transmitting properties; the first oxide semiconductor layer and the second oxide semiconductor layer each contain In, Ga, and Zn; each of the first insulating layer and the second insulating layer includes silicon oxide; a peripheral portion of the first oxide semiconductor layer having a region in contact with the second insulating layer; a peripheral portion of the second oxide semiconductor layer having a region in contact with the second insulating layer; Display device.

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