Light-emitting device

Abstract

To provide a semiconductor device in which transistors with different characteristics, specifically a transistor with the excellent dynamic characteristic (on characteristic or frequency characteristic (called f-characteristic)) and a transistor with suppressed off current are provided on the same substrate, and provide a method for manufacturing the semiconductor device by a simple method.SOLUTION: An oxide semiconductor layer that is intrinsic or substantially intrinsic and includes a crystal region on a surface is used for a transistor. As the semiconductor that is intrinsic or substantially intrinsic, a semiconductor from which impurities to become electron donors in the oxide semiconductor are removed and which has a larger energy gap than the silicon semiconductor is used. By controlling the potential of a pair of conductive films disposed above and below the oxide semiconductor layer through an insulating film so as to change the position of a channel to be formed in the oxide semiconductor layer, the electric characteristic of the transistor may be controlled.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device using a transistor.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers generally to semiconductor elements and circuits, electro-optical devices having semiconductor elements and circuits, and electronic All of the equipment is semiconductor equipment. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is Transistors are used in semiconductor devices such as LCD TVs. Silicon-based semiconductor materials are well known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors have been attracting attention.

[0004] Transistors are mainly made of semiconductors such as amorphous silicon or polycrystalline silicon. Amorphous silicon transistors are made using field-effect transfer Although the degree of uniformity is low, it can accommodate large-area glass substrates, while polycrystalline silicon is used. The transistors used in this study have high field-effect mobility, but require a crystallization process such as laser annealing. However, this method has the characteristic that it is not necessarily suitable for enlarging the area of ​​the glass substrate.

[0005] Zinc oxide or a material containing zinc oxide is known as an oxide semiconductor material. And the electron carrier concentration is 10 18 / cm 3 Amorphous oxide (oxide semiconductor) Thin film transistors formed from these materials have been disclosed (Patent Documents 1 to 3).

[0006] In addition, in an active matrix semiconductor device such as a liquid crystal display device, the screen size There is a trend toward larger screen sizes of 60 inches or more, and even larger screen sizes of 120 inches or more. The development is also taking into consideration the screen size. In addition, the screen resolution is also high definition. Image quality (HD, 1366 x 768), Full HD image quality (FHD, 1920 x 1080 ) and the trend is toward higher definition, with resolutions of 3840 x 2048 or 4096 x 2160. The development of so-called 4K digital cinema display devices is also being rushed.

[0007] As display devices become more highly precise, the number of pixels required increases dramatically. The write time per unit is shortened, and the transistor has high operating speed and high on-current. On the other hand, in recent years, there has been a growing demand for energy-efficient displays. Therefore, transistors with low off-state current and no unnecessary leakage current are also required. There is a demand for devices with reduced leakage current. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165527 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-165529 Summary of the Invention [Problem to be solved by the invention]

[0009] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. Although the field effect mobility is superior to that of transistors using polycrystalline silicon, it is inferior. Further improvement is required.

[0010] In addition, the oxide semiconductor may have a deviation from the stoichiometric composition during the formation process. For example, the electrical conductivity of the oxide semiconductor changes depending on the amount of oxygen. Hydrogen mixed in during the formation of the conductor thin film forms an oxygen (O)-hydrogen (H) bond and becomes an electron donor ( The OH bond acts as a polar donor, which changes the electrical conductivity. Therefore, it is important to consider the characteristics of active devices such as transistors made of oxide semiconductors. This is a factor that can cause fluctuations.

[0011] The electron carrier concentration is 10 18 / cm 3 Even if it is less than 100%, in the case of an oxide semiconductor, The transistor disclosed in the patent document is n-type, and the on-off ratio of the transistor is 10 3 Only available The reason for the low on-off ratio of such transistors is that the off-current is high. This is what is done.

[0012] The present invention has been made under such technical background. Transistors with different characteristics, specifically, dynamic characteristics (called on-state characteristics) and frequency characteristics (called f characteristics) A transistor with excellent characteristics and a transistor with reduced off-state current are fabricated on the same substrate. Another object of the present invention is to provide a semiconductor device having a structure including: One of the objectives is to provide a method for producing the same. [Means for solving the problem]

[0013] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device that is intrinsic or substantially intrinsic and has a crystalline region on its surface. The intrinsic or substantially intrinsic semiconductor is an oxide semiconductor layer containing By removing impurities that act as electron donors, the energy gap is smaller than that of silicon semiconductors. In addition, insulating films are disposed above and below the oxide semiconductor layer. The position of a channel formed in the oxide semiconductor layer is changed by controlling the potential of the pair of conductive films. In this way, the electrical characteristics of the transistor can be controlled.

[0014] One aspect of the present invention is to provide a transistor having excellent dynamic characteristics and a transistor having stable electrical characteristics on the same substrate. A semiconductor device including a transistor (for example, having an extremely reduced off-state current) Specifically, impurities that act as electron donors (donors) in the oxide semiconductor are removed, and silicon is By using oxide semiconductors with a larger energy gap than semiconductors, An oxide semiconductor layer that is intrinsic in nature and includes a crystalline region on the surface is used, and A plurality of transistors each having a structure in which a conductive film is disposed with an insulating film interposed therebetween are provided on the same substrate. It is a semiconductor device.

[0015] That is, one aspect of the present invention is a semiconductor device including a first electrode layer, a first insulating film on the first electrode layer, and a first an oxide semiconductor layer having a crystalline region on the surface thereof on the insulating film; and an oxide semiconductor layer on the first electrode layer. a second electrode layer and a third electrode layer, the second electrode being in contact with the first electrode layer and having an end portion overlapping the first electrode layer; a second insulating film including an oxide insulating film in contact with the oxide semiconductor layer, the third electrode layer, and the oxide semiconductor layer; a semiconductor substrate having a first electrode layer on the insulating film of the second insulating film and a fourth electrode layer overlapping with the oxide semiconductor layer; The semiconductor device is also a semiconductor device. It has multiple transistors with an energy gap of 2 eV or more.

[0016] Furthermore, one embodiment of the present invention is a semiconductor device including a depletion type transistor and an enhancement type transistor. and an inverter circuit including the semiconductor device including a transistor.

[0017] Another embodiment of the present invention is a semiconductor device according to any one of the above, which includes a pixel portion and a driver circuit portion that drives the pixel portion. A display device including a semiconductor device.

[0018] Further, in one embodiment of the present invention, in the semiconductor device, at least one transistor is a The first electrode layer is used as the main gate electrode of the other transistors, and the fourth electrode layer is used as the main gate electrode of the other transistors. This is a driving method using the electrode as a gate electrode.

[0019] Further, one embodiment of the present invention is a method for manufacturing a semiconductor device including a depletion type transistor in the inverter circuit. The fourth electrode layer is used as the main gate electrode of the enhancement type transistor. This is a driving method in which the fourth electrode layer is used as the main gate electrode.

[0020] Further, one embodiment of the present invention is a display device, The transistor uses the first electrode layer as a main gate electrode, and the driving circuit section has at least One transistor is driven using the fourth electrode layer as the main gate electrode.

[0021] In one embodiment of the present invention, a first electrode layer is formed, and a first insulating film is formed on the first electrode layer. an oxide semiconductor layer is formed on the first insulating film, and the oxide semiconductor layer is subjected to a dehydration or dehydrogenation treatment; The oxide semiconductor layer is formed on the first electrode layer by etching, and the oxide semiconductor layer is in contact with the first electrode layer. A second electrode layer and a third electrode layer are formed to overlap the electrode layer, and the second electrode layer and the third electrode layer are formed. a second insulating film including an oxide insulating film in contact with the oxide semiconductor layer; A semiconductor device including a first electrode layer and a fourth electrode layer overlapping with an oxide semiconductor layer formed over the film. In addition, the semiconductor device includes a semiconductor layer formed of an oxide semiconductor. The semiconductor device has a plurality of transistors with an energy gap of 2 eV or more on the same substrate.

[0022] In this specification, the EL layer refers to a layer provided between a pair of electrodes of a light-emitting element. Therefore, the light-emitting layer containing an organic compound, which is a light-emitting material sandwiched between the electrodes, is one of the EL layers. This is an aspect.

[0023] In this specification, the term "light emitting device" refers to an image display device, a light emitting device, or a light It also refers to a light source (including lighting devices) that has a connector, such as an FPC (Flexible Printed Circuit). le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packaging) e) is attached to the module, and the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) on a substrate on which a light emitting element is formed. s) All modules in which ICs (integrated circuits) are directly mounted using this method are also included in the light-emitting device. Let's say. [Effects of the Invention]

[0024] According to one embodiment of the present invention, a crystalline region of an oxide semiconductor layer is used as a channel formation region. This allows the operation of the circuits in the semiconductor device to be faster. By configuring a circuit using transistors that use silicon, the operation of the circuit in the semiconductor device can be stabilized. In addition, the off-state current is 1×10 -13 By reducing it to A or below This allows the number of storage capacitors included in the semiconductor device to be reduced or made smaller. A semiconductor device having a transistor on the same substrate can be provided. It can be produced in a convenient manner. [Brief explanation of the drawings]

[0025] [Figure 1] 1A to 1C illustrate a manufacturing method of a semiconductor device according to an embodiment; [Figure 2] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 3] 1A and 1B are diagrams illustrating an inverter circuit according to an embodiment; [Figure 4] 1A and 1B are diagrams illustrating a shift register according to an embodiment; [Figure 5] 1A and 1B are diagrams illustrating a pulse output circuit according to an embodiment. [Figure 6] 1A and 1B are diagrams illustrating a pulse output circuit according to an embodiment. [Figure 7] 1A and 1B are diagrams illustrating a pulse output circuit according to an embodiment. [Figure 8] 3 is a timing chart according to the embodiment. [Figure 9] FIG. 1 is a block diagram of a display device according to an embodiment. [Figure 10] 1A and 1B illustrate a driver circuit of a display device according to an embodiment. [Figure 11] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 14]1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 15] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 16] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 17] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 18] FIG. 1 is an external view showing an example of an electronic book. [Figure 19] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 20] FIG. 1 is an external view showing an example of a gaming machine. [Figure 21] FIG. 1 is an external view showing an example of a mobile phone. [Figure 22] 3A and 3B are diagrams illustrating a terminal portion of a display device according to an embodiment. [Figure 23] FIG. 10 is a longitudinal cross-sectional view of an inverted staggered transistor including an oxide semiconductor. [Figure 24] Energy band diagram (schematic diagram) at the A-A' cross section shown in Figure 23. (A) When the voltage between the source and drain is equipotential (VD=0), (B) when a positive potential (VD>0) is applied to the drain relative to the source. [Figure 25] 24 is an energy band diagram (schematic diagram) between B-B' in FIG. 23 when the gate voltage is 0V. [Figure 26] Energy band diagram (schematic diagram) between B-B' in Figure 23. (A) When a positive potential (VG>0) is applied to the gate (GE1), (B) When a negative potential (VG<0) is applied to the gate (GE1). [Figure 27] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that various modifications can be made to the modes and details. It will be easily understood. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In the drawings in this specification, parts having the same parts or similar functions are The same reference numerals are used to denote the same parts, and their explanations may be omitted.

[0027] (Embodiment 1) In this embodiment mode, a semiconductor device and a manufacturing method thereof will be described. One embodiment of a method for manufacturing a substrate with a circuit and a substrate with a circuit will be described with reference to FIG.

[0028] FIG. 1(E) shows a cross-sectional structure of a plurality of transistors fabricated on a circuitized substrate of a display device. An example is shown in FIG. 1E. The transistors 440A and 440B have a channel region of an oxide semiconductor layer. This is a four-terminal structure in which a pair of electrode layers are placed above and below the panel formation area via an insulating film. A pair of electrode layers is disposed above and below the channel formation region of the oxide semiconductor layer with an insulating film interposed therebetween. A transistor having a so-called dual gate structure is one example of the four-terminal structure of this embodiment. In addition, the transistor 440B is applied to a pixel of a display device, and the transistor 440A is applied to a pixel of a display device. A case where the present invention is applied to a part of a driving circuit arranged around an element part will be described.

[0029] The transistor 440A includes a first electrode layer 421a, a second electrode layer 421b, a third electrode layer 421c, and a fourth electrode layer 421d over a substrate 400 having an insulating surface. The first insulating layer 402, the oxide semiconductor layer 404a including the crystalline region 405a, and the second electrode layer 45 5a and a third electrode layer 455b. A second insulating layer 428 is provided in contact with the first insulating layer 405a. The fourth electrode layer 422a is disposed above the crystal region. The oxide semiconductor layer 404a including the insulating layer 405a overlaps with the first insulating layer 402 interposed therebetween. In addition, the second electrode layer 455a and the third electrode layer 455b are partly formed on the oxide semiconductor layer 404. It is formed above a and overlaps it.

[0030] The transistor 440B includes a first electrode layer 421b, a second electrode layer 421c, and a third electrode layer 421d over a substrate 400 having an insulating surface. the first insulating layer 402, the oxide semiconductor layer 404b including the crystalline region 405b, the second electrode layer 45 5c, and a third electrode layer 455d. A second insulating layer 428 is provided in contact with 405b, and a channel is formed through the second insulating layer 428. The fourth electrode layer 422b is disposed above the crystal region. The oxide semiconductor layer 404b including the insulating layer 405b overlaps with the first insulating layer 402 interposed therebetween. In addition, the second electrode layer 455c and the third electrode layer 455d are partially overlapped with the oxide semiconductor layer 404b. It is formed on top of the

[0031] The transistor 440A and the transistor 440B have a dual gate structure. In a dual-gate transistor, insulating films are placed above and below the oxide semiconductor layer. Either one or both of the electrode layers can be used as a gate electrode layer. The first electrode layer and the third electrode layer function as a source electrode layer and a drain electrode layer.

[0032] In this embodiment, the fourth electrode layer 422a of the transistor 440A is The second electrode layer 455 of the oxide semiconductor layer 404a is used as a main gate electrode. a region of the oxide semiconductor layer 404a in contact with the third electrode layer 455b and a region of the oxide semiconductor layer 404b in contact with the third electrode layer 455b. A channel is formed in the region where the second insulating layer 428 contacts the fourth electrode layer 422a and overlaps the fourth electrode layer 422a. It is done.

[0033] In this specification, the first electrodes arranged above and below the oxide semiconductor layer with insulating films interposed therebetween are layer and a fourth electrode layer, if the potential of the first electrode layer is equal to or greater than the potential of the fourth electrode layer, The first electrode layer is called the main gate electrode, and the potential of the fourth electrode layer is higher than the potential of the first electrode layer. In this case, the fourth electrode layer is referred to as the main gate electrode. Either of the fourth electrode layers may be GND, 0V, or floating. stomach.

[0034] The first electrode layer 421b of the transistor 440B is connected to the main gate of the transistor. Therefore, the region of the oxide semiconductor layer 404b in contact with the second electrode layer 455c and a region of the oxide semiconductor layer 404b in contact with the third electrode layer 455d. A channel is formed in the region that contacts the edge layer 402 and overlaps with the first electrode layer 421b.

[0035] The transistor 440B includes a first electrode layer 421b, a second electrode layer 455c, a third electrode layer 455d, and a By using a light-transmitting conductive film for the electrode layer 455d and the fourth electrode layer 422b, The light-transmitting transistor can be used as a light-transmitting transistor. When applied to the pixel, the aperture ratio of the pixel can be improved.

[0036] The light-transmitting conductive film is made of a conductive material that transmits visible light, for example In-Sn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn -Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxide conductive materials When using a sputtering method, SiO2 is used in an amount of 2% by weight or more and 10% by weight or less. % or less, and the transparent conductive film is formed using a target containing SiOx (X>0). It is preferable to make the material amorphous by incorporating the above.

[0037] The first electrode layer 421a, the second electrode layer 455a, and the third electrode layer 4 55b, and the fourth electrode layer 422a are made of Ti, Mo, W, Al, Cr, Cu, Ta A film containing an element selected from the above as a main component may be formed as a single film or a laminated film thereof. In particular, the second electrode layer 455a and the third electrode layer 455b electrically connected to the oxide semiconductor layer 455b is preferably made of a material containing a metal with high oxygen affinity.

[0038] The oxide semiconductor layer is made of quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides such as In-Sn-Ga-Zn-O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides An oxide semiconductor film such as an In—O-based, Sn—O-based, or Zn—O-based film can be used. The oxide semiconductor layer may contain SiO2.

[0039] The oxide semiconductor layer is InMO3(ZnO) m A thin film expressed as (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co. InMO3(ZnO) m Oxide semiconductors with a structure represented by (m>0) The oxide semiconductor layer containing Ga as M is the In-Ga-Zn-O In this paper, we refer to these semiconductors as In-Ga-Zn-O based oxide semiconductors, and their thin films are also referred to as In-Ga-Zn-O based films.

[0040] In addition, the oxide semiconductor layer is subjected to RTA (Rapid Thermal Anneal). Use materials that have been dehydrated or dehydrogenated at high temperature for a short time using methods such as hot thermal annealing. This heating process reduces the grain size of the surface layer of the oxide semiconductor layer to 1 nm or more and 20 nm or less. It has a crystalline region composed of so-called nanocrystals (also written as nanocrystals). The other parts are amorphous or a mixture of amorphous and microcrystalline regions with microcrystalline scattered throughout the amorphous regions. The size of the nanocrystals is merely an example, and the invention is not limited to the above numerical range. It is not to be interpreted.

[0041] By using an oxide semiconductor layer with such a structure, the surface layer is made up of nanocrystals. The dense crystalline region prevents moisture from re-entering the surface and oxygen from escaping, resulting in n-type conversion. As a result, the deterioration of electrical characteristics caused by the n-type structure, specifically the increase in off-state current, can be prevented. It can be prevented.

[0042] The crystalline region in the surface layer of the oxide semiconductor layer has a crystal structure in the direction substantially perpendicular to the surface of the oxide semiconductor layer. It has crystal grains oriented along the c-axis. For example, In-Ga-Zn-O oxides When using semiconductor materials, the crystalline region is formed by the c-axis of the In2Ga2ZnO7 crystal grains. The orientation is approximately perpendicular to the surface of the semiconductor layer. The nanocrystals are aligned so that their axes are perpendicular to the substrate plane (or the surface of the oxide semiconductor layer). By arranging the In2Ga2ZnO7, the direction of current flow in the transistor is This is the axial direction (or a-axis direction).

[0043] The crystalline region may include other elements than crystal grains. The crystal structure is not limited to the above, and may include crystal grains of other crystal structures. For example, In-Ga-Zn When using an oxide semiconductor material of the In-O system, in addition to the crystal grains of In2Ga2ZnO7, It may contain crystal grains of nGaZnO4.

[0044] 1A to 1E, a transistor 440A and a transistor 440B are formed on the same substrate. The process for fabricating resistor 440B will now be described.

[0045] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. The first electrode layer 421a and the first electrode layer 421b are formed by the process. To prevent this, at least the first electrode layer 421a and the end of the first electrode layer 421b are provided with a Preferably, the etching is carried out so as to form a tapered shape.

[0046] The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs. It can be applied not only to the first photolithography process but also to other photolithography processes. Cut.

[0047] The substrate 400 may be made of barium borosilicate glass, aluminoborosilicate glass, or or aluminosilicate glass, which are made by the fusion or float process. In addition to potassium glass substrates and ceramic substrates, it has heat resistance that can withstand the processing temperatures of this manufacturing process. Plastic substrates and the like can be used. In addition, the surface of a metal substrate such as a stainless steel alloy can be used. A substrate provided with an insulating film may be used.

[0048] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, a crystallized glass substrate or the like may also be used.

[0049] The first electrode layer 421a and the first electrode layer 421b are made of aluminum, copper, molybdenum, Metallic materials such as titanium, chromium, tantalum, tungsten, neodymium, and scandium, or alloy materials whose main components are these metal materials, or nitrogen compounds whose components are these metal materials The insulating layer can be formed as a single layer or a multilayer using a metal such as aluminum or copper. However, due to problems of heat resistance and corrosion, it is difficult to form the wire using high melting point metal materials. It is recommended to use them in combination. High melting point metal materials include molybdenum, titanium, chromium, Examples of materials that can be used include tantalum, tungsten, neodymium, and scandium.

[0050] At this time, the aperture ratio can be improved by using a conductive layer having light-transmitting properties for a part of the electrode layer or wiring layer. The light-transmitting conductive layer can be formed of, for example, indium oxide, indium oxide Tin oxide alloy, indium oxide zinc oxide alloy, zinc oxide, zinc aluminum oxide, oxynitride A conductive oxide layer containing zinc aluminum, zinc gallium oxide, or the like can be used. .

[0051] The first electrode layer 421a and the first electrode layer 421b may be formed using different materials. For example, in order to improve the aperture ratio of the pixel portion, the first electrode layer 421b may be made of a material that is transparent to visible light. The first electrode layer 42 of the drive circuit section is formed of a conductive layer having a high electrical resistance. 1a is a conductive film mainly composed of metal, such as titanium, molybdenum, tungsten, aluminum A film whose main component is an element selected from aluminum, chromium, copper, and tantalum, either as a single film or as a combination of these. It can also be formed using these laminated films.

[0052] In addition, an insulating layer serving as a base film is formed on the substrate 400, the first electrode layer 421a, and the first electrode layer 42 The base film has a function of preventing the diffusion of impurity elements from the substrate 400. and the film is selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. It can be formed by a laminated structure of one or more films.

[0053] Next, a first insulating layer 402 is formed on the first electrode layer 421a and the first electrode layer 421b. The first insulating layer 402 is formed of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, or the like. layer, silicon nitride layer, aluminum oxide layer, tantalum oxide layer, or other single layer or laminated film. In addition, the film thickness is set to 50 nm or more and 250 nm or less, and the CVD method or the sputtering method can be used. The first insulating layer 402 is formed by a deposition method or the like. A configuration with an edge layer is preferred.

[0054] In addition, the i-type or substantially i-type semiconductor used in this embodiment is obtained by removing impurities. The oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to the interface states and interface charges. Therefore, the interface with the insulating film is important. The insulating film in contact with the substrate must be of high quality.

[0055] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0056] In addition, the insulating film obtained by the high density plasma CVD device can be formed with a consistent thickness. In addition, the insulating film obtained by the high density plasma CVD equipment can precisely control the thickness of thin films.

[0057] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. Even if the insulating film is one in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by In any case, it is important that the quality of the gate insulating film is good, and that the oxidation Any material may be used as long as it can reduce the interface state density with the compound semiconductor and form a good interface.

[0058] The first insulating layer 402 is formed by a high density plasma CVD apparatus. The plasma CVD equipment is 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, An insulating film is formed.

[0059] The chamber was filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gases. A high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and insulating materials such as glass are An insulating film is formed on a substrate having a surface. After that, the supply of monosilane gas is stopped and the substrate is exposed to the atmosphere. Plasma treatment is performed on the insulating film surface by introducing nitrous oxide (N2O) and rare gases without exposing it to heat. It may be performed on the surface of the insulating film by introducing at least nitrous oxide (N2O) and a rare gas. The plasma treatment is carried out after the insulating film is formed. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0060] When forming the first insulating layer 402, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar include helium, argon, krypton, and xenon. Among these, it is preferable to use argon, which is inexpensive.

[0061] In addition, the insulating film obtained by the high density plasma device can be formed with a consistent thickness. The insulating film obtained by the high density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0062] The insulating film obtained through the above process sequence is different from the insulating film obtained using a conventional parallel plate PCVD device. The etching rates are significantly different when the same etchant is used. The insulating film obtained by the parallel plate PCVD equipment is 10% or more or 20% slower and more highly The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0063] The first insulating layer 402 is formed by depositing silicon oxide by a CVD method using organic silane gas. It is also possible to form a layer. The organic silane gas is ethyl silicate (TEOS: Formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane silane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (Si H(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. The following silicon-containing compounds can be used:

[0064] The first insulating layer 402 may be formed of an oxide of aluminum, yttrium, or hafnium. At least two or more of the following compounds are used: Compounds containing the above can also be used.

[0065] In this specification, an oxynitride is a compound having a composition in which oxygen atoms are more abundant than nitrogen atoms. Nitrided oxide refers to a substance with a higher number of nitrogen atoms than oxygen atoms. For example, a silicon oxynitride film has a composition that contains a large number of nitrogen atoms. The number of oxygen atoms is greater than that of electrons, and Rutherford backscattering (RBS) Backscattering Spectrometry and Hydrogen Forward Scattering (H When measured using FS (Hydrogen Forward Scattering) In this case, the concentration range is 50 atomic % or more and 70 atomic % or less for oxygen and 0.5 atomic % or more and 1.5 atomic % or less for nitrogen. 5 atomic % or less, silicon is 25 atomic % to 35 atomic % and hydrogen is 0.1 atomic % to 10 The silicon nitride oxide film is a film containing silicon dioxide in an amount of 0.1 atomic % or less. There are more nitrogen atoms than oxygen atoms, and the concentration is The range is 5 atomic % or more and 30 atomic % or less of oxygen, 20 atomic % or more and 55 atomic % or less of nitrogen, Silicon is between 25 atomic % and 35 atomic % and hydrogen is between 10 atomic % and 30 atomic % However, the atoms constituting silicon oxynitride or silicon nitride oxide are When the total of these is taken as 100 atomic %, the content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges. shall be included within the scope.

[0066] Next, a thin film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the first insulating layer 402. An oxide semiconductor film 403 having a thickness of 20 nm or less is formed (FIG. 1A).

[0067] Note that before the oxide semiconductor film 403 was formed, argon gas was introduced to generate plasma. In this way, dust adhering to the surface of the first insulating layer 402 can be removed. Reverse sputtering is a method of sputtering a substrate in an argon atmosphere without applying a voltage to the target side. A method of modifying the surface by applying voltage to the substrate side using an RF power supply to generate plasma near the substrate. In place of the argon atmosphere, nitrogen, helium, etc. may be used. It may be performed in an atmosphere containing oxygen, N2O, etc. in an argon atmosphere. It may be performed in an atmosphere containing Cl2, CF4, etc. After the reverse sputtering process, it is necessary to expose it to the atmosphere. By forming the oxide semiconductor film without using the first insulating layer 402, the first insulating layer 402 and the oxide semiconductor film 40 This can prevent dust and moisture from adhering to the interface of 3.

[0068] The oxide semiconductor film is made of the above-mentioned quaternary metal oxides, such as In-Sn-Ga-Zn-O and , ternary metal oxides such as In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O system, and binary metal oxides such as In-Zn-O system, Sn-Zn-O system, and Al-Zn- O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, and single-component metal oxides An oxide semiconductor film such as an In—O-based, Sn—O-based, or Zn—O-based film can be used. The oxide semiconductor film may contain SiO2. InMO3(ZnO) m Thin films denoted by (m>0) can be used.

[0069] The oxide semiconductor film is formed under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Formed by sputtering in a mixed atmosphere of rare gas (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is contained in an amount of 2% by weight or more and 10% by weight or less. The oxide semiconductor film is deposited using a target containing SiOx(X> 0) may be included.

[0070] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (composition ratio: I n2O3:Ga2O3:ZnO=1:1:1 [molar ratio], or In2O3:Ga2 O3:ZnO=1:1:2 [molar ratio]) and the distance between the substrate and the target 100mm, pressure 0.6Pa, direct current (DC) power supply 0.5kW, oxygen (oxygen flow rate 100 %) atmosphere. When a pulsed direct current (DC) power supply is used, the This is preferred because it reduces powdery substances (also called particles or dust) and makes the film thickness distribution uniform. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor film. Using a film formation target, a 15 nm thick In-Ga-Zn-O system film was formed by sputtering. A film is formed.

[0071] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0072] In addition, it is preferable to form an oxide semiconductor film successively over the first insulating layer 402. The multi-chamber sputtering equipment is a silicon or silicon oxide (artificial quartz) ter and a target for an oxide semiconductor film. The deposition chamber in which the target is installed has a cryopump as an exhaust means. Instead of the lion pump, a turbo molecular pump is used, and water is placed on the intake port of the turbo molecular pump. A cold trap may be provided to adsorb the components.

[0073] The deposition chamber evacuated using a cryopump contains, for example, hydrogen atoms and hydrogen atoms such as H2O. Since compounds containing carbon atoms, carbon atoms, and compounds containing carbon atoms are exhausted, the film formation chamber The concentration of impurities contained in the deposited oxide semiconductor film can be reduced.

[0074] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to a concentration of about several ppm or several ppb. It is preferable.

[0075] The oxide semiconductor film may be formed while the substrate is heated. The temperature is set to 200°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor film, the concentration of impurities contained in the formed oxide semiconductor film can be reduced. do.

[0076] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias pulse. The sputtering method is mainly used to form insulating films, while the DC sputtering method is mainly used to form metal conductive films. It is used when forming a film.

[0077] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0078] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0079] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0080] Next, a second photolithography process is performed to form a resist mask, and an In-Ga-Z The nO film is etched using organic solvents such as citric acid and oxalic acid. Acid can be used as an etchant. By etching the surface into a tapered shape, it is possible to prevent the wiring from being cut off due to the step shape. The etching here is not limited to wet etching, but may be dry etching. It's fine.

[0081] Next, the oxide semiconductor layers 404a and 404b are dehydrated or dehydrogenated. Alternatively, the first heat treatment for dehydrogenation may be performed by resistance heating or lamp irradiation under an inert gas atmosphere. What method should be used? At 500℃ to 750℃ (or below the distortion point of the glass substrate) RTA for 1 minute or more and 10 minutes or less, preferably 650°C, 3 minutes or more and 6 minutes or less This can be done using the RTA method. If the temperature is too high, dehydration or dehydrogenation can be achieved in a short time, and the temperature can be increased to exceed the strain point of the glass substrate. The heat treatment is not limited to this timing, and can be performed at any time during photolithography. This may be performed multiple times before and after the film forming process or the film forming process.

[0082] In this specification, the heat treatment under an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is also called heat treatment for dehydrogenation. Dehydrogenation does not only mean that H, OH, etc. are eliminated. For convenience, this process will be referred to as dehydration or dehydrogenation.

[0083] The heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is The hydrogenation was carried out in the same furnace as the hydrogenation, without contact with the atmosphere, and without re-introducing water or hydrogen. It is important to lower the temperature to the temperature where oxygen is depleted. The nitride semiconductor layer is made n-type (n - , n + etc.), that is, after reducing the resistance, oxygen is replenished. When a transistor is fabricated using an oxide semiconductor layer that has been made i-type by increasing the resistance by SiO 2 , The threshold voltage of the resistor can be set to a positive value, and the switch has a so-called normally-off characteristic. The gate voltage of the transistor is set to a positive threshold voltage as close as possible to 0V. It is desirable for a display device that a channel is formed by a voltage. If the gate voltage is negative, even if the gate voltage is 0V, a voltage is generated between the source and drain electrodes. Active matrix display devices are prone to current flow, which is known as normally-on characteristics. In this case, the electrical characteristics of the transistors that make up the circuit are important, and these electrical characteristics are displayed. The performance of the device is affected. In particular, the threshold voltage (Vth) of the transistor is an important electrical characteristic. Even if the field effect mobility is high, the threshold voltage is high, or If the threshold voltage is negative, it is difficult to control the circuit. In the case of a transistor, when the drive voltage is low, it does not perform the switching function as a transistor. In the case of an n-channel transistor, the gate Only when a positive voltage is applied to the gate electrode does a channel form and drain current begin to flow. A transistor is desirable. A transistor in which a channel does not form unless the driving voltage is high. A transistor in which a channel is formed and drain current flows even under negative voltage conditions is It is not suitable as a transistor to be used.

[0084] In addition, the gas atmosphere when the temperature is lowered from the heating temperature T is the same as the gas atmosphere heated to the heating temperature T. For example, the same gas atmosphere as that used for dehydration or dehydrogenation may be used. The furnace is kept free from exposure to the atmosphere and is filled with high-purity oxygen gas or N2O gas, ultra-dry air, and Cooling is carried out by filling the tank with water (dew point of -40°C or less, preferably -60°C or less).

[0085] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device should be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0086] When the heat treatment is performed in an inert gas atmosphere, the oxide semiconductor layer It becomes oxygen deficient and has low resistance, i.e., it becomes n-type (n - Then, the oxide semiconductor layer By forming an oxide insulating layer in contact with the oxide semiconductor layer, oxygen is supplied to oxygen vacant portions of the oxide semiconductor layer. This results in high resistance, i.e., i-type. This results in good electrical properties and reliability. Therefore, a transistor with good characteristics can be manufactured.

[0087] The oxide semiconductor layer that has been sufficiently dehydrated or dehydrogenated under the above conditions is analyzed by thermal desorption spectroscopy. (TDS: Thermal Desorption Spectroscopy) 45 Even when the temperature was raised to 0°C, two peaks in the spectrum indicating the desorption of water were observed, at least 250-3 One peak that appears around 00°C is not detected.

[0088] Note that the oxide semiconductor layers 404a and 404b are mostly formed. Although the amorphous material has many dangling bonds, the first heating step of the dehydration or dehydrogenation treatment By performing this, dangling bonds in close proximity bond with each other, forming an ordered amorphous structure. Furthermore, as the ordering progresses, the amorphous and microcrystalline regions are formed. The oxide semiconductor layer 404a and the oxide semiconductor layer 404b are formed as a mixture of crystals or as an amorphous layer. The crystalline region 405a and the crystalline region 405b are formed of nanocrystals on the surface of the conductor layer 404b. The oxide semiconductor layer 404a and the oxide semiconductor layer 4b are formed (FIG. 1B). The other regions of 04b are amorphous, or a mixture of amorphous and microcrystalline regions with microcrystalline interspersed in the amorphous regions. Note that the crystalline region 405a and the crystalline region 405b are formed by the oxide semiconductor layer 404a. and a part of the oxide semiconductor layer 404b. Hereinafter, these are referred to as the oxide semiconductor layer 404a or the oxide semiconductor layer 404b. The notation of the crystalline semiconductor layer 404b includes the crystalline region 405a or the crystalline region 405b. The particle size of the microcrystals is between 1 nm and 20 nm, which is called nanocrystals. It is smaller than the microcrystalline particles generally called microcrystals. be.

[0089] In the crystalline regions 405a and 405b, the c-axis is oriented perpendicular to the film surface. It is preferable that nanocrystals having a long axis in the c-axis direction and a short axis in the is preferably 1 nm to 20 nm.

[0090] Depending on the order of steps, a crystalline region may not be formed on the side surface of the oxide semiconductor layer. However, the area ratio of the side surface is small. Even if the temperature is low, the effects of suppressing deterioration of electrical characteristics and improving dielectric strength are maintained.

[0091] The first electrode layer 421a and the first electrode layer 421b are also formed under the conditions of the first heat treatment. Depending on the material, the film may crystallize to become a microcrystalline film or a polycrystalline film. When indium tin oxide is used for the first electrode layer 421a and the second electrode layer 421b, In the case of silicon oxide, the first heat treatment at 450°C for 1 hour results in crystallization. When tin is used for the first electrode layer 421a and the first electrode layer 421b, crystallization is unlikely to occur. Stake.

[0092] After the first heat treatment, the oxide semiconductor layers 404a and 404b become oxygen-deficient. The carrier concentration is higher than that immediately after the film formation, preferably 1×10 18 / cm 3 More than a rich career The oxide semiconductor layers 404a and 404b have a low resistance.

[0093] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography step for processing into an island-shaped oxide semiconductor layer.

[0094] Next, although not shown, a first electrode layer and a source electrode layer or a drain electrode layer (to be described later) are formed. An opening (also called a contact hole) for connecting layers is formed in the first insulating layer 402. A mask is formed on the first insulating layer 402 by photolithography, inkjet printing, or the like. The first insulating layer 402 is selectively etched using the mask to form contacts. The contact holes are formed by oxidizing the first insulating layer 402 after the first insulating layer 402 is formed. This may be performed before the formation of the compound semiconductor film 403 .

[0095] Next, a source electrode and a drain electrode (the same as this) are formed on the oxide semiconductor layers 404a and 404b. The conductive film is formed to a thickness of 100 nm or more and 50 nm or more. The thickness is preferably 200 nm to 300 nm.

[0096] The source and drain electrodes are made of metal materials such as Al, Cu, Cr, Ta, Ti, Mo, and W. The metal layer is made of a metal material or an alloy material containing the metal material. A high melting point metal layer such as Cr, Ta, Ti, Mo, or W is laminated on one or both of the above. In addition, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. may be formed on the Al film. Use an Al material that contains elements that prevent the formation of hillocks and whiskers. This makes it possible to improve the heat resistance.

[0097] The source and drain electrodes (including the wiring formed in the same layer) are made of conductive metal oxide. Conductive metal oxides include indium oxide (In2O3), oxide Tin oxide (SnO2), zinc oxide (ZnO), indium oxide tin oxide alloy (In2O3- SnO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2O3-ZnO) Alternatively, the metal oxide material may contain silicon or silicon oxide. Furthermore, the layer is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers can be used. The conductive film has at least heat resistance sufficient to withstand the second heat treatment to be performed later. It is preferable that the compound has the following structure:

[0098] The conductive film in contact with the oxide semiconductor layers 404a and 404b contains a metal with high oxygen affinity. The material is preferable. Metals with high oxygen affinity include titanium (Ti), manganese (Mn), Magnesium (Mg), Zirconium (Zr), Beryllium (Be), Thorium (Th) It is preferable that the material is selected from one or more of the following. A membrane is used.

[0099] When an oxide semiconductor layer is formed in contact with a conductive film having high oxygen affinity, the carrier density near the interface The resistance of the oxide semiconductor layer is increased, a low-resistance region is formed, and the contact resistance between the oxide semiconductor layer and the conductive film is reduced. This is because the conductive film with high oxygen affinity extracts oxygen from the oxide semiconductor layer. Therefore, a layer containing excess metal in the oxide semiconductor layer (also called a composite layer) is formed at the interface between the oxide semiconductor layer and the conductive film. This is called the formation of a conductive film or an oxidized conductive film, or both. For example, in a structure in which an In-Ga-Zn-O oxide semiconductor layer is in contact with a titanium film, In the vicinity of the interface between the oxide semiconductor layer and the titanium film, an indium-excess layer and a titanium oxide layer are formed. In addition, indium may be generated near the interface between the oxide semiconductor layer and the titanium film. Either an excessive titanium layer or a titanium oxide layer may form. The layer with excess indium, which is deficient in oxygen from the O-based oxide semiconductor layer, has high electrical conductivity and is highly oxidative. This can reduce the contact resistance between the compound semiconductor layer and the conductive film.

[0100] Note that a titanium film or a conductive titanium oxide film is used as the conductive film in contact with the oxide semiconductor layer. In this case, an In-Ga-Zn-O oxide semiconductor layer and a titanium oxide film may be used. In the structure where the oxide semiconductor layer and the titanium oxide film are in contact with each other, an indium monoxide film is formed near the interface where the oxide semiconductor layer and the titanium oxide film are in contact with each other. This can create an over-abundant layer.

[0101] Alternatively, a conductive material that transmits visible light can be used for the conductive film. The conductive material having transparency to visible light is selected from the group consisting of indium, tin, and zinc. Transparent conductive oxides containing indium oxide (In2O3) and indium oxide are preferred. In2O3-SnO2 (abbreviated as ITO) can be used. Alternatively, a transparent conductive oxide may be used in which an insulating oxide such as silicon oxide is added. By using a transparent conductive oxide as a conductive film, the aperture ratio of a display device can be improved. It is possible.

[0102] The conductive film can be formed by arc discharge ion plating or spraying. Conductive nanopastes such as silver, gold, and copper may also be used. It may also be formed by discharging using a jet method and then firing.

[0103] Next, a mask is formed on the conductive film by photolithography, ink jetting, or the like. The conductive film is then etched using the mask to form a source electrode and a drain electrode. In this embodiment, a conductive film having a thickness of 200 nm is formed by sputtering. A Ti film with a thickness of 1000 nm is formed, and then a resist mask is used to form the Ti film. The conductive film is selectively etched by etching method to form a layer that functions as a source electrode and a drain electrode. The second electrode layer 455a, the third electrode layer 455b, the second electrode layer 455c, and the third electrode layer 455d are The electrode layer 455d is formed.

[0104] Next, the second electrode layer 455a, the third electrode layer 455b, the second electrode layer 455c, and a second insulating layer covering the third electrode layer 455d and the exposed oxide semiconductor layers 404a and 404b; The second insulating layer 428 is formed (FIG. 1(D)). The thickness of the second insulating layer 428 is 50 nm to 250 nm. The following is preferable, and the second insulating layer 428 has an oxide insulating layer on the side in contact with the oxide semiconductor layer. The oxide insulating layer on the side of the second insulating layer 428 that is in contact with the oxide semiconductor layer is made of an oxide silicon oxynitride layer, silicon oxynitride layer, aluminum oxide layer, tantalum oxide layer, tantalum oxide layer An oxide insulating layer such as a hafnium oxide layer or a hafnium oxide layer can be used.

[0105] The oxide insulating layer is formed by mixing impurities such as water and hydrogen into the oxide insulating layer by a method such as sputtering. In this embodiment, a sputtering method is used. The substrate temperature during film formation is 300°C above room temperature. In this embodiment, the temperature is set to 100° C. Here, impurities such as water and hydrogen are not added during film formation. As a method to prevent the inclusion of impurities, before film formation, the film is heated at a temperature of 150°C to 350°C under reduced pressure for 2 Pre-baking is performed for 10 minutes or more, and an oxide insulating layer is formed without exposure to the air. It is desirable to form a silicon oxide film by sputtering using a rare gas (typically, In a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used to oxidize oxygen and rare gases. Silicon oxide can be formed by sputtering in a gas atmosphere. The oxide insulating layer formed in contact with the oxide semiconductor layer is resistant to moisture, hydrogen ions, and OH - Such as Formed while avoiding the mixing of pure materials.

[0106] In addition, an inorganic insulating film is laminated on the oxide insulating layer to prevent moisture, hydrogen ions, and OH - Such as It is preferable that the second insulating layer 428 has a structure that prevents impurities from entering the oxide semiconductor layer from the outside. Examples of inorganic insulating films stacked on the oxide insulating layer include a silicon oxide layer, a silicon oxynitride layer, and A silicon nitride oxide layer, a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer, etc. It is possible.

[0107] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm. Pressure: 0.4 Pa, DC power: 6 kW, oxygen (oxygen flow rate: 100%) atmosphere The second insulating layer 42 is formed by a pulse DC sputtering method. The film thickness is set to 300 nm. The sputtering gas used in forming the film 8 contains impurities such as hydrogen, water, hydroxyl groups, and hydrides. It is preferable to use a high-purity gas in which the concentration has been reduced to about several ppm or several ppb. .

[0108] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. RTA treatment may be performed for a short time. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor The oxide semiconductor layer is heated in contact with the conductor layer, and the resistance of the oxide semiconductor layer is reduced by the first heat treatment. Oxygen can be supplied to the defect area to increase resistance (i-type).

[0109] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. There is no problem if the silicon oxide film is formed afterwards, and it is not limited to the time immediately after the silicon oxide film is formed. stomach.

[0110] Next, a photolithography process is performed to form a resist mask, and the second insulating layer 428 A contact hole reaching the second electrode layer 455d is formed by etching.

[0111] Next, a conductive film is formed on the second insulating layer 428, and then the conductive film is subjected to photolithography. The process is performed to form the fourth electrode layer 422a, the fourth electrode layer 422b, and the pixel electrode layer 422c in a later process. A connection electrode layer 422c is formed to be connected to the electrode layer (FIG. 1(E)). A film mainly composed of an element selected from Cr, Cu, Ta, Ti, Mo, and W is used as a single film. However, the third electrode layer 455d and the pixel electrode layer may be directly connected to each other. If they are connected, the connection electrode layer 422c may be omitted.

[0112] In this embodiment, the fourth electrode layer 422a of the transistor 440A is The potential of the first electrode layer 421a is controlled by the potential of the fourth electrode layer 421b. It may be at a potential lower than 2a, or at GND, 0V, or in a floating state.

[0113] The first electrode layer 421b of the transistor 440B is connected to the main gate of the transistor. The potential of the fourth electrode layer 422b is higher than the potential of the first electrode layer 421b. It may be below, or at GND, 0V, or floating.

[0114] A pair of electrode layers is placed above and below the channel formation region of the oxide semiconductor layer via an insulating film. The reliability of the transistor can be improved by using a semiconductor structure. Bias-thermal stress test (hereinafter referred to as BT test) is used to check the reliability of transistors. In this case, it is possible to reduce the amount of change in the threshold voltage of the transistor before and after the BT test. Cut.

[0115] As shown in FIG. 2, a transistor using the first electrode layer as a main gate electrode has The fourth electrode layer may not be provided.

[0116] FIG. 2 shows an example of a cross-sectional structure of a plurality of transistors fabricated on a circuit-equipped substrate of a display device. The transistor 440A shown in FIG. 2 has insulating layers above and below a channel formation region of an oxide semiconductor layer. It is one of the four-terminal structures in which a pair of electrode layers are arranged through an insulating film, and the transistor 450 is It is a staggered type.

[0117] The transistor 440A is formed as part of a driver circuit arranged around the pixel portion of the display device. The transistor 450 is preferably a pixel, part of a driving circuit, or a protection circuit. It is preferable that the groove is formed in the path.

[0118] The transistor 450 includes a first electrode layer 421c, a first the insulating layer 402, the oxide semiconductor layer 404c including the crystalline region 405c, the second electrode layer 455, The third electrode layer 455f covers the transistor 450 and the crystalline region 40 The second insulating layer 428 is in contact with the first electrode layer 421c and the oxide semiconductor layer 40. 4c overlaps with the first insulating layer 402. In addition, the second electrode layer 455e and A third electrode layer 455f is formed above the oxide semiconductor layer 404c so as to partially overlap the oxide semiconductor layer 404c.

[0119] Note that a protective insulating layer may be formed to cover the transistors 440A and 440B. The insulating layer may be, for example, a silicon nitride film, a silicon nitride oxide film, or an aluminum nitride film. Use.

[0120] In addition, a planarization insulating layer may be provided over the fourth electrode layer 422b in the pixel portion. The edge layer may be made of acrylic, polyimide, benzocyclobutene, polyamide, epoxy, etc. In addition to the above organic materials, low dielectric constant materials can be used. low-k materials, siloxane resins, PSG (phosphor glass), BPSG (phosphor boro) In addition, multiple insulating layers made of these materials can be stacked. In addition, a color filter layer can also be used as a planarization insulating layer.

[0121] In addition, a capacitor wiring and a fourth electrode layer 421b can be fabricated using the same material and process as the first electrode layer 421b. The first insulating layer 402, the second insulating layer 422b, and the third insulating layer 422c are made of the same material and by the same process as the first insulating layer 402. Alternatively, a storage capacitor sandwiching a dielectric layer including an oxide insulating layer may also be formed on the same substrate. A pixel section is formed by arranging pixels each having a transistor 440B and a storage capacitor in a matrix. The substrate on which the driver circuit having the transistor 440A is arranged around the pixel portion is an active matrix. It can be used as one of the substrates for manufacturing a trix type display device.

[0122] In addition, when a display device is manufactured using the transistors 440A and 440B, the driving transistors A power supply line is provided which is electrically connected to the source electrode layer of the transistor, and the power supply line is connected to the gate The wiring is intersected and the connecting electrode layer 422c is made of the same material and formed in the same process as the connecting electrode layer 422c made of a metal conductive film. Alternatively, the power supply line may intersect with the source wiring and may be formed in the same layer as the first electrode layer 421b. It is made from the same material and through the same process.

[0123] In addition, when a light emitting device is manufactured, one electrode of the light emitting element is connected to the source voltage of the driving transistor. The electrode layer or drain electrode layer is electrically connected to the other electrode of the light-emitting element. The common potential line is connected to the connecting electrode layer 4 made of a metal conductive film. Alternatively, the common potential line is formed of the same material and in the same process as the first electrode layer 421b. It is made of the same material and in the same process.

[0124] The transistor including the oxide semiconductor layer in which the hydrogen concentration is reduced as described above has an off-state current The current is extremely low, 1×10 -13 A or less. As the transistor, for example, there is one that uses silicon carbide (for example, 4H—SiC). Semiconductors and 4H-SiC have several things in common, one of which is the carrier density. Using the Fermi-Dirac distribution at room temperature, the minority carriers in oxide semiconductors are 1 0 -7 / cm 3 This is estimated to be about 6.7 × 10 in 4H-SiC.-1 1 / cm 3 This is an extremely low value, similar to the intrinsic carrier density of silicon (1.4×10 1 0 / cm 3 If we compare it to the level of The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-SiC The energy band gap of is 3.26 eV, so it is a wide-gap semiconductor. In the above, oxide semiconductors and silicon carbide have something in common.

[0125] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The semiconductor process using silicon carbide is generally performed at a temperature of 1500 to 2000°C. This is done through activation heat treatment. At such high temperatures, the semiconductor substrate and semiconductor elements will be destroyed. Therefore, it is necessary to form an integrated circuit using other semiconductor materials and then use a silicon carbide semiconductor. On the other hand, oxide semiconductors are difficult to fabricate because they are heated at temperatures between 300 and 500°C (glass). It can be produced by heat treatment below the transition temperature (up to about 700°C), and After forming an integrated circuit using a conductive material, a semiconductor element is formed using an oxide semiconductor. This makes it possible to:

[0126] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced.

[0127] In oxide semiconductors, physical properties such as DOS (density of states) Although much research has been done, these studies have not yet fully addressed the idea of ​​sufficiently reducing DOS itself. In one embodiment of the disclosed invention, the present invention does not include a compound that can cause DOS in the energy gap. Water and hydrogen are removed from the oxide semiconductor, thereby manufacturing a highly purified oxide semiconductor. This is based on the idea of ​​sufficiently reducing DOS itself. This makes it possible to manufacture extremely superior industrial products.

[0128] Furthermore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and oxygen vacancies are eliminated. By reducing the DOS, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen is formed in close contact with the channel forming region, By supplying oxygen from the oxide film, it is possible to reduce DOS due to oxygen defects.

[0129] Defects in oxide semiconductors are caused by excess hydrogen at a level of 0.1 to 0.2 eV below the conduction band, or by oxygen. These defects are thought to be caused by deep levels due to deficiencies. The technical idea of ​​thoroughly removing hydrogen and providing a sufficient supply of oxygen is probably correct.

[0130] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type can be achieved by removing water and hydrogen. It can be said that this is not an i-type product made by adding pure substances, but rather involves a technological concept that has never been seen before.

[0131] A transistor using an oxide semiconductor has several characteristics. This will be explained using Figures 23 to 26. Note that the following explanation is merely a consideration. It should be noted that the validity of the invention is not denied based on the above. This will be explained next.

[0132] FIG. 23 is a longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the electrode (GE1) via a gate insulating film (GI), A source electrode (S) and a drain electrode (D) are provided on the insulating layer. A back gate (GE2) is provided via the edge layer.

[0133] FIG. 24 shows an energy band diagram (schematic diagram) in the cross section A-A' shown in FIG. 24(A) is the voltage between the source and drain as equipotential (V D = 0V) is shown in Fig. 24(B) is a positive potential (V D >0) is added.

[0134] Figures 25 and 26 are energy band diagrams (schematic diagrams) between B-B' in Figure 23. Figure 25 shows the state when the gate voltage is 0V. Figure 26(A) shows the gate (GE1) to a positive potential (V G >0) is applied, and carriers (electrons) are generated between the source and drain. ) flows. Also, FIG. 26(B) shows the ON state when a negative potential is applied to the gate (GE1). (V G <0) is applied and the transistor is in the off state (no minority carriers flow). The oxide semiconductor has a thickness of about 50 nm and is highly purified. The donor concentration is 1 × 10 18 / cm 3 If the value is less than 0.01, the depletion layer is oxidized in the off state. This spreads throughout the entire semiconductor, which means that it can be considered a fully depleted state.

[0135] Figure 27 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0136] Metals are degenerate, with the Fermi level located within the conduction band. It is n-type and its Fermi level (E f ) is the intrinsic Fermi element located in the center of the band gap. Level (E i ) and is located closer to the conduction band. It is known that some of the hydrogen atoms become donors and are one of the factors that cause the material to become N-type.

[0137] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. By removing impurities other than the main component of the oxide semiconductor and purifying it to the utmost, In other words, it is an attempt to make it intrinsic (type i) or intrinsic. Instead of simply converting it to i-type, impurities such as hydrogen and water are removed as much as possible to achieve high purity. The feature is that it is an i-type (intrinsic semiconductor) or close to it. Elmi level (E f ) is the intrinsic Fermi level (E i ) can be brought to the same level as

[0138] The band gap (E g ) is 3.15 eV, the electron affinity (χ) is The titanium (Ti) that makes up the source and drain electrodes is said to be 4.3 eV. The electron affinity function is approximately equal to the electron affinity (χ) of the oxide semiconductor. At the interface between the layers, no Schottky barrier is formed for electrons.

[0139] That is, when the work function (φM) of the metal and the electron affinity (χ) of the oxide semiconductor are equal, When a person comes into contact with the surface, an energy band diagram (schematic diagram) such as that shown in FIG. 24(A) is displayed.

[0140] In Figure 24(B), the black circles (●) represent electrons, and a positive voltage (V D >0) is applied If no voltage is applied to the gate (V G =0) is shown by a dashed line, and a positive voltage is applied to the gate. (V G The solid line shows the case where a positive voltage (V G >0) is applied. In this case, when a positive potential is applied to the drain, electrons cross the barrier (h) and are injected into the oxide semiconductor. In this case, the height of the barrier (h) is determined by the gate voltage and the drain voltage. The gate voltage (V G >0) is applied to the positive drain When a voltage is applied, the barrier height, i.e., the band, of Figure 24(A) without voltage application The barrier height (h) is smaller than half the gap (Eg). When no voltage is applied, the high potential barrier prevents carriers from flowing from the electrode to the oxide semiconductor. This indicates the off state, where no electrons are injected and no current flows. On the other hand, when a positive voltage is applied to the gate, As a result, the potential barrier decreases, and the device enters an on-state where current flows.

[0141] At this time, the electrons injected into the oxide semiconductor pass through the oxide semiconductor as shown in FIG. In addition, in FIG. 26(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. become.

[0142] In this way, the oxide semiconductor is highly purified so that it does not contain impurities other than the main component as much as possible. By making it intrinsic (i-type) or substantially intrinsic, the interface characteristics with the gate insulating film Therefore, the gate insulating film is required to be separated from the bulk characteristics. It is necessary to have a good interface with the semiconductor. For example, VHF band to microwave band An insulating film or a silicon dioxide film is produced by a CVD method using high density plasma generated at a power supply frequency of 1000 kHz. It is preferable to use an insulating film formed by a sputtering method.

[0143] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating film is improved. As a result, the transistor characteristics are such that the channel width W is 1×10 4 The channel length in μm Even with a 3 μm element, the off-state current at room temperature is 10 -13 A or less, and A threshold swing (S value) of 0.1V / dec. (gate insulating film thickness 100nm) is fully expected. Be waited for.

[0144] In this way, it is possible to purify the oxide semiconductor to the extent possible so that it does not contain impurities other than the main component. As a result, the operation of the transistor can be improved.

[0145] The transistor of this embodiment includes a highly purified oxide semiconductor layer. The body layer has a dense crystalline region on the surface composed of nanocrystals, and the crystalline region is highly purified from the surface This prevents moisture from re-entering the oxide semiconductor layer and preventing it from becoming n-type due to oxygen desorption. A pair of electrode layers is disposed above and below such a highly purified oxide semiconductor layer with an insulating film interposed therebetween. The four-terminal transistor has a positive threshold voltage and an extremely low off-state current. It has characteristics.

[0146] In addition, when the fourth electrode layer is used as a main gate electrode, the second electrode of the oxide semiconductor layer a second insulating layer sandwiched between a region of the oxide semiconductor layer contacting the third electrode layer and a region of the oxide semiconductor layer contacting the third electrode layer; A channel is formed in the region where the second electrode layer contacts the first electrode layer and overlaps with the fourth electrode layer. The region formed is also a crystalline region of the oxide semiconductor, and is approximately perpendicular to the surface of the oxide semiconductor layer. It has crystal grains oriented in the perpendicular direction along the c-axis. For example, In-Ga-Zn- When an O-based oxide semiconductor material is used, the c-axis is aligned with the substrate plane (or the oxide semiconductor layer surface). By arranging the nanocrystals perpendicular to the surface, a transistor can be created. The direction of the current in the In2Ga2ZnO7 is the b-axis (or a-axis) direction. The transistor using the fourth electrode layer as the main gate electrode has high dynamic characteristics (on-state characteristics and It exhibits frequency characteristics (called f characteristics), and is suitable for driving circuits that require high-speed operation, for example. It is suitable for the transistors used.

[0147] In addition, when the first electrode layer is used as a main gate electrode, the second electrode of the oxide semiconductor layer a first insulating layer sandwiched between a region of the oxide semiconductor layer contacting the third electrode layer and a region of the oxide semiconductor layer contacting the third electrode layer; A channel is formed in the region where the first electrode layer is in contact with the first electrode layer and overlaps the first electrode layer. The oxide semiconductor layer (highly purified oxide semiconductor layer) is made i-type or substantially i-type by The carrier concentration in the conductive layer is suppressed. On the other side, there is a dense crystalline region made up of nanocrystals, which prevents moisture from escaping from the surface. Therefore, the first electrode layer can be used as the main gate electrode. The transistor used as the electrode layer has extremely low off-state current and excellent reliability. For example, This is suitable for transistors used in pixel portions where a reduction in leakage current is required.

[0148] As described above, by selecting the gate electrode to be mainly used, it is possible to obtain a gate electrode having a crystalline region on the surface. A pair of electrode layers is disposed above and below the channel formation region of the oxide semiconductor layer via an insulating film. The electrical characteristics of the transistor terminal structure can be selected.

[0149] In addition, a channel formation region of an oxide semiconductor layer having a crystalline region on its surface is formed above and below the channel formation region via an insulating film. A plurality of transistors with a four-terminal structure, each with a pair of electrode layers, are provided on the same substrate, and mainly By selecting the gate electrode to be used, multiple transistors formed on the same substrate can be formed into different It can be operated with different characteristics.

[0150] In addition, it has a driver circuit capable of high-speed operation and a pixel section with reduced power consumption on the same substrate. A semiconductor device can be manufactured.

[0151] Note that in the transistor of one embodiment of the present invention, the gate electrode is mainly used as the first electrode. It is not necessary to fix it to either the first electrode layer or the fourth electrode layer, and it is possible to change the operating state of the circuit, It can be changed as appropriate depending on the production load.

[0152] Note that this embodiment mode can be freely combined with other embodiment modes.

[0153] (Embodiment 2) In this embodiment, a pair of electrodes is provided above and below a channel formation region of an oxide semiconductor layer with an insulating film interposed therebetween. The inverter circuit of the drive circuit is constructed using two transistors with a four-terminal structure that arranges the polar layer. An example of this will be described below with reference to FIG. 3. The transistor shown in FIG. 3(A) is a transistor according to the embodiment of the present invention. 1(E) are the same as the transistor 440A and the transistor 440B shown in FIG. 1(E), The same parts will be described using the same reference numerals.

[0154] The driving circuit for driving the pixel unit is arranged, for example, around the pixel unit, and includes an inverter circuit, It is constructed using capacitance, resistance, etc. One type of inverter circuit is composed of two n-channel transistors. For example, enhancement type transistors are formed by combining enhancement type transistors. and a depletion type transistor (hereinafter referred to as EDMOS circuit) and those formed by enhancement-type transistors (hereinafter referred to as EEMOS circuits). There is a road called a road.

[0155] The cross-sectional structure of the inverter circuit of the driver circuit is shown in FIG. The second transistor 440B can be formed in the same manner as in Embodiment 1, and therefore a detailed description thereof will not be given. After the contact hole 408 is formed in the second insulating layer 428, the fourth electrode A second electrode layer 422a and a fourth electrode layer 422b are provided, and a second electrode layer 422b is connected to the second electrode layer 422a through a contact hole 408. The second wiring 410b connected to the electrode layer 455c is directly connected to the fourth electrode layer 422b. Since the number of contact holes required for connection is small, the electrical resistance can be reduced. In addition, the area occupied by the contact holes can be reduced.

[0156] The first wiring 410 connected to the second electrode layer 455a of the first transistor 440A a is a power supply line (negative power supply line) to which a negative voltage VDL is applied. This power supply line is connected to the ground potential The power supply line (ground power supply line) may be the same.

[0157] In addition, a third wiring connected to the third electrode layer 455d of the second transistor 440B 410c is a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0158] FIG. 3C shows a top view of the inverter circuit of the driver circuit. The cross section taken along line Z1-Z2 corresponds to FIG.

[0159] The equivalent circuit of the EDMOS circuit is shown in Figure 3(B). 3(A), and the first transistor 440A is an enhancement type n-channel transistor. The first transistor 440B is a depletion-type n-channel transistor. This is an example of a register.

[0160] In this embodiment, the threshold voltages of the first transistor 440A and the second transistor 440B are In order to control the value, insulating films are formed above and below the channel formation region of the highly purified oxide semiconductor layer. The first electrode and the fourth electrode are provided with a first electrode and a fourth electrode interposed therebetween. A is an enhancement type and the second transistor 440B is a depletion type. A voltage is applied to each of the first and fourth electrodes.

[0161] In addition, in FIG. 3(A) and FIG. 3(C), the second wiring 410b is formed in the second insulating layer 428. 4 shows an example in which the fourth electrode layer 422b is directly connected to the second electrode layer 422c through a contact hole 408 formed in the first electrode layer 422a. However, this is not particularly limited, and a connecting electrode may be separately provided to connect the second wiring 410b and the fourth electrode layer 422. In this embodiment, the second transistor 440B may be electrically connected to the first transistor 440B. The fourth electrode layer is used as the main gate electrode. The first electrode layer of the transistor 440B may be used as the main gate electrode. There is no need to provide a contact hole 408 in the second insulating layer 428, and the first insulating layer 402 A contact hole is formed to connect the second electrode layer 455c and the first electrode layer 421b.

[0162] As described above, a pair of electrode layers are formed above and below the channel formation region of the oxide semiconductor layer via an insulating film. An inverter circuit can be configured using two transistors with a four-terminal structure. Controlling the threshold voltage of a transistor using the first electrode layer and the fourth electrode layer of a rugate structure Therefore, enhancement-type transistors and depletion-type transistors can be fabricated without separately forming oxide semiconductor films. The manufacturing process is simple because the transistors can be manufactured on the same substrate.

[0163] In addition, the transistor of one embodiment of the present invention using the fourth electrode layer as a main gate electrode may be The inverter circuit used has excellent dynamic characteristics.

[0164] This embodiment mode can be freely combined with other embodiment modes.

[0165] (Embodiment 3) In this embodiment, a pair of electrodes is provided above and below a channel formation region of an oxide semiconductor layer with an insulating film interposed therebetween. A pulse output circuit was created using two four-terminal transistors with polar layers. 4 and 5 show an example of connecting a plurality of pulse output circuits to form a shift register. This will be used to explain.

[0166] A transistor is a device having at least three terminals including a gate, a drain, and a source. The element has a channel region between the drain region and the source region, A current can flow through the in-region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is difficult to know which is the source or drain. Therefore, it is difficult to define whether the source or drain is the In some cases, the region that functions as a source or drain is not called a source or drain. In this case, they may be referred to as the first terminal and the second terminal, respectively.

[0167] FIG. 4A shows the configuration of the shift register. The shift register includes the first pulse output circuit 1 The pulse output circuit 10_N includes pulse output circuits 0_1 to N (N is a natural number of 3 or more).

[0168] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to the first wiring 11, the second wiring 12, the third wiring 13, and the fourth wiring 14 are connected to the first wiring 1 1 transmits a first clock signal CK1, and a second clock signal CK2 transmits from the second wiring 12. A third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. No. CK4 will be supplied.

[0169] The clock signal (CK) goes high (high signal, high power supply potential level) at regular intervals. It is a signal that alternates between a high level (also called a low signal or low power supply potential level) and a low level (also called a low signal or low power supply potential level). Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially clocked at 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are delayed by one period. The clock signal (CK4) is used to control the driving of the pulse output circuit. Depending on the input drive circuit, it may be called GCK or SCK, but here it is called CK. and give an explanation

[0170] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 4(B)). Although not shown, the power supply lines 51, 52, and 53 are connected to the power supply lines 51, 52, and 53. .

[0171] The first input terminal 21, the second input terminal 22, and the third input terminal 23 of the pulse output circuit are It is electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. In A), the first pulse output circuit 10_1 has a first input terminal 21 connected to a first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third The input terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. are actively connected.

[0172] In addition, in the first pulse output circuit 10_1, a start pulse SP1 ( The first start pulse is input to the n-th pulse output circuit 10_n in the second stage or later. (n is a natural number between 2 and N), the signal from the previous stage pulse output circuit (previous stage signal OUT(n-1) (n is a natural number greater than or equal to 2) is input.

[0173] In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages later, Similarly, in the n-th pulse output circuit 10_n at the second stage or later, The signal from the (n+2)th pulse output circuit 10_(n+2) of the stage (the subsequent signal OUT(n+ 2) is input. Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or the second stage. The first output signal (OUT(1)(SR) to OU) is input to the pulse output circuit in the previous stage. T(N)(SR)), a second output signal (OUT(1)~ OUT(N)) is output.

[0174] That is, in the first pulse output circuit 10_1, a first clock is input to a first input terminal 21. A clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, A third clock signal CK3 is input to the third input terminal 23, and a start signal CK4 is input to the fourth input terminal 24. A first pulse is input to the fifth input terminal 25, a second signal OUT(3) is input to the fifth input terminal 26, and a first The first output signal OUT(1)(SR) is output from the output terminal 26, and the second output terminal 27 As a result, the second output signal OUT(1) is output.

[0175] As shown in FIG. 4A, the last two stages of the shift register (10_N-1 and The next stage signal OUT(n+2) is not input to the first stage (10_N). The sixth wiring 16 outputs the second start pulse SP2, and the seventh wiring 17 outputs the third start pulse SP3. Alternatively, the signal SP3 can be generated separately inside the shift register. For example, the (N+1)th signal that does not contribute to the pulse output to the pixel unit may be used. The (N+1)th pulse output circuit 10_(N+2) A second start pulse (SP2) and a third start pulse (SP3) are generated from the dummy stage. Alternatively, a signal equivalent to the start pulse (SP3) may be generated.

[0176] Next, the structure of a pulse output circuit of one embodiment of the present invention will be described with reference to FIG.

[0177] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to a power supply line 51 to a power supply The power supply line 51 is connected to a first high power supply potential VDD, and the power supply line 52 is connected to a second high power supply potential VDD. The power supply line 51 supplies a high power supply potential VCC, and the power supply line 53 supplies a low power supply potential VSS. The magnitude relationship of the power supply potential of the power supply line 53 is as follows: the first high power supply potential VDD is higher than the second high power supply potential VC C is equal to or higher than the second high power supply potential VCC, and the second high power supply potential VCC is The potential VCC of the power supply line 52 is higher than the power supply potential VSS. The potential of the VDD pin may be equal to the VDD pin, but if it is lower than VDD, it may affect the operation. The potential applied to the gate electrode of the transistor can be kept low without This reduces the shift in the threshold voltage of the transistor and suppresses degradation.

[0178] The first clock signal (CK1) to the fourth clock signal (CK4) are generated at regular intervals. This signal alternates between H and L levels, but when it is H it is VDD and when it is L it is V Assume it is SS.

[0179] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N is a first transistor. The present embodiment has a first transistor 31 to an eleventh transistor 41 (see FIG. 4(C)). In this embodiment, two types of transistors are fabricated on the same substrate to form a pulse output circuit. The first pulse output circuit 10_1 to the second pulse output circuit 10_2 included in the shift register exemplified in this embodiment are Since the Nth pulse output circuit 10_N has the same configuration, the first pulse output The configuration and operation of the circuit 10_1 will be explained.

[0180] The first pulse output circuit 10_1 includes a first transistor 31 to an eleventh transistor 41. The first to eleventh transistors 31 to 41 are made of highly purified The transistor is an n-channel transistor in which a channel is formed in an oxide semiconductor layer.

[0181] Note that the highly purified oxide semiconductor layer of one embodiment of the present invention has a surface composed of nanocrystals. It has a dense crystalline region and can prevent moisture from re-entering the surface and oxygen from escaping, resulting in N-type conversion. A pair of electrode layers is disposed above and below such a highly purified oxide semiconductor layer via an insulating film. The four-terminal transistor used has a positive threshold voltage and an extremely low off-state current. It has excellent properties.

[0182] In particular, the surface on which the crystalline region is formed is the back channel side, and the substrate side is the first insulating layer. The transistor using the first electrode layer arranged at the In this embodiment, the first electrode layer is used as a main gate electrode. The transistors used as the electrodes are the second transistor 32 and the fifth transistor 35. Used for.

[0183] In addition, the pulse output circuit of this embodiment and a configuration in which a plurality of such pulse output circuits are connected In a shift register, an external signal is input directly to the gate electrode of a transistor. A transistor using the first electrode layer as a main gate electrode is particularly preferable. In the case of the pulse output circuit 10_1 of FIG. 1, a fourth input terminal to which a start pulse is input from the outside For example, the first transistor 31 and the fifth transistor 35 are connected to the transistor 24. The transistor using the first electrode layer as the main gate electrode is The withstand voltage between the gate and source or between the gate and drain is high, and abnormal input such as static electricity This force can prevent the occurrence of failures such as fluctuations in the threshold values ​​of transistors that make up the circuit.

[0184] The surface on which the crystal region is formed is used as a channel forming region, and the substrate is The transistor using the fourth electrode layer disposed on the opposite side to the first electrode layer as the main gate electrode has a high In this embodiment, the fourth electrode layer is used as a main gate electrode. The transistors are the third transistor 33, the sixth transistor 36, the tenth transistor 40 and the eleventh transistor 41.

[0185] Note that a transistor using the fourth electrode layer as a main gate electrode and a transistor using the first electrode layer as a main gate electrode are The transistor used as the main gate electrode is fabricated according to the method described in the first embodiment. Therefore, detailed description thereof will be omitted in this embodiment.

[0186] In addition, the first transistor 31, the fourth transistor 34, the seventh transistor 37 to The ninth transistor 39 is a transistor using the first electrode layer as a main gate electrode, for example. Either a transistor using a gate electrode or a transistor using the fourth electrode layer as the main gate electrode However, in this embodiment, the first electrode layer is used as a main gate electrode. The JIS standard shall apply.

[0187] In FIG. 4C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39. The second transistor 32 has a first terminal electrically connected to the input terminal 24 of the first transistor. The second terminal is electrically connected to the first terminal of the ninth transistor 39. and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal The fourth transistor 34 has a terminal electrically connected to the first output terminal 26. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal The terminals are connected to the gate electrodes of the second transistor 32 and the fourth transistor 34. The sixth input terminal 24 is electrically connected to the sixth gate electrode 22. The transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The gate electrode is electrically connected to the fifth input terminal 25. The first terminal is electrically connected to the power supply line 52, and the second terminal is the third terminal of the eighth transistor 38. The gate electrode is electrically connected to the second input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a fourth terminal connected to the gate electrode of the fourth transistor 33. the gate electrode of the transistor 34, the gate electrode of which is connected to the second input terminal 22 The ninth transistor 39 has a first terminal electrically connected to the first transistor The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are electrically connected. The gate electrode is electrically connected to the power supply line 52. The first terminal of the inverter 40 is electrically connected to the first input terminal 21, and the second terminal of the inverter 40 is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The first terminal of the eleventh transistor 41 is electrically connected to the power supply line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. .

[0188] In FIG. 4C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor The connection point of the gate electrode of the ninth transistor 40 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 , the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is In order to maintain the potential of node B, one electrode is electrically connected to node B. Specifically, one electrode of the capacitor may be connected to the node B. The other end may be electrically connected to the power supply line 53.

[0189] Next, the operation of the pulse output circuit shown in FIG. 5(A) will be explained with reference to FIG. 5(B) and FIGS. 6 to 8. Specifically, in the timing chart of FIG. 5B, , the second period 62, the third period 63, the fourth period 64, and the fifth period 65 will be explained. In Figures 6 and 7, the transistors in the on state (conducting state) in each period are indicated by solid lines, The transistors in the off state are shown by dashed lines.

[0190] Here, the output of the first pulse output circuit 10_1 will be described. The circuit 10_1 is a first circuit whose first input terminal 21 supplies a first clock signal (CK1). A second input terminal 22 electrically connected to line 11 provides a second clock signal (CK2). The third input terminal 23 is electrically connected to the second wiring 12 that corresponds to the third clock signal (C K3).

[0191] In the following description, the first transistor 31 to the eleventh transistor 41 are N The gate-source voltage (Vgs) is the threshold voltage (Vt h), the conduction state is established.

[0192] For the sake of simplicity, VSS=0 is used here, but this is not limiting. The difference between D and VCC, and the difference between VCC and VSS (when VDD > VCC) The threshold voltage of the transistor is set to be greater than the threshold voltage of the transistor, i.e., the transistor is set to the ON state ( The potential of the power supply line 52 is set lower than the potential of the power supply line 51. As a result, the second transistor 32, the fourth transistor 34, the ninth transistor 3 9. The potential applied to the gate electrode of the eleventh transistor 41 is kept low, and the pulse output the second transistor 32, the fourth transistor 34, and the ninth transistor 39 of the power circuit; In addition, the shift in the threshold voltage of the eleventh transistor 41 can be reduced, and deterioration can be suppressed. do.

[0193] In the first period 61, the first start pulse (SP1) becomes H level, and the first start pulse A fourth input terminal 2 of the first pulse output circuit 10_1 to which a start pulse (SP1) is input The first transistor 31 and the fifth transistor 35 electrically connected to the first transistor 4 are in a conductive state. In addition, since the third clock signal (CK3) is also at the H level, the seventh transistor 3 The ninth transistor 39 is also turned on. The second high power supply potential VCC is applied to the gate of the ninth transistor 39. When the voltage Vcc is applied, the ninth transistor 39 is also turned on (see FIG. 6(A)).

[0194] At this time, the first transistor 31 and the ninth transistor 39 are on, so that the node The potential at node A rises. Also, since the fifth transistor 35 is on, the potential at node B Descend.

[0195] The potential of the second terminal of the first transistor 31 is serves as a source, and the potential of the first power supply line 51 is changed to the threshold voltage of the first transistor 31. Therefore, it is VDD-Vth31 (Vth31 is the voltage of the first transistor 31). The threshold voltage Vth39 of the ninth transistor 39 and Vt In h31, if (VDD-Vth31) is equal to or greater than (VCC-Vth39), The potential of node A becomes VCC-Vth39, the ninth transistor 39 turns off, and node A It becomes floating while maintaining the potential (VCC-Vth39). 1) is less than (VCC-Vth39), the ninth transistor 39 will not be turned off. The potential at node A rises to (VDD-Vth31).

[0196] In this embodiment, the first to eleventh transistors 31 to 41 are all the same Since they have the same threshold voltage Vth0, the potential of node A is (VCC-Vth0). The ninth transistor 39 is turned off, and the node A maintains the potential (VCC-Vth0). It becomes floating.

[0197] Here, in the third transistor 33, the potential of the gate electrode is (VCC-Vth0). When the voltage between the gate and source of the third transistor 33 exceeds its threshold, That is, VCC-Vth0>Vth33 (Vth33 is the voltage of the third transistor 3 3, which is Vth0 in this embodiment, The inverter 33 turns on.

[0198] In the second period 62, the first input terminal 21 of the first pulse output circuit 10_1 is The clock signal (CK1) switches from L level to H level. Since the transistor 33 is on, a current flows between the source and drain, and appears at the output terminal 26. The potential of the output signal (OUT(1)(SR)) output from the third transistor 33, i.e., the second potential of the third transistor 33, The potential of the electrode (in this case, the source electrode) of the third transistor 33 begins to rise. There is a capacitive coupling due to the parasitic capacitance and channel capacitance between the sources, and the potential of the output terminal 26 As the potential of the gate electrode of the third transistor 33, which is in a floating state, increases, (Bootstrap operation). Finally, the voltage of the gate electrode of the third transistor 33 The potential becomes higher than (VDD+Vth33), and the potential of the output terminal 26 becomes equal to VDD. (See Figure 5(B) and Figure 6(B)).

[0199] At this time, the fourth input terminal 24 of the first pulse output circuit 10_1 is connected to the first start Since the pulse (SP1) is at H level, the fifth transistor 35 is turned on and the node B is maintained at the L level. Therefore, when the potential of the output terminal 26 changes from the L level to the H level, When the output voltage rises, the problem caused by the capacitive coupling between the output terminal 26 and the node B can be suppressed. do.

[0200] Next, in the first half of the third period 63, the first start pulse (SP1) becomes L level. The first transistor 31 and the fifth transistor 35 are turned off. Following step 2, the first clock signal (CK1) is maintained at the H level, and the potential of node A is also changed. Therefore, a high-level signal is supplied to the first electrode of the third transistor 33 (see FIG. 6(C)). In the first half of the third period 63, the transistors connected to the node B is turned off, and node B is in a floating state, but the potential of output terminal 26 does not change, so node The effect of the problem caused by the capacitive coupling between B and the output terminal 26 is almost negligible.

[0201] As shown in FIG. 5A, the ninth transistor, whose gate is applied with the second high power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0202] If the ninth transistor 39, to whose gate electrode the second high power supply potential VCC is applied, is not present, When the potential of the node A rises due to the bootstrap operation, the first transistor 31 The potential of the source, which is the second terminal, rises and becomes higher than the first high power supply potential VDD. As a result, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and the source, the gate and the drain During this period, a large bias voltage is applied, which causes a large stress on the transistor. This can be a factor in the deterioration of the sensor.

[0203] Therefore, a ninth transistor 39 is provided to the gate electrode of which the second high power supply potential VCC is applied. By keeping the voltage at node A low, the voltage at node A rises due to the bootstrap operation. This can prevent the potential of the second terminal of the first transistor 31 from increasing. By providing the ninth transistor 39, the gate and the source of the first transistor 31 are connected to each other. Therefore, the value of the negative bias voltage applied between the electrodes can be reduced. By configuring the circuit in this form, a voltage is applied between the gate and source of the first transistor 31. Since the negative bias voltage applied can be reduced, the first transistor 31 can be prevented from being damaged by stress. This can suppress deterioration of the material.

[0204] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of soft registers, the signal line driver circuit requires higher dynamic characteristics than the scanning line driver circuit. The ninth transistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0205] In the second half of the third period 63, the third clock signal (CK3) is switched to the H level. , the seventh transistor 37 is turned on. The clock signal (CK2) is held at the H level, and the eighth transistor 38 is on. , the potential at node B rises to VCC.

[0206] Since the potential of the node B has risen, the second transistor 32, the fourth transistor 34, and The eleventh transistor 41 is turned on, and the potential of the output terminal 27 (OUT(1)) becomes L level. It becomes a bell.

[0207] In the second half of the third period 63, the second transistor 32 is turned on, and the ninth transistor Since an L-level signal is supplied to the first terminal of the ninth transistor 39, is turned on, and the potential at node A drops.

[0208] Furthermore, the fourth transistor 34 is turned on, and the potential of the output terminal 26 drops. (See Figure 6(D)).

[0209] In the first half of the fourth period 64, the second clock signal (CK2) changes from the H level to the L level. , the eighth transistor 38 is turned off. However, the fifth input terminal 25 ( OUT(3)) is held at the H level, the sixth transistor 36 is in the ON state. Therefore, node B holds VCC (see FIG. 7(A)).

[0210] Thereafter, in the second half of the fourth period 64, the fifth input terminal 25 of the first pulse output circuit 10_1 (OUT(3)) becomes L level, and the sixth transistor 36 is turned off (see FIG. 7(B)). At this time, node B goes from being held at the VCC level to being in a floating state. Therefore, the second transistor 32, the fourth transistor 34, and the eleventh transistor 4 However, as shown in FIG. 5B, the potential of node B is V It drops from the CC level due to the off current of the transistor and the like.

[0211] After that, the circuit repeats the cyclic operation. This period is called the fifth period 65. (See FIG. 7(C) ), (D). During a certain period of the fifth period 65 (the second clock signal (CK2) and the third clock signal (CK3) When the clock signals (CK3) are both at H level, the seventh transistor 3 The seventh and eighth transistors 38 are turned on, and a signal of the VCC level is periodically supplied to node B. (See FIG. 7(D)).

[0212] In this way, a signal of VCC level is periodically supplied to node B during the fifth period 65. By doing so, it is possible to suppress malfunction of the pulse output circuit. By periodically turning on or off the eighth transistor 37 and the eighth transistor 38, This makes it possible to reduce the shift in the threshold voltage of the transistor.

[0213] During the fifth period 65, a signal of VCC level is input to the node B from the second power supply line 52. If the potential of node B drops while no current is being supplied, a capacitance element is provided in node B in advance, A configuration may be adopted in which the drop in the potential of the node B is alleviated.

[0214] The connection between the second input terminal 22 and the gate electrode of the eighth transistor 38 and the third input The connection between the terminal 23 and the gate electrode of the seventh transistor 37 is interchanged to form the eighth transistor. The clock signal supplied to the gate electrode of the seventh transistor 38 is changed to the gate voltage of the seventh transistor 37. The clock signal supplied to the gate electrode of the seventh transistor 37 is then supplied to the eighth transistor 38. The same effect can be achieved by supplying the same voltage to the gate electrode of the transistor 38.

[0215] In the pulse output circuit shown in FIG. 5(A), the second input terminal 22 and the third input terminal 23 By controlling the potential of the seventh transistor 37 and the eighth transistor 38, both the seventh transistor 37 and the eighth transistor 38 are turned on. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. Then, when the seventh transistor 37 and the eighth transistor 38 are both turned off, The potential of the gate electrode of the seventh transistor 37 is lowered, and the potential of the gate electrode of the eighth transistor 38 is lowered. The drop in the potential of the left electrode causes the potential of node B to drop twice.

[0216] On the other hand, in the pulse output circuit shown in FIG. 5(A), as in the period of FIG. 5(B), The seventh transistor 37 and the eighth transistor 38 are both in an on state. The seventh transistor 37 is turned on and the eighth transistor 38 is turned off. When the seventh and eighth transistors 38 are both turned off, the gate of the eighth transistor 38 The potential drop of the port electrode causes the potential of node B to drop only once, and the number of times the potential drops The number can be reduced to one.

[0217] That is, the gate electrode of the seventh transistor 37 receives the clock signal from the third input terminal 23. and supplies the clock signal from the second input terminal 22 to the gate electrode of the eighth transistor 38. Supplying this voltage is preferable because it reduces fluctuations in the potential of node B, resulting in reduced noise. It is suitable.

[0218] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a VCC level signal during this period, This can suppress malfunction of the output circuit.

[0219] The node B of the pulse output circuit described in this embodiment is connected to the VCC level in the second half of the fourth period 64. The potential of node B in the floating state changes from the state where the bell is held to the floating state. However, in this embodiment, the voltage may drop from the VCC level due to the off-current of the transistor 35. The fifth transistor 35 of the pulse output circuit of this configuration has an extremely low off-state current. Since a transistor using the first electrode layer as a main gate electrode is used, The potential of node B in the state is well maintained and drops less from the VCC level. Malfunctions of the semiconductor device are suppressed, improving reliability.

[0220] In addition, to suppress the off-state current of the transistor, the gate electrode is made into a double gate structure and a tri-gate structure. Since there is no need for a multi-gate structure such as a pull gate structure, the transistor can be made smaller. Furthermore, a capacitance element for maintaining the potential of node B is not required or can be made smaller. A pulse output circuit configured using such a miniaturized element, or a miniaturized By using a shift register configured using the pulse output circuit, This makes it possible to miniaturize the entire system.

[0221] In addition, a transistor using the first electrode layer as a main gate electrode has an extremely low off-state current. The pulse output of this embodiment is not only suppressed to a low level but also has a positive threshold voltage. In the circuit, the second transistor 32 is a transistor using the first electrode layer as the main gate electrode. Since a resistor is used, there is no loss when the voltage of node A is increased by the bootstrap operation. As a result, malfunctions of semiconductor devices are suppressed and reliability is improved. To rise.

[0222] In the pulse output circuit of this embodiment, the third transistor 33 and the sixth transistor The tenth transistor 36, the tenth transistor 40, and the eleventh transistor 41 are made of highly purified The fourth electrode layer using the crystalline region of the oxide semiconductor layer is used as a main gate electrode. The transistor using the fourth electrode layer as a main gate electrode is Since the third transistor 33 and the sixth transistor 34 have excellent f characteristics and high field-effect mobility, The switching of the transistor 36, the tenth transistor 40, and the eleventh transistor 41 This allows the transistor to be made smaller.

[0223] A pulse output circuit configured using such high-speed elements, or a high-speed By using a shift register configured using a pulse output circuit, the entire semiconductor device This makes it possible to speed up the process.

[0224] In addition, the shift register shown in this embodiment mode is configured to receive the m-th pulse as shown in FIG. The pulse output from the output circuit and the pulse output from the (m+1)th pulse output circuit are The driving method is half (1 / 4 period) overlapped. This is different from the conventional shift register. The pulse output from the mth pulse output circuit and the pulse output from the (m+1)th pulse output circuit are Compared to the driving method in which the output pulses do not overlap (see Figure 8(B)), the wiring is charged. In this way, the pulse output time from the mth pulse output circuit can be approximately doubled. The pulse output from the (m+1)th pulse output circuit overlaps by half (1 / 4 period). By using this driving method, it is possible to apply a large load and operate at a high frequency. Furthermore, it is possible to provide a pulse output circuit that can output a wide range of pulses. It is possible.

[0225] Note that the shift register and the pulse output circuit shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be implemented in combination with the configuration of the shift register and pulse output circuit shown in the embodiment. The present invention can also be applied to semiconductor devices. The term "semiconductor device" refers to a device that can function by utilizing semiconductor properties.

[0226] (Fourth embodiment) In this embodiment, the oxide semiconductor layer described in Embodiment 3 is provided above and below the channel formation region. A shift register was fabricated using a four-terminal transistor with a pair of electrode layers placed between insulating films. A switching transistor having a highly purified oxide semiconductor layer is used as a transistor for a switching resistor. An example of configuring a driving circuit for an active matrix display device by combining a driving circuit First, we will explain the outline of the active matrix display device using a block diagram. Then, the signal line driver circuit and the scanning line driver circuit using the shift register of the display device will be explained. The drive circuit will now be described.

[0227] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, a The pixel portion 5301 has a plurality of signal lines. A plurality of scanning lines are arranged extending from the signal line driving circuit 5304, and the first scanning line driving circuit 5 302 and the second scanning line driver circuit 5303. At the intersections with the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is made of FPC (Flexible Printed Circuit). Through a connection part such as a timing control circuit 5305 (controller, control IC (also called the "interface")

[0228] The transistor arranged in the pixel portion 5301 is the transistor of one embodiment of the present invention described in Embodiment 1. The transistor used in the pixel portion 5301 is A transistor using the first electrode layer arranged on the substrate side as a main gate electrode is particularly preferred. A transistor using the first electrode layer as a main gate electrode has a low off-state current. This not only increases the contrast of the displayed image but also reduces the power consumption of the display device. .

[0229] Note that the transistor described in Embodiment 1 is an n-channel transistor; Among the driving circuits, part of the driving circuit that can be configured with n-channel transistors is It is formed on the same substrate as the resistor.

[0230] In FIG. 9A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of components such as drive circuits provided outside the display device is reduced, which leads to cost reduction. In addition, when a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring. The number of connections between the wirings increases. If a driver circuit is provided on the same board 5300, the number of connections between the wirings increases. The number of connections can be reduced, and the reliability or yield can be improved.

[0231] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0232] In FIG. 9B, a circuit with a relatively low driving frequency (for example, the first scanning line driving circuit 5302 , and the second scanning line driver circuit 5303) are formed on the same substrate 5300 as the pixel portion 5301, and A signal line driver circuit 5304 with a relatively high frequency is formed on a substrate separate from the pixel portion 5301. For example, a transistor using a single crystal semiconductor is used to achieve a driving frequency The signal line driver circuit 5304, which has a relatively high resistance, can also be formed on a separate substrate. It is possible to increase the size of display devices, reduce the number of processes, reduce costs, or improve yields. can.

[0233] In this embodiment, a signal line driver circuit 5304 having a relatively high driving frequency is connected to the pixel portion 53 It is to be noted that the driving circuit is formed on the same substrate 5300 as that of the substrate 5300. In this case, the number of connections between wirings can be reduced, improving reliability and yield. It is possible.

[0234] Next, an example of the configuration and operation of a signal line driver circuit configured with n-channel transistors will be described. This will be explained using FIG. 10(A) and FIG. 10(B).

[0235] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of transistors 5603_1 to 5603_k (k is a natural number) In this embodiment, the transistors 5603_1 to 5603_k have n-channel A configuration in which a loop-type transistor is applied will be described.

[0236] Regarding the connection relationship of the signal line driver circuit, the switching circuit 5602_1 is taken as an example and shown in FIG. 10( The first terminals of the transistors 5603_1 to 5603_k are respectively The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k. The second terminals of the transistors 5603_1 to 5603_5 are connected to the signal lines S1 to Sk, respectively. The gate of 603_k is connected to the wiring 5605_1.

[0237] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 02_N in order. Since it can be produced by the method explained in 3, detailed explanation will be omitted here.

[0238] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function for controlling the conduction state between the wirings S1 to Sk, that is, the wirings 5604_1 to 5604_k. The transistor 5603_1 has a function of supplying a voltage to the signal lines S1 to Sk. .about.5603_k each function as a switch.

[0239] In this embodiment, a highly purified transistor is used for the switching circuit 5602. The crystalline region of the oxide semiconductor layer is used as a channel formation region, and the fourth electrode layer is used as a main gate electrode. The fourth electrode layer is used as the main gate electrode. The transistors used in these displays have excellent dynamic characteristics and fast switching operations. This allows for the high-speed writing required by next-generation display devices with high density. The transistor using the semiconductor layer for the channel formation region is manufactured by the method described in Embodiment 1. Therefore, detailed explanations will be omitted here.

[0240] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0241] Next, the operation of the signal line driver circuit of FIG. 10(A) will be explained with reference to the timing chart of FIG. 10(B). 10B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0242] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0243] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 03_1~5603_k will be turned on, so wires 5604_1~5604_k and signal line At this time, the wirings 5604_1 to 5604_k are connected to Da ta(S1)~Data(Sk) is input. Data(S1)~Data(Sk) is , each of which is connected to a pixel belonging to a selected row via a transistor 5603_1 to 5603_k. In this way, during the periods T1 to TN, the selected pixels are written to the pixels in the first to k-th columns. The video signal data (DATA) is written to the pixels in the selected row in order of k columns. can be.

[0244] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0245] The shift register 5601 of the driver circuit of this embodiment has the same structure as that described in Embodiment 3. The use of shift registers prevents malfunctions and ensures high reliability. By using a miniaturized shift register, the entire drive circuit can be miniaturized. do.

[0246] In addition, the switching circuit 5602 of the driver circuit of this embodiment is made of a highly purified oxide. The switching operation is fast because the crystalline region of the semiconductor layer is used for the channel formation region. Therefore, the driver circuit exemplified in this embodiment mode can write data to pixels at high speed, and the number of pixels is This is suitable for next-generation display devices with many high-resolution images.

[0247] The shift register described in the third embodiment can also be applied to the scanning line driving circuit. The driving circuit includes a shift register, and in some cases a level shifter and a buffer. In the scanning line driver circuit, a clock signal (CL A selection signal is generated by inputting a start pulse signal (SP) and a start pulse signal (K). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. Since the transistors of the pixels in one line must all be turned on at once, the buffer is large. A device capable of passing a large current is used.

[0248] The active matrix display device described in this embodiment and the external device communicate with each other via the terminal section. Therefore, abnormal input from the outside (such as static electricity) To prevent malfunctions such as fluctuations in the threshold of the transistor, a protection circuit is provided in the drive circuit. The high breakdown voltage between the gate and source and between the gate and drain makes it suitable for transistors used in protection circuits. A transistor using the first electrode layer as a main gate electrode is suitable as the transistor. do.

[0249] (Embodiment 5) In this embodiment, an example of the structure of a terminal portion provided over the same substrate as a transistor is shown in FIG. 22, the same parts as those in FIG. 1 will be described using the same reference numerals.

[0250] 22(A1) and 22(A2) are a cross-sectional view and a top view of the gate line terminal portion, respectively. FIG. 22(A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 22(A2). In FIG. 22(A1), the conductive layer 415 formed on the second insulating layer 428 is It is a terminal electrode for connection that functions as a terminal. The first terminal 411 is made of the same material as the gate wiring, and the second terminal 412 is made of the same material as the source wiring. The connection electrode 412 overlaps with the first insulating layer 402 and is in direct contact with the first insulating layer 402 for electrical continuity. In addition, the connection electrode 412 and the conductive layer 415 are provided in a contact on the second insulating layer 428. The electrodes are in direct contact with each other through holes for electrical continuity.

[0251] 22(B1) and 22(B2) are a cross-sectional view and a top view of a source wiring terminal portion. Also, Fig. 22(B1) is taken along the line C3-C4 in Fig. 22(B2). In FIG. 22(B1), a conductive layer formed on the second insulating layer 428 is The layer 418 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, an electrode layer 416 made of the same material as the gate wiring is connected to the source wiring. The first insulating layer 402 is interposed between the first terminal 411 and the second terminal 414 so as to overlap the second terminal 414 to be electrically connected. The electrode layer 416 is formed below the second terminal 414. The electrode layer 416 is electrically connected to the second terminal 414. The electrode layer 416 is set to a potential different from that of the second terminal 414, for example, floating, G If you set it to ND, 0V, etc., you can set the capacitance for noise prevention or static electricity prevention. The second terminal 414 can be formed by connecting a conductive layer 428 to the second insulating layer 428. It is electrically connected to 418.

[0252] A plurality of gate lines, source lines, common potential lines, and power supply lines are provided according to the pixel density. In addition, in the terminal section, a first terminal having the same potential as the gate wiring, a source wiring, a second terminal at the same potential as the line, a third terminal at the same potential as the power supply line, and a fourth terminal at the same potential as the common potential line. The number of each terminal can be set to any number. It is sufficient if the implementer decides accordingly.

[0253] This embodiment mode can be freely combined with other embodiment modes.

[0254] (Embodiment 6) The transistor described in Embodiment 1 is manufactured, and the transistor is used in a pixel portion and a driver circuit. By using the above, a semiconductor device (also called a display device) having a display function can be manufactured. In addition, the transistor described in Embodiment 1 may be mounted on the same substrate as a pixel portion or on the entire driver circuit. The system on panel can be formed integrally on the substrate.

[0255] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitting diode (LED), specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0256] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0257] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) using the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0258] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. 11. FIG. 11 shows an embodiment formed on a first substrate 4001. Highly reliable transistors containing the In-Ga-Zn-O-based film shown in 1 as an oxide semiconductor layer The electrodes 4010 and 4011 and the liquid crystal element 4013 are sealed between the second substrate 4006. 11(A1) is a top view of the panel sealed with material 4005. This corresponds to the cross-sectional view at MN in (A2).

[0259] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0260] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting a signal line driver circuit 4003 by the OG method, and FIG. 11(A2) is a TAB method. This is an example in which the signal line driver circuit 4003 is mounted by the method.

[0261] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 11B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4010 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011. do.

[0262] The transistors 4010 and 4011 are made of an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable transistor described in Embodiment 1 can be applied to this embodiment. In this embodiment, the transistors 4010 and 4011 are n-channel transistors.

[0263] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 and the counter electrode 4031 are formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033. However, the color filters are provided on either the first substrate 4001 or the second substrate 4006. is also good.

[0264] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Also, aluminum foil can be covered with PVF film or polyester film. It is also possible to use a sheet having a structure in which the sheet is sandwiched between two thin films.

[0265] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. The common connection portion is used to connect the opposing electrode layer via conductive particles disposed between the pair of substrates. The conductive particles can be electrically connected to the common potential line. Included in 4005.

[0266] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs. c. or more and 100 μsec or less, and because it is optically isotropic, no alignment treatment is required. The viewing angle dependency is small.

[0267] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention can also be applied to a reflective liquid crystal display device. It can also be applied to a semi-transmissive liquid crystal display device.

[0268] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0269] In this embodiment, in order to reduce the surface irregularities caused by the transistor, In order to improve the reliability of the transistor, the transistor obtained in the first embodiment is It is covered with insulating layers (insulating layer 4020, insulating layer 4021) that function as insulating films. The protective film prevents the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective film is made of silicon oxide by sputtering. Silicon film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide a single layer of an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film In this embodiment, an example in which the protective film is formed by sputtering is shown. However, there is no particular limitation and various methods may be used for forming the layer.

[0270] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. When a silicon film is used, the aluminum film used as the source electrode layer and the drain electrode layer can be It is effective in preventing locking.

[0271] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When this happens, mobile ions such as sodium penetrate into the semiconductor region, affecting the electrical properties of the transistor. It is possible to suppress the change.

[0272] After forming the protective film, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). may be performed.

[0273] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant resins such as styrene resin, polyimide, benzocyclobutene resin, polyamide, and epoxy resin In addition to the above organic materials, low dielectric constant materials (L low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) In addition, a plurality of insulating films made of these materials can be stacked. In this way, the insulating layer 4021 may be formed.

[0274] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0275] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, At the same time as the annealing process, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). The insulating layer 4021 may be baked and the oxide semiconductor layer may be annealed at the same time, which may increase efficiency. This makes it possible to manufacture semiconductor devices easily.

[0276] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0277] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0278] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0279] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0280] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive film as the transistors 4010 and 4011. The source electrode layer and the drain electrode layer are formed of the same conductive film.

[0281] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0282] In FIG. 11, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0283] FIG. 12 shows a transistor substrate 26 manufactured using the transistor described in Embodiment 1. 1 shows an example of a liquid crystal display module constructed as a semiconductor device using the semiconductor device.

[0284] FIG. 12 shows an example of a liquid crystal display module, which includes a transistor substrate 2600 and an opposing substrate 260. 1 is fixed by a sealing material 2602, and a pixel portion 2603 including a transistor and the like is provided between them. A display element 2604 including a liquid crystal layer, a colored layer 2605, etc. are provided to form a display area. The colored layer 2605 is necessary for color display. In the case of the RGB system, it is red, green, and blue. A colored layer corresponding to each color is provided for each pixel. On the outer side of the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and is mounted on a circuit board 261. 2 is a wiring circuit portion 26 of the transistor substrate 2600 by a flexible wiring substrate 2609. It is connected to the 08 and incorporates external circuits such as control circuits and power supply circuits. The polarizing plate and the liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0285] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0286] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0287] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0288] (Embodiment 7) In this embodiment, an electronic device is used as a semiconductor device to which the transistor described in Embodiment 1 is applied. Here is an example of a grouper:

[0289] Figure 13 shows an active matrix electronic paper as an example of a semiconductor device. The transistor described in Embodiment 1 is used as the transistor 581 used in the device. It is possible.

[0290] The electronic paper in Figure 13 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0291] The transistor 581 sealed between the substrate 580 and the substrate 596 is a transistor according to one embodiment of the present invention. The first electrode layer 587 is insulated from the second electrode layer 588 by the source electrode layer or the drain electrode layer. The first electrode layer 58 is electrically connected to the first electrode layer 58 through an opening formed in the first electrode layer 583 and the second electrode layer 585. Between the second electrode layer 588 and the second electrode layer 589 are black areas 590a and white areas 590b. A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, and the spherical The particle 589 is filled with a filler 595 such as a resin (see FIG. 13). The cavity 594 in 89 is filled with liquid and has black area 590a and white area In this embodiment, the first electrode layer 587 has a grain having a thickness of 590b. The first electrode layer 586 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The transistor 581 is electrically connected to a common potential line provided on the same substrate. Using any one of the common connection parts shown in form 1, conductive particles arranged between a pair of substrates The second electrode layer 588 and a common potential line can be electrically connected via the wiring.

[0292] Also, instead of the twist ball, an electrophoretic element can be used. and a particle with a diameter of 10 μm or more that contains positively charged white particles and negatively charged black particles. Microcapsules with a size of approximately 0.1 μm or less are used. The microcapsules are subjected to an electric field by the first and second electrode layers. When the light is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. The display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lines No light is required, the power consumption is low, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image that has been displayed will be retained. Therefore, it is possible to transmit a signal from a radio wave source to a semiconductor device with a display function (simply a display device, or Even if the display device (also referred to as a semiconductor device having a display device) is placed far away, the displayed image It will be possible to save it.

[0293] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0294] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0295] (Embodiment 8) In this embodiment, a light-emitting device is used as a semiconductor device to which the transistor described in Embodiment 1 is applied. An example of a display device is shown below. The display element of the display device is an electroluminescent device. The light-emitting element that uses electroluminescence is shown. The luminescent material is classified as either an organic compound or an inorganic compound. The former is called an organic EL element, and the latter is called an inorganic EL element.

[0296] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These carriers are then injected into a layer containing a light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0297] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0298] FIG. 14 shows a display device to which digital time gray scale driving can be applied as an example of a semiconductor device to which the present invention is applied. 1 is a diagram illustrating an example of an element configuration. Note that OS in the diagram represents an oxide semiconductor. This indicates that the transistor uses a silicon carbide (SiC) conductor.

[0299] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The oxide semiconductor layer (In—Ga—Zn—O-based film) shown in Embodiment 1 is used as a channel-type An example in which two n-channel transistors are used in the formation region in one pixel is shown.

[0300] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate. That's fine.

[0301] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0302] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0303] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0304] Also, when analog grayscale driving is used instead of digital time grayscale driving, the signal input is different. By doing so, the same pixel configuration as in FIG. 14 can be used.

[0305] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0306] Note that the pixel configuration shown in Fig. 14 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0307] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be explained using an example in which the capacitor is n-type. C) Transistors 7001 and 701 which are driving transistors used in the semiconductor device 1 and 7021 can be manufactured in the same manner as the transistor shown in Embodiment 1, and This is a highly reliable transistor that contains an -O-based film as an oxide semiconductor layer.

[0308] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides. The present invention can also be applied to the above light-emitting devices.

[0309] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0310] The driving transistor 7011 is an n-type transistor, and light emitted from the light emitting element 7012 is incident on the first electrode 7013. FIG. 15(A) shows a cross-sectional view of a pixel when light is emitted to the driving transistor 7013 side. A conductive layer having transparency to visible light and electrically connected to the drain electrode layer of the sta- tor 7011 is A first electrode 7013 of the light-emitting element 7012 is formed on the film 7017. On the layer 7013, an EL layer 7014 and a second electrode 7015 are laminated in this order.

[0311] The conductive film 7017 having a property of transmitting visible light is formed by using an indium tin oxide film containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide with titanium oxide Oxide, silicon oxide-added indium tin oxide, etc., which has transparency to visible light A conductive film can be used.

[0312] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, In addition to alloys containing these metals (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In FIG. 15A, the film thickness of the first electrode 7013 is set to a thickness that allows visible light to pass through (preferably For example, an aluminum film having a thickness of 20 nm is used. is used as the first electrode 7013 .

[0313] After a conductive film having a light-transmitting property to visible light and an aluminum film are stacked, selective The conductive film 7017 and the first electrode 7013 are formed by etching. In this case, etching can be performed using the same mask, which is preferable. It's nice.

[0314] The partition wall 7019 is formed on the protective insulating layer 7035 and the insulating layer 7032. The conductive film 7017 is disposed on the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7013 may be covered with a partition wall. organic resin film such as acrylate resin, polyamide, epoxy resin, inorganic insulating film or organic polysiloxane The partition wall 7019 is formed by using a photosensitive resin material, and is 13, and an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7019, In this case, the step of forming a resist mask can be omitted.

[0315] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is made of at least It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7014 is made up of multiple layers, On the first electrode 7013 functioning as a The hole injection layer is laminated in this order. Note that it is not necessary to provide all of these layers.

[0316] The stacking order is not limited to the above, and the first electrode 7013 may function as an anode. Layers of hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked on top of 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a By stacking the layers in the order of the incoming layers, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. Therefore, it is preferable.

[0317] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, a material with a large work function ( Specifically, materials with an energy of 4.0 eV or more, such as ZrN, Ti, W, Ni, Pt, Cr, etc. Transparent conductive materials such as ITO, IZO, and ZnO are preferred. A shielding film 7016, for example, a metal that blocks light or a metal that reflects light, is used. In this embodiment, an ITO film is used as the second electrode 7015 and a Ti film is used as the shielding film 7016. do.

[0318] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. 15(A), the light-emitting element Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0319] In FIG. 15A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, and passes through the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7030, and The light is then emitted through the substrate 7010.

[0320] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0321] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. 15A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as acrylic resin, and is colored. It has the function of flattening the unevenness caused by the filter layer 7033.

[0322] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0323] In FIG. 15B, the drain electrode layer of the driving transistor 7021 is electrically connected to the drain electrode layer of the driving transistor 7022. The first electrode 70 of the light-emitting element 7022 is formed on the conductive film 7027 that transmits visible light. 23 is formed, and an EL layer 7024 and a second electrode 7025 are formed on the first electrode 7023. They are stacked in order.

[0324] The conductive film 7027 having a property of transmitting visible light is formed by using an indium tin oxide film containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide with titanium oxide Oxide, silicon oxide-added indium tin oxide, etc., which has transparency to visible light A conductive film can be used.

[0325] In addition, various materials can be used for the first electrode 7023. For example, When using 23 as a cathode, a material with a small work function (specifically, 3.8 eV or less), e.g. For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, In addition to alloys containing these metals (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are also included. In this embodiment, the first electrode 7023 is used as a cathode, and the film thickness thereof is The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, the thickness is set to 20 nm. An aluminum film having the formula:

[0326] After a conductive film having a light-transmitting property to visible light and an aluminum film are stacked, selective The conductive film 7027 and the first electrode 7023 are formed by etching. In this case, etching can be preferably performed using the same mask.

[0327] The partition wall 7029 is formed on the protective insulating layer 7045 and the insulating layer 7042, and The conductive film 7027 is disposed on the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7023 may be covered with a partition wall. organic resin film such as acrylate resin, polyamide, epoxy resin, inorganic insulating film or organic polysiloxane The partition wall 7029 is formed by using a photosensitive resin material, and is 23, and an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7029, In this case, the step of forming a resist mask can be omitted.

[0328] The EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It can be made up of a single layer or multiple layers stacked together. When the EL layer 7024 is made up of multiple layers, it functions as a cathode. On the first electrode 7023, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed. It is not necessary to provide all of these layers.

[0329] The stacking order is not limited to the above, and the first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode, and an electron injection layer 7024 is provided on the cathode. The power consumption is reduced by stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This is preferable because

[0330] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment mode, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is used as an anode. Form.

[0331] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. 15(B), the light-emitting element The light emitted from 7022 travels between the second electrode 7025 and the first electrode 70 as shown by the arrows. 23It is fired on both sides.

[0332] In FIG. 15B, light emitted from the light-emitting element 7022 toward the first electrode 7023 One light passes through the color filter layer 7043 and enters the insulating layer 7042 and the oxide insulating layer 704 1. The light is emitted through the gate insulating layer 7040 and the substrate 7020.

[0333] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0334] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0335] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0336] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0337] In FIG. 15C, a transistor 7001 serving as a driving transistor is an n-type transistor, and a light-emitting element 7 7 shows a cross-sectional view of a pixel in the case where light emitted from 002 exits to the second electrode 7005 side. In FIG. 15C, the drain electrode layer of the driving transistor 7001 is electrically connected to the drain electrode layer of the driving transistor 7002. A first electrode 7003 of the light emitting element 7002 is formed on the first electrode 7003. An L layer 7004 and a second electrode 7005 are laminated in this order.

[0338] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, Li or Cs, Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, and alloys containing these metals In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0339] The partition wall 7009 is formed on the protective insulating layer 7052 and the insulating layer 7055, and The first electrode 7003 is placed on the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7003 may be covered with a partition wall. The partition wall 7009 may be made of polyimide, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, or organic polymer films The partition wall 7009 is formed by using a photosensitive resin material, and the first electrode An opening is formed on 7003, and the sidewall of the opening has a continuous curvature. It is preferable to form the partition wall 7009 so that it has a flat surface. In this case, the step of forming a resist mask can be omitted.

[0340] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7004 is made up of a plurality of layers, On the first electrode 7003 used as a light-emitting layer, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport ... The insulating layer, the insulating film, and the insulating film are laminated in this order. Note that it is not necessary to provide all of these layers.

[0341] The stacking order is not limited to the above, and the hole injection layer may be formed on the first electrode 7003 used as an anode. Alternatively, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order.

[0342] In Figure 15(C), hole injection is performed on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0343] However, when the transistor 7001 is an n-type, an electron injection layer and an electron The order of stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the drive circuit. This is preferable because it can suppress a voltage rise and reduce power consumption.

[0344] The second electrode 7005 is formed using a conductive material that transmits visible light. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Indium tin oxide, indium zinc oxide, indium tin oxide doped with silicon oxide, etc. Any conductive film that transmits visible light may be used.

[0345] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 15(C), the light emitting element 700 Light emitted from 2 is emitted to the second electrode 7005 side as shown by the arrow.

[0346] In FIG. 15C, the drain electrode layer of the transistor 7001 is formed of an oxide insulating layer. 7051, a protective insulating layer 7052, and an insulating layer 7055 through contact holes provided therein. The planarization insulating layer 7053 is made of polyimide, acrylic, or the like. Resin materials such as polyethylene terephthalate, benzocyclobutene, polyamide, and epoxy resin can be used. In addition to the above resin materials, low-dielectric constant materials (low-k materials), siloxane-based resins, etc. , PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. By stacking a plurality of insulating films made of these materials, a planarizing insulating layer 7053 is formed. The method for forming the planarization insulating layer 7053 is not particularly limited, and may be any of the following depending on the material. Sputtering method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet Jet method, screen printing, offset printing, etc.), doctor knife, roll coater, A ten coater, knife coater, etc. can be used.

[0347] In the structure of FIG. 15C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is added to make four types. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0348] In the structure of FIG. 15(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0349] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be formed to emit an area color light.

[0350] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0351] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0352] The transistor that controls the driving of the light-emitting element (drive transistor) and the light-emitting element are electrically However, a current control transistor may be connected between the driving transistor and the light emitting element. A transistor may be connected.

[0353] Note that the semiconductor device shown in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0354] Next, a light-emitting device corresponding to one mode of a semiconductor device to which the transistor described in Embodiment 1 is applied will be described. The appearance and cross section of the display panel (also called a light-emitting panel) will be described with reference to FIG. 16(A) is a diagram showing a structure in which a transistor and a light emitting element formed on a first substrate are connected to a second substrate. 16(B) is a top view of the panel sealed with a sealant between them, and FIG. 16(A) is a top view of the panel sealed with a sealant between them. This corresponds to the cross section at HI.

[0355] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0356] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. 16B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0357] The transistors 4509 and 4510 are made of an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable transistor described in Embodiment 1 can be applied to this embodiment. In this embodiment, the transistors 4509 and 4510 are n-channel transistors.

[0358] The channel of the oxide semiconductor layer of the transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the hole formation region. By placing the conductive layer at a position that overlaps the channel formation region, The amount of change in the threshold voltage of the transistor 4509 can be reduced. The potential of the gate electrode layer of the transistor 4509 may be the same as or different from that of the gate electrode layer of the transistor 4509. Alternatively, the conductive layer 4540 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0359] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light-emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the stacked structure of the second electrode layer 4513 is not limited to the structure shown in this embodiment mode. The configuration of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0360] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0361] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0362] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon nitride oxide film, a DLC film, etc.

[0363] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0364] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the transistors 4509 and 451 The source electrode layer and the drain electrode layer of the transistor 10 are formed from the same conductive film as the source electrode layer and the drain electrode layer of the transistor 10.

[0365] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0366] The substrate positioned in the direction of light extraction from the light emitting element 4511 is transparent to visible light. In that case, glass plates, plastic plates, polyester films, etc. Alternatively, a material that is translucent to visible light, such as an acrylic film, is used.

[0367] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV In this embodiment, nitrogen is used as the filler. The material used was

[0368] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0369] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0370] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0371] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0372] (Embodiment 9) The semiconductor device to which the transistor described in Embodiment 1 is applied is used as electronic paper. Electronic paper can be used in all types of electronic devices that display information. For example, electronic paper can be used to display electronic books, Stars, in-car advertisements on trains and other vehicles, displays on various cards such as credit cards, etc. Examples of electronic devices are shown in Figures 17 and 18.

[0373] FIG. 17(A) shows a poster 2631 made of electronic paper. When printed materials are used, the advertisements are replaced manually, but when electronic paper is used, The display of the advertisement can be changed in a short time. Also, the display is stable without any distortion. The poster may be configured to be capable of transmitting and receiving information wirelessly.

[0374] FIG. 17(B) shows an advertisement 2632 inside a vehicle such as a train. When using printed paper, advertisements are exchanged manually, but with electronic paper, This allows you to change the display of your advertisements in a short time without requiring a lot of manpower. It is possible to obtain a stable image without any distortion. It may also be possible to use the following.

[0375] 18 shows an example of an electronic book. For example, an electronic book 2700 is housed in a housing 27 The housing 2701 and the housing 2703 are The shaft 2711 is an integral part of the opening and closing operation. This configuration makes it possible to operate like a paper book.

[0376] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are also configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, if a sentence is displayed on the right display (display 2705 in FIG. 18) and In FIG. 18, an image can be displayed on the display unit 2707).

[0377] 18 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. Good too.

[0378] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0379] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0380] (Embodiment 10) The semiconductor device using the transistor described in Embodiment 1 can be used in a variety of electronic devices (including gaming machines). The electronic device can be applied to, for example, a television device (including a television , or television receiver), computer monitors, digital cameras , digital video cameras, digital photo frames, mobile phones (mobile phones, mobile phone accessories) (also called "devices"), portable game consoles, personal digital assistants, audio playback devices, large game machines such as pachinko machines Examples include a gaming machine.

[0381] FIG. 19A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0382] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0383] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0384] FIG. 19(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0385] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0386] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0387] FIG. 20(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 20(A) also includes a speaker unit 9884, a recording medium insertion unit 988, 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient if the configuration includes the semiconductor device, and other auxiliary equipment is provided as appropriate. The portable gaming machine shown in FIG. 20(A) can be used to play a game using a program recorded on a recording medium. It has the function of reading out the game program or data and displaying it on the display, and wirelessly communicating with other portable gaming machines. The portable gaming machine shown in FIG. 20(A) has the following functions: The function is not limited to this and may have various functions.

[0388] FIG. 20(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to this, and it is sufficient that the present invention is configured to include at least the semiconductor device according to the present invention. The configuration can be such that appropriate equipment is provided.

[0389] 21A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002 incorporated in the It is equipped with a speaker 1005, a microphone 1006, etc.

[0390] The mobile phone 1000 shown in FIG. 21A displays information by touching the display unit 1002 with a finger or the like. You can also make calls, write emails, and perform other operations. This can be done by touching the display portion 1002 with a finger or the like.

[0391] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0392] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0393] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0394] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0395] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0396] The display unit 1002 can also function as an image sensor. By touching the device with your palm or fingers and capturing an image of your palm print or fingerprint, you can authenticate your identity. In addition, a backlight that emits near-infrared light to the display unit or a sensing light that emits near-infrared light By using a source, it is also possible to image finger veins, palm veins, etc.

[0397] FIG. 21B is also an example of a mobile phone. The mobile phone in FIG. 21B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used independently. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry.

[0398] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so. [Explanation of symbols]

[0399] 10 Pulse output circuit 11 First Wire 12 Second wiring 13 Third Wire 14 Fourth Wire 15 The fifth wire 16 Sixth Wire 17 Seventh Wire 21 First input terminal 22 Second input terminal 23 Third input terminal 24 4th input terminal 25 5th input terminal 26 First output terminal 27 Second output terminal 31 First transistor 32 Second transistor 33 The third transistor 34 The Fourth Transistor 35 The Fifth Transistor 36 The Sixth Transistor 37 The Seventh Transistor 38 The 8th Transistor 39 The 9th Transistor 40 The 10th Transistor 41 The 11th Transistor 51 Power line 52 Power line 53 Power line 61 First Period 62 Second Period 63 Third Period 64 Fourth Period 65 Fifth Period 400 boards 402 First insulating layer 403 Oxide semiconductor film 404a Oxide semiconductor layer 404b Oxide semiconductor layer 404c Oxide semiconductor layer 405a Crystal region 405b Crystal region 405c crystal region 408 Contact Hole 410a First wiring 410b Second wiring 410c third wiring 411 First Terminal 412 Connection electrode 414 Second Terminal 415 Conductive Layer 416 Electrode layer 418 Conductive Layer 421a First electrode layer 421b First electrode layer 421c First electrode layer 422a Fourth electrode layer 422b Fourth electrode layer 422c Connection electrode layer 428 Second insulating layer 440A transistor 440B transistor 450 transistors 455a Second electrode layer 455b Third electrode layer 455c Second electrode layer 455d Third electrode layer 455e Second electrode layer 455f Third electrode layer 580 board 581 Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 PCB 1000 mobile phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 2600 Transistor Board 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4040 Conductive layer 4042 Conductive layer 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7000 boards 7001 Drive transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 board 7011 Drive transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7020 board 7021 Drive transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Conductive film 7029 Bulkhead 7030 Gate insulating layer 7031 Oxide insulating layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Gate insulating layer 7041 Oxide insulating layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7051 Oxide insulating layer 7052 Protective insulation layer 7053 Planarization insulating layer 7055 Insulation layer 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

1. A light emitting device comprising: a color filter layer; and a light emitting element having a region disposed above the color filter layer, an oxide semiconductor layer having a channel formation region of a transistor; a first conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the transistor; a second conductive layer electrically connected to the oxide semiconductor layer; an insulating layer having a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; the color filter layer having a region disposed above the insulating layer; a first resin layer having a region disposed above the color filter layer; a pixel electrode of the light-emitting element having a region disposed above the first resin layer; a second resin layer having a region disposed above the first resin layer and a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the second resin layer, Light emitted from the light-emitting element passes through the color filter layer and is emitted, the first resin layer has a region that is in contact with an upper surface of the insulating layer in a region that does not overlap with the color filter layer, the first resin layer has a first contact hole in a region not overlapping with the color filter layer; the insulating layer has a second contact hole overlapping the first contact hole in a region not overlapping the color filter layer; an upper surface of the insulating layer has, in a region overlapping with the second conductive layer, a region that is not in contact with the first resin layer and is not in contact with the color filter layer; the pixel electrode is electrically connected to the second conductive layer through a region where the first contact hole and the second contact hole overlap; the second resin layer has a region in contact with an upper surface of the pixel electrode in a region where the first contact hole and the second contact hole overlap; Light-emitting device.

2. A light emitting device comprising: a color filter layer; and a light emitting element having a region disposed above the color filter layer, an oxide semiconductor layer having a channel formation region of a transistor; a first conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the transistor; a second conductive layer electrically connected to the oxide semiconductor layer; an insulating layer having a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; the color filter layer having a region disposed above the insulating layer; a first resin layer having a region disposed above the color filter layer; a pixel electrode of the light-emitting element having a region disposed above the first resin layer; a second resin layer having a region disposed above the first resin layer and a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the second resin layer, Light emitted from the light-emitting element passes through the color filter layer and is emitted, the first resin layer has a region that is in contact with an upper surface of the insulating layer in a region that does not overlap with the color filter layer, the first resin layer has a first contact hole in a region not overlapping with the color filter layer; the insulating layer has a second contact hole overlapping the first contact hole in a region not overlapping the color filter layer; an upper surface of the insulating layer has, in a region overlapping with the second conductive layer, a region that is not in contact with the first resin layer and is not in contact with the color filter layer; the pixel electrode is electrically connected to the second conductive layer through a region where the first contact hole and the second contact hole overlap; the second resin layer has a region overlapping with the second conductive layer in a region where the first contact hole and the second contact hole overlap; Light-emitting device.

3. A light emitting device comprising: a color filter layer; and a light emitting element having a region disposed above the color filter layer, a third conductive layer serving as a first gate electrode of the transistor; an oxide semiconductor layer having a region located above the third conductive layer and including a channel formation region of the transistor; a first conductive layer having a region located above the oxide semiconductor layer and functioning as a second gate electrode of the transistor; a second conductive layer electrically connected to the oxide semiconductor layer; an insulating layer having a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; the color filter layer having a region disposed above the insulating layer; a first resin layer having a region disposed above the color filter layer; a pixel electrode of the light-emitting element having a region disposed above the first resin layer; a second resin layer having a region disposed above the first resin layer and a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the second resin layer, Light emitted from the light-emitting element passes through the color filter layer and is emitted, the first resin layer has a region that is in contact with an upper surface of the insulating layer in a region that does not overlap with the color filter layer, the first resin layer has a first contact hole in a region not overlapping with the color filter layer; the insulating layer has a second contact hole overlapping the first contact hole in a region not overlapping the color filter layer; an upper surface of the insulating layer has, in a region overlapping with the second conductive layer, a region that is not in contact with the first resin layer and is not in contact with the color filter layer; the pixel electrode is electrically connected to the second conductive layer through a region where the first contact hole and the second contact hole overlap; the second resin layer has a region in contact with an upper surface of the pixel electrode in a region where the first contact hole and the second contact hole overlap; Light-emitting device.

4. A light emitting device comprising: a color filter layer; and a light emitting element having a region disposed above the color filter layer, a third conductive layer serving as a first gate electrode of the transistor; an oxide semiconductor layer having a region located above the third conductive layer and including a channel formation region of the transistor; a first conductive layer having a region located above the oxide semiconductor layer and functioning as a second gate electrode of the transistor; a second conductive layer electrically connected to the oxide semiconductor layer; an insulating layer having a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the second conductive layer; the color filter layer having a region disposed above the insulating layer; a first resin layer having a region disposed above the color filter layer; a pixel electrode of the light-emitting element having a region disposed above the first resin layer; a second resin layer having a region disposed above the first resin layer and a region disposed above the pixel electrode; the pixel electrode has a region that does not overlap with the second resin layer, Light emitted from the light-emitting element passes through the color filter layer and is emitted, the first resin layer has a region that is in contact with an upper surface of the insulating layer in a region that does not overlap with the color filter layer, the first resin layer has a first contact hole in a region not overlapping with the color filter layer; the insulating layer has a second contact hole overlapping the first contact hole in a region not overlapping the color filter layer; an upper surface of the insulating layer has, in a region overlapping with the second conductive layer, a region that is not in contact with the first resin layer and is not in contact with the color filter layer; the pixel electrode is electrically connected to the second conductive layer through a region where the first contact hole and the second contact hole overlap; the second resin layer has a region overlapping with the second conductive layer in a region where the first contact hole and the second contact hole overlap; Light-emitting device.

Images